Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 27 | #include <linux/cpufreq.h> |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 31 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 34 | #include <drm/drm_edid.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "drmP.h" |
| 36 | #include "intel_drv.h" |
| 37 | #include "i915_drm.h" |
| 38 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 39 | #include "i915_trace.h" |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 40 | #include "drm_dp_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 41 | #include "drm_crtc_helper.h" |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 42 | #include <linux/dma_remapping.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 43 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
| 45 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 47 | static void intel_update_watermarks(struct drm_device *dev); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 50 | |
| 51 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 52 | /* given values */ |
| 53 | int n; |
| 54 | int m1, m2; |
| 55 | int p1, p2; |
| 56 | /* derived values */ |
| 57 | int dot; |
| 58 | int vco; |
| 59 | int m; |
| 60 | int p; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 61 | } intel_clock_t; |
| 62 | |
| 63 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 64 | int min, max; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 65 | } intel_range_t; |
| 66 | |
| 67 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 68 | int dot_limit; |
| 69 | int p2_slow, p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 70 | } intel_p2_t; |
| 71 | |
| 72 | #define INTEL_P2_NUM 2 |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 73 | typedef struct intel_limit intel_limit_t; |
| 74 | struct intel_limit { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 76 | intel_p2_t p2; |
| 77 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 78 | int, int, intel_clock_t *, intel_clock_t *); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 79 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 80 | |
Jesse Barnes | 2377b74 | 2010-07-07 14:06:43 -0700 | [diff] [blame] | 81 | /* FDI */ |
| 82 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
| 83 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 84 | static bool |
| 85 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 86 | int target, int refclk, intel_clock_t *match_clock, |
| 87 | intel_clock_t *best_clock); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 88 | static bool |
| 89 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 90 | int target, int refclk, intel_clock_t *match_clock, |
| 91 | intel_clock_t *best_clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 92 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 93 | static bool |
| 94 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 95 | int target, int refclk, intel_clock_t *match_clock, |
| 96 | intel_clock_t *best_clock); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 97 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 98 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 99 | int target, int refclk, intel_clock_t *match_clock, |
| 100 | intel_clock_t *best_clock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 101 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 102 | static inline u32 /* units of 100MHz */ |
| 103 | intel_fdi_link_freq(struct drm_device *dev) |
| 104 | { |
Chris Wilson | 8b99e68 | 2010-10-13 09:59:17 +0100 | [diff] [blame] | 105 | if (IS_GEN5(dev)) { |
| 106 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 107 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 108 | } else |
| 109 | return 27; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 110 | } |
| 111 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 112 | static const intel_limit_t intel_limits_i8xx_dvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 113 | .dot = { .min = 25000, .max = 350000 }, |
| 114 | .vco = { .min = 930000, .max = 1400000 }, |
| 115 | .n = { .min = 3, .max = 16 }, |
| 116 | .m = { .min = 96, .max = 140 }, |
| 117 | .m1 = { .min = 18, .max = 26 }, |
| 118 | .m2 = { .min = 6, .max = 16 }, |
| 119 | .p = { .min = 4, .max = 128 }, |
| 120 | .p1 = { .min = 2, .max = 33 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 121 | .p2 = { .dot_limit = 165000, |
| 122 | .p2_slow = 4, .p2_fast = 2 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 123 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 124 | }; |
| 125 | |
| 126 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 127 | .dot = { .min = 25000, .max = 350000 }, |
| 128 | .vco = { .min = 930000, .max = 1400000 }, |
| 129 | .n = { .min = 3, .max = 16 }, |
| 130 | .m = { .min = 96, .max = 140 }, |
| 131 | .m1 = { .min = 18, .max = 26 }, |
| 132 | .m2 = { .min = 6, .max = 16 }, |
| 133 | .p = { .min = 4, .max = 128 }, |
| 134 | .p1 = { .min = 1, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 135 | .p2 = { .dot_limit = 165000, |
| 136 | .p2_slow = 14, .p2_fast = 7 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 137 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 138 | }; |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 139 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 140 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 141 | .dot = { .min = 20000, .max = 400000 }, |
| 142 | .vco = { .min = 1400000, .max = 2800000 }, |
| 143 | .n = { .min = 1, .max = 6 }, |
| 144 | .m = { .min = 70, .max = 120 }, |
| 145 | .m1 = { .min = 10, .max = 22 }, |
| 146 | .m2 = { .min = 5, .max = 9 }, |
| 147 | .p = { .min = 5, .max = 80 }, |
| 148 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 149 | .p2 = { .dot_limit = 200000, |
| 150 | .p2_slow = 10, .p2_fast = 5 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 151 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 155 | .dot = { .min = 20000, .max = 400000 }, |
| 156 | .vco = { .min = 1400000, .max = 2800000 }, |
| 157 | .n = { .min = 1, .max = 6 }, |
| 158 | .m = { .min = 70, .max = 120 }, |
| 159 | .m1 = { .min = 10, .max = 22 }, |
| 160 | .m2 = { .min = 5, .max = 9 }, |
| 161 | .p = { .min = 7, .max = 98 }, |
| 162 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 163 | .p2 = { .dot_limit = 112000, |
| 164 | .p2_slow = 14, .p2_fast = 7 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 165 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 166 | }; |
| 167 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 168 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 169 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 170 | .dot = { .min = 25000, .max = 270000 }, |
| 171 | .vco = { .min = 1750000, .max = 3500000}, |
| 172 | .n = { .min = 1, .max = 4 }, |
| 173 | .m = { .min = 104, .max = 138 }, |
| 174 | .m1 = { .min = 17, .max = 23 }, |
| 175 | .m2 = { .min = 5, .max = 11 }, |
| 176 | .p = { .min = 10, .max = 30 }, |
| 177 | .p1 = { .min = 1, .max = 3}, |
| 178 | .p2 = { .dot_limit = 270000, |
| 179 | .p2_slow = 10, |
| 180 | .p2_fast = 10 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 181 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 182 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 183 | }; |
| 184 | |
| 185 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 186 | .dot = { .min = 22000, .max = 400000 }, |
| 187 | .vco = { .min = 1750000, .max = 3500000}, |
| 188 | .n = { .min = 1, .max = 4 }, |
| 189 | .m = { .min = 104, .max = 138 }, |
| 190 | .m1 = { .min = 16, .max = 23 }, |
| 191 | .m2 = { .min = 5, .max = 11 }, |
| 192 | .p = { .min = 5, .max = 80 }, |
| 193 | .p1 = { .min = 1, .max = 8}, |
| 194 | .p2 = { .dot_limit = 165000, |
| 195 | .p2_slow = 10, .p2_fast = 5 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 196 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 197 | }; |
| 198 | |
| 199 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 200 | .dot = { .min = 20000, .max = 115000 }, |
| 201 | .vco = { .min = 1750000, .max = 3500000 }, |
| 202 | .n = { .min = 1, .max = 3 }, |
| 203 | .m = { .min = 104, .max = 138 }, |
| 204 | .m1 = { .min = 17, .max = 23 }, |
| 205 | .m2 = { .min = 5, .max = 11 }, |
| 206 | .p = { .min = 28, .max = 112 }, |
| 207 | .p1 = { .min = 2, .max = 8 }, |
| 208 | .p2 = { .dot_limit = 0, |
| 209 | .p2_slow = 14, .p2_fast = 14 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 210 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 211 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 215 | .dot = { .min = 80000, .max = 224000 }, |
| 216 | .vco = { .min = 1750000, .max = 3500000 }, |
| 217 | .n = { .min = 1, .max = 3 }, |
| 218 | .m = { .min = 104, .max = 138 }, |
| 219 | .m1 = { .min = 17, .max = 23 }, |
| 220 | .m2 = { .min = 5, .max = 11 }, |
| 221 | .p = { .min = 14, .max = 42 }, |
| 222 | .p1 = { .min = 2, .max = 6 }, |
| 223 | .p2 = { .dot_limit = 0, |
| 224 | .p2_slow = 7, .p2_fast = 7 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 225 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 226 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | static const intel_limit_t intel_limits_g4x_display_port = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 230 | .dot = { .min = 161670, .max = 227000 }, |
| 231 | .vco = { .min = 1750000, .max = 3500000}, |
| 232 | .n = { .min = 1, .max = 2 }, |
| 233 | .m = { .min = 97, .max = 108 }, |
| 234 | .m1 = { .min = 0x10, .max = 0x12 }, |
| 235 | .m2 = { .min = 0x05, .max = 0x06 }, |
| 236 | .p = { .min = 10, .max = 20 }, |
| 237 | .p1 = { .min = 1, .max = 2}, |
| 238 | .p2 = { .dot_limit = 0, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 239 | .p2_slow = 10, .p2_fast = 10 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 240 | .find_pll = intel_find_pll_g4x_dp, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 241 | }; |
| 242 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 243 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 244 | .dot = { .min = 20000, .max = 400000}, |
| 245 | .vco = { .min = 1700000, .max = 3500000 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 246 | /* Pineview's Ncounter is a ring counter */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 247 | .n = { .min = 3, .max = 6 }, |
| 248 | .m = { .min = 2, .max = 256 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 249 | /* Pineview only has one combined m divider, which we treat as m2. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 250 | .m1 = { .min = 0, .max = 0 }, |
| 251 | .m2 = { .min = 0, .max = 254 }, |
| 252 | .p = { .min = 5, .max = 80 }, |
| 253 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 254 | .p2 = { .dot_limit = 200000, |
| 255 | .p2_slow = 10, .p2_fast = 5 }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 256 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 257 | }; |
| 258 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 259 | static const intel_limit_t intel_limits_pineview_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 260 | .dot = { .min = 20000, .max = 400000 }, |
| 261 | .vco = { .min = 1700000, .max = 3500000 }, |
| 262 | .n = { .min = 3, .max = 6 }, |
| 263 | .m = { .min = 2, .max = 256 }, |
| 264 | .m1 = { .min = 0, .max = 0 }, |
| 265 | .m2 = { .min = 0, .max = 254 }, |
| 266 | .p = { .min = 7, .max = 112 }, |
| 267 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 268 | .p2 = { .dot_limit = 112000, |
| 269 | .p2_slow = 14, .p2_fast = 14 }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 270 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 271 | }; |
| 272 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 273 | /* Ironlake / Sandybridge |
| 274 | * |
| 275 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 276 | * the range value for them is (actual_value - 2). |
| 277 | */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 278 | static const intel_limit_t intel_limits_ironlake_dac = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 279 | .dot = { .min = 25000, .max = 350000 }, |
| 280 | .vco = { .min = 1760000, .max = 3510000 }, |
| 281 | .n = { .min = 1, .max = 5 }, |
| 282 | .m = { .min = 79, .max = 127 }, |
| 283 | .m1 = { .min = 12, .max = 22 }, |
| 284 | .m2 = { .min = 5, .max = 9 }, |
| 285 | .p = { .min = 5, .max = 80 }, |
| 286 | .p1 = { .min = 1, .max = 8 }, |
| 287 | .p2 = { .dot_limit = 225000, |
| 288 | .p2_slow = 10, .p2_fast = 5 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 289 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 290 | }; |
| 291 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 292 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 293 | .dot = { .min = 25000, .max = 350000 }, |
| 294 | .vco = { .min = 1760000, .max = 3510000 }, |
| 295 | .n = { .min = 1, .max = 3 }, |
| 296 | .m = { .min = 79, .max = 118 }, |
| 297 | .m1 = { .min = 12, .max = 22 }, |
| 298 | .m2 = { .min = 5, .max = 9 }, |
| 299 | .p = { .min = 28, .max = 112 }, |
| 300 | .p1 = { .min = 2, .max = 8 }, |
| 301 | .p2 = { .dot_limit = 225000, |
| 302 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 303 | .find_pll = intel_g4x_find_best_PLL, |
| 304 | }; |
| 305 | |
| 306 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 307 | .dot = { .min = 25000, .max = 350000 }, |
| 308 | .vco = { .min = 1760000, .max = 3510000 }, |
| 309 | .n = { .min = 1, .max = 3 }, |
| 310 | .m = { .min = 79, .max = 127 }, |
| 311 | .m1 = { .min = 12, .max = 22 }, |
| 312 | .m2 = { .min = 5, .max = 9 }, |
| 313 | .p = { .min = 14, .max = 56 }, |
| 314 | .p1 = { .min = 2, .max = 8 }, |
| 315 | .p2 = { .dot_limit = 225000, |
| 316 | .p2_slow = 7, .p2_fast = 7 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 317 | .find_pll = intel_g4x_find_best_PLL, |
| 318 | }; |
| 319 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 320 | /* LVDS 100mhz refclk limits. */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 321 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 322 | .dot = { .min = 25000, .max = 350000 }, |
| 323 | .vco = { .min = 1760000, .max = 3510000 }, |
| 324 | .n = { .min = 1, .max = 2 }, |
| 325 | .m = { .min = 79, .max = 126 }, |
| 326 | .m1 = { .min = 12, .max = 22 }, |
| 327 | .m2 = { .min = 5, .max = 9 }, |
| 328 | .p = { .min = 28, .max = 112 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 329 | .p1 = { .min = 2, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 330 | .p2 = { .dot_limit = 225000, |
| 331 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 332 | .find_pll = intel_g4x_find_best_PLL, |
| 333 | }; |
| 334 | |
| 335 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 336 | .dot = { .min = 25000, .max = 350000 }, |
| 337 | .vco = { .min = 1760000, .max = 3510000 }, |
| 338 | .n = { .min = 1, .max = 3 }, |
| 339 | .m = { .min = 79, .max = 126 }, |
| 340 | .m1 = { .min = 12, .max = 22 }, |
| 341 | .m2 = { .min = 5, .max = 9 }, |
| 342 | .p = { .min = 14, .max = 42 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 343 | .p1 = { .min = 2, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 344 | .p2 = { .dot_limit = 225000, |
| 345 | .p2_slow = 7, .p2_fast = 7 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 346 | .find_pll = intel_g4x_find_best_PLL, |
| 347 | }; |
| 348 | |
| 349 | static const intel_limit_t intel_limits_ironlake_display_port = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 350 | .dot = { .min = 25000, .max = 350000 }, |
| 351 | .vco = { .min = 1760000, .max = 3510000}, |
| 352 | .n = { .min = 1, .max = 2 }, |
| 353 | .m = { .min = 81, .max = 90 }, |
| 354 | .m1 = { .min = 12, .max = 22 }, |
| 355 | .m2 = { .min = 5, .max = 9 }, |
| 356 | .p = { .min = 10, .max = 20 }, |
| 357 | .p1 = { .min = 1, .max = 2}, |
| 358 | .p2 = { .dot_limit = 0, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 359 | .p2_slow = 10, .p2_fast = 10 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 360 | .find_pll = intel_find_pll_ironlake_dp, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 361 | }; |
| 362 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 363 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
| 364 | int refclk) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 365 | { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 366 | struct drm_device *dev = crtc->dev; |
| 367 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 368 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 369 | |
| 370 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 371 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
| 372 | LVDS_CLKB_POWER_UP) { |
| 373 | /* LVDS dual channel */ |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 374 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 375 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 376 | else |
| 377 | limit = &intel_limits_ironlake_dual_lvds; |
| 378 | } else { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 379 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 380 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 381 | else |
| 382 | limit = &intel_limits_ironlake_single_lvds; |
| 383 | } |
| 384 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 385 | HAS_eDP) |
| 386 | limit = &intel_limits_ironlake_display_port; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 387 | else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 388 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 389 | |
| 390 | return limit; |
| 391 | } |
| 392 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 393 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 394 | { |
| 395 | struct drm_device *dev = crtc->dev; |
| 396 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 397 | const intel_limit_t *limit; |
| 398 | |
| 399 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 400 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 401 | LVDS_CLKB_POWER_UP) |
| 402 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 403 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 404 | else |
| 405 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 406 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 407 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 408 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 409 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 410 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 411 | limit = &intel_limits_g4x_sdvo; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 412 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 413 | limit = &intel_limits_g4x_display_port; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 414 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 415 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 416 | |
| 417 | return limit; |
| 418 | } |
| 419 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 420 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 421 | { |
| 422 | struct drm_device *dev = crtc->dev; |
| 423 | const intel_limit_t *limit; |
| 424 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 425 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 426 | limit = intel_ironlake_limit(crtc, refclk); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 427 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 428 | limit = intel_g4x_limit(crtc); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 429 | } else if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 431 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 432 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 433 | limit = &intel_limits_pineview_sdvo; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 434 | } else if (!IS_GEN2(dev)) { |
| 435 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 436 | limit = &intel_limits_i9xx_lvds; |
| 437 | else |
| 438 | limit = &intel_limits_i9xx_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 439 | } else { |
| 440 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 441 | limit = &intel_limits_i8xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 442 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 443 | limit = &intel_limits_i8xx_dvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 444 | } |
| 445 | return limit; |
| 446 | } |
| 447 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 448 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 449 | static void pineview_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 450 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 451 | clock->m = clock->m2 + 2; |
| 452 | clock->p = clock->p1 * clock->p2; |
| 453 | clock->vco = refclk * clock->m / clock->n; |
| 454 | clock->dot = clock->vco / clock->p; |
| 455 | } |
| 456 | |
| 457 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
| 458 | { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 459 | if (IS_PINEVIEW(dev)) { |
| 460 | pineview_clock(refclk, clock); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 461 | return; |
| 462 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 463 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 464 | clock->p = clock->p1 * clock->p2; |
| 465 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 466 | clock->dot = clock->vco / clock->p; |
| 467 | } |
| 468 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 469 | /** |
| 470 | * Returns whether any output on the specified pipe is of the specified type |
| 471 | */ |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 472 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 473 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 474 | struct drm_device *dev = crtc->dev; |
| 475 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 476 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 477 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 478 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 479 | if (encoder->base.crtc == crtc && encoder->type == type) |
| 480 | return true; |
| 481 | |
| 482 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 483 | } |
| 484 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 485 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 486 | /** |
| 487 | * Returns whether the given set of divisors are valid for a given refclk with |
| 488 | * the given connectors. |
| 489 | */ |
| 490 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 491 | static bool intel_PLL_is_valid(struct drm_device *dev, |
| 492 | const intel_limit_t *limit, |
| 493 | const intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 494 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 495 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 496 | INTELPllInvalid("p1 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 497 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 498 | INTELPllInvalid("p out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 499 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 500 | INTELPllInvalid("m2 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 501 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 502 | INTELPllInvalid("m1 out of range\n"); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 503 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 504 | INTELPllInvalid("m1 <= m2\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 505 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 506 | INTELPllInvalid("m out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 507 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 508 | INTELPllInvalid("n out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 509 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 510 | INTELPllInvalid("vco out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 511 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 512 | * connector, etc., rather than just a single range. |
| 513 | */ |
| 514 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 515 | INTELPllInvalid("dot out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 516 | |
| 517 | return true; |
| 518 | } |
| 519 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 520 | static bool |
| 521 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 522 | int target, int refclk, intel_clock_t *match_clock, |
| 523 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 524 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 525 | { |
| 526 | struct drm_device *dev = crtc->dev; |
| 527 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 528 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 529 | int err = target; |
| 530 | |
Bruno Prémont | bc5e571 | 2009-08-08 13:01:17 +0200 | [diff] [blame] | 531 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Florian Mickler | 832cc28 | 2009-07-13 18:40:32 +0800 | [diff] [blame] | 532 | (I915_READ(LVDS)) != 0) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 533 | /* |
| 534 | * For LVDS, if the panel is on, just rely on its current |
| 535 | * settings for dual-channel. We haven't figured out how to |
| 536 | * reliably set up different single/dual channel state, if we |
| 537 | * even can. |
| 538 | */ |
| 539 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 540 | LVDS_CLKB_POWER_UP) |
| 541 | clock.p2 = limit->p2.p2_fast; |
| 542 | else |
| 543 | clock.p2 = limit->p2.p2_slow; |
| 544 | } else { |
| 545 | if (target < limit->p2.dot_limit) |
| 546 | clock.p2 = limit->p2.p2_slow; |
| 547 | else |
| 548 | clock.p2 = limit->p2.p2_fast; |
| 549 | } |
| 550 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 551 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 552 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 553 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 554 | clock.m1++) { |
| 555 | for (clock.m2 = limit->m2.min; |
| 556 | clock.m2 <= limit->m2.max; clock.m2++) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 557 | /* m1 is always 0 in Pineview */ |
| 558 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 559 | break; |
| 560 | for (clock.n = limit->n.min; |
| 561 | clock.n <= limit->n.max; clock.n++) { |
| 562 | for (clock.p1 = limit->p1.min; |
| 563 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 564 | int this_err; |
| 565 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 566 | intel_clock(dev, refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 567 | if (!intel_PLL_is_valid(dev, limit, |
| 568 | &clock)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 569 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 570 | if (match_clock && |
| 571 | clock.p != match_clock->p) |
| 572 | continue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 573 | |
| 574 | this_err = abs(clock.dot - target); |
| 575 | if (this_err < err) { |
| 576 | *best_clock = clock; |
| 577 | err = this_err; |
| 578 | } |
| 579 | } |
| 580 | } |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | return (err != target); |
| 585 | } |
| 586 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 587 | static bool |
| 588 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 589 | int target, int refclk, intel_clock_t *match_clock, |
| 590 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 591 | { |
| 592 | struct drm_device *dev = crtc->dev; |
| 593 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 594 | intel_clock_t clock; |
| 595 | int max_n; |
| 596 | bool found; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 597 | /* approximately equals target * 0.00585 */ |
| 598 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 599 | found = false; |
| 600 | |
| 601 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 602 | int lvds_reg; |
| 603 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 604 | if (HAS_PCH_SPLIT(dev)) |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 605 | lvds_reg = PCH_LVDS; |
| 606 | else |
| 607 | lvds_reg = LVDS; |
| 608 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 609 | LVDS_CLKB_POWER_UP) |
| 610 | clock.p2 = limit->p2.p2_fast; |
| 611 | else |
| 612 | clock.p2 = limit->p2.p2_slow; |
| 613 | } else { |
| 614 | if (target < limit->p2.dot_limit) |
| 615 | clock.p2 = limit->p2.p2_slow; |
| 616 | else |
| 617 | clock.p2 = limit->p2.p2_fast; |
| 618 | } |
| 619 | |
| 620 | memset(best_clock, 0, sizeof(*best_clock)); |
| 621 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 622 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 623 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 624 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 625 | for (clock.m1 = limit->m1.max; |
| 626 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 627 | for (clock.m2 = limit->m2.max; |
| 628 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 629 | for (clock.p1 = limit->p1.max; |
| 630 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 631 | int this_err; |
| 632 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 633 | intel_clock(dev, refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 634 | if (!intel_PLL_is_valid(dev, limit, |
| 635 | &clock)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 636 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 637 | if (match_clock && |
| 638 | clock.p != match_clock->p) |
| 639 | continue; |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 640 | |
| 641 | this_err = abs(clock.dot - target); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 642 | if (this_err < err_most) { |
| 643 | *best_clock = clock; |
| 644 | err_most = this_err; |
| 645 | max_n = clock.n; |
| 646 | found = true; |
| 647 | } |
| 648 | } |
| 649 | } |
| 650 | } |
| 651 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 652 | return found; |
| 653 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 654 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 655 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 656 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 657 | int target, int refclk, intel_clock_t *match_clock, |
| 658 | intel_clock_t *best_clock) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 659 | { |
| 660 | struct drm_device *dev = crtc->dev; |
| 661 | intel_clock_t clock; |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 662 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 663 | if (target < 200000) { |
| 664 | clock.n = 1; |
| 665 | clock.p1 = 2; |
| 666 | clock.p2 = 10; |
| 667 | clock.m1 = 12; |
| 668 | clock.m2 = 9; |
| 669 | } else { |
| 670 | clock.n = 2; |
| 671 | clock.p1 = 1; |
| 672 | clock.p2 = 10; |
| 673 | clock.m1 = 14; |
| 674 | clock.m2 = 8; |
| 675 | } |
| 676 | intel_clock(dev, refclk, &clock); |
| 677 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 678 | return true; |
| 679 | } |
| 680 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 681 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
| 682 | static bool |
| 683 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 684 | int target, int refclk, intel_clock_t *match_clock, |
| 685 | intel_clock_t *best_clock) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 686 | { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 687 | intel_clock_t clock; |
| 688 | if (target < 200000) { |
| 689 | clock.p1 = 2; |
| 690 | clock.p2 = 10; |
| 691 | clock.n = 2; |
| 692 | clock.m1 = 23; |
| 693 | clock.m2 = 8; |
| 694 | } else { |
| 695 | clock.p1 = 1; |
| 696 | clock.p2 = 10; |
| 697 | clock.n = 1; |
| 698 | clock.m1 = 14; |
| 699 | clock.m2 = 2; |
| 700 | } |
| 701 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
| 702 | clock.p = (clock.p1 * clock.p2); |
| 703 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
| 704 | clock.vco = 0; |
| 705 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 706 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 707 | } |
| 708 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 709 | /** |
| 710 | * intel_wait_for_vblank - wait for vblank on a given pipe |
| 711 | * @dev: drm device |
| 712 | * @pipe: pipe to wait for |
| 713 | * |
| 714 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
| 715 | * mode setting code. |
| 716 | */ |
| 717 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 718 | { |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 719 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 720 | int pipestat_reg = PIPESTAT(pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 721 | |
Chris Wilson | 300387c | 2010-09-05 20:25:43 +0100 | [diff] [blame] | 722 | /* Clear existing vblank status. Note this will clear any other |
| 723 | * sticky status fields as well. |
| 724 | * |
| 725 | * This races with i915_driver_irq_handler() with the result |
| 726 | * that either function could miss a vblank event. Here it is not |
| 727 | * fatal, as we will either wait upon the next vblank interrupt or |
| 728 | * timeout. Generally speaking intel_wait_for_vblank() is only |
| 729 | * called during modeset at which time the GPU should be idle and |
| 730 | * should *not* be performing page flips and thus not waiting on |
| 731 | * vblanks... |
| 732 | * Currently, the result of us stealing a vblank from the irq |
| 733 | * handler is that a single frame will be skipped during swapbuffers. |
| 734 | */ |
| 735 | I915_WRITE(pipestat_reg, |
| 736 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
| 737 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 738 | /* Wait for vblank interrupt bit to set */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 739 | if (wait_for(I915_READ(pipestat_reg) & |
| 740 | PIPE_VBLANK_INTERRUPT_STATUS, |
| 741 | 50)) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 742 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
| 743 | } |
| 744 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 745 | /* |
| 746 | * intel_wait_for_pipe_off - wait for pipe to turn off |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 747 | * @dev: drm device |
| 748 | * @pipe: pipe to wait for |
| 749 | * |
| 750 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 751 | * spinning on the vblank interrupt status bit, since we won't actually |
| 752 | * see an interrupt when the pipe is disabled. |
| 753 | * |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 754 | * On Gen4 and above: |
| 755 | * wait for the pipe register state bit to turn off |
| 756 | * |
| 757 | * Otherwise: |
| 758 | * wait for the display line value to settle (it usually |
| 759 | * ends up stopping at the start of the next frame). |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 760 | * |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 761 | */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 762 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 763 | { |
| 764 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 765 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 766 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 767 | int reg = PIPECONF(pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 768 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 769 | /* Wait for the Pipe State to go off */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 770 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
| 771 | 100)) |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 772 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
| 773 | } else { |
| 774 | u32 last_line; |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 775 | int reg = PIPEDSL(pipe); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 776 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
| 777 | |
| 778 | /* Wait for the display line to settle */ |
| 779 | do { |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 780 | last_line = I915_READ(reg) & DSL_LINEMASK; |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 781 | mdelay(5); |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 782 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 783 | time_after(timeout, jiffies)); |
| 784 | if (time_after(jiffies, timeout)) |
| 785 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
| 786 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 787 | } |
| 788 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 789 | static const char *state_string(bool enabled) |
| 790 | { |
| 791 | return enabled ? "on" : "off"; |
| 792 | } |
| 793 | |
| 794 | /* Only for pre-ILK configs */ |
| 795 | static void assert_pll(struct drm_i915_private *dev_priv, |
| 796 | enum pipe pipe, bool state) |
| 797 | { |
| 798 | int reg; |
| 799 | u32 val; |
| 800 | bool cur_state; |
| 801 | |
| 802 | reg = DPLL(pipe); |
| 803 | val = I915_READ(reg); |
| 804 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 805 | WARN(cur_state != state, |
| 806 | "PLL state assertion failure (expected %s, current %s)\n", |
| 807 | state_string(state), state_string(cur_state)); |
| 808 | } |
| 809 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 810 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 811 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 812 | /* For ILK+ */ |
| 813 | static void assert_pch_pll(struct drm_i915_private *dev_priv, |
| 814 | enum pipe pipe, bool state) |
| 815 | { |
| 816 | int reg; |
| 817 | u32 val; |
| 818 | bool cur_state; |
| 819 | |
Jesse Barnes | d3ccbe8 | 2011-10-12 09:27:42 -0700 | [diff] [blame] | 820 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 821 | u32 pch_dpll; |
| 822 | |
| 823 | pch_dpll = I915_READ(PCH_DPLL_SEL); |
| 824 | |
| 825 | /* Make sure the selected PLL is enabled to the transcoder */ |
| 826 | WARN(!((pch_dpll >> (4 * pipe)) & 8), |
| 827 | "transcoder %d PLL not enabled\n", pipe); |
| 828 | |
| 829 | /* Convert the transcoder pipe number to a pll pipe number */ |
| 830 | pipe = (pch_dpll >> (4 * pipe)) & 1; |
| 831 | } |
| 832 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 833 | reg = PCH_DPLL(pipe); |
| 834 | val = I915_READ(reg); |
| 835 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 836 | WARN(cur_state != state, |
| 837 | "PCH PLL state assertion failure (expected %s, current %s)\n", |
| 838 | state_string(state), state_string(cur_state)); |
| 839 | } |
| 840 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) |
| 841 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) |
| 842 | |
| 843 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 844 | enum pipe pipe, bool state) |
| 845 | { |
| 846 | int reg; |
| 847 | u32 val; |
| 848 | bool cur_state; |
| 849 | |
| 850 | reg = FDI_TX_CTL(pipe); |
| 851 | val = I915_READ(reg); |
| 852 | cur_state = !!(val & FDI_TX_ENABLE); |
| 853 | WARN(cur_state != state, |
| 854 | "FDI TX state assertion failure (expected %s, current %s)\n", |
| 855 | state_string(state), state_string(cur_state)); |
| 856 | } |
| 857 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 858 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 859 | |
| 860 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 861 | enum pipe pipe, bool state) |
| 862 | { |
| 863 | int reg; |
| 864 | u32 val; |
| 865 | bool cur_state; |
| 866 | |
| 867 | reg = FDI_RX_CTL(pipe); |
| 868 | val = I915_READ(reg); |
| 869 | cur_state = !!(val & FDI_RX_ENABLE); |
| 870 | WARN(cur_state != state, |
| 871 | "FDI RX state assertion failure (expected %s, current %s)\n", |
| 872 | state_string(state), state_string(cur_state)); |
| 873 | } |
| 874 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 875 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 876 | |
| 877 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 878 | enum pipe pipe) |
| 879 | { |
| 880 | int reg; |
| 881 | u32 val; |
| 882 | |
| 883 | /* ILK FDI PLL is always enabled */ |
| 884 | if (dev_priv->info->gen == 5) |
| 885 | return; |
| 886 | |
| 887 | reg = FDI_TX_CTL(pipe); |
| 888 | val = I915_READ(reg); |
| 889 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
| 890 | } |
| 891 | |
| 892 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, |
| 893 | enum pipe pipe) |
| 894 | { |
| 895 | int reg; |
| 896 | u32 val; |
| 897 | |
| 898 | reg = FDI_RX_CTL(pipe); |
| 899 | val = I915_READ(reg); |
| 900 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); |
| 901 | } |
| 902 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 903 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 904 | enum pipe pipe) |
| 905 | { |
| 906 | int pp_reg, lvds_reg; |
| 907 | u32 val; |
| 908 | enum pipe panel_pipe = PIPE_A; |
Thomas Jarosch | 0de3b48 | 2011-08-25 15:37:45 +0200 | [diff] [blame] | 909 | bool locked = true; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 910 | |
| 911 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 912 | pp_reg = PCH_PP_CONTROL; |
| 913 | lvds_reg = PCH_LVDS; |
| 914 | } else { |
| 915 | pp_reg = PP_CONTROL; |
| 916 | lvds_reg = LVDS; |
| 917 | } |
| 918 | |
| 919 | val = I915_READ(pp_reg); |
| 920 | if (!(val & PANEL_POWER_ON) || |
| 921 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
| 922 | locked = false; |
| 923 | |
| 924 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
| 925 | panel_pipe = PIPE_B; |
| 926 | |
| 927 | WARN(panel_pipe == pipe && locked, |
| 928 | "panel assertion failure, pipe %c regs locked\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 929 | pipe_name(pipe)); |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 930 | } |
| 931 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 932 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 933 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 934 | { |
| 935 | int reg; |
| 936 | u32 val; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 937 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 938 | |
Daniel Vetter | 8e63678 | 2012-01-22 01:36:48 +0100 | [diff] [blame] | 939 | /* if we need the pipe A quirk it must be always on */ |
| 940 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
| 941 | state = true; |
| 942 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 943 | reg = PIPECONF(pipe); |
| 944 | val = I915_READ(reg); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 945 | cur_state = !!(val & PIPECONF_ENABLE); |
| 946 | WARN(cur_state != state, |
| 947 | "pipe %c assertion failure (expected %s, current %s)\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 948 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 949 | } |
| 950 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 951 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 952 | enum plane plane, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 953 | { |
| 954 | int reg; |
| 955 | u32 val; |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 956 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 957 | |
| 958 | reg = DSPCNTR(plane); |
| 959 | val = I915_READ(reg); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 960 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
| 961 | WARN(cur_state != state, |
| 962 | "plane %c assertion failure (expected %s, current %s)\n", |
| 963 | plane_name(plane), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 964 | } |
| 965 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 966 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 967 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 968 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 969 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 970 | enum pipe pipe) |
| 971 | { |
| 972 | int reg, i; |
| 973 | u32 val; |
| 974 | int cur_pipe; |
| 975 | |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 976 | /* Planes are fixed to pipes on ILK+ */ |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 977 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 978 | reg = DSPCNTR(pipe); |
| 979 | val = I915_READ(reg); |
| 980 | WARN((val & DISPLAY_PLANE_ENABLE), |
| 981 | "plane %c assertion failure, should be disabled but not\n", |
| 982 | plane_name(pipe)); |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 983 | return; |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 984 | } |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 985 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 986 | /* Need to check both planes against the pipe */ |
| 987 | for (i = 0; i < 2; i++) { |
| 988 | reg = DSPCNTR(i); |
| 989 | val = I915_READ(reg); |
| 990 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
| 991 | DISPPLANE_SEL_PIPE_SHIFT; |
| 992 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 993 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 994 | plane_name(i), pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 995 | } |
| 996 | } |
| 997 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 998 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
| 999 | { |
| 1000 | u32 val; |
| 1001 | bool enabled; |
| 1002 | |
| 1003 | val = I915_READ(PCH_DREF_CONTROL); |
| 1004 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 1005 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 1006 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 1007 | } |
| 1008 | |
| 1009 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1010 | enum pipe pipe) |
| 1011 | { |
| 1012 | int reg; |
| 1013 | u32 val; |
| 1014 | bool enabled; |
| 1015 | |
| 1016 | reg = TRANSCONF(pipe); |
| 1017 | val = I915_READ(reg); |
| 1018 | enabled = !!(val & TRANS_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1019 | WARN(enabled, |
| 1020 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1021 | pipe_name(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1022 | } |
| 1023 | |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1024 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1025 | enum pipe pipe, u32 port_sel, u32 val) |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1026 | { |
| 1027 | if ((val & DP_PORT_EN) == 0) |
| 1028 | return false; |
| 1029 | |
| 1030 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1031 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
| 1032 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
| 1033 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1034 | return false; |
| 1035 | } else { |
| 1036 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1037 | return false; |
| 1038 | } |
| 1039 | return true; |
| 1040 | } |
| 1041 | |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1042 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1043 | enum pipe pipe, u32 val) |
| 1044 | { |
| 1045 | if ((val & PORT_ENABLE) == 0) |
| 1046 | return false; |
| 1047 | |
| 1048 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1049 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1050 | return false; |
| 1051 | } else { |
| 1052 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) |
| 1053 | return false; |
| 1054 | } |
| 1055 | return true; |
| 1056 | } |
| 1057 | |
| 1058 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1059 | enum pipe pipe, u32 val) |
| 1060 | { |
| 1061 | if ((val & LVDS_PORT_EN) == 0) |
| 1062 | return false; |
| 1063 | |
| 1064 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1065 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1066 | return false; |
| 1067 | } else { |
| 1068 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1069 | return false; |
| 1070 | } |
| 1071 | return true; |
| 1072 | } |
| 1073 | |
| 1074 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1075 | enum pipe pipe, u32 val) |
| 1076 | { |
| 1077 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1078 | return false; |
| 1079 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1080 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1081 | return false; |
| 1082 | } else { |
| 1083 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1084 | return false; |
| 1085 | } |
| 1086 | return true; |
| 1087 | } |
| 1088 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1089 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1090 | enum pipe pipe, int reg, u32 port_sel) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1091 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1092 | u32 val = I915_READ(reg); |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1093 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1094 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1095 | reg, pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1096 | } |
| 1097 | |
| 1098 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
| 1099 | enum pipe pipe, int reg) |
| 1100 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1101 | u32 val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1102 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
Adam Jackson | 23c99e7 | 2011-10-07 14:38:43 -0400 | [diff] [blame] | 1103 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1104 | reg, pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1105 | } |
| 1106 | |
| 1107 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1108 | enum pipe pipe) |
| 1109 | { |
| 1110 | int reg; |
| 1111 | u32 val; |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1112 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1113 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1114 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1115 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1116 | |
| 1117 | reg = PCH_ADPA; |
| 1118 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1119 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1120 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1121 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1122 | |
| 1123 | reg = PCH_LVDS; |
| 1124 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1125 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1126 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1127 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1128 | |
| 1129 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); |
| 1130 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); |
| 1131 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); |
| 1132 | } |
| 1133 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1134 | /** |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1135 | * intel_enable_pll - enable a PLL |
| 1136 | * @dev_priv: i915 private structure |
| 1137 | * @pipe: pipe PLL to enable |
| 1138 | * |
| 1139 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to |
| 1140 | * make sure the PLL reg is writable first though, since the panel write |
| 1141 | * protect mechanism may be enabled. |
| 1142 | * |
| 1143 | * Note! This is for pre-ILK only. |
| 1144 | */ |
| 1145 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1146 | { |
| 1147 | int reg; |
| 1148 | u32 val; |
| 1149 | |
| 1150 | /* No really, not for ILK+ */ |
| 1151 | BUG_ON(dev_priv->info->gen >= 5); |
| 1152 | |
| 1153 | /* PLL is protected by panel, make sure we can write it */ |
| 1154 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
| 1155 | assert_panel_unlocked(dev_priv, pipe); |
| 1156 | |
| 1157 | reg = DPLL(pipe); |
| 1158 | val = I915_READ(reg); |
| 1159 | val |= DPLL_VCO_ENABLE; |
| 1160 | |
| 1161 | /* We do this three times for luck */ |
| 1162 | I915_WRITE(reg, val); |
| 1163 | POSTING_READ(reg); |
| 1164 | udelay(150); /* wait for warmup */ |
| 1165 | I915_WRITE(reg, val); |
| 1166 | POSTING_READ(reg); |
| 1167 | udelay(150); /* wait for warmup */ |
| 1168 | I915_WRITE(reg, val); |
| 1169 | POSTING_READ(reg); |
| 1170 | udelay(150); /* wait for warmup */ |
| 1171 | } |
| 1172 | |
| 1173 | /** |
| 1174 | * intel_disable_pll - disable a PLL |
| 1175 | * @dev_priv: i915 private structure |
| 1176 | * @pipe: pipe PLL to disable |
| 1177 | * |
| 1178 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1179 | * |
| 1180 | * Note! This is for pre-ILK only. |
| 1181 | */ |
| 1182 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1183 | { |
| 1184 | int reg; |
| 1185 | u32 val; |
| 1186 | |
| 1187 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1188 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1189 | return; |
| 1190 | |
| 1191 | /* Make sure the pipe isn't still relying on us */ |
| 1192 | assert_pipe_disabled(dev_priv, pipe); |
| 1193 | |
| 1194 | reg = DPLL(pipe); |
| 1195 | val = I915_READ(reg); |
| 1196 | val &= ~DPLL_VCO_ENABLE; |
| 1197 | I915_WRITE(reg, val); |
| 1198 | POSTING_READ(reg); |
| 1199 | } |
| 1200 | |
| 1201 | /** |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1202 | * intel_enable_pch_pll - enable PCH PLL |
| 1203 | * @dev_priv: i915 private structure |
| 1204 | * @pipe: pipe PLL to enable |
| 1205 | * |
| 1206 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 1207 | * drives the transcoder clock. |
| 1208 | */ |
| 1209 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, |
| 1210 | enum pipe pipe) |
| 1211 | { |
| 1212 | int reg; |
| 1213 | u32 val; |
| 1214 | |
Jesse Barnes | 4c609cb | 2011-09-02 12:52:11 -0700 | [diff] [blame] | 1215 | if (pipe > 1) |
| 1216 | return; |
| 1217 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1218 | /* PCH only available on ILK+ */ |
| 1219 | BUG_ON(dev_priv->info->gen < 5); |
| 1220 | |
| 1221 | /* PCH refclock must be enabled first */ |
| 1222 | assert_pch_refclk_enabled(dev_priv); |
| 1223 | |
| 1224 | reg = PCH_DPLL(pipe); |
| 1225 | val = I915_READ(reg); |
| 1226 | val |= DPLL_VCO_ENABLE; |
| 1227 | I915_WRITE(reg, val); |
| 1228 | POSTING_READ(reg); |
| 1229 | udelay(200); |
| 1230 | } |
| 1231 | |
| 1232 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, |
| 1233 | enum pipe pipe) |
| 1234 | { |
| 1235 | int reg; |
Jesse Barnes | 7a41986 | 2011-11-15 10:28:53 -0800 | [diff] [blame] | 1236 | u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, |
| 1237 | pll_sel = TRANSC_DPLL_ENABLE; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1238 | |
Jesse Barnes | 4c609cb | 2011-09-02 12:52:11 -0700 | [diff] [blame] | 1239 | if (pipe > 1) |
| 1240 | return; |
| 1241 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1242 | /* PCH only available on ILK+ */ |
| 1243 | BUG_ON(dev_priv->info->gen < 5); |
| 1244 | |
| 1245 | /* Make sure transcoder isn't still depending on us */ |
| 1246 | assert_transcoder_disabled(dev_priv, pipe); |
| 1247 | |
Jesse Barnes | 7a41986 | 2011-11-15 10:28:53 -0800 | [diff] [blame] | 1248 | if (pipe == 0) |
| 1249 | pll_sel |= TRANSC_DPLLA_SEL; |
| 1250 | else if (pipe == 1) |
| 1251 | pll_sel |= TRANSC_DPLLB_SEL; |
| 1252 | |
| 1253 | |
| 1254 | if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) |
| 1255 | return; |
| 1256 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1257 | reg = PCH_DPLL(pipe); |
| 1258 | val = I915_READ(reg); |
| 1259 | val &= ~DPLL_VCO_ENABLE; |
| 1260 | I915_WRITE(reg, val); |
| 1261 | POSTING_READ(reg); |
| 1262 | udelay(200); |
| 1263 | } |
| 1264 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1265 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
| 1266 | enum pipe pipe) |
| 1267 | { |
| 1268 | int reg; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1269 | u32 val, pipeconf_val; |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1270 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1271 | |
| 1272 | /* PCH only available on ILK+ */ |
| 1273 | BUG_ON(dev_priv->info->gen < 5); |
| 1274 | |
| 1275 | /* Make sure PCH DPLL is enabled */ |
| 1276 | assert_pch_pll_enabled(dev_priv, pipe); |
| 1277 | |
| 1278 | /* FDI must be feeding us bits for PCH ports */ |
| 1279 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1280 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1281 | |
| 1282 | reg = TRANSCONF(pipe); |
| 1283 | val = I915_READ(reg); |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1284 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1285 | |
| 1286 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 1287 | /* |
| 1288 | * make the BPC in transcoder be consistent with |
| 1289 | * that in pipeconf reg. |
| 1290 | */ |
| 1291 | val &= ~PIPE_BPC_MASK; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1292 | val |= pipeconf_val & PIPE_BPC_MASK; |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1293 | } |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1294 | |
| 1295 | val &= ~TRANS_INTERLACE_MASK; |
| 1296 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1297 | if (HAS_PCH_IBX(dev_priv->dev) && |
| 1298 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
| 1299 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 1300 | else |
| 1301 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1302 | else |
| 1303 | val |= TRANS_PROGRESSIVE; |
| 1304 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1305 | I915_WRITE(reg, val | TRANS_ENABLE); |
| 1306 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
| 1307 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
| 1308 | } |
| 1309 | |
| 1310 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, |
| 1311 | enum pipe pipe) |
| 1312 | { |
| 1313 | int reg; |
| 1314 | u32 val; |
| 1315 | |
| 1316 | /* FDI relies on the transcoder */ |
| 1317 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 1318 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 1319 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1320 | /* Ports must be off as well */ |
| 1321 | assert_pch_ports_disabled(dev_priv, pipe); |
| 1322 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1323 | reg = TRANSCONF(pipe); |
| 1324 | val = I915_READ(reg); |
| 1325 | val &= ~TRANS_ENABLE; |
| 1326 | I915_WRITE(reg, val); |
| 1327 | /* wait for PCH transcoder off, transcoder state */ |
| 1328 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
Jesse Barnes | 4c9c18c | 2011-10-13 09:46:32 -0700 | [diff] [blame] | 1329 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1330 | } |
| 1331 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1332 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1333 | * intel_enable_pipe - enable a pipe, asserting requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1334 | * @dev_priv: i915 private structure |
| 1335 | * @pipe: pipe to enable |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1336 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1337 | * |
| 1338 | * Enable @pipe, making sure that various hardware specific requirements |
| 1339 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
| 1340 | * |
| 1341 | * @pipe should be %PIPE_A or %PIPE_B. |
| 1342 | * |
| 1343 | * Will wait until the pipe is actually running (i.e. first vblank) before |
| 1344 | * returning. |
| 1345 | */ |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1346 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 1347 | bool pch_port) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1348 | { |
| 1349 | int reg; |
| 1350 | u32 val; |
| 1351 | |
| 1352 | /* |
| 1353 | * A pipe without a PLL won't actually be able to drive bits from |
| 1354 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 1355 | * need the check. |
| 1356 | */ |
| 1357 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
| 1358 | assert_pll_enabled(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1359 | else { |
| 1360 | if (pch_port) { |
| 1361 | /* if driving the PCH, we need FDI enabled */ |
| 1362 | assert_fdi_rx_pll_enabled(dev_priv, pipe); |
| 1363 | assert_fdi_tx_pll_enabled(dev_priv, pipe); |
| 1364 | } |
| 1365 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 1366 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1367 | |
| 1368 | reg = PIPECONF(pipe); |
| 1369 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1370 | if (val & PIPECONF_ENABLE) |
| 1371 | return; |
| 1372 | |
| 1373 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1374 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1375 | } |
| 1376 | |
| 1377 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1378 | * intel_disable_pipe - disable a pipe, asserting requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1379 | * @dev_priv: i915 private structure |
| 1380 | * @pipe: pipe to disable |
| 1381 | * |
| 1382 | * Disable @pipe, making sure that various hardware specific requirements |
| 1383 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
| 1384 | * |
| 1385 | * @pipe should be %PIPE_A or %PIPE_B. |
| 1386 | * |
| 1387 | * Will wait until the pipe has shut down before returning. |
| 1388 | */ |
| 1389 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
| 1390 | enum pipe pipe) |
| 1391 | { |
| 1392 | int reg; |
| 1393 | u32 val; |
| 1394 | |
| 1395 | /* |
| 1396 | * Make sure planes won't keep trying to pump pixels to us, |
| 1397 | * or we might hang the display. |
| 1398 | */ |
| 1399 | assert_planes_disabled(dev_priv, pipe); |
| 1400 | |
| 1401 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1402 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1403 | return; |
| 1404 | |
| 1405 | reg = PIPECONF(pipe); |
| 1406 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1407 | if ((val & PIPECONF_ENABLE) == 0) |
| 1408 | return; |
| 1409 | |
| 1410 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1411 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
| 1412 | } |
| 1413 | |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1414 | /* |
| 1415 | * Plane regs are double buffered, going from enabled->disabled needs a |
| 1416 | * trigger in order to latch. The display address reg provides this. |
| 1417 | */ |
| 1418 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
| 1419 | enum plane plane) |
| 1420 | { |
| 1421 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
| 1422 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
| 1423 | } |
| 1424 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1425 | /** |
| 1426 | * intel_enable_plane - enable a display plane on a given pipe |
| 1427 | * @dev_priv: i915 private structure |
| 1428 | * @plane: plane to enable |
| 1429 | * @pipe: pipe being fed |
| 1430 | * |
| 1431 | * Enable @plane on @pipe, making sure that @pipe is running first. |
| 1432 | */ |
| 1433 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
| 1434 | enum plane plane, enum pipe pipe) |
| 1435 | { |
| 1436 | int reg; |
| 1437 | u32 val; |
| 1438 | |
| 1439 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
| 1440 | assert_pipe_enabled(dev_priv, pipe); |
| 1441 | |
| 1442 | reg = DSPCNTR(plane); |
| 1443 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1444 | if (val & DISPLAY_PLANE_ENABLE) |
| 1445 | return; |
| 1446 | |
| 1447 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1448 | intel_flush_display_plane(dev_priv, plane); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1449 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1450 | } |
| 1451 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1452 | /** |
| 1453 | * intel_disable_plane - disable a display plane |
| 1454 | * @dev_priv: i915 private structure |
| 1455 | * @plane: plane to disable |
| 1456 | * @pipe: pipe consuming the data |
| 1457 | * |
| 1458 | * Disable @plane; should be an independent operation. |
| 1459 | */ |
| 1460 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
| 1461 | enum plane plane, enum pipe pipe) |
| 1462 | { |
| 1463 | int reg; |
| 1464 | u32 val; |
| 1465 | |
| 1466 | reg = DSPCNTR(plane); |
| 1467 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1468 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
| 1469 | return; |
| 1470 | |
| 1471 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1472 | intel_flush_display_plane(dev_priv, plane); |
| 1473 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1474 | } |
| 1475 | |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1476 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1477 | enum pipe pipe, int reg, u32 port_sel) |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1478 | { |
| 1479 | u32 val = I915_READ(reg); |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1480 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1481 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1482 | I915_WRITE(reg, val & ~DP_PORT_EN); |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1483 | } |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1484 | } |
| 1485 | |
| 1486 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, |
| 1487 | enum pipe pipe, int reg) |
| 1488 | { |
| 1489 | u32 val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1490 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1491 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
| 1492 | reg, pipe); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1493 | I915_WRITE(reg, val & ~PORT_ENABLE); |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1494 | } |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1495 | } |
| 1496 | |
| 1497 | /* Disable any ports connected to this transcoder */ |
| 1498 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, |
| 1499 | enum pipe pipe) |
| 1500 | { |
| 1501 | u32 reg, val; |
| 1502 | |
| 1503 | val = I915_READ(PCH_PP_CONTROL); |
| 1504 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); |
| 1505 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1506 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1507 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1508 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1509 | |
| 1510 | reg = PCH_ADPA; |
| 1511 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1512 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1513 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
| 1514 | |
| 1515 | reg = PCH_LVDS; |
| 1516 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1517 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
| 1518 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1519 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
| 1520 | POSTING_READ(reg); |
| 1521 | udelay(100); |
| 1522 | } |
| 1523 | |
| 1524 | disable_pch_hdmi(dev_priv, pipe, HDMIB); |
| 1525 | disable_pch_hdmi(dev_priv, pipe, HDMIC); |
| 1526 | disable_pch_hdmi(dev_priv, pipe, HDMID); |
| 1527 | } |
| 1528 | |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 1529 | static void i8xx_disable_fbc(struct drm_device *dev) |
| 1530 | { |
| 1531 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1532 | u32 fbc_ctl; |
| 1533 | |
| 1534 | /* Disable compression */ |
| 1535 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 1536 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 1537 | return; |
| 1538 | |
| 1539 | fbc_ctl &= ~FBC_CTL_EN; |
| 1540 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1541 | |
| 1542 | /* Wait for compressing bit to clear */ |
| 1543 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
| 1544 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 1545 | return; |
| 1546 | } |
| 1547 | |
| 1548 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 1549 | } |
| 1550 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1551 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1552 | { |
| 1553 | struct drm_device *dev = crtc->dev; |
| 1554 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1555 | struct drm_framebuffer *fb = crtc->fb; |
| 1556 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1557 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1559 | int cfb_pitch; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1560 | int plane, i; |
| 1561 | u32 fbc_ctl, fbc_ctl2; |
| 1562 | |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1563 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1564 | if (fb->pitches[0] < cfb_pitch) |
| 1565 | cfb_pitch = fb->pitches[0]; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1566 | |
| 1567 | /* FBC_CTL wants 64B units */ |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1568 | cfb_pitch = (cfb_pitch / 64) - 1; |
| 1569 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1570 | |
| 1571 | /* Clear old tags */ |
| 1572 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 1573 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 1574 | |
| 1575 | /* Set it up... */ |
Chris Wilson | de56851 | 2011-07-08 12:22:39 +0100 | [diff] [blame] | 1576 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
| 1577 | fbc_ctl2 |= plane; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1578 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 1579 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 1580 | |
| 1581 | /* enable it... */ |
| 1582 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
Jesse Barnes | ee25df2 | 2010-02-06 10:41:53 -0800 | [diff] [blame] | 1583 | if (IS_I945GM(dev)) |
Priit Laes | 4967790 | 2010-03-02 11:37:00 +0200 | [diff] [blame] | 1584 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1585 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1586 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1587 | fbc_ctl |= obj->fence_reg; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1588 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1589 | |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1590 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
| 1591 | cfb_pitch, crtc->y, intel_crtc->plane); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1592 | } |
| 1593 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1594 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1595 | { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1596 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1597 | |
| 1598 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 1599 | } |
| 1600 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1601 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1602 | { |
| 1603 | struct drm_device *dev = crtc->dev; |
| 1604 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1605 | struct drm_framebuffer *fb = crtc->fb; |
| 1606 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1607 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1608 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1609 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1610 | unsigned long stall_watermark = 200; |
| 1611 | u32 dpfc_ctl; |
| 1612 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1613 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1614 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
Chris Wilson | de56851 | 2011-07-08 12:22:39 +0100 | [diff] [blame] | 1615 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1616 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1617 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1618 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1619 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1620 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 1621 | |
| 1622 | /* enable it... */ |
| 1623 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
| 1624 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1625 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1626 | } |
| 1627 | |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 1628 | static void g4x_disable_fbc(struct drm_device *dev) |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1629 | { |
| 1630 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1631 | u32 dpfc_ctl; |
| 1632 | |
| 1633 | /* Disable compression */ |
| 1634 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1635 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 1636 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1637 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1638 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1639 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 1640 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1641 | } |
| 1642 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1643 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1644 | { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1645 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1646 | |
| 1647 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 1648 | } |
| 1649 | |
Jesse Barnes | 4efe070 | 2011-01-18 11:25:41 -0800 | [diff] [blame] | 1650 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
| 1651 | { |
| 1652 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1653 | u32 blt_ecoskpd; |
| 1654 | |
| 1655 | /* Make sure blitter notifies FBC of writes */ |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 1656 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 4efe070 | 2011-01-18 11:25:41 -0800 | [diff] [blame] | 1657 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
| 1658 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
| 1659 | GEN6_BLITTER_LOCK_SHIFT; |
| 1660 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 1661 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
| 1662 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 1663 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
| 1664 | GEN6_BLITTER_LOCK_SHIFT); |
| 1665 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 1666 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 1667 | gen6_gt_force_wake_put(dev_priv); |
Jesse Barnes | 4efe070 | 2011-01-18 11:25:41 -0800 | [diff] [blame] | 1668 | } |
| 1669 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1670 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1671 | { |
| 1672 | struct drm_device *dev = crtc->dev; |
| 1673 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1674 | struct drm_framebuffer *fb = crtc->fb; |
| 1675 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1676 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1678 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1679 | unsigned long stall_watermark = 200; |
| 1680 | u32 dpfc_ctl; |
| 1681 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1682 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1683 | dpfc_ctl &= DPFC_RESERVED; |
| 1684 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
Chris Wilson | 9ce9d06 | 2011-07-08 12:22:40 +0100 | [diff] [blame] | 1685 | /* Set persistent mode for front-buffer rendering, ala X. */ |
| 1686 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1687 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
Chris Wilson | de56851 | 2011-07-08 12:22:39 +0100 | [diff] [blame] | 1688 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1689 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1690 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1691 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1692 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1693 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1694 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1695 | /* enable it... */ |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1696 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1697 | |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 1698 | if (IS_GEN6(dev)) { |
| 1699 | I915_WRITE(SNB_DPFC_CTL_SA, |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1700 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 1701 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
Jesse Barnes | 4efe070 | 2011-01-18 11:25:41 -0800 | [diff] [blame] | 1702 | sandybridge_blit_fbc_update(dev); |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 1703 | } |
| 1704 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1705 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
| 1706 | } |
| 1707 | |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 1708 | static void ironlake_disable_fbc(struct drm_device *dev) |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1709 | { |
| 1710 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1711 | u32 dpfc_ctl; |
| 1712 | |
| 1713 | /* Disable compression */ |
| 1714 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1715 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 1716 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1717 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1718 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1719 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 1720 | } |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1721 | } |
| 1722 | |
| 1723 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
| 1724 | { |
| 1725 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1726 | |
| 1727 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 1728 | } |
| 1729 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1730 | bool intel_fbc_enabled(struct drm_device *dev) |
| 1731 | { |
| 1732 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1733 | |
| 1734 | if (!dev_priv->display.fbc_enabled) |
| 1735 | return false; |
| 1736 | |
| 1737 | return dev_priv->display.fbc_enabled(dev); |
| 1738 | } |
| 1739 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1740 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 1741 | { |
| 1742 | struct intel_fbc_work *work = |
| 1743 | container_of(to_delayed_work(__work), |
| 1744 | struct intel_fbc_work, work); |
| 1745 | struct drm_device *dev = work->crtc->dev; |
| 1746 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1747 | |
| 1748 | mutex_lock(&dev->struct_mutex); |
| 1749 | if (work == dev_priv->fbc_work) { |
| 1750 | /* Double check that we haven't switched fb without cancelling |
| 1751 | * the prior work. |
| 1752 | */ |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1753 | if (work->crtc->fb == work->fb) { |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1754 | dev_priv->display.enable_fbc(work->crtc, |
| 1755 | work->interval); |
| 1756 | |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1757 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
| 1758 | dev_priv->cfb_fb = work->crtc->fb->base.id; |
| 1759 | dev_priv->cfb_y = work->crtc->y; |
| 1760 | } |
| 1761 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1762 | dev_priv->fbc_work = NULL; |
| 1763 | } |
| 1764 | mutex_unlock(&dev->struct_mutex); |
| 1765 | |
| 1766 | kfree(work); |
| 1767 | } |
| 1768 | |
| 1769 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
| 1770 | { |
| 1771 | if (dev_priv->fbc_work == NULL) |
| 1772 | return; |
| 1773 | |
| 1774 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
| 1775 | |
| 1776 | /* Synchronisation is provided by struct_mutex and checking of |
| 1777 | * dev_priv->fbc_work, so we can perform the cancellation |
| 1778 | * entirely asynchronously. |
| 1779 | */ |
| 1780 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) |
| 1781 | /* tasklet was killed before being run, clean up */ |
| 1782 | kfree(dev_priv->fbc_work); |
| 1783 | |
| 1784 | /* Mark the work as no longer wanted so that if it does |
| 1785 | * wake-up (because the work was already running and waiting |
| 1786 | * for our mutex), it will discover that is no longer |
| 1787 | * necessary to run. |
| 1788 | */ |
| 1789 | dev_priv->fbc_work = NULL; |
| 1790 | } |
| 1791 | |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 1792 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1793 | { |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1794 | struct intel_fbc_work *work; |
| 1795 | struct drm_device *dev = crtc->dev; |
| 1796 | struct drm_i915_private *dev_priv = dev->dev_private; |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1797 | |
| 1798 | if (!dev_priv->display.enable_fbc) |
| 1799 | return; |
| 1800 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1801 | intel_cancel_fbc_work(dev_priv); |
| 1802 | |
| 1803 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 1804 | if (work == NULL) { |
| 1805 | dev_priv->display.enable_fbc(crtc, interval); |
| 1806 | return; |
| 1807 | } |
| 1808 | |
| 1809 | work->crtc = crtc; |
| 1810 | work->fb = crtc->fb; |
| 1811 | work->interval = interval; |
| 1812 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
| 1813 | |
| 1814 | dev_priv->fbc_work = work; |
| 1815 | |
| 1816 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); |
| 1817 | |
| 1818 | /* Delay the actual enabling to let pageflipping cease and the |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1819 | * display to settle before starting the compression. Note that |
| 1820 | * this delay also serves a second purpose: it allows for a |
| 1821 | * vblank to pass after disabling the FBC before we attempt |
| 1822 | * to modify the control registers. |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1823 | * |
| 1824 | * A more complicated solution would involve tracking vblanks |
| 1825 | * following the termination of the page-flipping sequence |
| 1826 | * and indeed performing the enable as a co-routine and not |
| 1827 | * waiting synchronously upon the vblank. |
| 1828 | */ |
| 1829 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1830 | } |
| 1831 | |
| 1832 | void intel_disable_fbc(struct drm_device *dev) |
| 1833 | { |
| 1834 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1835 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 1836 | intel_cancel_fbc_work(dev_priv); |
| 1837 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1838 | if (!dev_priv->display.disable_fbc) |
| 1839 | return; |
| 1840 | |
| 1841 | dev_priv->display.disable_fbc(dev); |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1842 | dev_priv->cfb_plane = -1; |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1843 | } |
| 1844 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1845 | /** |
| 1846 | * intel_update_fbc - enable/disable FBC as needed |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1847 | * @dev: the drm_device |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1848 | * |
| 1849 | * Set up the framebuffer compression hardware at mode set time. We |
| 1850 | * enable it if possible: |
| 1851 | * - plane A only (on pre-965) |
| 1852 | * - no pixel mulitply/line duplication |
| 1853 | * - no alpha buffer discard |
| 1854 | * - no dual wide |
| 1855 | * - framebuffer <= 2048 in width, 1536 in height |
| 1856 | * |
| 1857 | * We can't assume that any compression will take place (worst case), |
| 1858 | * so the compressed buffer has to be the same size as the uncompressed |
| 1859 | * one. It also must reside (along with the line length buffer) in |
| 1860 | * stolen memory. |
| 1861 | * |
| 1862 | * We need to enable/disable FBC on a global basis. |
| 1863 | */ |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1864 | static void intel_update_fbc(struct drm_device *dev) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1865 | { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1867 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
| 1868 | struct intel_crtc *intel_crtc; |
| 1869 | struct drm_framebuffer *fb; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1870 | struct intel_framebuffer *intel_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1871 | struct drm_i915_gem_object *obj; |
Keith Packard | cd0de03 | 2011-09-19 21:34:19 -0700 | [diff] [blame] | 1872 | int enable_fbc; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1873 | |
| 1874 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1875 | |
| 1876 | if (!i915_powersave) |
| 1877 | return; |
| 1878 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1879 | if (!I915_HAS_FBC(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1880 | return; |
| 1881 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1882 | /* |
| 1883 | * If FBC is already on, we just have to verify that we can |
| 1884 | * keep it that way... |
| 1885 | * Need to disable if: |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1886 | * - more than one pipe is active |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1887 | * - changing FBC params (stride, fence, mode) |
| 1888 | * - new fb is too large to fit in compressed buffer |
| 1889 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 1890 | */ |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1891 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 1892 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1893 | if (crtc) { |
| 1894 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
| 1895 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
| 1896 | goto out_disable; |
| 1897 | } |
| 1898 | crtc = tmp_crtc; |
| 1899 | } |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1900 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1901 | |
| 1902 | if (!crtc || crtc->fb == NULL) { |
| 1903 | DRM_DEBUG_KMS("no output, disabling\n"); |
| 1904 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1905 | goto out_disable; |
| 1906 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1907 | |
| 1908 | intel_crtc = to_intel_crtc(crtc); |
| 1909 | fb = crtc->fb; |
| 1910 | intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1911 | obj = intel_fb->obj; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1912 | |
Keith Packard | cd0de03 | 2011-09-19 21:34:19 -0700 | [diff] [blame] | 1913 | enable_fbc = i915_enable_fbc; |
| 1914 | if (enable_fbc < 0) { |
| 1915 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
| 1916 | enable_fbc = 1; |
Chris Wilson | d56d8b2 | 2011-11-08 23:17:34 +0000 | [diff] [blame] | 1917 | if (INTEL_INFO(dev)->gen <= 6) |
Keith Packard | cd0de03 | 2011-09-19 21:34:19 -0700 | [diff] [blame] | 1918 | enable_fbc = 0; |
| 1919 | } |
| 1920 | if (!enable_fbc) { |
| 1921 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1922 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
| 1923 | goto out_disable; |
| 1924 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1925 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1926 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1927 | "compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1928 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1929 | goto out_disable; |
| 1930 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1931 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
| 1932 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1933 | DRM_DEBUG_KMS("mode incompatible with compression, " |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1934 | "disabling\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1935 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1936 | goto out_disable; |
| 1937 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1938 | if ((crtc->mode.hdisplay > 2048) || |
| 1939 | (crtc->mode.vdisplay > 1536)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1940 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1941 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1942 | goto out_disable; |
| 1943 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1944 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1945 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1946 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1947 | goto out_disable; |
| 1948 | } |
Chris Wilson | de56851 | 2011-07-08 12:22:39 +0100 | [diff] [blame] | 1949 | |
| 1950 | /* The use of a CPU fence is mandatory in order to detect writes |
| 1951 | * by the CPU to the scanout and trigger updates to the FBC. |
| 1952 | */ |
| 1953 | if (obj->tiling_mode != I915_TILING_X || |
| 1954 | obj->fence_reg == I915_FENCE_REG_NONE) { |
| 1955 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1956 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1957 | goto out_disable; |
| 1958 | } |
| 1959 | |
Jason Wessel | c924b93 | 2010-08-05 09:22:32 -0500 | [diff] [blame] | 1960 | /* If the kernel debugger is active, always disable compression */ |
| 1961 | if (in_dbg_master()) |
| 1962 | goto out_disable; |
| 1963 | |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 1964 | /* If the scanout has not changed, don't modify the FBC settings. |
| 1965 | * Note that we make the fundamental assumption that the fb->obj |
| 1966 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 1967 | * without first being decoupled from the scanout and FBC disabled. |
| 1968 | */ |
| 1969 | if (dev_priv->cfb_plane == intel_crtc->plane && |
| 1970 | dev_priv->cfb_fb == fb->base.id && |
| 1971 | dev_priv->cfb_y == crtc->y) |
| 1972 | return; |
| 1973 | |
| 1974 | if (intel_fbc_enabled(dev)) { |
| 1975 | /* We update FBC along two paths, after changing fb/crtc |
| 1976 | * configuration (modeswitching) and after page-flipping |
| 1977 | * finishes. For the latter, we know that not only did |
| 1978 | * we disable the FBC at the start of the page-flip |
| 1979 | * sequence, but also more than one vblank has passed. |
| 1980 | * |
| 1981 | * For the former case of modeswitching, it is possible |
| 1982 | * to switch between two FBC valid configurations |
| 1983 | * instantaneously so we do need to disable the FBC |
| 1984 | * before we can modify its control registers. We also |
| 1985 | * have to wait for the next vblank for that to take |
| 1986 | * effect. However, since we delay enabling FBC we can |
| 1987 | * assume that a vblank has passed since disabling and |
| 1988 | * that we can safely alter the registers in the deferred |
| 1989 | * callback. |
| 1990 | * |
| 1991 | * In the scenario that we go from a valid to invalid |
| 1992 | * and then back to valid FBC configuration we have |
| 1993 | * no strict enforcement that a vblank occurred since |
| 1994 | * disabling the FBC. However, along all current pipe |
| 1995 | * disabling paths we do need to wait for a vblank at |
| 1996 | * some point. And we wait before enabling FBC anyway. |
| 1997 | */ |
| 1998 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
| 1999 | intel_disable_fbc(dev); |
| 2000 | } |
| 2001 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 2002 | intel_enable_fbc(crtc, 500); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2003 | return; |
| 2004 | |
| 2005 | out_disable: |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2006 | /* Multiple disables should be harmless */ |
Chris Wilson | a939406 | 2010-05-27 13:18:16 +0100 | [diff] [blame] | 2007 | if (intel_fbc_enabled(dev)) { |
| 2008 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 2009 | intel_disable_fbc(dev); |
Chris Wilson | a939406 | 2010-05-27 13:18:16 +0100 | [diff] [blame] | 2010 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2011 | } |
| 2012 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 2013 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2014 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2015 | struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2016 | struct intel_ring_buffer *pipelined) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2017 | { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2018 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2019 | u32 alignment; |
| 2020 | int ret; |
| 2021 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2022 | switch (obj->tiling_mode) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2023 | case I915_TILING_NONE: |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 2024 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 2025 | alignment = 128 * 1024; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2026 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 2027 | alignment = 4 * 1024; |
| 2028 | else |
| 2029 | alignment = 64 * 1024; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2030 | break; |
| 2031 | case I915_TILING_X: |
| 2032 | /* pin() will align the object as required by fence */ |
| 2033 | alignment = 0; |
| 2034 | break; |
| 2035 | case I915_TILING_Y: |
| 2036 | /* FIXME: Is this true? */ |
| 2037 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
| 2038 | return -EINVAL; |
| 2039 | default: |
| 2040 | BUG(); |
| 2041 | } |
| 2042 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2043 | dev_priv->mm.interruptible = false; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2044 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2045 | if (ret) |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2046 | goto err_interruptible; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2047 | |
| 2048 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 2049 | * fence, whereas 965+ only requires a fence if using |
| 2050 | * framebuffer compression. For simplicity, we always install |
| 2051 | * a fence as the cost is not that onerous. |
| 2052 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2053 | if (obj->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2054 | ret = i915_gem_object_get_fence(obj, pipelined); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2055 | if (ret) |
| 2056 | goto err_unpin; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2057 | |
| 2058 | i915_gem_object_pin_fence(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2059 | } |
| 2060 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2061 | dev_priv->mm.interruptible = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2062 | return 0; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2063 | |
| 2064 | err_unpin: |
| 2065 | i915_gem_object_unpin(obj); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2066 | err_interruptible: |
| 2067 | dev_priv->mm.interruptible = true; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2068 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2069 | } |
| 2070 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2071 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
| 2072 | { |
| 2073 | i915_gem_object_unpin_fence(obj); |
| 2074 | i915_gem_object_unpin(obj); |
| 2075 | } |
| 2076 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2077 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 2078 | int x, int y) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2079 | { |
| 2080 | struct drm_device *dev = crtc->dev; |
| 2081 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2083 | struct intel_framebuffer *intel_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2084 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2085 | int plane = intel_crtc->plane; |
| 2086 | unsigned long Start, Offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2087 | u32 dspcntr; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2088 | u32 reg; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2089 | |
| 2090 | switch (plane) { |
| 2091 | case 0: |
| 2092 | case 1: |
| 2093 | break; |
| 2094 | default: |
| 2095 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
| 2096 | return -EINVAL; |
| 2097 | } |
| 2098 | |
| 2099 | intel_fb = to_intel_framebuffer(fb); |
| 2100 | obj = intel_fb->obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2101 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2102 | reg = DSPCNTR(plane); |
| 2103 | dspcntr = I915_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2104 | /* Mask out pixel format bits in case we change it */ |
| 2105 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 2106 | switch (fb->bits_per_pixel) { |
| 2107 | case 8: |
| 2108 | dspcntr |= DISPPLANE_8BPP; |
| 2109 | break; |
| 2110 | case 16: |
| 2111 | if (fb->depth == 15) |
| 2112 | dspcntr |= DISPPLANE_15_16BPP; |
| 2113 | else |
| 2114 | dspcntr |= DISPPLANE_16BPP; |
| 2115 | break; |
| 2116 | case 24: |
| 2117 | case 32: |
| 2118 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 2119 | break; |
| 2120 | default: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2121 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2122 | return -EINVAL; |
| 2123 | } |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2124 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2125 | if (obj->tiling_mode != I915_TILING_NONE) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2126 | dspcntr |= DISPPLANE_TILED; |
| 2127 | else |
| 2128 | dspcntr &= ~DISPPLANE_TILED; |
| 2129 | } |
| 2130 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2131 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2132 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2133 | Start = obj->gtt_offset; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2134 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2135 | |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 2136 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2137 | Start, Offset, x, y, fb->pitches[0]); |
| 2138 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2139 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2140 | I915_WRITE(DSPSURF(plane), Start); |
| 2141 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2142 | I915_WRITE(DSPADDR(plane), Offset); |
| 2143 | } else |
| 2144 | I915_WRITE(DSPADDR(plane), Start + Offset); |
| 2145 | POSTING_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2146 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2147 | return 0; |
| 2148 | } |
| 2149 | |
| 2150 | static int ironlake_update_plane(struct drm_crtc *crtc, |
| 2151 | struct drm_framebuffer *fb, int x, int y) |
| 2152 | { |
| 2153 | struct drm_device *dev = crtc->dev; |
| 2154 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2156 | struct intel_framebuffer *intel_fb; |
| 2157 | struct drm_i915_gem_object *obj; |
| 2158 | int plane = intel_crtc->plane; |
| 2159 | unsigned long Start, Offset; |
| 2160 | u32 dspcntr; |
| 2161 | u32 reg; |
| 2162 | |
| 2163 | switch (plane) { |
| 2164 | case 0: |
| 2165 | case 1: |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2166 | case 2: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2167 | break; |
| 2168 | default: |
| 2169 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
| 2170 | return -EINVAL; |
| 2171 | } |
| 2172 | |
| 2173 | intel_fb = to_intel_framebuffer(fb); |
| 2174 | obj = intel_fb->obj; |
| 2175 | |
| 2176 | reg = DSPCNTR(plane); |
| 2177 | dspcntr = I915_READ(reg); |
| 2178 | /* Mask out pixel format bits in case we change it */ |
| 2179 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 2180 | switch (fb->bits_per_pixel) { |
| 2181 | case 8: |
| 2182 | dspcntr |= DISPPLANE_8BPP; |
| 2183 | break; |
| 2184 | case 16: |
| 2185 | if (fb->depth != 16) |
| 2186 | return -EINVAL; |
| 2187 | |
| 2188 | dspcntr |= DISPPLANE_16BPP; |
| 2189 | break; |
| 2190 | case 24: |
| 2191 | case 32: |
| 2192 | if (fb->depth == 24) |
| 2193 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 2194 | else if (fb->depth == 30) |
| 2195 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
| 2196 | else |
| 2197 | return -EINVAL; |
| 2198 | break; |
| 2199 | default: |
| 2200 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
| 2201 | return -EINVAL; |
| 2202 | } |
| 2203 | |
| 2204 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2205 | dspcntr |= DISPPLANE_TILED; |
| 2206 | else |
| 2207 | dspcntr &= ~DISPPLANE_TILED; |
| 2208 | |
| 2209 | /* must disable */ |
| 2210 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2211 | |
| 2212 | I915_WRITE(reg, dspcntr); |
| 2213 | |
| 2214 | Start = obj->gtt_offset; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2215 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2216 | |
| 2217 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2218 | Start, Offset, x, y, fb->pitches[0]); |
| 2219 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2220 | I915_WRITE(DSPSURF(plane), Start); |
| 2221 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2222 | I915_WRITE(DSPADDR(plane), Offset); |
| 2223 | POSTING_READ(reg); |
| 2224 | |
| 2225 | return 0; |
| 2226 | } |
| 2227 | |
| 2228 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 2229 | static int |
| 2230 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 2231 | int x, int y, enum mode_set_atomic state) |
| 2232 | { |
| 2233 | struct drm_device *dev = crtc->dev; |
| 2234 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2235 | int ret; |
| 2236 | |
| 2237 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
| 2238 | if (ret) |
| 2239 | return ret; |
| 2240 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 2241 | intel_update_fbc(dev); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 2242 | intel_increase_pllclock(crtc); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2243 | |
| 2244 | return 0; |
| 2245 | } |
| 2246 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2247 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2248 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
| 2249 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2250 | { |
| 2251 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2252 | struct drm_i915_master_private *master_priv; |
| 2253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2254 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2255 | |
| 2256 | /* no fb bound */ |
| 2257 | if (!crtc->fb) { |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2258 | DRM_ERROR("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2259 | return 0; |
| 2260 | } |
| 2261 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2262 | switch (intel_crtc->plane) { |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2263 | case 0: |
| 2264 | case 1: |
| 2265 | break; |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2266 | case 2: |
| 2267 | if (IS_IVYBRIDGE(dev)) |
| 2268 | break; |
| 2269 | /* fall through otherwise */ |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2270 | default: |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2271 | DRM_ERROR("no plane for crtc\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2272 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2273 | } |
| 2274 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2275 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2276 | ret = intel_pin_and_fence_fb_obj(dev, |
| 2277 | to_intel_framebuffer(crtc->fb)->obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2278 | NULL); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2279 | if (ret != 0) { |
| 2280 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2281 | DRM_ERROR("pin & fence failed\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2282 | return ret; |
| 2283 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2284 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2285 | if (old_fb) { |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2286 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2287 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2288 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2289 | wait_event(dev_priv->pending_flip_queue, |
Chris Wilson | 01eec72 | 2011-02-11 20:47:45 +0000 | [diff] [blame] | 2290 | atomic_read(&dev_priv->mm.wedged) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2291 | atomic_read(&obj->pending_flip) == 0); |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2292 | |
| 2293 | /* Big Hammer, we also need to ensure that any pending |
| 2294 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 2295 | * current scanout is retired before unpinning the old |
| 2296 | * framebuffer. |
Chris Wilson | 01eec72 | 2011-02-11 20:47:45 +0000 | [diff] [blame] | 2297 | * |
| 2298 | * This should only fail upon a hung GPU, in which case we |
| 2299 | * can safely continue. |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2300 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2301 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 01eec72 | 2011-02-11 20:47:45 +0000 | [diff] [blame] | 2302 | (void) ret; |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2303 | } |
| 2304 | |
Jason Wessel | 21c74a8 | 2010-10-13 14:09:44 -0500 | [diff] [blame] | 2305 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
| 2306 | LEAVE_ATOMIC_MODE_SET); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 2307 | if (ret) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2308 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2309 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2310 | DRM_ERROR("failed to update base address\n"); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 2311 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2312 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2313 | |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 2314 | if (old_fb) { |
| 2315 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2316 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 2317 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2318 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2319 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2320 | |
| 2321 | if (!dev->primary->master) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2322 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2323 | |
| 2324 | master_priv = dev->primary->master->driver_priv; |
| 2325 | if (!master_priv->sarea_priv) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2326 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2327 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2328 | if (intel_crtc->pipe) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2329 | master_priv->sarea_priv->pipeB_x = x; |
| 2330 | master_priv->sarea_priv->pipeB_y = y; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2331 | } else { |
| 2332 | master_priv->sarea_priv->pipeA_x = x; |
| 2333 | master_priv->sarea_priv->pipeA_y = y; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2334 | } |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2335 | |
| 2336 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2337 | } |
| 2338 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2339 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2340 | { |
| 2341 | struct drm_device *dev = crtc->dev; |
| 2342 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2343 | u32 dpa_ctl; |
| 2344 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2345 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2346 | dpa_ctl = I915_READ(DP_A); |
| 2347 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 2348 | |
| 2349 | if (clock < 200000) { |
| 2350 | u32 temp; |
| 2351 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
| 2352 | /* workaround for 160Mhz: |
| 2353 | 1) program 0x4600c bits 15:0 = 0x8124 |
| 2354 | 2) program 0x46010 bit 0 = 1 |
| 2355 | 3) program 0x46034 bit 24 = 1 |
| 2356 | 4) program 0x64000 bit 14 = 1 |
| 2357 | */ |
| 2358 | temp = I915_READ(0x4600c); |
| 2359 | temp &= 0xffff0000; |
| 2360 | I915_WRITE(0x4600c, temp | 0x8124); |
| 2361 | |
| 2362 | temp = I915_READ(0x46010); |
| 2363 | I915_WRITE(0x46010, temp | 1); |
| 2364 | |
| 2365 | temp = I915_READ(0x46034); |
| 2366 | I915_WRITE(0x46034, temp | (1 << 24)); |
| 2367 | } else { |
| 2368 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 2369 | } |
| 2370 | I915_WRITE(DP_A, dpa_ctl); |
| 2371 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2372 | POSTING_READ(DP_A); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2373 | udelay(500); |
| 2374 | } |
| 2375 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2376 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 2377 | { |
| 2378 | struct drm_device *dev = crtc->dev; |
| 2379 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2381 | int pipe = intel_crtc->pipe; |
| 2382 | u32 reg, temp; |
| 2383 | |
| 2384 | /* enable normal train */ |
| 2385 | reg = FDI_TX_CTL(pipe); |
| 2386 | temp = I915_READ(reg); |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2387 | if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2388 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2389 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2390 | } else { |
| 2391 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2392 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2393 | } |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2394 | I915_WRITE(reg, temp); |
| 2395 | |
| 2396 | reg = FDI_RX_CTL(pipe); |
| 2397 | temp = I915_READ(reg); |
| 2398 | if (HAS_PCH_CPT(dev)) { |
| 2399 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2400 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 2401 | } else { |
| 2402 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2403 | temp |= FDI_LINK_TRAIN_NONE; |
| 2404 | } |
| 2405 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 2406 | |
| 2407 | /* wait one idle pattern time */ |
| 2408 | POSTING_READ(reg); |
| 2409 | udelay(1000); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2410 | |
| 2411 | /* IVB wants error correction enabled */ |
| 2412 | if (IS_IVYBRIDGE(dev)) |
| 2413 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 2414 | FDI_FE_ERRC_ENABLE); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2415 | } |
| 2416 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2417 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
| 2418 | { |
| 2419 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2420 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
| 2421 | |
| 2422 | flags |= FDI_PHASE_SYNC_OVR(pipe); |
| 2423 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ |
| 2424 | flags |= FDI_PHASE_SYNC_EN(pipe); |
| 2425 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ |
| 2426 | POSTING_READ(SOUTH_CHICKEN1); |
| 2427 | } |
| 2428 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2429 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 2430 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 2431 | { |
| 2432 | struct drm_device *dev = crtc->dev; |
| 2433 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2435 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2436 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2437 | u32 reg, temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2438 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2439 | /* FDI needs bits from pipe & plane first */ |
| 2440 | assert_pipe_enabled(dev_priv, pipe); |
| 2441 | assert_plane_enabled(dev_priv, plane); |
| 2442 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2443 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2444 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2445 | reg = FDI_RX_IMR(pipe); |
| 2446 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2447 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2448 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2449 | I915_WRITE(reg, temp); |
| 2450 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2451 | udelay(150); |
| 2452 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2453 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2454 | reg = FDI_TX_CTL(pipe); |
| 2455 | temp = I915_READ(reg); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 2456 | temp &= ~(7 << 19); |
| 2457 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2458 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2459 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2460 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2461 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2462 | reg = FDI_RX_CTL(pipe); |
| 2463 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2464 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2465 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2466 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2467 | |
| 2468 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2469 | udelay(150); |
| 2470 | |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2471 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2472 | if (HAS_PCH_IBX(dev)) { |
| 2473 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 2474 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 2475 | FDI_RX_PHASE_SYNC_POINTER_EN); |
| 2476 | } |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2477 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2478 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2479 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2480 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2481 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2482 | |
| 2483 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 2484 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2485 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2486 | break; |
| 2487 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2488 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2489 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2490 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2491 | |
| 2492 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2493 | reg = FDI_TX_CTL(pipe); |
| 2494 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2495 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2496 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2497 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2498 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2499 | reg = FDI_RX_CTL(pipe); |
| 2500 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2501 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2502 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2503 | I915_WRITE(reg, temp); |
| 2504 | |
| 2505 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2506 | udelay(150); |
| 2507 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2508 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2509 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2510 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2511 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2512 | |
| 2513 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2514 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2515 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2516 | break; |
| 2517 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2518 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2519 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2520 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2521 | |
| 2522 | DRM_DEBUG_KMS("FDI train done\n"); |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 2523 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2524 | } |
| 2525 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2526 | static const int snb_b_fdi_train_param[] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2527 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 2528 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 2529 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 2530 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 2531 | }; |
| 2532 | |
| 2533 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 2534 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 2535 | { |
| 2536 | struct drm_device *dev = crtc->dev; |
| 2537 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2539 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2540 | u32 reg, temp, i; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2541 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2542 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2543 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2544 | reg = FDI_RX_IMR(pipe); |
| 2545 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2546 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2547 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2548 | I915_WRITE(reg, temp); |
| 2549 | |
| 2550 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2551 | udelay(150); |
| 2552 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2553 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2554 | reg = FDI_TX_CTL(pipe); |
| 2555 | temp = I915_READ(reg); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 2556 | temp &= ~(7 << 19); |
| 2557 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2558 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2559 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2560 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2561 | /* SNB-B */ |
| 2562 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2563 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2564 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2565 | reg = FDI_RX_CTL(pipe); |
| 2566 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2567 | if (HAS_PCH_CPT(dev)) { |
| 2568 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2569 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2570 | } else { |
| 2571 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2572 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2573 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2574 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2575 | |
| 2576 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2577 | udelay(150); |
| 2578 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2579 | if (HAS_PCH_CPT(dev)) |
| 2580 | cpt_phase_pointer_enable(dev, pipe); |
| 2581 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2582 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2583 | reg = FDI_TX_CTL(pipe); |
| 2584 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2585 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2586 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2587 | I915_WRITE(reg, temp); |
| 2588 | |
| 2589 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2590 | udelay(500); |
| 2591 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2592 | reg = FDI_RX_IIR(pipe); |
| 2593 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2594 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2595 | |
| 2596 | if (temp & FDI_RX_BIT_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2597 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2598 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 2599 | break; |
| 2600 | } |
| 2601 | } |
| 2602 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2603 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2604 | |
| 2605 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2606 | reg = FDI_TX_CTL(pipe); |
| 2607 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2608 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2609 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 2610 | if (IS_GEN6(dev)) { |
| 2611 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2612 | /* SNB-B */ |
| 2613 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 2614 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2615 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2616 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2617 | reg = FDI_RX_CTL(pipe); |
| 2618 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2619 | if (HAS_PCH_CPT(dev)) { |
| 2620 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2621 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 2622 | } else { |
| 2623 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2624 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 2625 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2626 | I915_WRITE(reg, temp); |
| 2627 | |
| 2628 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2629 | udelay(150); |
| 2630 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2631 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2632 | reg = FDI_TX_CTL(pipe); |
| 2633 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2634 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2635 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2636 | I915_WRITE(reg, temp); |
| 2637 | |
| 2638 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2639 | udelay(500); |
| 2640 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2641 | reg = FDI_RX_IIR(pipe); |
| 2642 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2643 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2644 | |
| 2645 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2646 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2647 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2648 | break; |
| 2649 | } |
| 2650 | } |
| 2651 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2652 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2653 | |
| 2654 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 2655 | } |
| 2656 | |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2657 | /* Manual link training for Ivy Bridge A0 parts */ |
| 2658 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 2659 | { |
| 2660 | struct drm_device *dev = crtc->dev; |
| 2661 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2663 | int pipe = intel_crtc->pipe; |
| 2664 | u32 reg, temp, i; |
| 2665 | |
| 2666 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2667 | for train result */ |
| 2668 | reg = FDI_RX_IMR(pipe); |
| 2669 | temp = I915_READ(reg); |
| 2670 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2671 | temp &= ~FDI_RX_BIT_LOCK; |
| 2672 | I915_WRITE(reg, temp); |
| 2673 | |
| 2674 | POSTING_READ(reg); |
| 2675 | udelay(150); |
| 2676 | |
| 2677 | /* enable CPU FDI TX and PCH FDI RX */ |
| 2678 | reg = FDI_TX_CTL(pipe); |
| 2679 | temp = I915_READ(reg); |
| 2680 | temp &= ~(7 << 19); |
| 2681 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
| 2682 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 2683 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
| 2684 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2685 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Jesse Barnes | c4f9c4c | 2011-10-10 14:28:52 -0700 | [diff] [blame] | 2686 | temp |= FDI_COMPOSITE_SYNC; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2687 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 2688 | |
| 2689 | reg = FDI_RX_CTL(pipe); |
| 2690 | temp = I915_READ(reg); |
| 2691 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 2692 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2693 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
Jesse Barnes | c4f9c4c | 2011-10-10 14:28:52 -0700 | [diff] [blame] | 2694 | temp |= FDI_COMPOSITE_SYNC; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2695 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2696 | |
| 2697 | POSTING_READ(reg); |
| 2698 | udelay(150); |
| 2699 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2700 | if (HAS_PCH_CPT(dev)) |
| 2701 | cpt_phase_pointer_enable(dev, pipe); |
| 2702 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2703 | for (i = 0; i < 4; i++) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2704 | reg = FDI_TX_CTL(pipe); |
| 2705 | temp = I915_READ(reg); |
| 2706 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2707 | temp |= snb_b_fdi_train_param[i]; |
| 2708 | I915_WRITE(reg, temp); |
| 2709 | |
| 2710 | POSTING_READ(reg); |
| 2711 | udelay(500); |
| 2712 | |
| 2713 | reg = FDI_RX_IIR(pipe); |
| 2714 | temp = I915_READ(reg); |
| 2715 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2716 | |
| 2717 | if (temp & FDI_RX_BIT_LOCK || |
| 2718 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 2719 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 2720 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 2721 | break; |
| 2722 | } |
| 2723 | } |
| 2724 | if (i == 4) |
| 2725 | DRM_ERROR("FDI train 1 fail!\n"); |
| 2726 | |
| 2727 | /* Train 2 */ |
| 2728 | reg = FDI_TX_CTL(pipe); |
| 2729 | temp = I915_READ(reg); |
| 2730 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2731 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 2732 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2733 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 2734 | I915_WRITE(reg, temp); |
| 2735 | |
| 2736 | reg = FDI_RX_CTL(pipe); |
| 2737 | temp = I915_READ(reg); |
| 2738 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2739 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 2740 | I915_WRITE(reg, temp); |
| 2741 | |
| 2742 | POSTING_READ(reg); |
| 2743 | udelay(150); |
| 2744 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2745 | for (i = 0; i < 4; i++) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2746 | reg = FDI_TX_CTL(pipe); |
| 2747 | temp = I915_READ(reg); |
| 2748 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2749 | temp |= snb_b_fdi_train_param[i]; |
| 2750 | I915_WRITE(reg, temp); |
| 2751 | |
| 2752 | POSTING_READ(reg); |
| 2753 | udelay(500); |
| 2754 | |
| 2755 | reg = FDI_RX_IIR(pipe); |
| 2756 | temp = I915_READ(reg); |
| 2757 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2758 | |
| 2759 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 2760 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 2761 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2762 | break; |
| 2763 | } |
| 2764 | } |
| 2765 | if (i == 4) |
| 2766 | DRM_ERROR("FDI train 2 fail!\n"); |
| 2767 | |
| 2768 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 2769 | } |
| 2770 | |
| 2771 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2772 | { |
| 2773 | struct drm_device *dev = crtc->dev; |
| 2774 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2776 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2777 | u32 reg, temp; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2778 | |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 2779 | /* Write the TU size bits so error detection works */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2780 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 2781 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 2782 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2783 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2784 | reg = FDI_RX_CTL(pipe); |
| 2785 | temp = I915_READ(reg); |
| 2786 | temp &= ~((0x7 << 19) | (0x7 << 16)); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2787 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2788 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2789 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 2790 | |
| 2791 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2792 | udelay(200); |
| 2793 | |
| 2794 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2795 | temp = I915_READ(reg); |
| 2796 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 2797 | |
| 2798 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2799 | udelay(200); |
| 2800 | |
| 2801 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2802 | reg = FDI_TX_CTL(pipe); |
| 2803 | temp = I915_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2804 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2805 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
| 2806 | |
| 2807 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2808 | udelay(100); |
| 2809 | } |
| 2810 | } |
| 2811 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2812 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
| 2813 | { |
| 2814 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2815 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
| 2816 | |
| 2817 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); |
| 2818 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ |
| 2819 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); |
| 2820 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ |
| 2821 | POSTING_READ(SOUTH_CHICKEN1); |
| 2822 | } |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2823 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 2824 | { |
| 2825 | struct drm_device *dev = crtc->dev; |
| 2826 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2828 | int pipe = intel_crtc->pipe; |
| 2829 | u32 reg, temp; |
| 2830 | |
| 2831 | /* disable CPU FDI tx and PCH FDI rx */ |
| 2832 | reg = FDI_TX_CTL(pipe); |
| 2833 | temp = I915_READ(reg); |
| 2834 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 2835 | POSTING_READ(reg); |
| 2836 | |
| 2837 | reg = FDI_RX_CTL(pipe); |
| 2838 | temp = I915_READ(reg); |
| 2839 | temp &= ~(0x7 << 16); |
| 2840 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2841 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 2842 | |
| 2843 | POSTING_READ(reg); |
| 2844 | udelay(100); |
| 2845 | |
| 2846 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2847 | if (HAS_PCH_IBX(dev)) { |
| 2848 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2849 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
| 2850 | I915_READ(FDI_RX_CHICKEN(pipe) & |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2851 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2852 | } else if (HAS_PCH_CPT(dev)) { |
| 2853 | cpt_phase_pointer_disable(dev, pipe); |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2854 | } |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2855 | |
| 2856 | /* still set train pattern 1 */ |
| 2857 | reg = FDI_TX_CTL(pipe); |
| 2858 | temp = I915_READ(reg); |
| 2859 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2860 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2861 | I915_WRITE(reg, temp); |
| 2862 | |
| 2863 | reg = FDI_RX_CTL(pipe); |
| 2864 | temp = I915_READ(reg); |
| 2865 | if (HAS_PCH_CPT(dev)) { |
| 2866 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2867 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2868 | } else { |
| 2869 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2870 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2871 | } |
| 2872 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 2873 | temp &= ~(0x07 << 16); |
| 2874 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2875 | I915_WRITE(reg, temp); |
| 2876 | |
| 2877 | POSTING_READ(reg); |
| 2878 | udelay(100); |
| 2879 | } |
| 2880 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2881 | /* |
| 2882 | * When we disable a pipe, we need to clear any pending scanline wait events |
| 2883 | * to avoid hanging the ring, which we assume we are waiting on. |
| 2884 | */ |
| 2885 | static void intel_clear_scanline_wait(struct drm_device *dev) |
| 2886 | { |
| 2887 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 2888 | struct intel_ring_buffer *ring; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2889 | u32 tmp; |
| 2890 | |
| 2891 | if (IS_GEN2(dev)) |
| 2892 | /* Can't break the hang on i8xx */ |
| 2893 | return; |
| 2894 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2895 | ring = LP_RING(dev_priv); |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 2896 | tmp = I915_READ_CTL(ring); |
| 2897 | if (tmp & RING_WAIT) |
| 2898 | I915_WRITE_CTL(ring, tmp); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2899 | } |
| 2900 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2901 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
| 2902 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2903 | struct drm_i915_gem_object *obj; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2904 | struct drm_i915_private *dev_priv; |
| 2905 | |
| 2906 | if (crtc->fb == NULL) |
| 2907 | return; |
| 2908 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2909 | obj = to_intel_framebuffer(crtc->fb)->obj; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2910 | dev_priv = crtc->dev->dev_private; |
| 2911 | wait_event(dev_priv->pending_flip_queue, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2912 | atomic_read(&obj->pending_flip) == 0); |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2913 | } |
| 2914 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2915 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
| 2916 | { |
| 2917 | struct drm_device *dev = crtc->dev; |
| 2918 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2919 | struct intel_encoder *encoder; |
| 2920 | |
| 2921 | /* |
| 2922 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that |
| 2923 | * must be driven by its own crtc; no sharing is possible. |
| 2924 | */ |
| 2925 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 2926 | if (encoder->base.crtc != crtc) |
| 2927 | continue; |
| 2928 | |
| 2929 | switch (encoder->type) { |
| 2930 | case INTEL_OUTPUT_EDP: |
| 2931 | if (!intel_encoder_is_pch_edp(&encoder->base)) |
| 2932 | return false; |
| 2933 | continue; |
| 2934 | } |
| 2935 | } |
| 2936 | |
| 2937 | return true; |
| 2938 | } |
| 2939 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2940 | /* |
| 2941 | * Enable PCH resources required for PCH ports: |
| 2942 | * - PCH PLLs |
| 2943 | * - FDI training & RX/TX |
| 2944 | * - update transcoder timings |
| 2945 | * - DP transcoding bits |
| 2946 | * - transcoder |
| 2947 | */ |
| 2948 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2949 | { |
| 2950 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2951 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2953 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 2954 | u32 reg, temp, transc_sel; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2955 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2956 | /* For PCH output, training FDI link */ |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 2957 | dev_priv->display.fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2958 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 2959 | intel_enable_pch_pll(dev_priv, pipe); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2960 | |
| 2961 | if (HAS_PCH_CPT(dev)) { |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 2962 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
| 2963 | TRANSC_DPLLB_SEL; |
| 2964 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2965 | /* Be sure PCH DPLL SEL is set */ |
| 2966 | temp = I915_READ(PCH_DPLL_SEL); |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2967 | if (pipe == 0) { |
| 2968 | temp &= ~(TRANSA_DPLLB_SEL); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2969 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2970 | } else if (pipe == 1) { |
| 2971 | temp &= ~(TRANSB_DPLLB_SEL); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2972 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2973 | } else if (pipe == 2) { |
| 2974 | temp &= ~(TRANSC_DPLLB_SEL); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 2975 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2976 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2977 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2978 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2979 | |
Jesse Barnes | d9b6cb5 | 2011-01-04 15:09:35 -0800 | [diff] [blame] | 2980 | /* set transcoder timing, panel must allow it */ |
| 2981 | assert_panel_unlocked(dev_priv, pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2982 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
| 2983 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); |
| 2984 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); |
| 2985 | |
| 2986 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
| 2987 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); |
| 2988 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 2989 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2990 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2991 | intel_fdi_normal_train(crtc); |
| 2992 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2993 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 2994 | if (HAS_PCH_CPT(dev) && |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 2995 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 2996 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 2997 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2998 | reg = TRANS_DP_CTL(pipe); |
| 2999 | temp = I915_READ(reg); |
| 3000 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
Eric Anholt | 220cad3 | 2010-11-18 09:32:58 +0800 | [diff] [blame] | 3001 | TRANS_DP_SYNC_MASK | |
| 3002 | TRANS_DP_BPC_MASK); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3003 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
| 3004 | TRANS_DP_ENH_FRAMING); |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 3005 | temp |= bpc << 9; /* same format but at 11:9 */ |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3006 | |
| 3007 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3008 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3009 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3010 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3011 | |
| 3012 | switch (intel_trans_dp_port_sel(crtc)) { |
| 3013 | case PCH_DP_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3014 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3015 | break; |
| 3016 | case PCH_DP_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3017 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3018 | break; |
| 3019 | case PCH_DP_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3020 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3021 | break; |
| 3022 | default: |
| 3023 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3024 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3025 | break; |
| 3026 | } |
| 3027 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3028 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3029 | } |
| 3030 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 3031 | intel_enable_transcoder(dev_priv, pipe); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3032 | } |
| 3033 | |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3034 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
| 3035 | { |
| 3036 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3037 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); |
| 3038 | u32 temp; |
| 3039 | |
| 3040 | temp = I915_READ(dslreg); |
| 3041 | udelay(500); |
| 3042 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
| 3043 | /* Without this, mode sets may fail silently on FDI */ |
| 3044 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); |
| 3045 | udelay(250); |
| 3046 | I915_WRITE(tc2reg, 0); |
| 3047 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
| 3048 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); |
| 3049 | } |
| 3050 | } |
| 3051 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3052 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
| 3053 | { |
| 3054 | struct drm_device *dev = crtc->dev; |
| 3055 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3057 | int pipe = intel_crtc->pipe; |
| 3058 | int plane = intel_crtc->plane; |
| 3059 | u32 temp; |
| 3060 | bool is_pch_port; |
| 3061 | |
| 3062 | if (intel_crtc->active) |
| 3063 | return; |
| 3064 | |
| 3065 | intel_crtc->active = true; |
| 3066 | intel_update_watermarks(dev); |
| 3067 | |
| 3068 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 3069 | temp = I915_READ(PCH_LVDS); |
| 3070 | if ((temp & LVDS_PORT_EN) == 0) |
| 3071 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
| 3072 | } |
| 3073 | |
| 3074 | is_pch_port = intel_crtc_driving_pch(crtc); |
| 3075 | |
| 3076 | if (is_pch_port) |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3077 | ironlake_fdi_pll_enable(crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3078 | else |
| 3079 | ironlake_fdi_disable(crtc); |
| 3080 | |
| 3081 | /* Enable panel fitting for LVDS */ |
| 3082 | if (dev_priv->pch_pf_size && |
| 3083 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
| 3084 | /* Force use of hard-coded filter coefficients |
| 3085 | * as some pre-programmed values are broken, |
| 3086 | * e.g. x201. |
| 3087 | */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3088 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
| 3089 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
| 3090 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3091 | } |
| 3092 | |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 3093 | /* |
| 3094 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 3095 | * clocks enabled |
| 3096 | */ |
| 3097 | intel_crtc_load_lut(crtc); |
| 3098 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3099 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
| 3100 | intel_enable_plane(dev_priv, plane, pipe); |
| 3101 | |
| 3102 | if (is_pch_port) |
| 3103 | ironlake_pch_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3104 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3105 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 3106 | intel_update_fbc(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3107 | mutex_unlock(&dev->struct_mutex); |
| 3108 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3109 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3110 | } |
| 3111 | |
| 3112 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 3113 | { |
| 3114 | struct drm_device *dev = crtc->dev; |
| 3115 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3117 | int pipe = intel_crtc->pipe; |
| 3118 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3119 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3120 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3121 | if (!intel_crtc->active) |
| 3122 | return; |
| 3123 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3124 | intel_crtc_wait_for_pending_flips(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3125 | drm_vblank_off(dev, pipe); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3126 | intel_crtc_update_cursor(crtc, false); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3127 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 3128 | intel_disable_plane(dev_priv, plane, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3129 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 3130 | if (dev_priv->cfb_plane == plane) |
| 3131 | intel_disable_fbc(dev); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3132 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 3133 | intel_disable_pipe(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3134 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3135 | /* Disable PF */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3136 | I915_WRITE(PF_CTL(pipe), 0); |
| 3137 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3138 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3139 | ironlake_fdi_disable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3140 | |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 3141 | /* This is a horrible layering violation; we should be doing this in |
| 3142 | * the connector/encoder ->prepare instead, but we don't always have |
| 3143 | * enough information there about the config to know whether it will |
| 3144 | * actually be necessary or just cause undesired flicker. |
| 3145 | */ |
| 3146 | intel_disable_pch_ports(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3147 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 3148 | intel_disable_transcoder(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3149 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3150 | if (HAS_PCH_CPT(dev)) { |
| 3151 | /* disable TRANS_DP_CTL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3152 | reg = TRANS_DP_CTL(pipe); |
| 3153 | temp = I915_READ(reg); |
| 3154 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
Eric Anholt | cb3543c | 2011-02-02 12:08:07 -0800 | [diff] [blame] | 3155 | temp |= TRANS_DP_PORT_SEL_NONE; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3156 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3157 | |
| 3158 | /* disable DPLL_SEL */ |
| 3159 | temp = I915_READ(PCH_DPLL_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3160 | switch (pipe) { |
| 3161 | case 0: |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 3162 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3163 | break; |
| 3164 | case 1: |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3165 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3166 | break; |
| 3167 | case 2: |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 3168 | /* C shares PLL A or B */ |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 3169 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3170 | break; |
| 3171 | default: |
| 3172 | BUG(); /* wtf */ |
| 3173 | } |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3174 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3175 | } |
| 3176 | |
| 3177 | /* disable PCH DPLL */ |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 3178 | if (!intel_crtc->no_pll) |
| 3179 | intel_disable_pch_pll(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3180 | |
| 3181 | /* Switch from PCDclk to Rawclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3182 | reg = FDI_RX_CTL(pipe); |
| 3183 | temp = I915_READ(reg); |
| 3184 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3185 | |
| 3186 | /* Disable CPU FDI TX PLL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3187 | reg = FDI_TX_CTL(pipe); |
| 3188 | temp = I915_READ(reg); |
| 3189 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 3190 | |
| 3191 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3192 | udelay(100); |
| 3193 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3194 | reg = FDI_RX_CTL(pipe); |
| 3195 | temp = I915_READ(reg); |
| 3196 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3197 | |
| 3198 | /* Wait for the clocks to turn off. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3199 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3200 | udelay(100); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3201 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3202 | intel_crtc->active = false; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3203 | intel_update_watermarks(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3204 | |
| 3205 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3206 | intel_update_fbc(dev); |
| 3207 | intel_clear_scanline_wait(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3208 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3209 | } |
| 3210 | |
| 3211 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 3212 | { |
| 3213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3214 | int pipe = intel_crtc->pipe; |
| 3215 | int plane = intel_crtc->plane; |
| 3216 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3217 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 3218 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 3219 | */ |
| 3220 | switch (mode) { |
| 3221 | case DRM_MODE_DPMS_ON: |
| 3222 | case DRM_MODE_DPMS_STANDBY: |
| 3223 | case DRM_MODE_DPMS_SUSPEND: |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 3224 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3225 | ironlake_crtc_enable(crtc); |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 3226 | break; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 3227 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3228 | case DRM_MODE_DPMS_OFF: |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 3229 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3230 | ironlake_crtc_disable(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3231 | break; |
| 3232 | } |
| 3233 | } |
| 3234 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 3235 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 3236 | { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 3237 | if (!enable && intel_crtc->overlay) { |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 3238 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3239 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 3240 | |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 3241 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3242 | dev_priv->mm.interruptible = false; |
| 3243 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 3244 | dev_priv->mm.interruptible = true; |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 3245 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 3246 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 3247 | |
Chris Wilson | 5dcdbcb | 2010-08-12 13:50:28 +0100 | [diff] [blame] | 3248 | /* Let userspace switch the overlay on again. In most cases userspace |
| 3249 | * has to recompute where to put it anyway. |
| 3250 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 3251 | } |
| 3252 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3253 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3254 | { |
| 3255 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3256 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3258 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3259 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3260 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3261 | if (intel_crtc->active) |
| 3262 | return; |
| 3263 | |
| 3264 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3265 | intel_update_watermarks(dev); |
| 3266 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 3267 | intel_enable_pll(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 3268 | intel_enable_pipe(dev_priv, pipe, false); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 3269 | intel_enable_plane(dev_priv, plane, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3270 | |
| 3271 | intel_crtc_load_lut(crtc); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 3272 | intel_update_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3273 | |
| 3274 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
| 3275 | intel_crtc_dpms_overlay(intel_crtc, true); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3276 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3277 | } |
| 3278 | |
| 3279 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 3280 | { |
| 3281 | struct drm_device *dev = crtc->dev; |
| 3282 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3284 | int pipe = intel_crtc->pipe; |
| 3285 | int plane = intel_crtc->plane; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3286 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3287 | if (!intel_crtc->active) |
| 3288 | return; |
| 3289 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3290 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3291 | intel_crtc_wait_for_pending_flips(crtc); |
| 3292 | drm_vblank_off(dev, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3293 | intel_crtc_dpms_overlay(intel_crtc, false); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3294 | intel_crtc_update_cursor(crtc, false); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3295 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 3296 | if (dev_priv->cfb_plane == plane) |
| 3297 | intel_disable_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3298 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 3299 | intel_disable_plane(dev_priv, plane, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 3300 | intel_disable_pipe(dev_priv, pipe); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 3301 | intel_disable_pll(dev_priv, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3302 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3303 | intel_crtc->active = false; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3304 | intel_update_fbc(dev); |
| 3305 | intel_update_watermarks(dev); |
| 3306 | intel_clear_scanline_wait(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3307 | } |
| 3308 | |
| 3309 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 3310 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3311 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 3312 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 3313 | */ |
| 3314 | switch (mode) { |
| 3315 | case DRM_MODE_DPMS_ON: |
| 3316 | case DRM_MODE_DPMS_STANDBY: |
| 3317 | case DRM_MODE_DPMS_SUSPEND: |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3318 | i9xx_crtc_enable(crtc); |
| 3319 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3320 | case DRM_MODE_DPMS_OFF: |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3321 | i9xx_crtc_disable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3322 | break; |
| 3323 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3324 | } |
| 3325 | |
| 3326 | /** |
| 3327 | * Sets the power management mode of the pipe and plane. |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3328 | */ |
| 3329 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 3330 | { |
| 3331 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3332 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3333 | struct drm_i915_master_private *master_priv; |
| 3334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3335 | int pipe = intel_crtc->pipe; |
| 3336 | bool enabled; |
| 3337 | |
Chris Wilson | 032d2a0 | 2010-09-06 16:17:22 +0100 | [diff] [blame] | 3338 | if (intel_crtc->dpms_mode == mode) |
| 3339 | return; |
| 3340 | |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 3341 | intel_crtc->dpms_mode = mode; |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 3342 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3343 | dev_priv->display.dpms(crtc, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3344 | |
| 3345 | if (!dev->primary->master) |
| 3346 | return; |
| 3347 | |
| 3348 | master_priv = dev->primary->master->driver_priv; |
| 3349 | if (!master_priv->sarea_priv) |
| 3350 | return; |
| 3351 | |
| 3352 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
| 3353 | |
| 3354 | switch (pipe) { |
| 3355 | case 0: |
| 3356 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 3357 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 3358 | break; |
| 3359 | case 1: |
| 3360 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 3361 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 3362 | break; |
| 3363 | default: |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3364 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3365 | break; |
| 3366 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3367 | } |
| 3368 | |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3369 | static void intel_crtc_disable(struct drm_crtc *crtc) |
| 3370 | { |
| 3371 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 3372 | struct drm_device *dev = crtc->dev; |
| 3373 | |
| 3374 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 3375 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
| 3376 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3377 | |
| 3378 | if (crtc->fb) { |
| 3379 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3380 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3381 | mutex_unlock(&dev->struct_mutex); |
| 3382 | } |
| 3383 | } |
| 3384 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3385 | /* Prepare for a mode set. |
| 3386 | * |
| 3387 | * Note we could be a lot smarter here. We need to figure out which outputs |
| 3388 | * will be enabled, which disabled (in short, how the config will changes) |
| 3389 | * and perform the minimum necessary steps to accomplish that, e.g. updating |
| 3390 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, |
| 3391 | * panel fitting is in the proper state, etc. |
| 3392 | */ |
| 3393 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3394 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3395 | i9xx_crtc_disable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3396 | } |
| 3397 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3398 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3399 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3400 | i9xx_crtc_enable(crtc); |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3401 | } |
| 3402 | |
| 3403 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) |
| 3404 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3405 | ironlake_crtc_disable(crtc); |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3406 | } |
| 3407 | |
| 3408 | static void ironlake_crtc_commit(struct drm_crtc *crtc) |
| 3409 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3410 | ironlake_crtc_enable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3411 | } |
| 3412 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3413 | void intel_encoder_prepare(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3414 | { |
| 3415 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 3416 | /* lvds has its own version of prepare see intel_lvds_prepare */ |
| 3417 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 3418 | } |
| 3419 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3420 | void intel_encoder_commit(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3421 | { |
| 3422 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3423 | struct drm_device *dev = encoder->dev; |
| 3424 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 3425 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
| 3426 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3427 | /* lvds has its own version of commit see intel_lvds_commit */ |
| 3428 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3429 | |
| 3430 | if (HAS_PCH_CPT(dev)) |
| 3431 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3432 | } |
| 3433 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3434 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 3435 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 3436 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3437 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3438 | drm_encoder_cleanup(encoder); |
| 3439 | kfree(intel_encoder); |
| 3440 | } |
| 3441 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3442 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
| 3443 | struct drm_display_mode *mode, |
| 3444 | struct drm_display_mode *adjusted_mode) |
| 3445 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3446 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 3447 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3448 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3449 | /* FDI link clock is fixed at 2.7G */ |
Jesse Barnes | 2377b74 | 2010-07-07 14:06:43 -0700 | [diff] [blame] | 3450 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
| 3451 | return false; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3452 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 3453 | |
Daniel Vetter | ca9bfa7 | 2012-01-28 14:49:20 +0100 | [diff] [blame] | 3454 | /* All interlaced capable intel hw wants timings in frames. */ |
| 3455 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 3456 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3457 | return true; |
| 3458 | } |
| 3459 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3460 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3461 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3462 | return 400000; |
| 3463 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3464 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3465 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 3466 | { |
| 3467 | return 333000; |
| 3468 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3469 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3470 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 3471 | { |
| 3472 | return 200000; |
| 3473 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3474 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3475 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 3476 | { |
| 3477 | u16 gcfgc = 0; |
| 3478 | |
| 3479 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3480 | |
| 3481 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3482 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3483 | else { |
| 3484 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 3485 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 3486 | return 333000; |
| 3487 | default: |
| 3488 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 3489 | return 190000; |
| 3490 | } |
| 3491 | } |
| 3492 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3493 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3494 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 3495 | { |
| 3496 | return 266000; |
| 3497 | } |
| 3498 | |
| 3499 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 3500 | { |
| 3501 | u16 hpllcc = 0; |
| 3502 | /* Assume that the hardware is in the high speed state. This |
| 3503 | * should be the default. |
| 3504 | */ |
| 3505 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 3506 | case GC_CLOCK_133_200: |
| 3507 | case GC_CLOCK_100_200: |
| 3508 | return 200000; |
| 3509 | case GC_CLOCK_166_250: |
| 3510 | return 250000; |
| 3511 | case GC_CLOCK_100_133: |
| 3512 | return 133000; |
| 3513 | } |
| 3514 | |
| 3515 | /* Shouldn't happen */ |
| 3516 | return 0; |
| 3517 | } |
| 3518 | |
| 3519 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 3520 | { |
| 3521 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3522 | } |
| 3523 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3524 | struct fdi_m_n { |
| 3525 | u32 tu; |
| 3526 | u32 gmch_m; |
| 3527 | u32 gmch_n; |
| 3528 | u32 link_m; |
| 3529 | u32 link_n; |
| 3530 | }; |
| 3531 | |
| 3532 | static void |
| 3533 | fdi_reduce_ratio(u32 *num, u32 *den) |
| 3534 | { |
| 3535 | while (*num > 0xffffff || *den > 0xffffff) { |
| 3536 | *num >>= 1; |
| 3537 | *den >>= 1; |
| 3538 | } |
| 3539 | } |
| 3540 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3541 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3542 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
| 3543 | int link_clock, struct fdi_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3544 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3545 | m_n->tu = 64; /* default size */ |
| 3546 | |
Chris Wilson | 22ed111 | 2010-12-04 01:01:29 +0000 | [diff] [blame] | 3547 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
| 3548 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
| 3549 | m_n->gmch_n = link_clock * nlanes * 8; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3550 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 3551 | |
Chris Wilson | 22ed111 | 2010-12-04 01:01:29 +0000 | [diff] [blame] | 3552 | m_n->link_m = pixel_clock; |
| 3553 | m_n->link_n = link_clock; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3554 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 3555 | } |
| 3556 | |
| 3557 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3558 | struct intel_watermark_params { |
| 3559 | unsigned long fifo_size; |
| 3560 | unsigned long max_wm; |
| 3561 | unsigned long default_wm; |
| 3562 | unsigned long guard_size; |
| 3563 | unsigned long cacheline_size; |
| 3564 | }; |
| 3565 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3566 | /* Pineview has different values for various configs */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3567 | static const struct intel_watermark_params pineview_display_wm = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3568 | PINEVIEW_DISPLAY_FIFO, |
| 3569 | PINEVIEW_MAX_WM, |
| 3570 | PINEVIEW_DFT_WM, |
| 3571 | PINEVIEW_GUARD_WM, |
| 3572 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3573 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3574 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3575 | PINEVIEW_DISPLAY_FIFO, |
| 3576 | PINEVIEW_MAX_WM, |
| 3577 | PINEVIEW_DFT_HPLLOFF_WM, |
| 3578 | PINEVIEW_GUARD_WM, |
| 3579 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3580 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3581 | static const struct intel_watermark_params pineview_cursor_wm = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3582 | PINEVIEW_CURSOR_FIFO, |
| 3583 | PINEVIEW_CURSOR_MAX_WM, |
| 3584 | PINEVIEW_CURSOR_DFT_WM, |
| 3585 | PINEVIEW_CURSOR_GUARD_WM, |
| 3586 | PINEVIEW_FIFO_LINE_SIZE, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3587 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3588 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3589 | PINEVIEW_CURSOR_FIFO, |
| 3590 | PINEVIEW_CURSOR_MAX_WM, |
| 3591 | PINEVIEW_CURSOR_DFT_WM, |
| 3592 | PINEVIEW_CURSOR_GUARD_WM, |
| 3593 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3594 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3595 | static const struct intel_watermark_params g4x_wm_info = { |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3596 | G4X_FIFO_SIZE, |
| 3597 | G4X_MAX_WM, |
| 3598 | G4X_MAX_WM, |
| 3599 | 2, |
| 3600 | G4X_FIFO_LINE_SIZE, |
| 3601 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3602 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3603 | I965_CURSOR_FIFO, |
| 3604 | I965_CURSOR_MAX_WM, |
| 3605 | I965_CURSOR_DFT_WM, |
| 3606 | 2, |
| 3607 | G4X_FIFO_LINE_SIZE, |
| 3608 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3609 | static const struct intel_watermark_params i965_cursor_wm_info = { |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3610 | I965_CURSOR_FIFO, |
| 3611 | I965_CURSOR_MAX_WM, |
| 3612 | I965_CURSOR_DFT_WM, |
| 3613 | 2, |
| 3614 | I915_FIFO_LINE_SIZE, |
| 3615 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3616 | static const struct intel_watermark_params i945_wm_info = { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3617 | I945_FIFO_SIZE, |
| 3618 | I915_MAX_WM, |
| 3619 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3620 | 2, |
| 3621 | I915_FIFO_LINE_SIZE |
| 3622 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3623 | static const struct intel_watermark_params i915_wm_info = { |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3624 | I915_FIFO_SIZE, |
| 3625 | I915_MAX_WM, |
| 3626 | 1, |
| 3627 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3628 | I915_FIFO_LINE_SIZE |
| 3629 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3630 | static const struct intel_watermark_params i855_wm_info = { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3631 | I855GM_FIFO_SIZE, |
| 3632 | I915_MAX_WM, |
| 3633 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3634 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3635 | I830_FIFO_LINE_SIZE |
| 3636 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3637 | static const struct intel_watermark_params i830_wm_info = { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3638 | I830_FIFO_SIZE, |
| 3639 | I915_MAX_WM, |
| 3640 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3641 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3642 | I830_FIFO_LINE_SIZE |
| 3643 | }; |
| 3644 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3645 | static const struct intel_watermark_params ironlake_display_wm_info = { |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3646 | ILK_DISPLAY_FIFO, |
| 3647 | ILK_DISPLAY_MAXWM, |
| 3648 | ILK_DISPLAY_DFTWM, |
| 3649 | 2, |
| 3650 | ILK_FIFO_LINE_SIZE |
| 3651 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3652 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3653 | ILK_CURSOR_FIFO, |
| 3654 | ILK_CURSOR_MAXWM, |
| 3655 | ILK_CURSOR_DFTWM, |
| 3656 | 2, |
| 3657 | ILK_FIFO_LINE_SIZE |
| 3658 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3659 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3660 | ILK_DISPLAY_SR_FIFO, |
| 3661 | ILK_DISPLAY_MAX_SRWM, |
| 3662 | ILK_DISPLAY_DFT_SRWM, |
| 3663 | 2, |
| 3664 | ILK_FIFO_LINE_SIZE |
| 3665 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3666 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3667 | ILK_CURSOR_SR_FIFO, |
| 3668 | ILK_CURSOR_MAX_SRWM, |
| 3669 | ILK_CURSOR_DFT_SRWM, |
| 3670 | 2, |
| 3671 | ILK_FIFO_LINE_SIZE |
| 3672 | }; |
| 3673 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3674 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 3675 | SNB_DISPLAY_FIFO, |
| 3676 | SNB_DISPLAY_MAXWM, |
| 3677 | SNB_DISPLAY_DFTWM, |
| 3678 | 2, |
| 3679 | SNB_FIFO_LINE_SIZE |
| 3680 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3681 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 3682 | SNB_CURSOR_FIFO, |
| 3683 | SNB_CURSOR_MAXWM, |
| 3684 | SNB_CURSOR_DFTWM, |
| 3685 | 2, |
| 3686 | SNB_FIFO_LINE_SIZE |
| 3687 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3688 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 3689 | SNB_DISPLAY_SR_FIFO, |
| 3690 | SNB_DISPLAY_MAX_SRWM, |
| 3691 | SNB_DISPLAY_DFT_SRWM, |
| 3692 | 2, |
| 3693 | SNB_FIFO_LINE_SIZE |
| 3694 | }; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3695 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 3696 | SNB_CURSOR_SR_FIFO, |
| 3697 | SNB_CURSOR_MAX_SRWM, |
| 3698 | SNB_CURSOR_DFT_SRWM, |
| 3699 | 2, |
| 3700 | SNB_FIFO_LINE_SIZE |
| 3701 | }; |
| 3702 | |
| 3703 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3704 | /** |
| 3705 | * intel_calculate_wm - calculate watermark level |
| 3706 | * @clock_in_khz: pixel clock |
| 3707 | * @wm: chip FIFO params |
| 3708 | * @pixel_size: display pixel size |
| 3709 | * @latency_ns: memory latency for the platform |
| 3710 | * |
| 3711 | * Calculate the watermark level (the level at which the display plane will |
| 3712 | * start fetching from memory again). Each chip has a different display |
| 3713 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 3714 | * in the correct intel_watermark_params structure. |
| 3715 | * |
| 3716 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 3717 | * on the pixel size. When it reaches the watermark level, it'll start |
| 3718 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 3719 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 3720 | * will occur, and a display engine hang could result. |
| 3721 | */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3722 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3723 | const struct intel_watermark_params *wm, |
| 3724 | int fifo_size, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3725 | int pixel_size, |
| 3726 | unsigned long latency_ns) |
| 3727 | { |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 3728 | long entries_required, wm_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3729 | |
Jesse Barnes | d660467 | 2009-09-11 12:25:56 -0700 | [diff] [blame] | 3730 | /* |
| 3731 | * Note: we need to make sure we don't overflow for various clock & |
| 3732 | * latency values. |
| 3733 | * clocks go from a few thousand to several hundred thousand. |
| 3734 | * latency is usually a few thousand |
| 3735 | */ |
| 3736 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 3737 | 1000; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3738 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3739 | |
Joe Perches | bbb0aef | 2011-04-17 20:35:52 -0700 | [diff] [blame] | 3740 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3741 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3742 | wm_size = fifo_size - (entries_required + wm->guard_size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3743 | |
Joe Perches | bbb0aef | 2011-04-17 20:35:52 -0700 | [diff] [blame] | 3744 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3745 | |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 3746 | /* Don't promote wm_size to unsigned... */ |
| 3747 | if (wm_size > (long)wm->max_wm) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3748 | wm_size = wm->max_wm; |
Chris Wilson | c3add4b | 2010-09-08 09:14:08 +0100 | [diff] [blame] | 3749 | if (wm_size <= 0) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3750 | wm_size = wm->default_wm; |
| 3751 | return wm_size; |
| 3752 | } |
| 3753 | |
| 3754 | struct cxsr_latency { |
| 3755 | int is_desktop; |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3756 | int is_ddr3; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3757 | unsigned long fsb_freq; |
| 3758 | unsigned long mem_freq; |
| 3759 | unsigned long display_sr; |
| 3760 | unsigned long display_hpll_disable; |
| 3761 | unsigned long cursor_sr; |
| 3762 | unsigned long cursor_hpll_disable; |
| 3763 | }; |
| 3764 | |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3765 | static const struct cxsr_latency cxsr_latency_table[] = { |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3766 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 3767 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 3768 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 3769 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 3770 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3771 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3772 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 3773 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 3774 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 3775 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 3776 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3777 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3778 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 3779 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 3780 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 3781 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 3782 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3783 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3784 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 3785 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 3786 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 3787 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 3788 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3789 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3790 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 3791 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 3792 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 3793 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 3794 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3795 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3796 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 3797 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 3798 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 3799 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 3800 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3801 | }; |
| 3802 | |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3803 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
| 3804 | int is_ddr3, |
| 3805 | int fsb, |
| 3806 | int mem) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3807 | { |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3808 | const struct cxsr_latency *latency; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3809 | int i; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3810 | |
| 3811 | if (fsb == 0 || mem == 0) |
| 3812 | return NULL; |
| 3813 | |
| 3814 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 3815 | latency = &cxsr_latency_table[i]; |
| 3816 | if (is_desktop == latency->is_desktop && |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3817 | is_ddr3 == latency->is_ddr3 && |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 3818 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 3819 | return latency; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3820 | } |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 3821 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3822 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 3823 | |
| 3824 | return NULL; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3825 | } |
| 3826 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3827 | static void pineview_disable_cxsr(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3828 | { |
| 3829 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3830 | |
| 3831 | /* deactivate cxsr */ |
Chris Wilson | 3e33d94 | 2010-08-04 11:17:25 +0100 | [diff] [blame] | 3832 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3833 | } |
| 3834 | |
Jesse Barnes | bcc24fb | 2009-08-31 10:24:31 -0700 | [diff] [blame] | 3835 | /* |
| 3836 | * Latency for FIFO fetches is dependent on several factors: |
| 3837 | * - memory configuration (speed, channels) |
| 3838 | * - chipset |
| 3839 | * - current MCH state |
| 3840 | * It can be fairly high in some situations, so here we assume a fairly |
| 3841 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 3842 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 3843 | * and power consumption (set it too low to save power and we might see |
| 3844 | * FIFO underruns and display "flicker"). |
| 3845 | * |
| 3846 | * A value of 5us seems to be a good balance; safe for very low end |
| 3847 | * platforms but not overly aggressive on lower latency configs. |
| 3848 | */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3849 | static const int latency_ns = 5000; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3850 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3851 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3852 | { |
| 3853 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3854 | uint32_t dsparb = I915_READ(DSPARB); |
| 3855 | int size; |
| 3856 | |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3857 | size = dsparb & 0x7f; |
| 3858 | if (plane) |
| 3859 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3860 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3861 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3862 | plane ? "B" : "A", size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3863 | |
| 3864 | return size; |
| 3865 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3866 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3867 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
| 3868 | { |
| 3869 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3870 | uint32_t dsparb = I915_READ(DSPARB); |
| 3871 | int size; |
| 3872 | |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3873 | size = dsparb & 0x1ff; |
| 3874 | if (plane) |
| 3875 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3876 | size >>= 1; /* Convert to cachelines */ |
| 3877 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3878 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3879 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3880 | |
| 3881 | return size; |
| 3882 | } |
| 3883 | |
| 3884 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
| 3885 | { |
| 3886 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3887 | uint32_t dsparb = I915_READ(DSPARB); |
| 3888 | int size; |
| 3889 | |
| 3890 | size = dsparb & 0x7f; |
| 3891 | size >>= 2; /* Convert to cachelines */ |
| 3892 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3893 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3894 | plane ? "B" : "A", |
| 3895 | size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3896 | |
| 3897 | return size; |
| 3898 | } |
| 3899 | |
| 3900 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
| 3901 | { |
| 3902 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3903 | uint32_t dsparb = I915_READ(DSPARB); |
| 3904 | int size; |
| 3905 | |
| 3906 | size = dsparb & 0x7f; |
| 3907 | size >>= 1; /* Convert to cachelines */ |
| 3908 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3909 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3910 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3911 | |
| 3912 | return size; |
| 3913 | } |
| 3914 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3915 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 3916 | { |
| 3917 | struct drm_crtc *crtc, *enabled = NULL; |
| 3918 | |
| 3919 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 3920 | if (crtc->enabled && crtc->fb) { |
| 3921 | if (enabled) |
| 3922 | return NULL; |
| 3923 | enabled = crtc; |
| 3924 | } |
| 3925 | } |
| 3926 | |
| 3927 | return enabled; |
| 3928 | } |
| 3929 | |
| 3930 | static void pineview_update_wm(struct drm_device *dev) |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3931 | { |
| 3932 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3933 | struct drm_crtc *crtc; |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3934 | const struct cxsr_latency *latency; |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3935 | u32 reg; |
| 3936 | unsigned long wm; |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3937 | |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3938 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3939 | dev_priv->fsb_freq, dev_priv->mem_freq); |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3940 | if (!latency) { |
| 3941 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 3942 | pineview_disable_cxsr(dev); |
| 3943 | return; |
| 3944 | } |
| 3945 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3946 | crtc = single_enabled_crtc(dev); |
| 3947 | if (crtc) { |
| 3948 | int clock = crtc->mode.clock; |
| 3949 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3950 | |
| 3951 | /* Display SR */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3952 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 3953 | pineview_display_wm.fifo_size, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3954 | pixel_size, latency->display_sr); |
| 3955 | reg = I915_READ(DSPFW1); |
| 3956 | reg &= ~DSPFW_SR_MASK; |
| 3957 | reg |= wm << DSPFW_SR_SHIFT; |
| 3958 | I915_WRITE(DSPFW1, reg); |
| 3959 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 3960 | |
| 3961 | /* cursor SR */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3962 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 3963 | pineview_display_wm.fifo_size, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3964 | pixel_size, latency->cursor_sr); |
| 3965 | reg = I915_READ(DSPFW3); |
| 3966 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 3967 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 3968 | I915_WRITE(DSPFW3, reg); |
| 3969 | |
| 3970 | /* Display HPLL off SR */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3971 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 3972 | pineview_display_hplloff_wm.fifo_size, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3973 | pixel_size, latency->display_hpll_disable); |
| 3974 | reg = I915_READ(DSPFW3); |
| 3975 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 3976 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 3977 | I915_WRITE(DSPFW3, reg); |
| 3978 | |
| 3979 | /* cursor HPLL off SR */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 3980 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 3981 | pineview_display_hplloff_wm.fifo_size, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3982 | pixel_size, latency->cursor_hpll_disable); |
| 3983 | reg = I915_READ(DSPFW3); |
| 3984 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 3985 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 3986 | I915_WRITE(DSPFW3, reg); |
| 3987 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 3988 | |
| 3989 | /* activate cxsr */ |
Chris Wilson | 3e33d94 | 2010-08-04 11:17:25 +0100 | [diff] [blame] | 3990 | I915_WRITE(DSPFW3, |
| 3991 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3992 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
| 3993 | } else { |
| 3994 | pineview_disable_cxsr(dev); |
| 3995 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
| 3996 | } |
| 3997 | } |
| 3998 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 3999 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 4000 | int plane, |
| 4001 | const struct intel_watermark_params *display, |
| 4002 | int display_latency_ns, |
| 4003 | const struct intel_watermark_params *cursor, |
| 4004 | int cursor_latency_ns, |
| 4005 | int *plane_wm, |
| 4006 | int *cursor_wm) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4007 | { |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4008 | struct drm_crtc *crtc; |
| 4009 | int htotal, hdisplay, clock, pixel_size; |
| 4010 | int line_time_us, line_count; |
| 4011 | int entries, tlb_miss; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4012 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4013 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 5c72d06 | 2011-04-13 09:28:23 +0100 | [diff] [blame] | 4014 | if (crtc->fb == NULL || !crtc->enabled) { |
| 4015 | *cursor_wm = cursor->guard_size; |
| 4016 | *plane_wm = display->guard_size; |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4017 | return false; |
Chris Wilson | 5c72d06 | 2011-04-13 09:28:23 +0100 | [diff] [blame] | 4018 | } |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4019 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4020 | htotal = crtc->mode.htotal; |
| 4021 | hdisplay = crtc->mode.hdisplay; |
| 4022 | clock = crtc->mode.clock; |
| 4023 | pixel_size = crtc->fb->bits_per_pixel / 8; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4024 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4025 | /* Use the small buffer method to calculate plane watermark */ |
| 4026 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 4027 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 4028 | if (tlb_miss > 0) |
| 4029 | entries += tlb_miss; |
| 4030 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 4031 | *plane_wm = entries + display->guard_size; |
| 4032 | if (*plane_wm > (int)display->max_wm) |
| 4033 | *plane_wm = display->max_wm; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4034 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4035 | /* Use the large buffer method to calculate cursor watermark */ |
| 4036 | line_time_us = ((htotal * 1000) / clock); |
| 4037 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
| 4038 | entries = line_count * 64 * pixel_size; |
| 4039 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 4040 | if (tlb_miss > 0) |
| 4041 | entries += tlb_miss; |
| 4042 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 4043 | *cursor_wm = entries + cursor->guard_size; |
| 4044 | if (*cursor_wm > (int)cursor->max_wm) |
| 4045 | *cursor_wm = (int)cursor->max_wm; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4046 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4047 | return true; |
| 4048 | } |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4049 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4050 | /* |
| 4051 | * Check the wm result. |
| 4052 | * |
| 4053 | * If any calculated watermark values is larger than the maximum value that |
| 4054 | * can be programmed into the associated watermark register, that watermark |
| 4055 | * must be disabled. |
| 4056 | */ |
| 4057 | static bool g4x_check_srwm(struct drm_device *dev, |
| 4058 | int display_wm, int cursor_wm, |
| 4059 | const struct intel_watermark_params *display, |
| 4060 | const struct intel_watermark_params *cursor) |
| 4061 | { |
| 4062 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 4063 | display_wm, cursor_wm); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4064 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4065 | if (display_wm > display->max_wm) { |
Joe Perches | bbb0aef | 2011-04-17 20:35:52 -0700 | [diff] [blame] | 4066 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4067 | display_wm, display->max_wm); |
| 4068 | return false; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4069 | } |
| 4070 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4071 | if (cursor_wm > cursor->max_wm) { |
Joe Perches | bbb0aef | 2011-04-17 20:35:52 -0700 | [diff] [blame] | 4072 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4073 | cursor_wm, cursor->max_wm); |
| 4074 | return false; |
| 4075 | } |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4076 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4077 | if (!(display_wm || cursor_wm)) { |
| 4078 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 4079 | return false; |
| 4080 | } |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4081 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4082 | return true; |
| 4083 | } |
| 4084 | |
| 4085 | static bool g4x_compute_srwm(struct drm_device *dev, |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4086 | int plane, |
| 4087 | int latency_ns, |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4088 | const struct intel_watermark_params *display, |
| 4089 | const struct intel_watermark_params *cursor, |
| 4090 | int *display_wm, int *cursor_wm) |
| 4091 | { |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4092 | struct drm_crtc *crtc; |
| 4093 | int hdisplay, htotal, pixel_size, clock; |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4094 | unsigned long line_time_us; |
| 4095 | int line_count, line_size; |
| 4096 | int small, large; |
| 4097 | int entries; |
| 4098 | |
| 4099 | if (!latency_ns) { |
| 4100 | *display_wm = *cursor_wm = 0; |
| 4101 | return false; |
| 4102 | } |
| 4103 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4104 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 4105 | hdisplay = crtc->mode.hdisplay; |
| 4106 | htotal = crtc->mode.htotal; |
| 4107 | clock = crtc->mode.clock; |
| 4108 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 4109 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4110 | line_time_us = (htotal * 1000) / clock; |
| 4111 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 4112 | line_size = hdisplay * pixel_size; |
| 4113 | |
| 4114 | /* Use the minimum of the small and large buffer method for primary */ |
| 4115 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 4116 | large = line_count * line_size; |
| 4117 | |
| 4118 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 4119 | *display_wm = entries + display->guard_size; |
| 4120 | |
| 4121 | /* calculate the self-refresh watermark for display cursor */ |
| 4122 | entries = line_count * pixel_size * 64; |
| 4123 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 4124 | *cursor_wm = entries + cursor->guard_size; |
| 4125 | |
| 4126 | return g4x_check_srwm(dev, |
| 4127 | *display_wm, *cursor_wm, |
| 4128 | display, cursor); |
| 4129 | } |
| 4130 | |
Yuanhan Liu | 7ccb4a5 | 2011-03-18 07:37:35 +0000 | [diff] [blame] | 4131 | #define single_plane_enabled(mask) is_power_of_2(mask) |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4132 | |
| 4133 | static void g4x_update_wm(struct drm_device *dev) |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4134 | { |
| 4135 | static const int sr_latency_ns = 12000; |
| 4136 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4137 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4138 | int plane_sr, cursor_sr; |
| 4139 | unsigned int enabled = 0; |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4140 | |
| 4141 | if (g4x_compute_wm0(dev, 0, |
| 4142 | &g4x_wm_info, latency_ns, |
| 4143 | &g4x_cursor_wm_info, latency_ns, |
| 4144 | &planea_wm, &cursora_wm)) |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4145 | enabled |= 1; |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4146 | |
| 4147 | if (g4x_compute_wm0(dev, 1, |
| 4148 | &g4x_wm_info, latency_ns, |
| 4149 | &g4x_cursor_wm_info, latency_ns, |
| 4150 | &planeb_wm, &cursorb_wm)) |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4151 | enabled |= 2; |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4152 | |
| 4153 | plane_sr = cursor_sr = 0; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4154 | if (single_plane_enabled(enabled) && |
| 4155 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 4156 | sr_latency_ns, |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4157 | &g4x_wm_info, |
| 4158 | &g4x_cursor_wm_info, |
| 4159 | &plane_sr, &cursor_sr)) |
| 4160 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 4161 | else |
| 4162 | I915_WRITE(FW_BLC_SELF, |
| 4163 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
| 4164 | |
Chris Wilson | 308977a | 2011-02-02 10:41:20 +0000 | [diff] [blame] | 4165 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 4166 | planea_wm, cursora_wm, |
| 4167 | planeb_wm, cursorb_wm, |
| 4168 | plane_sr, cursor_sr); |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4169 | |
| 4170 | I915_WRITE(DSPFW1, |
| 4171 | (plane_sr << DSPFW_SR_SHIFT) | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4172 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4173 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 4174 | planea_wm); |
| 4175 | I915_WRITE(DSPFW2, |
| 4176 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4177 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 4178 | /* HPLL off in SR has some issues on G4x... disable it */ |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4179 | I915_WRITE(DSPFW3, |
| 4180 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 4181 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4182 | } |
| 4183 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4184 | static void i965_update_wm(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4185 | { |
| 4186 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4187 | struct drm_crtc *crtc; |
| 4188 | int srwm = 1; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 4189 | int cursor_sr = 16; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4190 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 4191 | /* Calc sr entries for one plane configs */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4192 | crtc = single_enabled_crtc(dev); |
| 4193 | if (crtc) { |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 4194 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 4195 | static const int sr_latency_ns = 12000; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4196 | int clock = crtc->mode.clock; |
| 4197 | int htotal = crtc->mode.htotal; |
| 4198 | int hdisplay = crtc->mode.hdisplay; |
| 4199 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
| 4200 | unsigned long line_time_us; |
| 4201 | int entries; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 4202 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4203 | line_time_us = ((htotal * 1000) / clock); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 4204 | |
| 4205 | /* Use ns/us then divide to preserve precision */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4206 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 4207 | pixel_size * hdisplay; |
| 4208 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4209 | srwm = I965_FIFO_SIZE - entries; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 4210 | if (srwm < 0) |
| 4211 | srwm = 1; |
Zhao Yakui | 1b07e04 | 2010-06-12 14:32:24 +0800 | [diff] [blame] | 4212 | srwm &= 0x1ff; |
Chris Wilson | 308977a | 2011-02-02 10:41:20 +0000 | [diff] [blame] | 4213 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 4214 | entries, srwm); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 4215 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4216 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4217 | pixel_size * 64; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4218 | entries = DIV_ROUND_UP(entries, |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 4219 | i965_cursor_wm_info.cacheline_size); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 4220 | cursor_sr = i965_cursor_wm_info.fifo_size - |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4221 | (entries + i965_cursor_wm_info.guard_size); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 4222 | |
| 4223 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 4224 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 4225 | |
| 4226 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 4227 | "cursor %d\n", srwm, cursor_sr); |
| 4228 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4229 | if (IS_CRESTLINE(dev)) |
Jesse Barnes | adcdbc6 | 2010-06-30 13:49:37 -0700 | [diff] [blame] | 4230 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 4231 | } else { |
| 4232 | /* Turn off self refresh if both pipes are enabled */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4233 | if (IS_CRESTLINE(dev)) |
Jesse Barnes | adcdbc6 | 2010-06-30 13:49:37 -0700 | [diff] [blame] | 4234 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 4235 | & ~FW_BLC_SELF_EN); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 4236 | } |
| 4237 | |
| 4238 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 4239 | srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4240 | |
| 4241 | /* 965 has limitations... */ |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 4242 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
| 4243 | (8 << 16) | (8 << 8) | (8 << 0)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4244 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 4245 | /* update cursor SR watermark */ |
| 4246 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4247 | } |
| 4248 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4249 | static void i9xx_update_wm(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4250 | { |
| 4251 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4252 | const struct intel_watermark_params *wm_info; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4253 | uint32_t fwater_lo; |
| 4254 | uint32_t fwater_hi; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4255 | int cwm, srwm = 1; |
| 4256 | int fifo_size; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4257 | int planea_wm, planeb_wm; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4258 | struct drm_crtc *crtc, *enabled = NULL; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4259 | |
Chris Wilson | 72557b4 | 2011-01-31 10:29:55 +0000 | [diff] [blame] | 4260 | if (IS_I945GM(dev)) |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4261 | wm_info = &i945_wm_info; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4262 | else if (!IS_GEN2(dev)) |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4263 | wm_info = &i915_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4264 | else |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4265 | wm_info = &i855_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4266 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4267 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 4268 | crtc = intel_get_crtc_for_plane(dev, 0); |
| 4269 | if (crtc->enabled && crtc->fb) { |
| 4270 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
| 4271 | wm_info, fifo_size, |
| 4272 | crtc->fb->bits_per_pixel / 8, |
| 4273 | latency_ns); |
| 4274 | enabled = crtc; |
| 4275 | } else |
| 4276 | planea_wm = fifo_size - wm_info->guard_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4277 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4278 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 4279 | crtc = intel_get_crtc_for_plane(dev, 1); |
| 4280 | if (crtc->enabled && crtc->fb) { |
| 4281 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
| 4282 | wm_info, fifo_size, |
| 4283 | crtc->fb->bits_per_pixel / 8, |
| 4284 | latency_ns); |
| 4285 | if (enabled == NULL) |
| 4286 | enabled = crtc; |
| 4287 | else |
| 4288 | enabled = NULL; |
| 4289 | } else |
| 4290 | planeb_wm = fifo_size - wm_info->guard_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4291 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4292 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4293 | |
| 4294 | /* |
| 4295 | * Overlay gets an aggressive default since video jitter is bad. |
| 4296 | */ |
| 4297 | cwm = 2; |
| 4298 | |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 4299 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
| 4300 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 4301 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
| 4302 | else if (IS_I915GM(dev)) |
| 4303 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
| 4304 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4305 | /* Calc sr entries for one plane configs */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4306 | if (HAS_FW_BLC(dev) && enabled) { |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4307 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 4308 | static const int sr_latency_ns = 6000; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4309 | int clock = enabled->mode.clock; |
| 4310 | int htotal = enabled->mode.htotal; |
| 4311 | int hdisplay = enabled->mode.hdisplay; |
| 4312 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
| 4313 | unsigned long line_time_us; |
| 4314 | int entries; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4315 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4316 | line_time_us = (htotal * 1000) / clock; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4317 | |
| 4318 | /* Use ns/us then divide to preserve precision */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4319 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 4320 | pixel_size * hdisplay; |
| 4321 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 4322 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 4323 | srwm = wm_info->fifo_size - entries; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4324 | if (srwm < 0) |
| 4325 | srwm = 1; |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 4326 | |
| 4327 | if (IS_I945G(dev) || IS_I945GM(dev)) |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 4328 | I915_WRITE(FW_BLC_SELF, |
| 4329 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 4330 | else if (IS_I915GM(dev)) |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 4331 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4332 | } |
| 4333 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4334 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4335 | planea_wm, planeb_wm, cwm, srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4336 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4337 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 4338 | fwater_hi = (cwm & 0x1f); |
| 4339 | |
| 4340 | /* Set request length to 8 cachelines per fetch */ |
| 4341 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 4342 | fwater_hi = fwater_hi | (1 << 8); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4343 | |
| 4344 | I915_WRITE(FW_BLC, fwater_lo); |
| 4345 | I915_WRITE(FW_BLC2, fwater_hi); |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 4346 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4347 | if (HAS_FW_BLC(dev)) { |
| 4348 | if (enabled) { |
| 4349 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 4350 | I915_WRITE(FW_BLC_SELF, |
| 4351 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
| 4352 | else if (IS_I915GM(dev)) |
| 4353 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
| 4354 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
| 4355 | } else |
| 4356 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
| 4357 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4358 | } |
| 4359 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4360 | static void i830_update_wm(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4361 | { |
| 4362 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4363 | struct drm_crtc *crtc; |
| 4364 | uint32_t fwater_lo; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 4365 | int planea_wm; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4366 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4367 | crtc = single_enabled_crtc(dev); |
| 4368 | if (crtc == NULL) |
| 4369 | return; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4370 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4371 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
| 4372 | dev_priv->display.get_fifo_size(dev, 0), |
| 4373 | crtc->fb->bits_per_pixel / 8, |
| 4374 | latency_ns); |
| 4375 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 4376 | fwater_lo |= (3<<8) | planea_wm; |
| 4377 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4378 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4379 | |
| 4380 | I915_WRITE(FW_BLC, fwater_lo); |
| 4381 | } |
| 4382 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4383 | #define ILK_LP0_PLANE_LATENCY 700 |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 4384 | #define ILK_LP0_CURSOR_LATENCY 1300 |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4385 | |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4386 | /* |
| 4387 | * Check the wm result. |
| 4388 | * |
| 4389 | * If any calculated watermark values is larger than the maximum value that |
| 4390 | * can be programmed into the associated watermark register, that watermark |
| 4391 | * must be disabled. |
| 4392 | */ |
| 4393 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
| 4394 | int fbc_wm, int display_wm, int cursor_wm, |
| 4395 | const struct intel_watermark_params *display, |
| 4396 | const struct intel_watermark_params *cursor) |
| 4397 | { |
| 4398 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4399 | |
| 4400 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
| 4401 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
| 4402 | |
| 4403 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
| 4404 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
| 4405 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
| 4406 | |
| 4407 | /* fbc has it's own way to disable FBC WM */ |
| 4408 | I915_WRITE(DISP_ARB_CTL, |
| 4409 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
| 4410 | return false; |
| 4411 | } |
| 4412 | |
| 4413 | if (display_wm > display->max_wm) { |
| 4414 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
| 4415 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
| 4416 | return false; |
| 4417 | } |
| 4418 | |
| 4419 | if (cursor_wm > cursor->max_wm) { |
| 4420 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
| 4421 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
| 4422 | return false; |
| 4423 | } |
| 4424 | |
| 4425 | if (!(fbc_wm || display_wm || cursor_wm)) { |
| 4426 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
| 4427 | return false; |
| 4428 | } |
| 4429 | |
| 4430 | return true; |
| 4431 | } |
| 4432 | |
| 4433 | /* |
| 4434 | * Compute watermark values of WM[1-3], |
| 4435 | */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4436 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
| 4437 | int latency_ns, |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4438 | const struct intel_watermark_params *display, |
| 4439 | const struct intel_watermark_params *cursor, |
| 4440 | int *fbc_wm, int *display_wm, int *cursor_wm) |
| 4441 | { |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4442 | struct drm_crtc *crtc; |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4443 | unsigned long line_time_us; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4444 | int hdisplay, htotal, pixel_size, clock; |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4445 | int line_count, line_size; |
| 4446 | int small, large; |
| 4447 | int entries; |
| 4448 | |
| 4449 | if (!latency_ns) { |
| 4450 | *fbc_wm = *display_wm = *cursor_wm = 0; |
| 4451 | return false; |
| 4452 | } |
| 4453 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4454 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 4455 | hdisplay = crtc->mode.hdisplay; |
| 4456 | htotal = crtc->mode.htotal; |
| 4457 | clock = crtc->mode.clock; |
| 4458 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 4459 | |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4460 | line_time_us = (htotal * 1000) / clock; |
| 4461 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 4462 | line_size = hdisplay * pixel_size; |
| 4463 | |
| 4464 | /* Use the minimum of the small and large buffer method for primary */ |
| 4465 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 4466 | large = line_count * line_size; |
| 4467 | |
| 4468 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 4469 | *display_wm = entries + display->guard_size; |
| 4470 | |
| 4471 | /* |
| 4472 | * Spec says: |
| 4473 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
| 4474 | */ |
| 4475 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
| 4476 | |
| 4477 | /* calculate the self-refresh watermark for display cursor */ |
| 4478 | entries = line_count * pixel_size * 64; |
| 4479 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 4480 | *cursor_wm = entries + cursor->guard_size; |
| 4481 | |
| 4482 | return ironlake_check_srwm(dev, level, |
| 4483 | *fbc_wm, *display_wm, *cursor_wm, |
| 4484 | display, cursor); |
| 4485 | } |
| 4486 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4487 | static void ironlake_update_wm(struct drm_device *dev) |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4488 | { |
| 4489 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4490 | int fbc_wm, plane_wm, cursor_wm; |
| 4491 | unsigned int enabled; |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 4492 | |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 4493 | enabled = 0; |
Chris Wilson | 9f40510 | 2011-05-12 22:17:14 +0100 | [diff] [blame] | 4494 | if (g4x_compute_wm0(dev, 0, |
| 4495 | &ironlake_display_wm_info, |
| 4496 | ILK_LP0_PLANE_LATENCY, |
| 4497 | &ironlake_cursor_wm_info, |
| 4498 | ILK_LP0_CURSOR_LATENCY, |
| 4499 | &plane_wm, &cursor_wm)) { |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 4500 | I915_WRITE(WM0_PIPEA_ILK, |
| 4501 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 4502 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 4503 | " plane %d, " "cursor: %d\n", |
| 4504 | plane_wm, cursor_wm); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4505 | enabled |= 1; |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 4506 | } |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4507 | |
Chris Wilson | 9f40510 | 2011-05-12 22:17:14 +0100 | [diff] [blame] | 4508 | if (g4x_compute_wm0(dev, 1, |
| 4509 | &ironlake_display_wm_info, |
| 4510 | ILK_LP0_PLANE_LATENCY, |
| 4511 | &ironlake_cursor_wm_info, |
| 4512 | ILK_LP0_CURSOR_LATENCY, |
| 4513 | &plane_wm, &cursor_wm)) { |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 4514 | I915_WRITE(WM0_PIPEB_ILK, |
| 4515 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 4516 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 4517 | " plane %d, cursor: %d\n", |
| 4518 | plane_wm, cursor_wm); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4519 | enabled |= 2; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4520 | } |
| 4521 | |
| 4522 | /* |
| 4523 | * Calculate and update the self-refresh watermark only when one |
| 4524 | * display plane is used. |
| 4525 | */ |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4526 | I915_WRITE(WM3_LP_ILK, 0); |
| 4527 | I915_WRITE(WM2_LP_ILK, 0); |
| 4528 | I915_WRITE(WM1_LP_ILK, 0); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4529 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4530 | if (!single_plane_enabled(enabled)) |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4531 | return; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4532 | enabled = ffs(enabled) - 1; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 4533 | |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4534 | /* WM1 */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4535 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 4536 | ILK_READ_WM1_LATENCY() * 500, |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4537 | &ironlake_display_srwm_info, |
| 4538 | &ironlake_cursor_srwm_info, |
| 4539 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 4540 | return; |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 4541 | |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4542 | I915_WRITE(WM1_LP_ILK, |
| 4543 | WM1_LP_SR_EN | |
| 4544 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 4545 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 4546 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 4547 | cursor_wm); |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 4548 | |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4549 | /* WM2 */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4550 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 4551 | ILK_READ_WM2_LATENCY() * 500, |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4552 | &ironlake_display_srwm_info, |
| 4553 | &ironlake_cursor_srwm_info, |
| 4554 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 4555 | return; |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 4556 | |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4557 | I915_WRITE(WM2_LP_ILK, |
| 4558 | WM2_LP_EN | |
| 4559 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 4560 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 4561 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 4562 | cursor_wm); |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4563 | |
| 4564 | /* |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4565 | * WM3 is unsupported on ILK, probably because we don't have latency |
| 4566 | * data for that power state |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4567 | */ |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4568 | } |
| 4569 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4570 | void sandybridge_update_wm(struct drm_device *dev) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4571 | { |
| 4572 | struct drm_i915_private *dev_priv = dev->dev_private; |
Yuanhan Liu | a0fa62d | 2010-12-23 16:35:40 +0800 | [diff] [blame] | 4573 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
Jesse Barnes | 4784264 | 2012-01-16 11:57:54 -0800 | [diff] [blame] | 4574 | u32 val; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4575 | int fbc_wm, plane_wm, cursor_wm; |
| 4576 | unsigned int enabled; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4577 | |
| 4578 | enabled = 0; |
Chris Wilson | 9f40510 | 2011-05-12 22:17:14 +0100 | [diff] [blame] | 4579 | if (g4x_compute_wm0(dev, 0, |
| 4580 | &sandybridge_display_wm_info, latency, |
| 4581 | &sandybridge_cursor_wm_info, latency, |
| 4582 | &plane_wm, &cursor_wm)) { |
Jesse Barnes | 4784264 | 2012-01-16 11:57:54 -0800 | [diff] [blame] | 4583 | val = I915_READ(WM0_PIPEA_ILK); |
| 4584 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 4585 | I915_WRITE(WM0_PIPEA_ILK, val | |
| 4586 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4587 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 4588 | " plane %d, " "cursor: %d\n", |
| 4589 | plane_wm, cursor_wm); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4590 | enabled |= 1; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4591 | } |
| 4592 | |
Chris Wilson | 9f40510 | 2011-05-12 22:17:14 +0100 | [diff] [blame] | 4593 | if (g4x_compute_wm0(dev, 1, |
| 4594 | &sandybridge_display_wm_info, latency, |
| 4595 | &sandybridge_cursor_wm_info, latency, |
| 4596 | &plane_wm, &cursor_wm)) { |
Jesse Barnes | 4784264 | 2012-01-16 11:57:54 -0800 | [diff] [blame] | 4597 | val = I915_READ(WM0_PIPEB_ILK); |
| 4598 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 4599 | I915_WRITE(WM0_PIPEB_ILK, val | |
| 4600 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4601 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 4602 | " plane %d, cursor: %d\n", |
| 4603 | plane_wm, cursor_wm); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4604 | enabled |= 2; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4605 | } |
| 4606 | |
Jesse Barnes | d6c892d | 2011-10-12 15:36:42 -0700 | [diff] [blame] | 4607 | /* IVB has 3 pipes */ |
| 4608 | if (IS_IVYBRIDGE(dev) && |
| 4609 | g4x_compute_wm0(dev, 2, |
| 4610 | &sandybridge_display_wm_info, latency, |
| 4611 | &sandybridge_cursor_wm_info, latency, |
| 4612 | &plane_wm, &cursor_wm)) { |
Jesse Barnes | 4784264 | 2012-01-16 11:57:54 -0800 | [diff] [blame] | 4613 | val = I915_READ(WM0_PIPEC_IVB); |
| 4614 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 4615 | I915_WRITE(WM0_PIPEC_IVB, val | |
| 4616 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
Jesse Barnes | d6c892d | 2011-10-12 15:36:42 -0700 | [diff] [blame] | 4617 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
| 4618 | " plane %d, cursor: %d\n", |
| 4619 | plane_wm, cursor_wm); |
| 4620 | enabled |= 3; |
| 4621 | } |
| 4622 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4623 | /* |
| 4624 | * Calculate and update the self-refresh watermark only when one |
| 4625 | * display plane is used. |
| 4626 | * |
| 4627 | * SNB support 3 levels of watermark. |
| 4628 | * |
| 4629 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
| 4630 | * and disabled in the descending order |
| 4631 | * |
| 4632 | */ |
| 4633 | I915_WRITE(WM3_LP_ILK, 0); |
| 4634 | I915_WRITE(WM2_LP_ILK, 0); |
| 4635 | I915_WRITE(WM1_LP_ILK, 0); |
| 4636 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4637 | if (!single_plane_enabled(enabled) || |
| 4638 | dev_priv->sprite_scaling_enabled) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4639 | return; |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4640 | enabled = ffs(enabled) - 1; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4641 | |
| 4642 | /* WM1 */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4643 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 4644 | SNB_READ_WM1_LATENCY() * 500, |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4645 | &sandybridge_display_srwm_info, |
| 4646 | &sandybridge_cursor_srwm_info, |
| 4647 | &fbc_wm, &plane_wm, &cursor_wm)) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4648 | return; |
| 4649 | |
| 4650 | I915_WRITE(WM1_LP_ILK, |
| 4651 | WM1_LP_SR_EN | |
| 4652 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 4653 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 4654 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 4655 | cursor_wm); |
| 4656 | |
| 4657 | /* WM2 */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4658 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 4659 | SNB_READ_WM2_LATENCY() * 500, |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4660 | &sandybridge_display_srwm_info, |
| 4661 | &sandybridge_cursor_srwm_info, |
| 4662 | &fbc_wm, &plane_wm, &cursor_wm)) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4663 | return; |
| 4664 | |
| 4665 | I915_WRITE(WM2_LP_ILK, |
| 4666 | WM2_LP_EN | |
| 4667 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 4668 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 4669 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 4670 | cursor_wm); |
| 4671 | |
| 4672 | /* WM3 */ |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4673 | if (!ironlake_compute_srwm(dev, 3, enabled, |
| 4674 | SNB_READ_WM3_LATENCY() * 500, |
Jesse Barnes | b79d499 | 2010-12-21 13:10:23 -0800 | [diff] [blame] | 4675 | &sandybridge_display_srwm_info, |
| 4676 | &sandybridge_cursor_srwm_info, |
| 4677 | &fbc_wm, &plane_wm, &cursor_wm)) |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 4678 | return; |
| 4679 | |
| 4680 | I915_WRITE(WM3_LP_ILK, |
| 4681 | WM3_LP_EN | |
| 4682 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 4683 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 4684 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 4685 | cursor_wm); |
| 4686 | } |
| 4687 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4688 | static bool |
| 4689 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
| 4690 | uint32_t sprite_width, int pixel_size, |
| 4691 | const struct intel_watermark_params *display, |
| 4692 | int display_latency_ns, int *sprite_wm) |
| 4693 | { |
| 4694 | struct drm_crtc *crtc; |
| 4695 | int clock; |
| 4696 | int entries, tlb_miss; |
| 4697 | |
| 4698 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 4699 | if (crtc->fb == NULL || !crtc->enabled) { |
| 4700 | *sprite_wm = display->guard_size; |
| 4701 | return false; |
| 4702 | } |
| 4703 | |
| 4704 | clock = crtc->mode.clock; |
| 4705 | |
| 4706 | /* Use the small buffer method to calculate the sprite watermark */ |
| 4707 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 4708 | tlb_miss = display->fifo_size*display->cacheline_size - |
| 4709 | sprite_width * 8; |
| 4710 | if (tlb_miss > 0) |
| 4711 | entries += tlb_miss; |
| 4712 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 4713 | *sprite_wm = entries + display->guard_size; |
| 4714 | if (*sprite_wm > (int)display->max_wm) |
| 4715 | *sprite_wm = display->max_wm; |
| 4716 | |
| 4717 | return true; |
| 4718 | } |
| 4719 | |
| 4720 | static bool |
| 4721 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
| 4722 | uint32_t sprite_width, int pixel_size, |
| 4723 | const struct intel_watermark_params *display, |
| 4724 | int latency_ns, int *sprite_wm) |
| 4725 | { |
| 4726 | struct drm_crtc *crtc; |
| 4727 | unsigned long line_time_us; |
| 4728 | int clock; |
| 4729 | int line_count, line_size; |
| 4730 | int small, large; |
| 4731 | int entries; |
| 4732 | |
| 4733 | if (!latency_ns) { |
| 4734 | *sprite_wm = 0; |
| 4735 | return false; |
| 4736 | } |
| 4737 | |
| 4738 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 4739 | clock = crtc->mode.clock; |
Hai Lan | 4e9bb47 | 2012-02-15 19:07:02 +0800 | [diff] [blame] | 4740 | if (!clock) { |
| 4741 | *sprite_wm = 0; |
| 4742 | return false; |
| 4743 | } |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4744 | |
| 4745 | line_time_us = (sprite_width * 1000) / clock; |
Hai Lan | 4e9bb47 | 2012-02-15 19:07:02 +0800 | [diff] [blame] | 4746 | if (!line_time_us) { |
| 4747 | *sprite_wm = 0; |
| 4748 | return false; |
| 4749 | } |
| 4750 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4751 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 4752 | line_size = sprite_width * pixel_size; |
| 4753 | |
| 4754 | /* Use the minimum of the small and large buffer method for primary */ |
| 4755 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 4756 | large = line_count * line_size; |
| 4757 | |
| 4758 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 4759 | *sprite_wm = entries + display->guard_size; |
| 4760 | |
| 4761 | return *sprite_wm > 0x3ff ? false : true; |
| 4762 | } |
| 4763 | |
| 4764 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
| 4765 | uint32_t sprite_width, int pixel_size) |
| 4766 | { |
| 4767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4768 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
Jesse Barnes | 4784264 | 2012-01-16 11:57:54 -0800 | [diff] [blame] | 4769 | u32 val; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4770 | int sprite_wm, reg; |
| 4771 | int ret; |
| 4772 | |
| 4773 | switch (pipe) { |
| 4774 | case 0: |
| 4775 | reg = WM0_PIPEA_ILK; |
| 4776 | break; |
| 4777 | case 1: |
| 4778 | reg = WM0_PIPEB_ILK; |
| 4779 | break; |
| 4780 | case 2: |
| 4781 | reg = WM0_PIPEC_IVB; |
| 4782 | break; |
| 4783 | default: |
| 4784 | return; /* bad pipe */ |
| 4785 | } |
| 4786 | |
| 4787 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
| 4788 | &sandybridge_display_wm_info, |
| 4789 | latency, &sprite_wm); |
| 4790 | if (!ret) { |
| 4791 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", |
| 4792 | pipe); |
| 4793 | return; |
| 4794 | } |
| 4795 | |
Jesse Barnes | 4784264 | 2012-01-16 11:57:54 -0800 | [diff] [blame] | 4796 | val = I915_READ(reg); |
| 4797 | val &= ~WM0_PIPE_SPRITE_MASK; |
| 4798 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4799 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
| 4800 | |
| 4801 | |
| 4802 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 4803 | pixel_size, |
| 4804 | &sandybridge_display_srwm_info, |
| 4805 | SNB_READ_WM1_LATENCY() * 500, |
| 4806 | &sprite_wm); |
| 4807 | if (!ret) { |
| 4808 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", |
| 4809 | pipe); |
| 4810 | return; |
| 4811 | } |
| 4812 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
| 4813 | |
| 4814 | /* Only IVB has two more LP watermarks for sprite */ |
| 4815 | if (!IS_IVYBRIDGE(dev)) |
| 4816 | return; |
| 4817 | |
| 4818 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 4819 | pixel_size, |
| 4820 | &sandybridge_display_srwm_info, |
| 4821 | SNB_READ_WM2_LATENCY() * 500, |
| 4822 | &sprite_wm); |
| 4823 | if (!ret) { |
| 4824 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", |
| 4825 | pipe); |
| 4826 | return; |
| 4827 | } |
| 4828 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
| 4829 | |
| 4830 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 4831 | pixel_size, |
| 4832 | &sandybridge_display_srwm_info, |
| 4833 | SNB_READ_WM3_LATENCY() * 500, |
| 4834 | &sprite_wm); |
| 4835 | if (!ret) { |
| 4836 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", |
| 4837 | pipe); |
| 4838 | return; |
| 4839 | } |
| 4840 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
| 4841 | } |
| 4842 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4843 | /** |
| 4844 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 4845 | * |
| 4846 | * Calculate watermark values for the various WM regs based on current mode |
| 4847 | * and plane configuration. |
| 4848 | * |
| 4849 | * There are several cases to deal with here: |
| 4850 | * - normal (i.e. non-self-refresh) |
| 4851 | * - self-refresh (SR) mode |
| 4852 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 4853 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 4854 | * lines), so need to account for TLB latency |
| 4855 | * |
| 4856 | * The normal calculation is: |
| 4857 | * watermark = dotclock * bytes per pixel * latency |
| 4858 | * where latency is platform & configuration dependent (we assume pessimal |
| 4859 | * values here). |
| 4860 | * |
| 4861 | * The SR calculation is: |
| 4862 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 4863 | * bytes per pixel |
| 4864 | * where |
| 4865 | * line time = htotal / dotclock |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 4866 | * surface width = hdisplay for normal plane and 64 for cursor |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4867 | * and latency is assumed to be high, as above. |
| 4868 | * |
| 4869 | * The final value programmed to the register should always be rounded up, |
| 4870 | * and include an extra 2 entries to account for clock crossings. |
| 4871 | * |
| 4872 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 4873 | * to set the non-SR watermarks to 8. |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4874 | */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4875 | static void intel_update_watermarks(struct drm_device *dev) |
| 4876 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4877 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4878 | |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 4879 | if (dev_priv->display.update_wm) |
| 4880 | dev_priv->display.update_wm(dev); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4881 | } |
| 4882 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 4883 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
| 4884 | uint32_t sprite_width, int pixel_size) |
| 4885 | { |
| 4886 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4887 | |
| 4888 | if (dev_priv->display.update_sprite_wm) |
| 4889 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
| 4890 | pixel_size); |
| 4891 | } |
| 4892 | |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 4893 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 4894 | { |
Keith Packard | 72bbe58 | 2011-09-26 16:09:45 -0700 | [diff] [blame] | 4895 | if (i915_panel_use_ssc >= 0) |
| 4896 | return i915_panel_use_ssc != 0; |
| 4897 | return dev_priv->lvds_use_ssc |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 4898 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 4899 | } |
| 4900 | |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4901 | /** |
| 4902 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send |
| 4903 | * @crtc: CRTC structure |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 4904 | * @mode: requested mode |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4905 | * |
| 4906 | * A pipe may be connected to one or more outputs. Based on the depth of the |
| 4907 | * attached framebuffer, choose a good color depth to use on the pipe. |
| 4908 | * |
| 4909 | * If possible, match the pipe depth to the fb depth. In some cases, this |
| 4910 | * isn't ideal, because the connected output supports a lesser or restricted |
| 4911 | * set of depths. Resolve that here: |
| 4912 | * LVDS typically supports only 6bpc, so clamp down in that case |
| 4913 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc |
| 4914 | * Displays may support a restricted set as well, check EDID and clamp as |
| 4915 | * appropriate. |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 4916 | * DP may want to dither down to 6bpc to fit larger modes |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4917 | * |
| 4918 | * RETURNS: |
| 4919 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, |
| 4920 | * true if they don't match). |
| 4921 | */ |
| 4922 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 4923 | unsigned int *pipe_bpp, |
| 4924 | struct drm_display_mode *mode) |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4925 | { |
| 4926 | struct drm_device *dev = crtc->dev; |
| 4927 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4928 | struct drm_encoder *encoder; |
| 4929 | struct drm_connector *connector; |
| 4930 | unsigned int display_bpc = UINT_MAX, bpc; |
| 4931 | |
| 4932 | /* Walk the encoders & connectors on this crtc, get min bpc */ |
| 4933 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 4934 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 4935 | |
| 4936 | if (encoder->crtc != crtc) |
| 4937 | continue; |
| 4938 | |
| 4939 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { |
| 4940 | unsigned int lvds_bpc; |
| 4941 | |
| 4942 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == |
| 4943 | LVDS_A3_POWER_UP) |
| 4944 | lvds_bpc = 8; |
| 4945 | else |
| 4946 | lvds_bpc = 6; |
| 4947 | |
| 4948 | if (lvds_bpc < display_bpc) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 4949 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4950 | display_bpc = lvds_bpc; |
| 4951 | } |
| 4952 | continue; |
| 4953 | } |
| 4954 | |
| 4955 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
| 4956 | /* Use VBT settings if we have an eDP panel */ |
| 4957 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; |
| 4958 | |
| 4959 | if (edp_bpc < display_bpc) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 4960 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4961 | display_bpc = edp_bpc; |
| 4962 | } |
| 4963 | continue; |
| 4964 | } |
| 4965 | |
| 4966 | /* Not one of the known troublemakers, check the EDID */ |
| 4967 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 4968 | head) { |
| 4969 | if (connector->encoder != encoder) |
| 4970 | continue; |
| 4971 | |
Jesse Barnes | 62ac41a | 2011-07-28 12:55:14 -0700 | [diff] [blame] | 4972 | /* Don't use an invalid EDID bpc value */ |
| 4973 | if (connector->display_info.bpc && |
| 4974 | connector->display_info.bpc < display_bpc) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 4975 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4976 | display_bpc = connector->display_info.bpc; |
| 4977 | } |
| 4978 | } |
| 4979 | |
| 4980 | /* |
| 4981 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
| 4982 | * through, clamp it down. (Note: >12bpc will be caught below.) |
| 4983 | */ |
| 4984 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
| 4985 | if (display_bpc > 8 && display_bpc < 12) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 4986 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4987 | display_bpc = 12; |
| 4988 | } else { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 4989 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4990 | display_bpc = 8; |
| 4991 | } |
| 4992 | } |
| 4993 | } |
| 4994 | |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 4995 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
| 4996 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); |
| 4997 | display_bpc = 6; |
| 4998 | } |
| 4999 | |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5000 | /* |
| 5001 | * We could just drive the pipe at the highest bpc all the time and |
| 5002 | * enable dithering as needed, but that costs bandwidth. So choose |
| 5003 | * the minimum value that expresses the full color range of the fb but |
| 5004 | * also stays within the max display bpc discovered above. |
| 5005 | */ |
| 5006 | |
| 5007 | switch (crtc->fb->depth) { |
| 5008 | case 8: |
| 5009 | bpc = 8; /* since we go through a colormap */ |
| 5010 | break; |
| 5011 | case 15: |
| 5012 | case 16: |
| 5013 | bpc = 6; /* min is 18bpp */ |
| 5014 | break; |
| 5015 | case 24: |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 5016 | bpc = 8; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5017 | break; |
| 5018 | case 30: |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 5019 | bpc = 10; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5020 | break; |
| 5021 | case 48: |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 5022 | bpc = 12; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5023 | break; |
| 5024 | default: |
| 5025 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); |
| 5026 | bpc = min((unsigned int)8, display_bpc); |
| 5027 | break; |
| 5028 | } |
| 5029 | |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 5030 | display_bpc = min(display_bpc, bpc); |
| 5031 | |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 5032 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
| 5033 | bpc, display_bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5034 | |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 5035 | *pipe_bpp = display_bpc * 3; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5036 | |
| 5037 | return display_bpc != bpc; |
| 5038 | } |
| 5039 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5040 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
| 5041 | { |
| 5042 | struct drm_device *dev = crtc->dev; |
| 5043 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5044 | int refclk; |
| 5045 | |
| 5046 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 5047 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
| 5048 | refclk = dev_priv->lvds_ssc_freq * 1000; |
| 5049 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
| 5050 | refclk / 1000); |
| 5051 | } else if (!IS_GEN2(dev)) { |
| 5052 | refclk = 96000; |
| 5053 | } else { |
| 5054 | refclk = 48000; |
| 5055 | } |
| 5056 | |
| 5057 | return refclk; |
| 5058 | } |
| 5059 | |
| 5060 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, |
| 5061 | intel_clock_t *clock) |
| 5062 | { |
| 5063 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 5064 | this mirrors vbios setting. */ |
| 5065 | if (adjusted_mode->clock >= 100000 |
| 5066 | && adjusted_mode->clock < 140500) { |
| 5067 | clock->p1 = 2; |
| 5068 | clock->p2 = 10; |
| 5069 | clock->n = 3; |
| 5070 | clock->m1 = 16; |
| 5071 | clock->m2 = 8; |
| 5072 | } else if (adjusted_mode->clock >= 140500 |
| 5073 | && adjusted_mode->clock <= 200000) { |
| 5074 | clock->p1 = 1; |
| 5075 | clock->p2 = 10; |
| 5076 | clock->n = 6; |
| 5077 | clock->m1 = 12; |
| 5078 | clock->m2 = 8; |
| 5079 | } |
| 5080 | } |
| 5081 | |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5082 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
| 5083 | intel_clock_t *clock, |
| 5084 | intel_clock_t *reduced_clock) |
| 5085 | { |
| 5086 | struct drm_device *dev = crtc->dev; |
| 5087 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5089 | int pipe = intel_crtc->pipe; |
| 5090 | u32 fp, fp2 = 0; |
| 5091 | |
| 5092 | if (IS_PINEVIEW(dev)) { |
| 5093 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; |
| 5094 | if (reduced_clock) |
| 5095 | fp2 = (1 << reduced_clock->n) << 16 | |
| 5096 | reduced_clock->m1 << 8 | reduced_clock->m2; |
| 5097 | } else { |
| 5098 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; |
| 5099 | if (reduced_clock) |
| 5100 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | |
| 5101 | reduced_clock->m2; |
| 5102 | } |
| 5103 | |
| 5104 | I915_WRITE(FP0(pipe), fp); |
| 5105 | |
| 5106 | intel_crtc->lowfreq_avail = false; |
| 5107 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 5108 | reduced_clock && i915_powersave) { |
| 5109 | I915_WRITE(FP1(pipe), fp2); |
| 5110 | intel_crtc->lowfreq_avail = true; |
| 5111 | } else { |
| 5112 | I915_WRITE(FP1(pipe), fp); |
| 5113 | } |
| 5114 | } |
| 5115 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5116 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
| 5117 | struct drm_display_mode *mode, |
| 5118 | struct drm_display_mode *adjusted_mode, |
| 5119 | int x, int y, |
| 5120 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5121 | { |
| 5122 | struct drm_device *dev = crtc->dev; |
| 5123 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5125 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 5126 | int plane = intel_crtc->plane; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 5127 | int refclk, num_connectors = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5128 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 5129 | u32 dpll, dspcntr, pipeconf, vsyncshift; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5130 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5131 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5132 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5133 | struct intel_encoder *encoder; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 5134 | const intel_limit_t *limit; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 5135 | int ret; |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5136 | u32 temp; |
Bryan Freed | aa9b500 | 2011-01-12 13:43:19 -0800 | [diff] [blame] | 5137 | u32 lvds_sync = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5138 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5139 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 5140 | if (encoder->base.crtc != crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5141 | continue; |
| 5142 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5143 | switch (encoder->type) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5144 | case INTEL_OUTPUT_LVDS: |
| 5145 | is_lvds = true; |
| 5146 | break; |
| 5147 | case INTEL_OUTPUT_SDVO: |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 5148 | case INTEL_OUTPUT_HDMI: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5149 | is_sdvo = true; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5150 | if (encoder->needs_tv_clock) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 5151 | is_tv = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5152 | break; |
| 5153 | case INTEL_OUTPUT_DVO: |
| 5154 | is_dvo = true; |
| 5155 | break; |
| 5156 | case INTEL_OUTPUT_TVOUT: |
| 5157 | is_tv = true; |
| 5158 | break; |
| 5159 | case INTEL_OUTPUT_ANALOG: |
| 5160 | is_crt = true; |
| 5161 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5162 | case INTEL_OUTPUT_DISPLAYPORT: |
| 5163 | is_dp = true; |
| 5164 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5165 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 5166 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 5167 | num_connectors++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5168 | } |
| 5169 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5170 | refclk = i9xx_get_refclk(crtc, num_connectors); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5171 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 5172 | /* |
| 5173 | * Returns a set of divisors for the desired target clock with the given |
| 5174 | * refclk, or FALSE. The returned values represent the clock equation: |
| 5175 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 5176 | */ |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 5177 | limit = intel_limit(crtc, refclk); |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 5178 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
| 5179 | &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5180 | if (!ok) { |
| 5181 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5182 | return -EINVAL; |
| 5183 | } |
| 5184 | |
| 5185 | /* Ensure that the cursor is valid for the new mode before changing... */ |
| 5186 | intel_crtc_update_cursor(crtc, true); |
| 5187 | |
| 5188 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 5189 | /* |
| 5190 | * Ensure we match the reduced clock's P to the target clock. |
| 5191 | * If the clocks don't match, we can't switch the display clock |
| 5192 | * by using the FP0/FP1. In such case we will disable the LVDS |
| 5193 | * downclock feature. |
| 5194 | */ |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5195 | has_reduced_clock = limit->find_pll(limit, crtc, |
| 5196 | dev_priv->lvds_downclock, |
| 5197 | refclk, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 5198 | &clock, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5199 | &reduced_clock); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5200 | } |
| 5201 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5202 | if (is_sdvo && is_tv) |
| 5203 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5204 | |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5205 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
| 5206 | &reduced_clock : NULL); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5207 | |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5208 | dpll = DPLL_VGA_MODE_DIS; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5209 | |
| 5210 | if (!IS_GEN2(dev)) { |
| 5211 | if (is_lvds) |
| 5212 | dpll |= DPLLB_MODE_LVDS; |
| 5213 | else |
| 5214 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 5215 | if (is_sdvo) { |
| 5216 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 5217 | if (pixel_multiplier > 1) { |
| 5218 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 5219 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5220 | } |
| 5221 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 5222 | } |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5223 | if (is_dp) |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5224 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 5225 | |
| 5226 | /* compute bitmask from p1 value */ |
| 5227 | if (IS_PINEVIEW(dev)) |
| 5228 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 5229 | else { |
| 5230 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5231 | if (IS_G4X(dev) && has_reduced_clock) |
| 5232 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 5233 | } |
| 5234 | switch (clock.p2) { |
| 5235 | case 5: |
| 5236 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 5237 | break; |
| 5238 | case 7: |
| 5239 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 5240 | break; |
| 5241 | case 10: |
| 5242 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 5243 | break; |
| 5244 | case 14: |
| 5245 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 5246 | break; |
| 5247 | } |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5248 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5249 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 5250 | } else { |
| 5251 | if (is_lvds) { |
| 5252 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5253 | } else { |
| 5254 | if (clock.p1 == 2) |
| 5255 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 5256 | else |
| 5257 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5258 | if (clock.p2 == 4) |
| 5259 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 5260 | } |
| 5261 | } |
| 5262 | |
| 5263 | if (is_sdvo && is_tv) |
| 5264 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 5265 | else if (is_tv) |
| 5266 | /* XXX: just matching BIOS for now */ |
| 5267 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 5268 | dpll |= 3; |
| 5269 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 5270 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 5271 | else |
| 5272 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 5273 | |
| 5274 | /* setup pipeconf */ |
| 5275 | pipeconf = I915_READ(PIPECONF(pipe)); |
| 5276 | |
| 5277 | /* Set up the display plane register */ |
| 5278 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 5279 | |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5280 | if (pipe == 0) |
| 5281 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
| 5282 | else |
| 5283 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5284 | |
| 5285 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
| 5286 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
| 5287 | * core speed. |
| 5288 | * |
| 5289 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
| 5290 | * pipe == 0 check? |
| 5291 | */ |
| 5292 | if (mode->clock > |
| 5293 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
| 5294 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
| 5295 | else |
| 5296 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
| 5297 | } |
| 5298 | |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 5299 | /* default to 8bpc */ |
| 5300 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); |
| 5301 | if (is_dp) { |
| 5302 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
| 5303 | pipeconf |= PIPECONF_BPP_6 | |
| 5304 | PIPECONF_DITHER_EN | |
| 5305 | PIPECONF_DITHER_TYPE_SP; |
| 5306 | } |
| 5307 | } |
| 5308 | |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5309 | dpll |= DPLL_VCO_ENABLE; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5310 | |
| 5311 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
| 5312 | drm_mode_debug_printmodeline(mode); |
| 5313 | |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5314 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5315 | |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5316 | POSTING_READ(DPLL(pipe)); |
Eric Anholt | c713bb0 | 2011-03-30 13:01:05 -0700 | [diff] [blame] | 5317 | udelay(150); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5318 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5319 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 5320 | * This is an exception to the general rule that mode_set doesn't turn |
| 5321 | * things on. |
| 5322 | */ |
| 5323 | if (is_lvds) { |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5324 | temp = I915_READ(LVDS); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5325 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
| 5326 | if (pipe == 1) { |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5327 | temp |= LVDS_PIPEB_SELECT; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5328 | } else { |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5329 | temp &= ~LVDS_PIPEB_SELECT; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5330 | } |
| 5331 | /* set the corresponsding LVDS_BORDER bit */ |
| 5332 | temp |= dev_priv->lvds_border_bits; |
| 5333 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 5334 | * set the DPLLs for dual-channel mode or not. |
| 5335 | */ |
| 5336 | if (clock.p2 == 7) |
| 5337 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
| 5338 | else |
| 5339 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
| 5340 | |
| 5341 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 5342 | * appropriately here, but we need to look more thoroughly into how |
| 5343 | * panels behave in the two modes. |
| 5344 | */ |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5345 | /* set the dithering flag on LVDS as needed */ |
| 5346 | if (INTEL_INFO(dev)->gen >= 4) { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5347 | if (dev_priv->lvds_dither) |
| 5348 | temp |= LVDS_ENABLE_DITHER; |
| 5349 | else |
| 5350 | temp &= ~LVDS_ENABLE_DITHER; |
| 5351 | } |
| 5352 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 5353 | lvds_sync |= LVDS_HSYNC_POLARITY; |
| 5354 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 5355 | lvds_sync |= LVDS_VSYNC_POLARITY; |
| 5356 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) |
| 5357 | != lvds_sync) { |
| 5358 | char flags[2] = "-+"; |
| 5359 | DRM_INFO("Changing LVDS panel from " |
| 5360 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", |
| 5361 | flags[!(temp & LVDS_HSYNC_POLARITY)], |
| 5362 | flags[!(temp & LVDS_VSYNC_POLARITY)], |
| 5363 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], |
| 5364 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); |
| 5365 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
| 5366 | temp |= lvds_sync; |
| 5367 | } |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5368 | I915_WRITE(LVDS, temp); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5369 | } |
| 5370 | |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5371 | if (is_dp) { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5372 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5373 | } |
| 5374 | |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5375 | I915_WRITE(DPLL(pipe), dpll); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5376 | |
Eric Anholt | c713bb0 | 2011-03-30 13:01:05 -0700 | [diff] [blame] | 5377 | /* Wait for the clocks to stabilize. */ |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5378 | POSTING_READ(DPLL(pipe)); |
Eric Anholt | c713bb0 | 2011-03-30 13:01:05 -0700 | [diff] [blame] | 5379 | udelay(150); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5380 | |
Eric Anholt | c713bb0 | 2011-03-30 13:01:05 -0700 | [diff] [blame] | 5381 | if (INTEL_INFO(dev)->gen >= 4) { |
| 5382 | temp = 0; |
| 5383 | if (is_sdvo) { |
| 5384 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 5385 | if (temp > 1) |
| 5386 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 5387 | else |
| 5388 | temp = 0; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5389 | } |
Eric Anholt | c713bb0 | 2011-03-30 13:01:05 -0700 | [diff] [blame] | 5390 | I915_WRITE(DPLL_MD(pipe), temp); |
| 5391 | } else { |
| 5392 | /* The pixel multiplier can only be updated once the |
| 5393 | * DPLL is enabled and the clocks are stable. |
| 5394 | * |
| 5395 | * So write it again. |
| 5396 | */ |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5397 | I915_WRITE(DPLL(pipe), dpll); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5398 | } |
| 5399 | |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5400 | if (HAS_PIPE_CXSR(dev)) { |
| 5401 | if (intel_crtc->lowfreq_avail) { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5402 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 5403 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5404 | } else { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5405 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
| 5406 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 5407 | } |
| 5408 | } |
| 5409 | |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 5410 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
Daniel Vetter | dbb0257 | 2012-01-28 14:49:23 +0100 | [diff] [blame] | 5411 | if (!IS_GEN2(dev) && |
| 5412 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5413 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 5414 | /* the chip adds 2 halflines automatically */ |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5415 | adjusted_mode->crtc_vtotal -= 1; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5416 | adjusted_mode->crtc_vblank_end -= 1; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 5417 | vsyncshift = adjusted_mode->crtc_hsync_start |
| 5418 | - adjusted_mode->crtc_htotal/2; |
| 5419 | } else { |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 5420 | pipeconf |= PIPECONF_PROGRESSIVE; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 5421 | vsyncshift = 0; |
| 5422 | } |
| 5423 | |
| 5424 | if (!IS_GEN3(dev)) |
| 5425 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5426 | |
| 5427 | I915_WRITE(HTOTAL(pipe), |
| 5428 | (adjusted_mode->crtc_hdisplay - 1) | |
| 5429 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 5430 | I915_WRITE(HBLANK(pipe), |
| 5431 | (adjusted_mode->crtc_hblank_start - 1) | |
| 5432 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 5433 | I915_WRITE(HSYNC(pipe), |
| 5434 | (adjusted_mode->crtc_hsync_start - 1) | |
| 5435 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 5436 | |
| 5437 | I915_WRITE(VTOTAL(pipe), |
| 5438 | (adjusted_mode->crtc_vdisplay - 1) | |
| 5439 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
| 5440 | I915_WRITE(VBLANK(pipe), |
| 5441 | (adjusted_mode->crtc_vblank_start - 1) | |
| 5442 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
| 5443 | I915_WRITE(VSYNC(pipe), |
| 5444 | (adjusted_mode->crtc_vsync_start - 1) | |
| 5445 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 5446 | |
| 5447 | /* pipesrc and dspsize control the size that is scaled from, |
| 5448 | * which should always be the user's requested size. |
| 5449 | */ |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5450 | I915_WRITE(DSPSIZE(plane), |
| 5451 | ((mode->vdisplay - 1) << 16) | |
| 5452 | (mode->hdisplay - 1)); |
| 5453 | I915_WRITE(DSPPOS(plane), 0); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5454 | I915_WRITE(PIPESRC(pipe), |
| 5455 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
| 5456 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5457 | I915_WRITE(PIPECONF(pipe), pipeconf); |
| 5458 | POSTING_READ(PIPECONF(pipe)); |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5459 | intel_enable_pipe(dev_priv, pipe, false); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5460 | |
| 5461 | intel_wait_for_vblank(dev, pipe); |
| 5462 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5463 | I915_WRITE(DSPCNTR(plane), dspcntr); |
| 5464 | POSTING_READ(DSPCNTR(plane)); |
Keith Packard | 284d952 | 2011-06-06 17:12:49 -0700 | [diff] [blame] | 5465 | intel_enable_plane(dev_priv, plane, pipe); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5466 | |
| 5467 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
| 5468 | |
| 5469 | intel_update_watermarks(dev); |
| 5470 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5471 | return ret; |
| 5472 | } |
| 5473 | |
Keith Packard | 9fb526d | 2011-09-26 22:24:57 -0700 | [diff] [blame] | 5474 | /* |
| 5475 | * Initialize reference clocks when the driver loads |
| 5476 | */ |
| 5477 | void ironlake_init_pch_refclk(struct drm_device *dev) |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5478 | { |
| 5479 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5480 | struct drm_mode_config *mode_config = &dev->mode_config; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5481 | struct intel_encoder *encoder; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5482 | u32 temp; |
| 5483 | bool has_lvds = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5484 | bool has_cpu_edp = false; |
| 5485 | bool has_pch_edp = false; |
| 5486 | bool has_panel = false; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5487 | bool has_ck505 = false; |
| 5488 | bool can_ssc = false; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5489 | |
| 5490 | /* We need to take the global config into account */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5491 | list_for_each_entry(encoder, &mode_config->encoder_list, |
| 5492 | base.head) { |
| 5493 | switch (encoder->type) { |
| 5494 | case INTEL_OUTPUT_LVDS: |
| 5495 | has_panel = true; |
| 5496 | has_lvds = true; |
| 5497 | break; |
| 5498 | case INTEL_OUTPUT_EDP: |
| 5499 | has_panel = true; |
| 5500 | if (intel_encoder_is_pch_edp(&encoder->base)) |
| 5501 | has_pch_edp = true; |
| 5502 | else |
| 5503 | has_cpu_edp = true; |
| 5504 | break; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5505 | } |
| 5506 | } |
| 5507 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5508 | if (HAS_PCH_IBX(dev)) { |
| 5509 | has_ck505 = dev_priv->display_clock_mode; |
| 5510 | can_ssc = has_ck505; |
| 5511 | } else { |
| 5512 | has_ck505 = false; |
| 5513 | can_ssc = true; |
| 5514 | } |
| 5515 | |
| 5516 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", |
| 5517 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, |
| 5518 | has_ck505); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5519 | |
| 5520 | /* Ironlake: try to setup display ref clock before DPLL |
| 5521 | * enabling. This is only under driver's control after |
| 5522 | * PCH B stepping, previous chipset stepping should be |
| 5523 | * ignoring this setting. |
| 5524 | */ |
| 5525 | temp = I915_READ(PCH_DREF_CONTROL); |
| 5526 | /* Always enable nonspread source */ |
| 5527 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5528 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5529 | if (has_ck505) |
| 5530 | temp |= DREF_NONSPREAD_CK505_ENABLE; |
| 5531 | else |
| 5532 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5533 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5534 | if (has_panel) { |
| 5535 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 5536 | temp |= DREF_SSC_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5537 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5538 | /* SSC must be turned on before enabling the CPU output */ |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5539 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5540 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5541 | temp |= DREF_SSC1_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5542 | } |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5543 | |
| 5544 | /* Get SSC going before enabling the outputs */ |
| 5545 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 5546 | POSTING_READ(PCH_DREF_CONTROL); |
| 5547 | udelay(200); |
| 5548 | |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5549 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 5550 | |
| 5551 | /* Enable CPU source on CPU attached eDP */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5552 | if (has_cpu_edp) { |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5553 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5554 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5555 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5556 | } |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5557 | else |
| 5558 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5559 | } else |
| 5560 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 5561 | |
| 5562 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 5563 | POSTING_READ(PCH_DREF_CONTROL); |
| 5564 | udelay(200); |
| 5565 | } else { |
| 5566 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
| 5567 | |
| 5568 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 5569 | |
| 5570 | /* Turn off CPU output */ |
| 5571 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 5572 | |
| 5573 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 5574 | POSTING_READ(PCH_DREF_CONTROL); |
| 5575 | udelay(200); |
| 5576 | |
| 5577 | /* Turn off the SSC source */ |
| 5578 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 5579 | temp |= DREF_SSC_SOURCE_DISABLE; |
| 5580 | |
| 5581 | /* Turn off SSC1 */ |
| 5582 | temp &= ~ DREF_SSC1_ENABLE; |
| 5583 | |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5584 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 5585 | POSTING_READ(PCH_DREF_CONTROL); |
| 5586 | udelay(200); |
| 5587 | } |
| 5588 | } |
| 5589 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 5590 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
| 5591 | { |
| 5592 | struct drm_device *dev = crtc->dev; |
| 5593 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5594 | struct intel_encoder *encoder; |
| 5595 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 5596 | struct intel_encoder *edp_encoder = NULL; |
| 5597 | int num_connectors = 0; |
| 5598 | bool is_lvds = false; |
| 5599 | |
| 5600 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 5601 | if (encoder->base.crtc != crtc) |
| 5602 | continue; |
| 5603 | |
| 5604 | switch (encoder->type) { |
| 5605 | case INTEL_OUTPUT_LVDS: |
| 5606 | is_lvds = true; |
| 5607 | break; |
| 5608 | case INTEL_OUTPUT_EDP: |
| 5609 | edp_encoder = encoder; |
| 5610 | break; |
| 5611 | } |
| 5612 | num_connectors++; |
| 5613 | } |
| 5614 | |
| 5615 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
| 5616 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
| 5617 | dev_priv->lvds_ssc_freq); |
| 5618 | return dev_priv->lvds_ssc_freq * 1000; |
| 5619 | } |
| 5620 | |
| 5621 | return 120000; |
| 5622 | } |
| 5623 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5624 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
| 5625 | struct drm_display_mode *mode, |
| 5626 | struct drm_display_mode *adjusted_mode, |
| 5627 | int x, int y, |
| 5628 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5629 | { |
| 5630 | struct drm_device *dev = crtc->dev; |
| 5631 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5633 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 5634 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5635 | int refclk, num_connectors = 0; |
| 5636 | intel_clock_t clock, reduced_clock; |
| 5637 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 5638 | bool ok, has_reduced_clock = false, is_sdvo = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5639 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
| 5640 | struct intel_encoder *has_edp_encoder = NULL; |
| 5641 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 5642 | struct intel_encoder *encoder; |
| 5643 | const intel_limit_t *limit; |
| 5644 | int ret; |
| 5645 | struct fdi_m_n m_n = {0}; |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5646 | u32 temp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5647 | u32 lvds_sync = 0; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5648 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
| 5649 | unsigned int pipe_bpp; |
| 5650 | bool dither; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5651 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5652 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 5653 | if (encoder->base.crtc != crtc) |
| 5654 | continue; |
| 5655 | |
| 5656 | switch (encoder->type) { |
| 5657 | case INTEL_OUTPUT_LVDS: |
| 5658 | is_lvds = true; |
| 5659 | break; |
| 5660 | case INTEL_OUTPUT_SDVO: |
| 5661 | case INTEL_OUTPUT_HDMI: |
| 5662 | is_sdvo = true; |
| 5663 | if (encoder->needs_tv_clock) |
| 5664 | is_tv = true; |
| 5665 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5666 | case INTEL_OUTPUT_TVOUT: |
| 5667 | is_tv = true; |
| 5668 | break; |
| 5669 | case INTEL_OUTPUT_ANALOG: |
| 5670 | is_crt = true; |
| 5671 | break; |
| 5672 | case INTEL_OUTPUT_DISPLAYPORT: |
| 5673 | is_dp = true; |
| 5674 | break; |
| 5675 | case INTEL_OUTPUT_EDP: |
| 5676 | has_edp_encoder = encoder; |
| 5677 | break; |
| 5678 | } |
| 5679 | |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 5680 | num_connectors++; |
| 5681 | } |
| 5682 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 5683 | refclk = ironlake_get_refclk(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5684 | |
| 5685 | /* |
| 5686 | * Returns a set of divisors for the desired target clock with the given |
| 5687 | * refclk, or FALSE. The returned values represent the clock equation: |
| 5688 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 5689 | */ |
| 5690 | limit = intel_limit(crtc, refclk); |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 5691 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
| 5692 | &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5693 | if (!ok) { |
| 5694 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 5695 | return -EINVAL; |
| 5696 | } |
| 5697 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 5698 | /* Ensure that the cursor is valid for the new mode before changing... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 5699 | intel_crtc_update_cursor(crtc, true); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 5700 | |
Zhao Yakui | ddc9003 | 2010-01-06 22:05:56 +0800 | [diff] [blame] | 5701 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 5702 | /* |
| 5703 | * Ensure we match the reduced clock's P to the target clock. |
| 5704 | * If the clocks don't match, we can't switch the display clock |
| 5705 | * by using the FP0/FP1. In such case we will disable the LVDS |
| 5706 | * downclock feature. |
| 5707 | */ |
Zhao Yakui | ddc9003 | 2010-01-06 22:05:56 +0800 | [diff] [blame] | 5708 | has_reduced_clock = limit->find_pll(limit, crtc, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5709 | dev_priv->lvds_downclock, |
| 5710 | refclk, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 5711 | &clock, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5712 | &reduced_clock); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5713 | } |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 5714 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 5715 | this mirrors vbios setting. */ |
| 5716 | if (is_sdvo && is_tv) { |
| 5717 | if (adjusted_mode->clock >= 100000 |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5718 | && adjusted_mode->clock < 140500) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 5719 | clock.p1 = 2; |
| 5720 | clock.p2 = 10; |
| 5721 | clock.n = 3; |
| 5722 | clock.m1 = 16; |
| 5723 | clock.m2 = 8; |
| 5724 | } else if (adjusted_mode->clock >= 140500 |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5725 | && adjusted_mode->clock <= 200000) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 5726 | clock.p1 = 1; |
| 5727 | clock.p2 = 10; |
| 5728 | clock.n = 6; |
| 5729 | clock.m1 = 12; |
| 5730 | clock.m2 = 8; |
| 5731 | } |
| 5732 | } |
| 5733 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5734 | /* FDI link */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5735 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 5736 | lane = 0; |
| 5737 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
| 5738 | according to current link config */ |
| 5739 | if (has_edp_encoder && |
| 5740 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
| 5741 | target_clock = mode->clock; |
| 5742 | intel_edp_link_config(has_edp_encoder, |
| 5743 | &lane, &link_bw); |
| 5744 | } else { |
| 5745 | /* [e]DP over FDI requires target mode clock |
| 5746 | instead of link clock */ |
| 5747 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5748 | target_clock = mode->clock; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5749 | else |
| 5750 | target_clock = adjusted_mode->clock; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 5751 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5752 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 5753 | * each output octet as 10 bits. The actual frequency |
| 5754 | * is stored as a divider into a 100MHz clock, and the |
| 5755 | * mode pixel clock is stored in units of 1KHz. |
| 5756 | * Hence the bw of each lane in terms of the mode signal |
| 5757 | * is: |
| 5758 | */ |
| 5759 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5760 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5761 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5762 | /* determine panel color depth */ |
| 5763 | temp = I915_READ(PIPECONF(pipe)); |
| 5764 | temp &= ~PIPE_BPC_MASK; |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 5765 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5766 | switch (pipe_bpp) { |
| 5767 | case 18: |
| 5768 | temp |= PIPE_6BPC; |
| 5769 | break; |
| 5770 | case 24: |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5771 | temp |= PIPE_8BPC; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5772 | break; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5773 | case 30: |
| 5774 | temp |= PIPE_10BPC; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5775 | break; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5776 | case 36: |
| 5777 | temp |= PIPE_12BPC; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5778 | break; |
| 5779 | default: |
Jesse Barnes | 62ac41a | 2011-07-28 12:55:14 -0700 | [diff] [blame] | 5780 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
| 5781 | pipe_bpp); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5782 | temp |= PIPE_8BPC; |
| 5783 | pipe_bpp = 24; |
| 5784 | break; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5785 | } |
| 5786 | |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5787 | intel_crtc->bpp = pipe_bpp; |
| 5788 | I915_WRITE(PIPECONF(pipe), temp); |
| 5789 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5790 | if (!lane) { |
| 5791 | /* |
| 5792 | * Account for spread spectrum to avoid |
| 5793 | * oversubscribing the link. Max center spread |
| 5794 | * is 2.5%; use 5% for safety's sake. |
| 5795 | */ |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5796 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5797 | lane = bps / (link_bw * 8) + 1; |
| 5798 | } |
| 5799 | |
| 5800 | intel_crtc->fdi_lanes = lane; |
| 5801 | |
| 5802 | if (pixel_multiplier > 1) |
| 5803 | link_bw *= pixel_multiplier; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5804 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
| 5805 | &m_n); |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5806 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 5807 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
| 5808 | if (has_reduced_clock) |
| 5809 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
| 5810 | reduced_clock.m2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5811 | |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 5812 | /* Enable autotuning of the PLL clock (if permissible) */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5813 | factor = 21; |
| 5814 | if (is_lvds) { |
| 5815 | if ((intel_panel_use_ssc(dev_priv) && |
| 5816 | dev_priv->lvds_ssc_freq == 100) || |
| 5817 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) |
| 5818 | factor = 25; |
| 5819 | } else if (is_sdvo && is_tv) |
| 5820 | factor = 20; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 5821 | |
Jesse Barnes | cb0e093 | 2011-07-28 14:50:30 -0700 | [diff] [blame] | 5822 | if (clock.m < factor * clock.n) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5823 | fp |= FP_CB_TUNE; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 5824 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5825 | dpll = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5826 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 5827 | if (is_lvds) |
| 5828 | dpll |= DPLLB_MODE_LVDS; |
| 5829 | else |
| 5830 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 5831 | if (is_sdvo) { |
| 5832 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 5833 | if (pixel_multiplier > 1) { |
| 5834 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5835 | } |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 5836 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 5837 | } |
| 5838 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
| 5839 | dpll |= DPLL_DVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5840 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 5841 | /* compute bitmask from p1 value */ |
| 5842 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5843 | /* also FPA1 */ |
| 5844 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 5845 | |
| 5846 | switch (clock.p2) { |
| 5847 | case 5: |
| 5848 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 5849 | break; |
| 5850 | case 7: |
| 5851 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 5852 | break; |
| 5853 | case 10: |
| 5854 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 5855 | break; |
| 5856 | case 14: |
| 5857 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 5858 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5859 | } |
| 5860 | |
| 5861 | if (is_sdvo && is_tv) |
| 5862 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 5863 | else if (is_tv) |
| 5864 | /* XXX: just matching BIOS for now */ |
| 5865 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 5866 | dpll |= 3; |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 5867 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5868 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 5869 | else |
| 5870 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 5871 | |
| 5872 | /* setup pipeconf */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5873 | pipeconf = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5874 | |
| 5875 | /* Set up the display plane register */ |
| 5876 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 5877 | |
Jesse Barnes | f7cb34d | 2011-10-12 10:49:14 -0700 | [diff] [blame] | 5878 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5879 | drm_mode_debug_printmodeline(mode); |
| 5880 | |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 5881 | /* PCH eDP needs FDI, but CPU eDP does not */ |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 5882 | if (!intel_crtc->no_pll) { |
| 5883 | if (!has_edp_encoder || |
| 5884 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
| 5885 | I915_WRITE(PCH_FP0(pipe), fp); |
| 5886 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5887 | |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 5888 | POSTING_READ(PCH_DPLL(pipe)); |
| 5889 | udelay(150); |
| 5890 | } |
| 5891 | } else { |
| 5892 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && |
| 5893 | fp == I915_READ(PCH_FP0(0))) { |
| 5894 | intel_crtc->use_pll_a = true; |
| 5895 | DRM_DEBUG_KMS("using pipe a dpll\n"); |
| 5896 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && |
| 5897 | fp == I915_READ(PCH_FP0(1))) { |
| 5898 | intel_crtc->use_pll_a = false; |
| 5899 | DRM_DEBUG_KMS("using pipe b dpll\n"); |
| 5900 | } else { |
| 5901 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); |
| 5902 | return -EINVAL; |
| 5903 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5904 | } |
| 5905 | |
| 5906 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 5907 | * This is an exception to the general rule that mode_set doesn't turn |
| 5908 | * things on. |
| 5909 | */ |
| 5910 | if (is_lvds) { |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5911 | temp = I915_READ(PCH_LVDS); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5912 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
Jesse Barnes | 7885d20 | 2012-01-12 14:51:17 -0800 | [diff] [blame] | 5913 | if (HAS_PCH_CPT(dev)) { |
| 5914 | temp &= ~PORT_TRANS_SEL_MASK; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 5915 | temp |= PORT_TRANS_SEL_CPT(pipe); |
Jesse Barnes | 7885d20 | 2012-01-12 14:51:17 -0800 | [diff] [blame] | 5916 | } else { |
| 5917 | if (pipe == 1) |
| 5918 | temp |= LVDS_PIPEB_SELECT; |
| 5919 | else |
| 5920 | temp &= ~LVDS_PIPEB_SELECT; |
| 5921 | } |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 5922 | |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 5923 | /* set the corresponsding LVDS_BORDER bit */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5924 | temp |= dev_priv->lvds_border_bits; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5925 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 5926 | * set the DPLLs for dual-channel mode or not. |
| 5927 | */ |
| 5928 | if (clock.p2 == 7) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5929 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5930 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5931 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5932 | |
| 5933 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 5934 | * appropriately here, but we need to look more thoroughly into how |
| 5935 | * panels behave in the two modes. |
| 5936 | */ |
Bryan Freed | aa9b500 | 2011-01-12 13:43:19 -0800 | [diff] [blame] | 5937 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 5938 | lvds_sync |= LVDS_HSYNC_POLARITY; |
| 5939 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 5940 | lvds_sync |= LVDS_VSYNC_POLARITY; |
| 5941 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) |
| 5942 | != lvds_sync) { |
| 5943 | char flags[2] = "-+"; |
| 5944 | DRM_INFO("Changing LVDS panel from " |
| 5945 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", |
| 5946 | flags[!(temp & LVDS_HSYNC_POLARITY)], |
| 5947 | flags[!(temp & LVDS_VSYNC_POLARITY)], |
| 5948 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], |
| 5949 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); |
| 5950 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
| 5951 | temp |= lvds_sync; |
| 5952 | } |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5953 | I915_WRITE(PCH_LVDS, temp); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5954 | } |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 5955 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5956 | pipeconf &= ~PIPECONF_DITHER_EN; |
| 5957 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 5958 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5959 | pipeconf |= PIPECONF_DITHER_EN; |
Daniel Vetter | f74974c | 2011-10-11 17:27:51 +0200 | [diff] [blame] | 5960 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 5961 | } |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 5962 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5963 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5964 | } else { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 5965 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 5966 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
| 5967 | I915_WRITE(TRANSDATA_N1(pipe), 0); |
| 5968 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); |
| 5969 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 5970 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5971 | |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 5972 | if (!intel_crtc->no_pll && |
| 5973 | (!has_edp_encoder || |
| 5974 | intel_encoder_is_pch_edp(&has_edp_encoder->base))) { |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5975 | I915_WRITE(PCH_DPLL(pipe), dpll); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5976 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5977 | /* Wait for the clocks to stabilize. */ |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5978 | POSTING_READ(PCH_DPLL(pipe)); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5979 | udelay(150); |
| 5980 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 5981 | /* The pixel multiplier can only be updated once the |
| 5982 | * DPLL is enabled and the clocks are stable. |
| 5983 | * |
| 5984 | * So write it again. |
| 5985 | */ |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 5986 | I915_WRITE(PCH_DPLL(pipe), dpll); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5987 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5988 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5989 | intel_crtc->lowfreq_avail = false; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 5990 | if (!intel_crtc->no_pll) { |
| 5991 | if (is_lvds && has_reduced_clock && i915_powersave) { |
| 5992 | I915_WRITE(PCH_FP1(pipe), fp2); |
| 5993 | intel_crtc->lowfreq_avail = true; |
| 5994 | if (HAS_PIPE_CXSR(dev)) { |
| 5995 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 5996 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 5997 | } |
| 5998 | } else { |
| 5999 | I915_WRITE(PCH_FP1(pipe), fp); |
| 6000 | if (HAS_PIPE_CXSR(dev)) { |
| 6001 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
| 6002 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 6003 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6004 | } |
| 6005 | } |
| 6006 | |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 6007 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 6008 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Daniel Vetter | 5def474 | 2012-01-28 14:49:22 +0100 | [diff] [blame] | 6009 | pipeconf |= PIPECONF_INTERLACED_ILK; |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 6010 | /* the chip adds 2 halflines automatically */ |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 6011 | adjusted_mode->crtc_vtotal -= 1; |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 6012 | adjusted_mode->crtc_vblank_end -= 1; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 6013 | I915_WRITE(VSYNCSHIFT(pipe), |
| 6014 | adjusted_mode->crtc_hsync_start |
| 6015 | - adjusted_mode->crtc_htotal/2); |
| 6016 | } else { |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 6017 | pipeconf |= PIPECONF_PROGRESSIVE; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 6018 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
| 6019 | } |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 6020 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6021 | I915_WRITE(HTOTAL(pipe), |
| 6022 | (adjusted_mode->crtc_hdisplay - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6023 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6024 | I915_WRITE(HBLANK(pipe), |
| 6025 | (adjusted_mode->crtc_hblank_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6026 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6027 | I915_WRITE(HSYNC(pipe), |
| 6028 | (adjusted_mode->crtc_hsync_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6029 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6030 | |
| 6031 | I915_WRITE(VTOTAL(pipe), |
| 6032 | (adjusted_mode->crtc_vdisplay - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6033 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6034 | I915_WRITE(VBLANK(pipe), |
| 6035 | (adjusted_mode->crtc_vblank_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6036 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6037 | I915_WRITE(VSYNC(pipe), |
| 6038 | (adjusted_mode->crtc_vsync_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6039 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6040 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 6041 | /* pipesrc controls the size that is scaled from, which should |
| 6042 | * always be the user's requested size. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6043 | */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6044 | I915_WRITE(PIPESRC(pipe), |
| 6045 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6046 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 6047 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 6048 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
| 6049 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
| 6050 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6051 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 6052 | if (has_edp_encoder && |
| 6053 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
| 6054 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6055 | } |
| 6056 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6057 | I915_WRITE(PIPECONF(pipe), pipeconf); |
| 6058 | POSTING_READ(PIPECONF(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6059 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 6060 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6061 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6062 | I915_WRITE(DSPCNTR(plane), dspcntr); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 6063 | POSTING_READ(DSPCNTR(plane)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6064 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 6065 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 6066 | |
| 6067 | intel_update_watermarks(dev); |
| 6068 | |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 6069 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6070 | } |
| 6071 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6072 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
| 6073 | struct drm_display_mode *mode, |
| 6074 | struct drm_display_mode *adjusted_mode, |
| 6075 | int x, int y, |
| 6076 | struct drm_framebuffer *old_fb) |
| 6077 | { |
| 6078 | struct drm_device *dev = crtc->dev; |
| 6079 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 6080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6081 | int pipe = intel_crtc->pipe; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6082 | int ret; |
| 6083 | |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 6084 | drm_vblank_pre_modeset(dev, pipe); |
| 6085 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6086 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
| 6087 | x, y, old_fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6088 | drm_vblank_post_modeset(dev, pipe); |
| 6089 | |
Jesse Barnes | d8e70a2 | 2011-11-15 10:28:54 -0800 | [diff] [blame] | 6090 | if (ret) |
| 6091 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; |
| 6092 | else |
| 6093 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; |
Keith Packard | 120eced | 2011-07-27 01:21:40 -0700 | [diff] [blame] | 6094 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6095 | return ret; |
| 6096 | } |
| 6097 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 6098 | static bool intel_eld_uptodate(struct drm_connector *connector, |
| 6099 | int reg_eldv, uint32_t bits_eldv, |
| 6100 | int reg_elda, uint32_t bits_elda, |
| 6101 | int reg_edid) |
| 6102 | { |
| 6103 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 6104 | uint8_t *eld = connector->eld; |
| 6105 | uint32_t i; |
| 6106 | |
| 6107 | i = I915_READ(reg_eldv); |
| 6108 | i &= bits_eldv; |
| 6109 | |
| 6110 | if (!eld[0]) |
| 6111 | return !i; |
| 6112 | |
| 6113 | if (!i) |
| 6114 | return false; |
| 6115 | |
| 6116 | i = I915_READ(reg_elda); |
| 6117 | i &= ~bits_elda; |
| 6118 | I915_WRITE(reg_elda, i); |
| 6119 | |
| 6120 | for (i = 0; i < eld[2]; i++) |
| 6121 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
| 6122 | return false; |
| 6123 | |
| 6124 | return true; |
| 6125 | } |
| 6126 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6127 | static void g4x_write_eld(struct drm_connector *connector, |
| 6128 | struct drm_crtc *crtc) |
| 6129 | { |
| 6130 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 6131 | uint8_t *eld = connector->eld; |
| 6132 | uint32_t eldv; |
| 6133 | uint32_t len; |
| 6134 | uint32_t i; |
| 6135 | |
| 6136 | i = I915_READ(G4X_AUD_VID_DID); |
| 6137 | |
| 6138 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
| 6139 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 6140 | else |
| 6141 | eldv = G4X_ELDV_DEVCTG; |
| 6142 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 6143 | if (intel_eld_uptodate(connector, |
| 6144 | G4X_AUD_CNTL_ST, eldv, |
| 6145 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
| 6146 | G4X_HDMIW_HDMIEDID)) |
| 6147 | return; |
| 6148 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6149 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 6150 | i &= ~(eldv | G4X_ELD_ADDR); |
| 6151 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
| 6152 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 6153 | |
| 6154 | if (!eld[0]) |
| 6155 | return; |
| 6156 | |
| 6157 | len = min_t(uint8_t, eld[2], len); |
| 6158 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 6159 | for (i = 0; i < len; i++) |
| 6160 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
| 6161 | |
| 6162 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 6163 | i |= eldv; |
| 6164 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 6165 | } |
| 6166 | |
| 6167 | static void ironlake_write_eld(struct drm_connector *connector, |
| 6168 | struct drm_crtc *crtc) |
| 6169 | { |
| 6170 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 6171 | uint8_t *eld = connector->eld; |
| 6172 | uint32_t eldv; |
| 6173 | uint32_t i; |
| 6174 | int len; |
| 6175 | int hdmiw_hdmiedid; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 6176 | int aud_config; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6177 | int aud_cntl_st; |
| 6178 | int aud_cntrl_st2; |
| 6179 | |
Wu Fengguang | b3f33cb | 2011-12-09 20:42:17 +0800 | [diff] [blame] | 6180 | if (HAS_PCH_IBX(connector->dev)) { |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6181 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 6182 | aud_config = IBX_AUD_CONFIG_A; |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6183 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
| 6184 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6185 | } else { |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6186 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 6187 | aud_config = CPT_AUD_CONFIG_A; |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6188 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
| 6189 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6190 | } |
| 6191 | |
| 6192 | i = to_intel_crtc(crtc)->pipe; |
| 6193 | hdmiw_hdmiedid += i * 0x100; |
| 6194 | aud_cntl_st += i * 0x100; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 6195 | aud_config += i * 0x100; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6196 | |
| 6197 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); |
| 6198 | |
| 6199 | i = I915_READ(aud_cntl_st); |
| 6200 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ |
| 6201 | if (!i) { |
| 6202 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
| 6203 | /* operate blindly on all ports */ |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6204 | eldv = IBX_ELD_VALIDB; |
| 6205 | eldv |= IBX_ELD_VALIDB << 4; |
| 6206 | eldv |= IBX_ELD_VALIDB << 8; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6207 | } else { |
| 6208 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6209 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6210 | } |
| 6211 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 6212 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 6213 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
| 6214 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 6215 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
| 6216 | } else |
| 6217 | I915_WRITE(aud_config, 0); |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 6218 | |
| 6219 | if (intel_eld_uptodate(connector, |
| 6220 | aud_cntrl_st2, eldv, |
| 6221 | aud_cntl_st, IBX_ELD_ADDRESS, |
| 6222 | hdmiw_hdmiedid)) |
| 6223 | return; |
| 6224 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6225 | i = I915_READ(aud_cntrl_st2); |
| 6226 | i &= ~eldv; |
| 6227 | I915_WRITE(aud_cntrl_st2, i); |
| 6228 | |
| 6229 | if (!eld[0]) |
| 6230 | return; |
| 6231 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6232 | i = I915_READ(aud_cntl_st); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 6233 | i &= ~IBX_ELD_ADDRESS; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6234 | I915_WRITE(aud_cntl_st, i); |
| 6235 | |
| 6236 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
| 6237 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 6238 | for (i = 0; i < len; i++) |
| 6239 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 6240 | |
| 6241 | i = I915_READ(aud_cntrl_st2); |
| 6242 | i |= eldv; |
| 6243 | I915_WRITE(aud_cntrl_st2, i); |
| 6244 | } |
| 6245 | |
| 6246 | void intel_write_eld(struct drm_encoder *encoder, |
| 6247 | struct drm_display_mode *mode) |
| 6248 | { |
| 6249 | struct drm_crtc *crtc = encoder->crtc; |
| 6250 | struct drm_connector *connector; |
| 6251 | struct drm_device *dev = encoder->dev; |
| 6252 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6253 | |
| 6254 | connector = drm_select_eld(encoder, mode); |
| 6255 | if (!connector) |
| 6256 | return; |
| 6257 | |
| 6258 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 6259 | connector->base.id, |
| 6260 | drm_get_connector_name(connector), |
| 6261 | connector->encoder->base.id, |
| 6262 | drm_get_encoder_name(connector->encoder)); |
| 6263 | |
| 6264 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
| 6265 | |
| 6266 | if (dev_priv->display.write_eld) |
| 6267 | dev_priv->display.write_eld(connector, crtc); |
| 6268 | } |
| 6269 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6270 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 6271 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 6272 | { |
| 6273 | struct drm_device *dev = crtc->dev; |
| 6274 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6276 | int palreg = PALETTE(intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6277 | int i; |
| 6278 | |
| 6279 | /* The clocks have to be on to load the palette. */ |
Alban Browaeys | aed3f09 | 2012-02-24 17:12:45 +0000 | [diff] [blame] | 6280 | if (!crtc->enabled || !intel_crtc->active) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6281 | return; |
| 6282 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 6283 | /* use legacy palette for Ironlake */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 6284 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6285 | palreg = LGC_PALETTE(intel_crtc->pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6286 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6287 | for (i = 0; i < 256; i++) { |
| 6288 | I915_WRITE(palreg + 4 * i, |
| 6289 | (intel_crtc->lut_r[i] << 16) | |
| 6290 | (intel_crtc->lut_g[i] << 8) | |
| 6291 | intel_crtc->lut_b[i]); |
| 6292 | } |
| 6293 | } |
| 6294 | |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6295 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
| 6296 | { |
| 6297 | struct drm_device *dev = crtc->dev; |
| 6298 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6299 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6300 | bool visible = base != 0; |
| 6301 | u32 cntl; |
| 6302 | |
| 6303 | if (intel_crtc->cursor_visible == visible) |
| 6304 | return; |
| 6305 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6306 | cntl = I915_READ(_CURACNTR); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6307 | if (visible) { |
| 6308 | /* On these chipsets we can only modify the base whilst |
| 6309 | * the cursor is disabled. |
| 6310 | */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6311 | I915_WRITE(_CURABASE, base); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6312 | |
| 6313 | cntl &= ~(CURSOR_FORMAT_MASK); |
| 6314 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
| 6315 | cntl |= CURSOR_ENABLE | |
| 6316 | CURSOR_GAMMA_ENABLE | |
| 6317 | CURSOR_FORMAT_ARGB; |
| 6318 | } else |
| 6319 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6320 | I915_WRITE(_CURACNTR, cntl); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6321 | |
| 6322 | intel_crtc->cursor_visible = visible; |
| 6323 | } |
| 6324 | |
| 6325 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
| 6326 | { |
| 6327 | struct drm_device *dev = crtc->dev; |
| 6328 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6330 | int pipe = intel_crtc->pipe; |
| 6331 | bool visible = base != 0; |
| 6332 | |
| 6333 | if (intel_crtc->cursor_visible != visible) { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 6334 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6335 | if (base) { |
| 6336 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
| 6337 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 6338 | cntl |= pipe << 28; /* Connect to correct pipe */ |
| 6339 | } else { |
| 6340 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 6341 | cntl |= CURSOR_MODE_DISABLE; |
| 6342 | } |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6343 | I915_WRITE(CURCNTR(pipe), cntl); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6344 | |
| 6345 | intel_crtc->cursor_visible = visible; |
| 6346 | } |
| 6347 | /* and commit changes on next vblank */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 6348 | I915_WRITE(CURBASE(pipe), base); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6349 | } |
| 6350 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 6351 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
| 6352 | { |
| 6353 | struct drm_device *dev = crtc->dev; |
| 6354 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6355 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6356 | int pipe = intel_crtc->pipe; |
| 6357 | bool visible = base != 0; |
| 6358 | |
| 6359 | if (intel_crtc->cursor_visible != visible) { |
| 6360 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
| 6361 | if (base) { |
| 6362 | cntl &= ~CURSOR_MODE; |
| 6363 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 6364 | } else { |
| 6365 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 6366 | cntl |= CURSOR_MODE_DISABLE; |
| 6367 | } |
| 6368 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
| 6369 | |
| 6370 | intel_crtc->cursor_visible = visible; |
| 6371 | } |
| 6372 | /* and commit changes on next vblank */ |
| 6373 | I915_WRITE(CURBASE_IVB(pipe), base); |
| 6374 | } |
| 6375 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6376 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 6377 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 6378 | bool on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6379 | { |
| 6380 | struct drm_device *dev = crtc->dev; |
| 6381 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6382 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6383 | int pipe = intel_crtc->pipe; |
| 6384 | int x = intel_crtc->cursor_x; |
| 6385 | int y = intel_crtc->cursor_y; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6386 | u32 base, pos; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6387 | bool visible; |
| 6388 | |
| 6389 | pos = 0; |
| 6390 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 6391 | if (on && crtc->enabled && crtc->fb) { |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6392 | base = intel_crtc->cursor_addr; |
| 6393 | if (x > (int) crtc->fb->width) |
| 6394 | base = 0; |
| 6395 | |
| 6396 | if (y > (int) crtc->fb->height) |
| 6397 | base = 0; |
| 6398 | } else |
| 6399 | base = 0; |
| 6400 | |
| 6401 | if (x < 0) { |
| 6402 | if (x + intel_crtc->cursor_width < 0) |
| 6403 | base = 0; |
| 6404 | |
| 6405 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 6406 | x = -x; |
| 6407 | } |
| 6408 | pos |= x << CURSOR_X_SHIFT; |
| 6409 | |
| 6410 | if (y < 0) { |
| 6411 | if (y + intel_crtc->cursor_height < 0) |
| 6412 | base = 0; |
| 6413 | |
| 6414 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 6415 | y = -y; |
| 6416 | } |
| 6417 | pos |= y << CURSOR_Y_SHIFT; |
| 6418 | |
| 6419 | visible = base != 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 6420 | if (!visible && !intel_crtc->cursor_visible) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6421 | return; |
| 6422 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 6423 | if (IS_IVYBRIDGE(dev)) { |
| 6424 | I915_WRITE(CURPOS_IVB(pipe), pos); |
| 6425 | ivb_update_cursor(crtc, base); |
| 6426 | } else { |
| 6427 | I915_WRITE(CURPOS(pipe), pos); |
| 6428 | if (IS_845G(dev) || IS_I865G(dev)) |
| 6429 | i845_update_cursor(crtc, base); |
| 6430 | else |
| 6431 | i9xx_update_cursor(crtc, base); |
| 6432 | } |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6433 | |
| 6434 | if (visible) |
| 6435 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); |
| 6436 | } |
| 6437 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6438 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6439 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6440 | uint32_t handle, |
| 6441 | uint32_t width, uint32_t height) |
| 6442 | { |
| 6443 | struct drm_device *dev = crtc->dev; |
| 6444 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6446 | struct drm_i915_gem_object *obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6447 | uint32_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6448 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6449 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 6450 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6451 | |
| 6452 | /* if we want to turn off the cursor ignore width and height */ |
| 6453 | if (!handle) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 6454 | DRM_DEBUG_KMS("cursor off\n"); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6455 | addr = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6456 | obj = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 6457 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6458 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6459 | } |
| 6460 | |
| 6461 | /* Currently we only support 64x64 cursors */ |
| 6462 | if (width != 64 || height != 64) { |
| 6463 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
| 6464 | return -EINVAL; |
| 6465 | } |
| 6466 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6467 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 6468 | if (&obj->base == NULL) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6469 | return -ENOENT; |
| 6470 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6471 | if (obj->base.size < width * height * 4) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6472 | DRM_ERROR("buffer is to small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 6473 | ret = -ENOMEM; |
| 6474 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6475 | } |
| 6476 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 6477 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 6478 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 6479 | if (!dev_priv->info->cursor_needs_physical) { |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 6480 | if (obj->tiling_mode) { |
| 6481 | DRM_ERROR("cursor cannot be tiled\n"); |
| 6482 | ret = -EINVAL; |
| 6483 | goto fail_locked; |
| 6484 | } |
| 6485 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 6486 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 6487 | if (ret) { |
| 6488 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 6489 | goto fail_locked; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 6490 | } |
| 6491 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 6492 | ret = i915_gem_object_put_fence(obj); |
| 6493 | if (ret) { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 6494 | DRM_ERROR("failed to release fence for cursor"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 6495 | goto fail_unpin; |
| 6496 | } |
| 6497 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6498 | addr = obj->gtt_offset; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 6499 | } else { |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 6500 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6501 | ret = i915_gem_attach_phys_object(dev, obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 6502 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
| 6503 | align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 6504 | if (ret) { |
| 6505 | DRM_ERROR("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 6506 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 6507 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6508 | addr = obj->phys_obj->handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6509 | } |
| 6510 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6511 | if (IS_GEN2(dev)) |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 6512 | I915_WRITE(CURSIZE, (height << 12) | width); |
| 6513 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6514 | finish: |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6515 | if (intel_crtc->cursor_bo) { |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 6516 | if (dev_priv->info->cursor_needs_physical) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6517 | if (intel_crtc->cursor_bo != obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 6518 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
| 6519 | } else |
| 6520 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6521 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6522 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 6523 | |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 6524 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6525 | |
| 6526 | intel_crtc->cursor_addr = addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6527 | intel_crtc->cursor_bo = obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6528 | intel_crtc->cursor_width = width; |
| 6529 | intel_crtc->cursor_height = height; |
| 6530 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 6531 | intel_crtc_update_cursor(crtc, true); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 6532 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6533 | return 0; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 6534 | fail_unpin: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6535 | i915_gem_object_unpin(obj); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 6536 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 6537 | mutex_unlock(&dev->struct_mutex); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 6538 | fail: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6539 | drm_gem_object_unreference_unlocked(&obj->base); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 6540 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6541 | } |
| 6542 | |
| 6543 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 6544 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6546 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 6547 | intel_crtc->cursor_x = x; |
| 6548 | intel_crtc->cursor_y = y; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6549 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 6550 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6551 | |
| 6552 | return 0; |
| 6553 | } |
| 6554 | |
| 6555 | /** Sets the color ramps on behalf of RandR */ |
| 6556 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 6557 | u16 blue, int regno) |
| 6558 | { |
| 6559 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6560 | |
| 6561 | intel_crtc->lut_r[regno] = red >> 8; |
| 6562 | intel_crtc->lut_g[regno] = green >> 8; |
| 6563 | intel_crtc->lut_b[regno] = blue >> 8; |
| 6564 | } |
| 6565 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 6566 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 6567 | u16 *blue, int regno) |
| 6568 | { |
| 6569 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6570 | |
| 6571 | *red = intel_crtc->lut_r[regno] << 8; |
| 6572 | *green = intel_crtc->lut_g[regno] << 8; |
| 6573 | *blue = intel_crtc->lut_b[regno] << 8; |
| 6574 | } |
| 6575 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6576 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 6577 | u16 *blue, uint32_t start, uint32_t size) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6578 | { |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 6579 | int end = (start + size > 256) ? 256 : start + size, i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6581 | |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 6582 | for (i = start; i < end; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6583 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 6584 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 6585 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 6586 | } |
| 6587 | |
| 6588 | intel_crtc_load_lut(crtc); |
| 6589 | } |
| 6590 | |
| 6591 | /** |
| 6592 | * Get a pipe with a simple mode set on it for doing load-based monitor |
| 6593 | * detection. |
| 6594 | * |
| 6595 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 6596 | * its requirements. The pipe will be connected to no other encoders. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6597 | * |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 6598 | * Currently this code will only succeed if there is a pipe with no encoders |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6599 | * configured for it. In the future, it could choose to temporarily disable |
| 6600 | * some outputs to free up a pipe for its use. |
| 6601 | * |
| 6602 | * \return crtc, or NULL if no pipes are available. |
| 6603 | */ |
| 6604 | |
| 6605 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 6606 | static struct drm_display_mode load_detect_mode = { |
| 6607 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 6608 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 6609 | }; |
| 6610 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6611 | static struct drm_framebuffer * |
| 6612 | intel_framebuffer_create(struct drm_device *dev, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6613 | struct drm_mode_fb_cmd2 *mode_cmd, |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6614 | struct drm_i915_gem_object *obj) |
| 6615 | { |
| 6616 | struct intel_framebuffer *intel_fb; |
| 6617 | int ret; |
| 6618 | |
| 6619 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 6620 | if (!intel_fb) { |
| 6621 | drm_gem_object_unreference_unlocked(&obj->base); |
| 6622 | return ERR_PTR(-ENOMEM); |
| 6623 | } |
| 6624 | |
| 6625 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
| 6626 | if (ret) { |
| 6627 | drm_gem_object_unreference_unlocked(&obj->base); |
| 6628 | kfree(intel_fb); |
| 6629 | return ERR_PTR(ret); |
| 6630 | } |
| 6631 | |
| 6632 | return &intel_fb->base; |
| 6633 | } |
| 6634 | |
| 6635 | static u32 |
| 6636 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 6637 | { |
| 6638 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 6639 | return ALIGN(pitch, 64); |
| 6640 | } |
| 6641 | |
| 6642 | static u32 |
| 6643 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 6644 | { |
| 6645 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
| 6646 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
| 6647 | } |
| 6648 | |
| 6649 | static struct drm_framebuffer * |
| 6650 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 6651 | struct drm_display_mode *mode, |
| 6652 | int depth, int bpp) |
| 6653 | { |
| 6654 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6655 | struct drm_mode_fb_cmd2 mode_cmd; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6656 | |
| 6657 | obj = i915_gem_alloc_object(dev, |
| 6658 | intel_framebuffer_size_for_mode(mode, bpp)); |
| 6659 | if (obj == NULL) |
| 6660 | return ERR_PTR(-ENOMEM); |
| 6661 | |
| 6662 | mode_cmd.width = mode->hdisplay; |
| 6663 | mode_cmd.height = mode->vdisplay; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6664 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 6665 | bpp); |
Dave Airlie | 5ca0c34 | 2012-02-23 15:33:40 +0000 | [diff] [blame] | 6666 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6667 | |
| 6668 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
| 6669 | } |
| 6670 | |
| 6671 | static struct drm_framebuffer * |
| 6672 | mode_fits_in_fbdev(struct drm_device *dev, |
| 6673 | struct drm_display_mode *mode) |
| 6674 | { |
| 6675 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6676 | struct drm_i915_gem_object *obj; |
| 6677 | struct drm_framebuffer *fb; |
| 6678 | |
| 6679 | if (dev_priv->fbdev == NULL) |
| 6680 | return NULL; |
| 6681 | |
| 6682 | obj = dev_priv->fbdev->ifb.obj; |
| 6683 | if (obj == NULL) |
| 6684 | return NULL; |
| 6685 | |
| 6686 | fb = &dev_priv->fbdev->ifb.base; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 6687 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 6688 | fb->bits_per_pixel)) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6689 | return NULL; |
| 6690 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 6691 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6692 | return NULL; |
| 6693 | |
| 6694 | return fb; |
| 6695 | } |
| 6696 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 6697 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
| 6698 | struct drm_connector *connector, |
| 6699 | struct drm_display_mode *mode, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6700 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6701 | { |
| 6702 | struct intel_crtc *intel_crtc; |
| 6703 | struct drm_crtc *possible_crtc; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6704 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6705 | struct drm_crtc *crtc = NULL; |
| 6706 | struct drm_device *dev = encoder->dev; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6707 | struct drm_framebuffer *old_fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6708 | int i = -1; |
| 6709 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6710 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 6711 | connector->base.id, drm_get_connector_name(connector), |
| 6712 | encoder->base.id, drm_get_encoder_name(encoder)); |
| 6713 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6714 | /* |
| 6715 | * Algorithm gets a little messy: |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 6716 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6717 | * - if the connector already has an assigned crtc, use it (but make |
| 6718 | * sure it's on first) |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 6719 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6720 | * - try to find the first unused crtc that can drive this connector, |
| 6721 | * and use that if we find one |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6722 | */ |
| 6723 | |
| 6724 | /* See if we already have a CRTC for this connector */ |
| 6725 | if (encoder->crtc) { |
| 6726 | crtc = encoder->crtc; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6727 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6728 | intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6729 | old->dpms_mode = intel_crtc->dpms_mode; |
| 6730 | old->load_detect_temp = false; |
| 6731 | |
| 6732 | /* Make sure the crtc and connector are running */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6733 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 6734 | struct drm_encoder_helper_funcs *encoder_funcs; |
| 6735 | struct drm_crtc_helper_funcs *crtc_funcs; |
| 6736 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6737 | crtc_funcs = crtc->helper_private; |
| 6738 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 6739 | |
| 6740 | encoder_funcs = encoder->helper_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6741 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 6742 | } |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6743 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 6744 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6745 | } |
| 6746 | |
| 6747 | /* Find an unused one (if possible) */ |
| 6748 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
| 6749 | i++; |
| 6750 | if (!(encoder->possible_crtcs & (1 << i))) |
| 6751 | continue; |
| 6752 | if (!possible_crtc->enabled) { |
| 6753 | crtc = possible_crtc; |
| 6754 | break; |
| 6755 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6756 | } |
| 6757 | |
| 6758 | /* |
| 6759 | * If we didn't find an unused CRTC, don't use any. |
| 6760 | */ |
| 6761 | if (!crtc) { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 6762 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
| 6763 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6764 | } |
| 6765 | |
| 6766 | encoder->crtc = crtc; |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 6767 | connector->encoder = encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6768 | |
| 6769 | intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6770 | old->dpms_mode = intel_crtc->dpms_mode; |
| 6771 | old->load_detect_temp = true; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6772 | old->release_fb = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6773 | |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 6774 | if (!mode) |
| 6775 | mode = &load_detect_mode; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6776 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6777 | old_fb = crtc->fb; |
| 6778 | |
| 6779 | /* We need a framebuffer large enough to accommodate all accesses |
| 6780 | * that the plane may generate whilst we perform load detection. |
| 6781 | * We can not rely on the fbcon either being present (we get called |
| 6782 | * during its initialisation to detect all boot displays, or it may |
| 6783 | * not even exist) or that it is large enough to satisfy the |
| 6784 | * requested mode. |
| 6785 | */ |
| 6786 | crtc->fb = mode_fits_in_fbdev(dev, mode); |
| 6787 | if (crtc->fb == NULL) { |
| 6788 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
| 6789 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
| 6790 | old->release_fb = crtc->fb; |
| 6791 | } else |
| 6792 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
| 6793 | if (IS_ERR(crtc->fb)) { |
| 6794 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
| 6795 | crtc->fb = old_fb; |
| 6796 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6797 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6798 | |
| 6799 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 6800 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6801 | if (old->release_fb) |
| 6802 | old->release_fb->funcs->destroy(old->release_fb); |
| 6803 | crtc->fb = old_fb; |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 6804 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6805 | } |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 6806 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6807 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 6808 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6809 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 6810 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6811 | } |
| 6812 | |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 6813 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6814 | struct drm_connector *connector, |
| 6815 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6816 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6817 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6818 | struct drm_device *dev = encoder->dev; |
| 6819 | struct drm_crtc *crtc = encoder->crtc; |
| 6820 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 6821 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 6822 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6823 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 6824 | connector->base.id, drm_get_connector_name(connector), |
| 6825 | encoder->base.id, drm_get_encoder_name(encoder)); |
| 6826 | |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6827 | if (old->load_detect_temp) { |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 6828 | connector->encoder = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6829 | drm_helper_disable_unused_functions(dev); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6830 | |
| 6831 | if (old->release_fb) |
| 6832 | old->release_fb->funcs->destroy(old->release_fb); |
| 6833 | |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 6834 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6835 | } |
| 6836 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 6837 | /* Switch crtc and encoder back off if necessary */ |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 6838 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
| 6839 | encoder_funcs->dpms(encoder, old->dpms_mode); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 6840 | crtc_funcs->dpms(crtc, old->dpms_mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6841 | } |
| 6842 | } |
| 6843 | |
| 6844 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 6845 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
| 6846 | { |
| 6847 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6849 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 6850 | u32 dpll = I915_READ(DPLL(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6851 | u32 fp; |
| 6852 | intel_clock_t clock; |
| 6853 | |
| 6854 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Chris Wilson | 39adb7a | 2011-04-22 22:17:21 +0100 | [diff] [blame] | 6855 | fp = I915_READ(FP0(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6856 | else |
Chris Wilson | 39adb7a | 2011-04-22 22:17:21 +0100 | [diff] [blame] | 6857 | fp = I915_READ(FP1(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6858 | |
| 6859 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 6860 | if (IS_PINEVIEW(dev)) { |
| 6861 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 6862 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 6863 | } else { |
| 6864 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 6865 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 6866 | } |
| 6867 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6868 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 6869 | if (IS_PINEVIEW(dev)) |
| 6870 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 6871 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 6872 | else |
| 6873 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6874 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 6875 | |
| 6876 | switch (dpll & DPLL_MODE_MASK) { |
| 6877 | case DPLLB_MODE_DAC_SERIAL: |
| 6878 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 6879 | 5 : 10; |
| 6880 | break; |
| 6881 | case DPLLB_MODE_LVDS: |
| 6882 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 6883 | 7 : 14; |
| 6884 | break; |
| 6885 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 6886 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6887 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
| 6888 | return 0; |
| 6889 | } |
| 6890 | |
| 6891 | /* XXX: Handle the 100Mhz refclk */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 6892 | intel_clock(dev, 96000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6893 | } else { |
| 6894 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
| 6895 | |
| 6896 | if (is_lvds) { |
| 6897 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 6898 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 6899 | clock.p2 = 14; |
| 6900 | |
| 6901 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 6902 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 6903 | /* XXX: might not be 66MHz */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 6904 | intel_clock(dev, 66000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6905 | } else |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 6906 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6907 | } else { |
| 6908 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 6909 | clock.p1 = 2; |
| 6910 | else { |
| 6911 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 6912 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 6913 | } |
| 6914 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 6915 | clock.p2 = 4; |
| 6916 | else |
| 6917 | clock.p2 = 2; |
| 6918 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 6919 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6920 | } |
| 6921 | } |
| 6922 | |
| 6923 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 6924 | * i830PllIsValid() because it relies on the xf86_config connector |
| 6925 | * configuration being accurate, which it isn't necessarily. |
| 6926 | */ |
| 6927 | |
| 6928 | return clock.dot; |
| 6929 | } |
| 6930 | |
| 6931 | /** Returns the currently programmed mode of the given pipe. */ |
| 6932 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 6933 | struct drm_crtc *crtc) |
| 6934 | { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 6935 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6937 | int pipe = intel_crtc->pipe; |
| 6938 | struct drm_display_mode *mode; |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 6939 | int htot = I915_READ(HTOTAL(pipe)); |
| 6940 | int hsync = I915_READ(HSYNC(pipe)); |
| 6941 | int vtot = I915_READ(VTOTAL(pipe)); |
| 6942 | int vsync = I915_READ(VSYNC(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6943 | |
| 6944 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 6945 | if (!mode) |
| 6946 | return NULL; |
| 6947 | |
| 6948 | mode->clock = intel_crtc_clock_get(dev, crtc); |
| 6949 | mode->hdisplay = (htot & 0xffff) + 1; |
| 6950 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 6951 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 6952 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 6953 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 6954 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 6955 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 6956 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 6957 | |
| 6958 | drm_mode_set_name(mode); |
| 6959 | drm_mode_set_crtcinfo(mode, 0); |
| 6960 | |
| 6961 | return mode; |
| 6962 | } |
| 6963 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6964 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
| 6965 | |
| 6966 | /* When this timer fires, we've been idle for awhile */ |
| 6967 | static void intel_gpu_idle_timer(unsigned long arg) |
| 6968 | { |
| 6969 | struct drm_device *dev = (struct drm_device *)arg; |
| 6970 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 6971 | |
Chris Wilson | ff7ea4c | 2010-12-08 09:43:41 +0000 | [diff] [blame] | 6972 | if (!list_empty(&dev_priv->mm.active_list)) { |
| 6973 | /* Still processing requests, so just re-arm the timer. */ |
| 6974 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 6975 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
| 6976 | return; |
| 6977 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6978 | |
Chris Wilson | ff7ea4c | 2010-12-08 09:43:41 +0000 | [diff] [blame] | 6979 | dev_priv->busy = false; |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 6980 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6981 | } |
| 6982 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6983 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
| 6984 | |
| 6985 | static void intel_crtc_idle_timer(unsigned long arg) |
| 6986 | { |
| 6987 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; |
| 6988 | struct drm_crtc *crtc = &intel_crtc->base; |
| 6989 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; |
Chris Wilson | ff7ea4c | 2010-12-08 09:43:41 +0000 | [diff] [blame] | 6990 | struct intel_framebuffer *intel_fb; |
| 6991 | |
| 6992 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 6993 | if (intel_fb && intel_fb->obj->active) { |
| 6994 | /* The framebuffer is still being accessed by the GPU. */ |
| 6995 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 6996 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 6997 | return; |
| 6998 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6999 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7000 | intel_crtc->busy = false; |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 7001 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7002 | } |
| 7003 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 7004 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7005 | { |
| 7006 | struct drm_device *dev = crtc->dev; |
| 7007 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7009 | int pipe = intel_crtc->pipe; |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 7010 | int dpll_reg = DPLL(pipe); |
| 7011 | int dpll; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7012 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 7013 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7014 | return; |
| 7015 | |
| 7016 | if (!dev_priv->lvds_downclock_avail) |
| 7017 | return; |
| 7018 | |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 7019 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7020 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 7021 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7022 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 7023 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7024 | |
| 7025 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 7026 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 7027 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 7028 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7029 | dpll = I915_READ(dpll_reg); |
| 7030 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 7031 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7032 | } |
| 7033 | |
| 7034 | /* Schedule downclock */ |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 7035 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 7036 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7037 | } |
| 7038 | |
| 7039 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 7040 | { |
| 7041 | struct drm_device *dev = crtc->dev; |
| 7042 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7044 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 7045 | int dpll_reg = DPLL(pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7046 | int dpll = I915_READ(dpll_reg); |
| 7047 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 7048 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7049 | return; |
| 7050 | |
| 7051 | if (!dev_priv->lvds_downclock_avail) |
| 7052 | return; |
| 7053 | |
| 7054 | /* |
| 7055 | * Since this is called by a timer, we should never get here in |
| 7056 | * the manual case. |
| 7057 | */ |
| 7058 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 7059 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7060 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 7061 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7062 | |
| 7063 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 7064 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 7065 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7066 | dpll = I915_READ(dpll_reg); |
| 7067 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 7068 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7069 | } |
| 7070 | |
| 7071 | } |
| 7072 | |
| 7073 | /** |
| 7074 | * intel_idle_update - adjust clocks for idleness |
| 7075 | * @work: work struct |
| 7076 | * |
| 7077 | * Either the GPU or display (or both) went idle. Check the busy status |
| 7078 | * here and adjust the CRTC and GPU clocks as necessary. |
| 7079 | */ |
| 7080 | static void intel_idle_update(struct work_struct *work) |
| 7081 | { |
| 7082 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 7083 | idle_work); |
| 7084 | struct drm_device *dev = dev_priv->dev; |
| 7085 | struct drm_crtc *crtc; |
| 7086 | struct intel_crtc *intel_crtc; |
| 7087 | |
| 7088 | if (!i915_powersave) |
| 7089 | return; |
| 7090 | |
| 7091 | mutex_lock(&dev->struct_mutex); |
| 7092 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 7093 | i915_update_gfx_val(dev_priv); |
| 7094 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7095 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 7096 | /* Skip inactive CRTCs */ |
| 7097 | if (!crtc->fb) |
| 7098 | continue; |
| 7099 | |
| 7100 | intel_crtc = to_intel_crtc(crtc); |
| 7101 | if (!intel_crtc->busy) |
| 7102 | intel_decrease_pllclock(crtc); |
| 7103 | } |
| 7104 | |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 7105 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7106 | mutex_unlock(&dev->struct_mutex); |
| 7107 | } |
| 7108 | |
| 7109 | /** |
| 7110 | * intel_mark_busy - mark the GPU and possibly the display busy |
| 7111 | * @dev: drm device |
| 7112 | * @obj: object we're operating on |
| 7113 | * |
| 7114 | * Callers can use this function to indicate that the GPU is busy processing |
| 7115 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout |
| 7116 | * buffer), we'll also mark the display as busy, so we know to increase its |
| 7117 | * clock frequency. |
| 7118 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7119 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7120 | { |
| 7121 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7122 | struct drm_crtc *crtc = NULL; |
| 7123 | struct intel_framebuffer *intel_fb; |
| 7124 | struct intel_crtc *intel_crtc; |
| 7125 | |
Zhenyu Wang | 5e17ee7 | 2009-09-03 09:30:06 +0800 | [diff] [blame] | 7126 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 7127 | return; |
| 7128 | |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 7129 | if (!dev_priv->busy) |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 7130 | dev_priv->busy = true; |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 7131 | else |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 7132 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 7133 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7134 | |
| 7135 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 7136 | if (!crtc->fb) |
| 7137 | continue; |
| 7138 | |
| 7139 | intel_crtc = to_intel_crtc(crtc); |
| 7140 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 7141 | if (intel_fb->obj == obj) { |
| 7142 | if (!intel_crtc->busy) { |
| 7143 | /* Non-busy -> busy, upclock */ |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 7144 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7145 | intel_crtc->busy = true; |
| 7146 | } else { |
| 7147 | /* Busy -> busy, put off timer */ |
| 7148 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 7149 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 7150 | } |
| 7151 | } |
| 7152 | } |
| 7153 | } |
| 7154 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7155 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 7156 | { |
| 7157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 7158 | struct drm_device *dev = crtc->dev; |
| 7159 | struct intel_unpin_work *work; |
| 7160 | unsigned long flags; |
| 7161 | |
| 7162 | spin_lock_irqsave(&dev->event_lock, flags); |
| 7163 | work = intel_crtc->unpin_work; |
| 7164 | intel_crtc->unpin_work = NULL; |
| 7165 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7166 | |
| 7167 | if (work) { |
| 7168 | cancel_work_sync(&work->work); |
| 7169 | kfree(work); |
| 7170 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7171 | |
| 7172 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 7173 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7174 | kfree(intel_crtc); |
| 7175 | } |
| 7176 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7177 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 7178 | { |
| 7179 | struct intel_unpin_work *work = |
| 7180 | container_of(__work, struct intel_unpin_work, work); |
| 7181 | |
| 7182 | mutex_lock(&work->dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 7183 | intel_unpin_fb_obj(work->old_fb_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7184 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
| 7185 | drm_gem_object_unreference(&work->old_fb_obj->base); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7186 | |
Chris Wilson | 7782de3 | 2011-07-08 12:22:41 +0100 | [diff] [blame] | 7187 | intel_update_fbc(work->dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7188 | mutex_unlock(&work->dev->struct_mutex); |
| 7189 | kfree(work); |
| 7190 | } |
| 7191 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 7192 | static void do_intel_finish_page_flip(struct drm_device *dev, |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7193 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7194 | { |
| 7195 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7197 | struct intel_unpin_work *work; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7198 | struct drm_i915_gem_object *obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7199 | struct drm_pending_vblank_event *e; |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7200 | struct timeval tnow, tvbl; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7201 | unsigned long flags; |
| 7202 | |
| 7203 | /* Ignore early vblank irqs */ |
| 7204 | if (intel_crtc == NULL) |
| 7205 | return; |
| 7206 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7207 | do_gettimeofday(&tnow); |
| 7208 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7209 | spin_lock_irqsave(&dev->event_lock, flags); |
| 7210 | work = intel_crtc->unpin_work; |
| 7211 | if (work == NULL || !work->pending) { |
| 7212 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7213 | return; |
| 7214 | } |
| 7215 | |
| 7216 | intel_crtc->unpin_work = NULL; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7217 | |
| 7218 | if (work->event) { |
| 7219 | e = work->event; |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7220 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 7221 | |
| 7222 | /* Called before vblank count and timestamps have |
| 7223 | * been updated for the vblank interval of flip |
| 7224 | * completion? Need to increment vblank count and |
| 7225 | * add one videorefresh duration to returned timestamp |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7226 | * to account for this. We assume this happened if we |
| 7227 | * get called over 0.9 frame durations after the last |
| 7228 | * timestamped vblank. |
| 7229 | * |
| 7230 | * This calculation can not be used with vrefresh rates |
| 7231 | * below 5Hz (10Hz to be on the safe side) without |
| 7232 | * promoting to 64 integers. |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 7233 | */ |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7234 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
| 7235 | 9 * crtc->framedur_ns) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 7236 | e->event.sequence++; |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7237 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
| 7238 | crtc->framedur_ns); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 7239 | } |
| 7240 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7241 | e->event.tv_sec = tvbl.tv_sec; |
| 7242 | e->event.tv_usec = tvbl.tv_usec; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 7243 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7244 | list_add_tail(&e->base.link, |
| 7245 | &e->base.file_priv->event_list); |
| 7246 | wake_up_interruptible(&e->base.file_priv->event_wait); |
| 7247 | } |
| 7248 | |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 7249 | drm_vblank_put(dev, intel_crtc->pipe); |
| 7250 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7251 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7252 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7253 | obj = work->old_fb_obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7254 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 7255 | atomic_clear_mask(1 << intel_crtc->plane, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7256 | &obj->pending_flip.counter); |
| 7257 | if (atomic_read(&obj->pending_flip) == 0) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 7258 | wake_up(&dev_priv->pending_flip_queue); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7259 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7260 | schedule_work(&work->work); |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 7261 | |
| 7262 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7263 | } |
| 7264 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 7265 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 7266 | { |
| 7267 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7268 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 7269 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7270 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 7271 | } |
| 7272 | |
| 7273 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 7274 | { |
| 7275 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7276 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 7277 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 7278 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 7279 | } |
| 7280 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7281 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 7282 | { |
| 7283 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7284 | struct intel_crtc *intel_crtc = |
| 7285 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 7286 | unsigned long flags; |
| 7287 | |
| 7288 | spin_lock_irqsave(&dev->event_lock, flags); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 7289 | if (intel_crtc->unpin_work) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 7290 | if ((++intel_crtc->unpin_work->pending) > 1) |
| 7291 | DRM_ERROR("Prepared flip multiple times\n"); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 7292 | } else { |
| 7293 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
| 7294 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7295 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7296 | } |
| 7297 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7298 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 7299 | struct drm_crtc *crtc, |
| 7300 | struct drm_framebuffer *fb, |
| 7301 | struct drm_i915_gem_object *obj) |
| 7302 | { |
| 7303 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7305 | unsigned long offset; |
| 7306 | u32 flip_mask; |
| 7307 | int ret; |
| 7308 | |
| 7309 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
| 7310 | if (ret) |
| 7311 | goto out; |
| 7312 | |
| 7313 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7314 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7315 | |
| 7316 | ret = BEGIN_LP_RING(6); |
| 7317 | if (ret) |
| 7318 | goto out; |
| 7319 | |
| 7320 | /* Can't queue multiple flips, so wait for the previous |
| 7321 | * one to finish before executing the next. |
| 7322 | */ |
| 7323 | if (intel_crtc->plane) |
| 7324 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 7325 | else |
| 7326 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 7327 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); |
| 7328 | OUT_RING(MI_NOOP); |
| 7329 | OUT_RING(MI_DISPLAY_FLIP | |
| 7330 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7331 | OUT_RING(fb->pitches[0]); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7332 | OUT_RING(obj->gtt_offset + offset); |
Daniel Vetter | c6a32fc | 2012-01-20 10:43:44 +0100 | [diff] [blame] | 7333 | OUT_RING(0); /* aux display base address, unused */ |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7334 | ADVANCE_LP_RING(); |
| 7335 | out: |
| 7336 | return ret; |
| 7337 | } |
| 7338 | |
| 7339 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 7340 | struct drm_crtc *crtc, |
| 7341 | struct drm_framebuffer *fb, |
| 7342 | struct drm_i915_gem_object *obj) |
| 7343 | { |
| 7344 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7346 | unsigned long offset; |
| 7347 | u32 flip_mask; |
| 7348 | int ret; |
| 7349 | |
| 7350 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
| 7351 | if (ret) |
| 7352 | goto out; |
| 7353 | |
| 7354 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7355 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7356 | |
| 7357 | ret = BEGIN_LP_RING(6); |
| 7358 | if (ret) |
| 7359 | goto out; |
| 7360 | |
| 7361 | if (intel_crtc->plane) |
| 7362 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 7363 | else |
| 7364 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 7365 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); |
| 7366 | OUT_RING(MI_NOOP); |
| 7367 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
| 7368 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7369 | OUT_RING(fb->pitches[0]); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7370 | OUT_RING(obj->gtt_offset + offset); |
| 7371 | OUT_RING(MI_NOOP); |
| 7372 | |
| 7373 | ADVANCE_LP_RING(); |
| 7374 | out: |
| 7375 | return ret; |
| 7376 | } |
| 7377 | |
| 7378 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 7379 | struct drm_crtc *crtc, |
| 7380 | struct drm_framebuffer *fb, |
| 7381 | struct drm_i915_gem_object *obj) |
| 7382 | { |
| 7383 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7385 | uint32_t pf, pipesrc; |
| 7386 | int ret; |
| 7387 | |
| 7388 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
| 7389 | if (ret) |
| 7390 | goto out; |
| 7391 | |
| 7392 | ret = BEGIN_LP_RING(4); |
| 7393 | if (ret) |
| 7394 | goto out; |
| 7395 | |
| 7396 | /* i965+ uses the linear or tiled offsets from the |
| 7397 | * Display Registers (which do not change across a page-flip) |
| 7398 | * so we need only reprogram the base address. |
| 7399 | */ |
| 7400 | OUT_RING(MI_DISPLAY_FLIP | |
| 7401 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7402 | OUT_RING(fb->pitches[0]); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7403 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
| 7404 | |
| 7405 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 7406 | * untested on non-native modes, so ignore it for now. |
| 7407 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 7408 | */ |
| 7409 | pf = 0; |
| 7410 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
| 7411 | OUT_RING(pf | pipesrc); |
| 7412 | ADVANCE_LP_RING(); |
| 7413 | out: |
| 7414 | return ret; |
| 7415 | } |
| 7416 | |
| 7417 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 7418 | struct drm_crtc *crtc, |
| 7419 | struct drm_framebuffer *fb, |
| 7420 | struct drm_i915_gem_object *obj) |
| 7421 | { |
| 7422 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7424 | uint32_t pf, pipesrc; |
| 7425 | int ret; |
| 7426 | |
| 7427 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
| 7428 | if (ret) |
| 7429 | goto out; |
| 7430 | |
| 7431 | ret = BEGIN_LP_RING(4); |
| 7432 | if (ret) |
| 7433 | goto out; |
| 7434 | |
| 7435 | OUT_RING(MI_DISPLAY_FLIP | |
| 7436 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7437 | OUT_RING(fb->pitches[0] | obj->tiling_mode); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7438 | OUT_RING(obj->gtt_offset); |
| 7439 | |
| 7440 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 7441 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
| 7442 | OUT_RING(pf | pipesrc); |
| 7443 | ADVANCE_LP_RING(); |
| 7444 | out: |
| 7445 | return ret; |
| 7446 | } |
| 7447 | |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 7448 | /* |
| 7449 | * On gen7 we currently use the blit ring because (in early silicon at least) |
| 7450 | * the render ring doesn't give us interrpts for page flip completion, which |
| 7451 | * means clients will hang after the first flip is queued. Fortunately the |
| 7452 | * blit ring generates interrupts properly, so use it instead. |
| 7453 | */ |
| 7454 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 7455 | struct drm_crtc *crtc, |
| 7456 | struct drm_framebuffer *fb, |
| 7457 | struct drm_i915_gem_object *obj) |
| 7458 | { |
| 7459 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7461 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
| 7462 | int ret; |
| 7463 | |
| 7464 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
| 7465 | if (ret) |
| 7466 | goto out; |
| 7467 | |
| 7468 | ret = intel_ring_begin(ring, 4); |
| 7469 | if (ret) |
| 7470 | goto out; |
| 7471 | |
| 7472 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7473 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 7474 | intel_ring_emit(ring, (obj->gtt_offset)); |
| 7475 | intel_ring_emit(ring, (MI_NOOP)); |
| 7476 | intel_ring_advance(ring); |
| 7477 | out: |
| 7478 | return ret; |
| 7479 | } |
| 7480 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7481 | static int intel_default_queue_flip(struct drm_device *dev, |
| 7482 | struct drm_crtc *crtc, |
| 7483 | struct drm_framebuffer *fb, |
| 7484 | struct drm_i915_gem_object *obj) |
| 7485 | { |
| 7486 | return -ENODEV; |
| 7487 | } |
| 7488 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7489 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 7490 | struct drm_framebuffer *fb, |
| 7491 | struct drm_pending_vblank_event *event) |
| 7492 | { |
| 7493 | struct drm_device *dev = crtc->dev; |
| 7494 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7495 | struct intel_framebuffer *intel_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7496 | struct drm_i915_gem_object *obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7498 | struct intel_unpin_work *work; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7499 | unsigned long flags; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 7500 | int ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7501 | |
| 7502 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 7503 | if (work == NULL) |
| 7504 | return -ENOMEM; |
| 7505 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7506 | work->event = event; |
| 7507 | work->dev = crtc->dev; |
| 7508 | intel_fb = to_intel_framebuffer(crtc->fb); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 7509 | work->old_fb_obj = intel_fb->obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7510 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 7511 | |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 7512 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
| 7513 | if (ret) |
| 7514 | goto free_work; |
| 7515 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7516 | /* We borrow the event spin lock for protecting unpin_work */ |
| 7517 | spin_lock_irqsave(&dev->event_lock, flags); |
| 7518 | if (intel_crtc->unpin_work) { |
| 7519 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7520 | kfree(work); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 7521 | drm_vblank_put(dev, intel_crtc->pipe); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 7522 | |
| 7523 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7524 | return -EBUSY; |
| 7525 | } |
| 7526 | intel_crtc->unpin_work = work; |
| 7527 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7528 | |
| 7529 | intel_fb = to_intel_framebuffer(fb); |
| 7530 | obj = intel_fb->obj; |
| 7531 | |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 7532 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7533 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 7534 | /* Reference the objects for the scheduled work. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7535 | drm_gem_object_reference(&work->old_fb_obj->base); |
| 7536 | drm_gem_object_reference(&obj->base); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7537 | |
| 7538 | crtc->fb = fb; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 7539 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 7540 | work->pending_flip_obj = obj; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 7541 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 7542 | work->enable_stall_check = true; |
| 7543 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 7544 | /* Block clients from rendering to the new back buffer until |
| 7545 | * the flip occurs and the object is no longer visible. |
| 7546 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7547 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 7548 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7549 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
| 7550 | if (ret) |
| 7551 | goto cleanup_pending; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7552 | |
Chris Wilson | 7782de3 | 2011-07-08 12:22:41 +0100 | [diff] [blame] | 7553 | intel_disable_fbc(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7554 | mutex_unlock(&dev->struct_mutex); |
| 7555 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 7556 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 7557 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7558 | return 0; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 7559 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 7560 | cleanup_pending: |
| 7561 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7562 | drm_gem_object_unreference(&work->old_fb_obj->base); |
| 7563 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 7564 | mutex_unlock(&dev->struct_mutex); |
| 7565 | |
| 7566 | spin_lock_irqsave(&dev->event_lock, flags); |
| 7567 | intel_crtc->unpin_work = NULL; |
| 7568 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 7569 | |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 7570 | drm_vblank_put(dev, intel_crtc->pipe); |
| 7571 | free_work: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 7572 | kfree(work); |
| 7573 | |
| 7574 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 7575 | } |
| 7576 | |
Chris Wilson | 47f1c6c | 2010-12-03 15:37:31 +0000 | [diff] [blame] | 7577 | static void intel_sanitize_modesetting(struct drm_device *dev, |
| 7578 | int pipe, int plane) |
| 7579 | { |
| 7580 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7581 | u32 reg, val; |
| 7582 | |
Chris Wilson | f47166d | 2012-03-22 15:00:50 +0000 | [diff] [blame] | 7583 | /* Clear any frame start delays used for debugging left by the BIOS */ |
| 7584 | for_each_pipe(pipe) { |
| 7585 | reg = PIPECONF(pipe); |
| 7586 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 7587 | } |
| 7588 | |
Chris Wilson | 47f1c6c | 2010-12-03 15:37:31 +0000 | [diff] [blame] | 7589 | if (HAS_PCH_SPLIT(dev)) |
| 7590 | return; |
| 7591 | |
| 7592 | /* Who knows what state these registers were left in by the BIOS or |
| 7593 | * grub? |
| 7594 | * |
| 7595 | * If we leave the registers in a conflicting state (e.g. with the |
| 7596 | * display plane reading from the other pipe than the one we intend |
| 7597 | * to use) then when we attempt to teardown the active mode, we will |
| 7598 | * not disable the pipes and planes in the correct order -- leaving |
| 7599 | * a plane reading from a disabled pipe and possibly leading to |
| 7600 | * undefined behaviour. |
| 7601 | */ |
| 7602 | |
| 7603 | reg = DSPCNTR(plane); |
| 7604 | val = I915_READ(reg); |
| 7605 | |
| 7606 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
| 7607 | return; |
| 7608 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) |
| 7609 | return; |
| 7610 | |
| 7611 | /* This display plane is active and attached to the other CPU pipe. */ |
| 7612 | pipe = !pipe; |
| 7613 | |
| 7614 | /* Disable the plane and wait for it to stop reading from the pipe. */ |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 7615 | intel_disable_plane(dev_priv, plane, pipe); |
| 7616 | intel_disable_pipe(dev_priv, pipe); |
Chris Wilson | 47f1c6c | 2010-12-03 15:37:31 +0000 | [diff] [blame] | 7617 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7618 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 7619 | static void intel_crtc_reset(struct drm_crtc *crtc) |
| 7620 | { |
| 7621 | struct drm_device *dev = crtc->dev; |
| 7622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7623 | |
| 7624 | /* Reset flags back to the 'unknown' status so that they |
| 7625 | * will be correctly set on the initial modeset. |
| 7626 | */ |
| 7627 | intel_crtc->dpms_mode = -1; |
| 7628 | |
| 7629 | /* We need to fix up any BIOS configuration that conflicts with |
| 7630 | * our expectations. |
| 7631 | */ |
| 7632 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); |
| 7633 | } |
| 7634 | |
| 7635 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
| 7636 | .dpms = intel_crtc_dpms, |
| 7637 | .mode_fixup = intel_crtc_mode_fixup, |
| 7638 | .mode_set = intel_crtc_mode_set, |
| 7639 | .mode_set_base = intel_pipe_set_base, |
| 7640 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
| 7641 | .load_lut = intel_crtc_load_lut, |
| 7642 | .disable = intel_crtc_disable, |
| 7643 | }; |
| 7644 | |
| 7645 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
| 7646 | .reset = intel_crtc_reset, |
| 7647 | .cursor_set = intel_crtc_cursor_set, |
| 7648 | .cursor_move = intel_crtc_cursor_move, |
| 7649 | .gamma_set = intel_crtc_gamma_set, |
| 7650 | .set_config = drm_crtc_helper_set_config, |
| 7651 | .destroy = intel_crtc_destroy, |
| 7652 | .page_flip = intel_crtc_page_flip, |
| 7653 | }; |
| 7654 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 7655 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7656 | { |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 7657 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7658 | struct intel_crtc *intel_crtc; |
| 7659 | int i; |
| 7660 | |
| 7661 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 7662 | if (intel_crtc == NULL) |
| 7663 | return; |
| 7664 | |
| 7665 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
| 7666 | |
| 7667 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7668 | for (i = 0; i < 256; i++) { |
| 7669 | intel_crtc->lut_r[i] = i; |
| 7670 | intel_crtc->lut_g[i] = i; |
| 7671 | intel_crtc->lut_b[i] = i; |
| 7672 | } |
| 7673 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 7674 | /* Swap pipes & planes for FBC on pre-965 */ |
| 7675 | intel_crtc->pipe = pipe; |
| 7676 | intel_crtc->plane = pipe; |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 7677 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 7678 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 7679 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 7680 | } |
| 7681 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 7682 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 7683 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 7684 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 7685 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 7686 | |
Chris Wilson | 5d1d0cc | 2011-01-24 15:02:15 +0000 | [diff] [blame] | 7687 | intel_crtc_reset(&intel_crtc->base); |
Chris Wilson | 04dbff5 | 2011-02-10 17:38:35 +0000 | [diff] [blame] | 7688 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 7689 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 7690 | |
| 7691 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 7692 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
| 7693 | intel_crtc->no_pll = true; |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 7694 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
| 7695 | intel_helper_funcs.commit = ironlake_crtc_commit; |
| 7696 | } else { |
| 7697 | intel_helper_funcs.prepare = i9xx_crtc_prepare; |
| 7698 | intel_helper_funcs.commit = i9xx_crtc_commit; |
| 7699 | } |
| 7700 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7701 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
| 7702 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7703 | intel_crtc->busy = false; |
| 7704 | |
| 7705 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, |
| 7706 | (unsigned long)intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7707 | } |
| 7708 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7709 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7710 | struct drm_file *file) |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7711 | { |
| 7712 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 7713 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 7714 | struct drm_mode_object *drmmode_obj; |
| 7715 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7716 | |
| 7717 | if (!dev_priv) { |
| 7718 | DRM_ERROR("called with no initialization\n"); |
| 7719 | return -EINVAL; |
| 7720 | } |
| 7721 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 7722 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 7723 | DRM_MODE_OBJECT_CRTC); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7724 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 7725 | if (!drmmode_obj) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7726 | DRM_ERROR("no such CRTC id\n"); |
| 7727 | return -EINVAL; |
| 7728 | } |
| 7729 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 7730 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 7731 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7732 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 7733 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 7734 | } |
| 7735 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 7736 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7737 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 7738 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7739 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7740 | int entry = 0; |
| 7741 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 7742 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 7743 | if (type_mask & encoder->clone_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7744 | index_mask |= (1 << entry); |
| 7745 | entry++; |
| 7746 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 7747 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7748 | return index_mask; |
| 7749 | } |
| 7750 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 7751 | static bool has_edp_a(struct drm_device *dev) |
| 7752 | { |
| 7753 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7754 | |
| 7755 | if (!IS_MOBILE(dev)) |
| 7756 | return false; |
| 7757 | |
| 7758 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 7759 | return false; |
| 7760 | |
| 7761 | if (IS_GEN5(dev) && |
| 7762 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
| 7763 | return false; |
| 7764 | |
| 7765 | return true; |
| 7766 | } |
| 7767 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7768 | static void intel_setup_outputs(struct drm_device *dev) |
| 7769 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7770 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 7771 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 7772 | bool dpd_is_edp = false; |
Chris Wilson | f3cfcba | 2012-02-09 09:35:53 +0000 | [diff] [blame] | 7773 | bool has_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7774 | |
Chris Wilson | f3cfcba | 2012-02-09 09:35:53 +0000 | [diff] [blame] | 7775 | has_lvds = intel_lvds_init(dev); |
Chris Wilson | c5d1b51 | 2010-11-29 18:00:23 +0000 | [diff] [blame] | 7776 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
| 7777 | /* disable the panel fitter on everything but LVDS */ |
| 7778 | I915_WRITE(PFIT_CONTROL, 0); |
| 7779 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7780 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 7781 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 7782 | dpd_is_edp = intel_dpd_is_edp(dev); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 7783 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 7784 | if (has_edp_a(dev)) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 7785 | intel_dp_init(dev, DP_A); |
| 7786 | |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 7787 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
| 7788 | intel_dp_init(dev, PCH_DP_D); |
| 7789 | } |
| 7790 | |
| 7791 | intel_crt_init(dev); |
| 7792 | |
| 7793 | if (HAS_PCH_SPLIT(dev)) { |
| 7794 | int found; |
| 7795 | |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 7796 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 7797 | /* PCH SDVOB multiplex with HDMIB */ |
| 7798 | found = intel_sdvo_init(dev, PCH_SDVOB); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 7799 | if (!found) |
| 7800 | intel_hdmi_init(dev, HDMIB); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 7801 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
| 7802 | intel_dp_init(dev, PCH_DP_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 7803 | } |
| 7804 | |
| 7805 | if (I915_READ(HDMIC) & PORT_DETECTED) |
| 7806 | intel_hdmi_init(dev, HDMIC); |
| 7807 | |
| 7808 | if (I915_READ(HDMID) & PORT_DETECTED) |
| 7809 | intel_hdmi_init(dev, HDMID); |
| 7810 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 7811 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
| 7812 | intel_dp_init(dev, PCH_DP_C); |
| 7813 | |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 7814 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 7815 | intel_dp_init(dev, PCH_DP_D); |
| 7816 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 7817 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 7818 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 7819 | |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7820 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7821 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7822 | found = intel_sdvo_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7823 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 7824 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7825 | intel_hdmi_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7826 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 7827 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7828 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
| 7829 | DRM_DEBUG_KMS("probing DP_B\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 7830 | intel_dp_init(dev, DP_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7831 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7832 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 7833 | |
| 7834 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 7835 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7836 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
| 7837 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7838 | found = intel_sdvo_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7839 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 7840 | |
| 7841 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
| 7842 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7843 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 7844 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7845 | intel_hdmi_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7846 | } |
| 7847 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
| 7848 | DRM_DEBUG_KMS("probing DP_C\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 7849 | intel_dp_init(dev, DP_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7850 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 7851 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 7852 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7853 | if (SUPPORTS_INTEGRATED_DP(dev) && |
| 7854 | (I915_READ(DP_D) & DP_DETECTED)) { |
| 7855 | DRM_DEBUG_KMS("probing DP_D\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 7856 | intel_dp_init(dev, DP_D); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 7857 | } |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 7858 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7859 | intel_dvo_init(dev); |
| 7860 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 7861 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7862 | intel_tv_init(dev); |
| 7863 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 7864 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 7865 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 7866 | encoder->base.possible_clones = |
| 7867 | intel_encoder_clones(dev, encoder->clone_mask); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7868 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 7869 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 7870 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
| 7871 | drm_helper_disable_unused_functions(dev); |
Keith Packard | 9fb526d | 2011-09-26 22:24:57 -0700 | [diff] [blame] | 7872 | |
| 7873 | if (HAS_PCH_SPLIT(dev)) |
| 7874 | ironlake_init_pch_refclk(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7875 | } |
| 7876 | |
| 7877 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 7878 | { |
| 7879 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7880 | |
| 7881 | drm_framebuffer_cleanup(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7882 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7883 | |
| 7884 | kfree(intel_fb); |
| 7885 | } |
| 7886 | |
| 7887 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7888 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7889 | unsigned int *handle) |
| 7890 | { |
| 7891 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7892 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7893 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7894 | return drm_gem_handle_create(file, &obj->base, handle); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7895 | } |
| 7896 | |
| 7897 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 7898 | .destroy = intel_user_framebuffer_destroy, |
| 7899 | .create_handle = intel_user_framebuffer_create_handle, |
| 7900 | }; |
| 7901 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 7902 | int intel_framebuffer_init(struct drm_device *dev, |
| 7903 | struct intel_framebuffer *intel_fb, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7904 | struct drm_mode_fb_cmd2 *mode_cmd, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7905 | struct drm_i915_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7906 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7907 | int ret; |
| 7908 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7909 | if (obj->tiling_mode == I915_TILING_Y) |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 7910 | return -EINVAL; |
| 7911 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7912 | if (mode_cmd->pitches[0] & 63) |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 7913 | return -EINVAL; |
| 7914 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7915 | switch (mode_cmd->pixel_format) { |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 7916 | case DRM_FORMAT_RGB332: |
| 7917 | case DRM_FORMAT_RGB565: |
| 7918 | case DRM_FORMAT_XRGB8888: |
Jesse Barnes | b250da7 | 2012-03-07 08:49:29 -0800 | [diff] [blame] | 7919 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 7920 | case DRM_FORMAT_ARGB8888: |
| 7921 | case DRM_FORMAT_XRGB2101010: |
| 7922 | case DRM_FORMAT_ARGB2101010: |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7923 | /* RGB formats are common across chipsets */ |
Jesse Barnes | b562674 | 2011-06-24 12:19:27 -0700 | [diff] [blame] | 7924 | break; |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 7925 | case DRM_FORMAT_YUYV: |
| 7926 | case DRM_FORMAT_UYVY: |
| 7927 | case DRM_FORMAT_YVYU: |
| 7928 | case DRM_FORMAT_VYUY: |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 7929 | break; |
| 7930 | default: |
Eugeni Dodonov | aca2584 | 2012-01-17 15:25:45 -0200 | [diff] [blame] | 7931 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
| 7932 | mode_cmd->pixel_format); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 7933 | return -EINVAL; |
| 7934 | } |
| 7935 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7936 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 7937 | if (ret) { |
| 7938 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 7939 | return ret; |
| 7940 | } |
| 7941 | |
| 7942 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7943 | intel_fb->obj = obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7944 | return 0; |
| 7945 | } |
| 7946 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7947 | static struct drm_framebuffer * |
| 7948 | intel_user_framebuffer_create(struct drm_device *dev, |
| 7949 | struct drm_file *filp, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7950 | struct drm_mode_fb_cmd2 *mode_cmd) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7951 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7952 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7953 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7954 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
| 7955 | mode_cmd->handles[0])); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 7956 | if (&obj->base == NULL) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 7957 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7958 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7959 | return intel_framebuffer_create(dev, mode_cmd, obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7960 | } |
| 7961 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7962 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7963 | .fb_create = intel_user_framebuffer_create, |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 7964 | .output_poll_changed = intel_fb_output_poll_changed, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7965 | }; |
| 7966 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7967 | static struct drm_i915_gem_object * |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 7968 | intel_alloc_context_page(struct drm_device *dev) |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7969 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7970 | struct drm_i915_gem_object *ctx; |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7971 | int ret; |
| 7972 | |
Ben Widawsky | 2c34b85 | 2011-03-19 18:14:26 -0700 | [diff] [blame] | 7973 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 7974 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 7975 | ctx = i915_gem_alloc_object(dev, 4096); |
| 7976 | if (!ctx) { |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7977 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 7978 | return NULL; |
| 7979 | } |
| 7980 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 7981 | ret = i915_gem_object_pin(ctx, 4096, true); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7982 | if (ret) { |
| 7983 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 7984 | goto err_unref; |
| 7985 | } |
| 7986 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 7987 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7988 | if (ret) { |
| 7989 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 7990 | goto err_unpin; |
| 7991 | } |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7992 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 7993 | return ctx; |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7994 | |
| 7995 | err_unpin: |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 7996 | i915_gem_object_unpin(ctx); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7997 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7998 | drm_gem_object_unreference(&ctx->base); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 7999 | mutex_unlock(&dev->struct_mutex); |
| 8000 | return NULL; |
| 8001 | } |
| 8002 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8003 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 8004 | { |
| 8005 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8006 | u16 rgvswctl; |
| 8007 | |
| 8008 | rgvswctl = I915_READ16(MEMSWCTL); |
| 8009 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 8010 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 8011 | return false; /* still busy with another command */ |
| 8012 | } |
| 8013 | |
| 8014 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 8015 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 8016 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 8017 | POSTING_READ16(MEMSWCTL); |
| 8018 | |
| 8019 | rgvswctl |= MEMCTL_CMD_STS; |
| 8020 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 8021 | |
| 8022 | return true; |
| 8023 | } |
| 8024 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8025 | void ironlake_enable_drps(struct drm_device *dev) |
| 8026 | { |
| 8027 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8028 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8029 | u8 fmax, fmin, fstart, vstart; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8030 | |
Jesse Barnes | ea056c1 | 2010-09-10 10:02:13 -0700 | [diff] [blame] | 8031 | /* Enable temp reporting */ |
| 8032 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 8033 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 8034 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8035 | /* 100ms RC evaluation intervals */ |
| 8036 | I915_WRITE(RCUPEI, 100000); |
| 8037 | I915_WRITE(RCDNEI, 100000); |
| 8038 | |
| 8039 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 8040 | I915_WRITE(RCBMAXAVG, 90000); |
| 8041 | I915_WRITE(RCBMINAVG, 80000); |
| 8042 | |
| 8043 | I915_WRITE(MEMIHYST, 1); |
| 8044 | |
| 8045 | /* Set up min, max, and cur for interrupt handling */ |
| 8046 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 8047 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 8048 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 8049 | MEMMODE_FSTART_SHIFT; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8050 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8051 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 8052 | PXVFREQ_PX_SHIFT; |
| 8053 | |
Jesse Barnes | 80dbf4b | 2010-11-01 14:12:01 -0700 | [diff] [blame] | 8054 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8055 | dev_priv->fstart = fstart; |
| 8056 | |
Jesse Barnes | 80dbf4b | 2010-11-01 14:12:01 -0700 | [diff] [blame] | 8057 | dev_priv->max_delay = fstart; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8058 | dev_priv->min_delay = fmin; |
| 8059 | dev_priv->cur_delay = fstart; |
| 8060 | |
Jesse Barnes | 80dbf4b | 2010-11-01 14:12:01 -0700 | [diff] [blame] | 8061 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 8062 | fmax, fmin, fstart); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8063 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8064 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 8065 | |
| 8066 | /* |
| 8067 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 8068 | */ |
| 8069 | |
| 8070 | I915_WRITE(VIDSTART, vstart); |
| 8071 | POSTING_READ(VIDSTART); |
| 8072 | |
| 8073 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 8074 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 8075 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 8076 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 8077 | DRM_ERROR("stuck trying to change perf mode\n"); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8078 | msleep(1); |
| 8079 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8080 | ironlake_set_drps(dev, fstart); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8081 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8082 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
| 8083 | I915_READ(0x112e0); |
| 8084 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); |
| 8085 | dev_priv->last_count2 = I915_READ(0x112f4); |
| 8086 | getrawmonotonic(&dev_priv->last_time2); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8087 | } |
| 8088 | |
| 8089 | void ironlake_disable_drps(struct drm_device *dev) |
| 8090 | { |
| 8091 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8092 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8093 | |
| 8094 | /* Ack interrupts, disable EFC interrupt */ |
| 8095 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 8096 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 8097 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 8098 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 8099 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 8100 | |
| 8101 | /* Go back to the starting frequency */ |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8102 | ironlake_set_drps(dev, dev_priv->fstart); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 8103 | msleep(1); |
| 8104 | rgvswctl |= MEMCTL_CMD_STS; |
| 8105 | I915_WRITE(MEMSWCTL, rgvswctl); |
| 8106 | msleep(1); |
| 8107 | |
| 8108 | } |
| 8109 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8110 | void gen6_set_rps(struct drm_device *dev, u8 val) |
| 8111 | { |
| 8112 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8113 | u32 swreq; |
| 8114 | |
| 8115 | swreq = (val & 0x3ff) << 25; |
| 8116 | I915_WRITE(GEN6_RPNSWREQ, swreq); |
| 8117 | } |
| 8118 | |
| 8119 | void gen6_disable_rps(struct drm_device *dev) |
| 8120 | { |
| 8121 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8122 | |
| 8123 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
| 8124 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
| 8125 | I915_WRITE(GEN6_PMIER, 0); |
Daniel Vetter | 6fdd4d9 | 2011-09-08 14:00:22 +0200 | [diff] [blame] | 8126 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 8127 | * item again unmasking PM interrupts because that is using a different |
| 8128 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
| 8129 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 8130 | |
| 8131 | spin_lock_irq(&dev_priv->rps_lock); |
| 8132 | dev_priv->pm_iir = 0; |
| 8133 | spin_unlock_irq(&dev_priv->rps_lock); |
| 8134 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8135 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
| 8136 | } |
| 8137 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 8138 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 8139 | { |
| 8140 | unsigned long freq; |
| 8141 | int div = (vidfreq & 0x3f0000) >> 16; |
| 8142 | int post = (vidfreq & 0x3000) >> 12; |
| 8143 | int pre = (vidfreq & 0x7); |
| 8144 | |
| 8145 | if (!pre) |
| 8146 | return 0; |
| 8147 | |
| 8148 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 8149 | |
| 8150 | return freq; |
| 8151 | } |
| 8152 | |
| 8153 | void intel_init_emon(struct drm_device *dev) |
| 8154 | { |
| 8155 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8156 | u32 lcfuse; |
| 8157 | u8 pxw[16]; |
| 8158 | int i; |
| 8159 | |
| 8160 | /* Disable to program */ |
| 8161 | I915_WRITE(ECR, 0); |
| 8162 | POSTING_READ(ECR); |
| 8163 | |
| 8164 | /* Program energy weights for various events */ |
| 8165 | I915_WRITE(SDEW, 0x15040d00); |
| 8166 | I915_WRITE(CSIEW0, 0x007f0000); |
| 8167 | I915_WRITE(CSIEW1, 0x1e220004); |
| 8168 | I915_WRITE(CSIEW2, 0x04000004); |
| 8169 | |
| 8170 | for (i = 0; i < 5; i++) |
| 8171 | I915_WRITE(PEW + (i * 4), 0); |
| 8172 | for (i = 0; i < 3; i++) |
| 8173 | I915_WRITE(DEW + (i * 4), 0); |
| 8174 | |
| 8175 | /* Program P-state weights to account for frequency power adjustment */ |
| 8176 | for (i = 0; i < 16; i++) { |
| 8177 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 8178 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 8179 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 8180 | PXVFREQ_PX_SHIFT; |
| 8181 | unsigned long val; |
| 8182 | |
| 8183 | val = vid * vid; |
| 8184 | val *= (freq / 1000); |
| 8185 | val *= 255; |
| 8186 | val /= (127*127*900); |
| 8187 | if (val > 0xff) |
| 8188 | DRM_ERROR("bad pxval: %ld\n", val); |
| 8189 | pxw[i] = val; |
| 8190 | } |
| 8191 | /* Render standby states get 0 weight */ |
| 8192 | pxw[14] = 0; |
| 8193 | pxw[15] = 0; |
| 8194 | |
| 8195 | for (i = 0; i < 4; i++) { |
| 8196 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 8197 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 8198 | I915_WRITE(PXW + (i * 4), val); |
| 8199 | } |
| 8200 | |
| 8201 | /* Adjust magic regs to magic values (more experimental results) */ |
| 8202 | I915_WRITE(OGW0, 0); |
| 8203 | I915_WRITE(OGW1, 0); |
| 8204 | I915_WRITE(EG0, 0x00007f00); |
| 8205 | I915_WRITE(EG1, 0x0000000e); |
| 8206 | I915_WRITE(EG2, 0x000e0000); |
| 8207 | I915_WRITE(EG3, 0x68000300); |
| 8208 | I915_WRITE(EG4, 0x42000000); |
| 8209 | I915_WRITE(EG5, 0x00140031); |
| 8210 | I915_WRITE(EG6, 0); |
| 8211 | I915_WRITE(EG7, 0); |
| 8212 | |
| 8213 | for (i = 0; i < 8; i++) |
| 8214 | I915_WRITE(PXWL + (i * 4), 0); |
| 8215 | |
| 8216 | /* Enable PMON + select events */ |
| 8217 | I915_WRITE(ECR, 0x80000019); |
| 8218 | |
| 8219 | lcfuse = I915_READ(LCFUSE02); |
| 8220 | |
| 8221 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); |
| 8222 | } |
| 8223 | |
Eugeni Dodonov | 83b7f9a | 2012-03-23 11:57:18 -0300 | [diff] [blame] | 8224 | static int intel_enable_rc6(struct drm_device *dev) |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 8225 | { |
| 8226 | /* |
| 8227 | * Respect the kernel parameter if it is set |
| 8228 | */ |
| 8229 | if (i915_enable_rc6 >= 0) |
| 8230 | return i915_enable_rc6; |
| 8231 | |
| 8232 | /* |
| 8233 | * Disable RC6 on Ironlake |
| 8234 | */ |
| 8235 | if (INTEL_INFO(dev)->gen == 5) |
| 8236 | return 0; |
| 8237 | |
| 8238 | /* |
Keith Packard | 371de6e | 2011-12-26 17:02:11 -0800 | [diff] [blame] | 8239 | * Disable rc6 on Sandybridge |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 8240 | */ |
| 8241 | if (INTEL_INFO(dev)->gen == 6) { |
Eugeni Dodonov | aa46419 | 2012-03-23 11:57:19 -0300 | [diff] [blame^] | 8242 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
| 8243 | return INTEL_RC6_ENABLE; |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 8244 | } |
Eugeni Dodonov | aa46419 | 2012-03-23 11:57:19 -0300 | [diff] [blame^] | 8245 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
| 8246 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 8247 | } |
| 8248 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8249 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8250 | { |
Jesse Barnes | a6044e2 | 2010-12-20 11:34:20 -0800 | [diff] [blame] | 8251 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 8252 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
Jesse Barnes | 7df8721 | 2011-03-30 14:08:56 -0700 | [diff] [blame] | 8253 | u32 pcu_mbox, rc6_mask = 0; |
Ben Widawsky | dd202c6 | 2012-02-09 10:15:18 +0100 | [diff] [blame] | 8254 | u32 gtfifodbg; |
Jesse Barnes | a6044e2 | 2010-12-20 11:34:20 -0800 | [diff] [blame] | 8255 | int cur_freq, min_freq, max_freq; |
Eugeni Dodonov | 83b7f9a | 2012-03-23 11:57:18 -0300 | [diff] [blame] | 8256 | int rc6_mode; |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8257 | int i; |
| 8258 | |
| 8259 | /* Here begins a magic sequence of register writes to enable |
| 8260 | * auto-downclocking. |
| 8261 | * |
| 8262 | * Perhaps there might be some value in exposing these to |
| 8263 | * userspace... |
| 8264 | */ |
| 8265 | I915_WRITE(GEN6_RC_STATE, 0); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 8266 | mutex_lock(&dev_priv->dev->struct_mutex); |
Ben Widawsky | dd202c6 | 2012-02-09 10:15:18 +0100 | [diff] [blame] | 8267 | |
| 8268 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 8269 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 8270 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 8271 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 8272 | } |
| 8273 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 8274 | gen6_gt_force_wake_get(dev_priv); |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8275 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8276 | /* disable the counters and set deterministic thresholds */ |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8277 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 8278 | |
| 8279 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 8280 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 8281 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 8282 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 8283 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 8284 | |
| 8285 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 8286 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); |
| 8287 | |
| 8288 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 8289 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
| 8290 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
| 8291 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
| 8292 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 8293 | |
Eugeni Dodonov | 83b7f9a | 2012-03-23 11:57:18 -0300 | [diff] [blame] | 8294 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 8295 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 8296 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 8297 | |
| 8298 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 8299 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
| 8300 | |
| 8301 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 8302 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 8303 | |
| 8304 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
| 8305 | (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off", |
| 8306 | (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off", |
| 8307 | (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off"); |
Jesse Barnes | 7df8721 | 2011-03-30 14:08:56 -0700 | [diff] [blame] | 8308 | |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8309 | I915_WRITE(GEN6_RC_CONTROL, |
Jesse Barnes | 7df8721 | 2011-03-30 14:08:56 -0700 | [diff] [blame] | 8310 | rc6_mask | |
Chris Wilson | 9c3d2f7 | 2010-12-17 10:54:26 +0000 | [diff] [blame] | 8311 | GEN6_RC_CTL_EI_MODE(1) | |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8312 | GEN6_RC_CTL_HW_ENABLE); |
| 8313 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8314 | I915_WRITE(GEN6_RPNSWREQ, |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8315 | GEN6_FREQUENCY(10) | |
| 8316 | GEN6_OFFSET(0) | |
| 8317 | GEN6_AGGRESSIVE_TURBO); |
| 8318 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 8319 | GEN6_FREQUENCY(12)); |
| 8320 | |
| 8321 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
| 8322 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 8323 | 18 << 24 | |
| 8324 | 6 << 16); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 8325 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
| 8326 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8327 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 8328 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8329 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 8330 | I915_WRITE(GEN6_RP_CONTROL, |
| 8331 | GEN6_RP_MEDIA_TURBO | |
Ben Widawsky | 6ed55ee | 2011-12-12 19:21:59 -0800 | [diff] [blame] | 8332 | GEN6_RP_MEDIA_HW_MODE | |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8333 | GEN6_RP_MEDIA_IS_GFX | |
| 8334 | GEN6_RP_ENABLE | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 8335 | GEN6_RP_UP_BUSY_AVG | |
| 8336 | GEN6_RP_DOWN_IDLE_CONT); |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8337 | |
| 8338 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 8339 | 500)) |
| 8340 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
| 8341 | |
| 8342 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 8343 | I915_WRITE(GEN6_PCODE_MAILBOX, |
| 8344 | GEN6_PCODE_READY | |
| 8345 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
| 8346 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 8347 | 500)) |
| 8348 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
| 8349 | |
Jesse Barnes | a6044e2 | 2010-12-20 11:34:20 -0800 | [diff] [blame] | 8350 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
| 8351 | max_freq = rp_state_cap & 0xff; |
| 8352 | cur_freq = (gt_perf_status & 0xff00) >> 8; |
| 8353 | |
| 8354 | /* Check for overclock support */ |
| 8355 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 8356 | 500)) |
| 8357 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); |
| 8358 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); |
| 8359 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); |
| 8360 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 8361 | 500)) |
| 8362 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
| 8363 | if (pcu_mbox & (1<<31)) { /* OC supported */ |
| 8364 | max_freq = pcu_mbox & 0xff; |
Jesse Barnes | e281fca | 2011-03-18 10:32:07 -0700 | [diff] [blame] | 8365 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
Jesse Barnes | a6044e2 | 2010-12-20 11:34:20 -0800 | [diff] [blame] | 8366 | } |
| 8367 | |
| 8368 | /* In units of 100MHz */ |
| 8369 | dev_priv->max_delay = max_freq; |
| 8370 | dev_priv->min_delay = min_freq; |
| 8371 | dev_priv->cur_delay = cur_freq; |
| 8372 | |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8373 | /* requires MSI enabled */ |
| 8374 | I915_WRITE(GEN6_PMIER, |
| 8375 | GEN6_PM_MBOX_EVENT | |
| 8376 | GEN6_PM_THERMAL_EVENT | |
| 8377 | GEN6_PM_RP_DOWN_TIMEOUT | |
| 8378 | GEN6_PM_RP_UP_THRESHOLD | |
| 8379 | GEN6_PM_RP_DOWN_THRESHOLD | |
| 8380 | GEN6_PM_RP_UP_EI_EXPIRED | |
| 8381 | GEN6_PM_RP_DOWN_EI_EXPIRED); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 8382 | spin_lock_irq(&dev_priv->rps_lock); |
| 8383 | WARN_ON(dev_priv->pm_iir != 0); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8384 | I915_WRITE(GEN6_PMIMR, 0); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 8385 | spin_unlock_irq(&dev_priv->rps_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 8386 | /* enable all PM interrupts */ |
| 8387 | I915_WRITE(GEN6_PMINTRMSK, 0); |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8388 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 8389 | gen6_gt_force_wake_put(dev_priv); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 8390 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8391 | } |
| 8392 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 8393 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
| 8394 | { |
| 8395 | int min_freq = 15; |
| 8396 | int gpu_freq, ia_freq, max_ia_freq; |
| 8397 | int scaling_factor = 180; |
| 8398 | |
| 8399 | max_ia_freq = cpufreq_quick_get_max(0); |
| 8400 | /* |
| 8401 | * Default to measured freq if none found, PCU will ensure we don't go |
| 8402 | * over |
| 8403 | */ |
| 8404 | if (!max_ia_freq) |
| 8405 | max_ia_freq = tsc_khz; |
| 8406 | |
| 8407 | /* Convert from kHz to MHz */ |
| 8408 | max_ia_freq /= 1000; |
| 8409 | |
| 8410 | mutex_lock(&dev_priv->dev->struct_mutex); |
| 8411 | |
| 8412 | /* |
| 8413 | * For each potential GPU frequency, load a ring frequency we'd like |
| 8414 | * to use for memory access. We do this by specifying the IA frequency |
| 8415 | * the PCU should use as a reference to determine the ring frequency. |
| 8416 | */ |
| 8417 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; |
| 8418 | gpu_freq--) { |
| 8419 | int diff = dev_priv->max_delay - gpu_freq; |
| 8420 | |
| 8421 | /* |
| 8422 | * For GPU frequencies less than 750MHz, just use the lowest |
| 8423 | * ring freq. |
| 8424 | */ |
| 8425 | if (gpu_freq < min_freq) |
| 8426 | ia_freq = 800; |
| 8427 | else |
| 8428 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 8429 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 8430 | |
| 8431 | I915_WRITE(GEN6_PCODE_DATA, |
| 8432 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | |
| 8433 | gpu_freq); |
| 8434 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | |
| 8435 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); |
| 8436 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & |
| 8437 | GEN6_PCODE_READY) == 0, 10)) { |
| 8438 | DRM_ERROR("pcode write of freq table timed out\n"); |
| 8439 | continue; |
| 8440 | } |
| 8441 | } |
| 8442 | |
| 8443 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 8444 | } |
| 8445 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8446 | static void ironlake_init_clock_gating(struct drm_device *dev) |
| 8447 | { |
| 8448 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8449 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 8450 | |
| 8451 | /* Required for FBC */ |
| 8452 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
| 8453 | DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 8454 | DPFDUNIT_CLOCK_GATE_DISABLE; |
| 8455 | /* Required for CxSR */ |
| 8456 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
| 8457 | |
| 8458 | I915_WRITE(PCH_3DCGDIS0, |
| 8459 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 8460 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 8461 | I915_WRITE(PCH_3DCGDIS1, |
| 8462 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 8463 | |
| 8464 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
| 8465 | |
| 8466 | /* |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8467 | * According to the spec the following bits should be set in |
| 8468 | * order to enable memory self-refresh |
| 8469 | * The bit 22/21 of 0x42004 |
| 8470 | * The bit 5 of 0x42020 |
| 8471 | * The bit 15 of 0x45000 |
| 8472 | */ |
| 8473 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 8474 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 8475 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
| 8476 | I915_WRITE(ILK_DSPCLK_GATE, |
| 8477 | (I915_READ(ILK_DSPCLK_GATE) | |
| 8478 | ILK_DPARB_CLK_GATE)); |
| 8479 | I915_WRITE(DISP_ARB_CTL, |
| 8480 | (I915_READ(DISP_ARB_CTL) | |
| 8481 | DISP_FBC_WM_DIS)); |
| 8482 | I915_WRITE(WM3_LP_ILK, 0); |
| 8483 | I915_WRITE(WM2_LP_ILK, 0); |
| 8484 | I915_WRITE(WM1_LP_ILK, 0); |
| 8485 | |
| 8486 | /* |
| 8487 | * Based on the document from hardware guys the following bits |
| 8488 | * should be set unconditionally in order to enable FBC. |
| 8489 | * The bit 22 of 0x42000 |
| 8490 | * The bit 22 of 0x42004 |
| 8491 | * The bit 7,8,9 of 0x42020. |
| 8492 | */ |
| 8493 | if (IS_IRONLAKE_M(dev)) { |
| 8494 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 8495 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 8496 | ILK_FBCQ_DIS); |
| 8497 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 8498 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 8499 | ILK_DPARB_GATE); |
| 8500 | I915_WRITE(ILK_DSPCLK_GATE, |
| 8501 | I915_READ(ILK_DSPCLK_GATE) | |
| 8502 | ILK_DPFC_DIS1 | |
| 8503 | ILK_DPFC_DIS2 | |
| 8504 | ILK_CLK_FBC); |
| 8505 | } |
| 8506 | |
| 8507 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 8508 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 8509 | ILK_ELPIN_409_SELECT); |
| 8510 | I915_WRITE(_3D_CHICKEN2, |
| 8511 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 8512 | _3D_CHICKEN2_WM_READ_PIPELINED); |
| 8513 | } |
| 8514 | |
| 8515 | static void gen6_init_clock_gating(struct drm_device *dev) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8516 | { |
| 8517 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 8518 | int pipe; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8519 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 8520 | |
| 8521 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8522 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8523 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 8524 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 8525 | ILK_ELPIN_409_SELECT); |
Eric Anholt | 8956c8b | 2010-03-18 13:21:14 -0700 | [diff] [blame] | 8526 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8527 | I915_WRITE(WM3_LP_ILK, 0); |
| 8528 | I915_WRITE(WM2_LP_ILK, 0); |
| 8529 | I915_WRITE(WM1_LP_ILK, 0); |
Eric Anholt | 8956c8b | 2010-03-18 13:21:14 -0700 | [diff] [blame] | 8530 | |
Eric Anholt | 406478d | 2011-11-07 16:07:04 -0800 | [diff] [blame] | 8531 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 8532 | * gating disable must be set. Failure to set it results in |
| 8533 | * flickering pixels due to Z write ordering failures after |
| 8534 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 8535 | * Sanctuary and Tropics, and apparently anything else with |
| 8536 | * alpha test or pixel discard. |
Eric Anholt | 9ca1d10 | 2011-11-07 16:07:05 -0800 | [diff] [blame] | 8537 | * |
| 8538 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 8539 | * but we didn't debug actual testcases to find it out. |
Eric Anholt | 406478d | 2011-11-07 16:07:04 -0800 | [diff] [blame] | 8540 | */ |
Eric Anholt | 9ca1d10 | 2011-11-07 16:07:05 -0800 | [diff] [blame] | 8541 | I915_WRITE(GEN6_UCGCTL2, |
| 8542 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 8543 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
Eric Anholt | 406478d | 2011-11-07 16:07:04 -0800 | [diff] [blame] | 8544 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8545 | /* |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8546 | * According to the spec the following bits should be |
| 8547 | * set in order to enable memory self-refresh and fbc: |
| 8548 | * The bit21 and bit22 of 0x42000 |
| 8549 | * The bit21 and bit22 of 0x42004 |
| 8550 | * The bit5 and bit7 of 0x42020 |
| 8551 | * The bit14 of 0x70180 |
| 8552 | * The bit14 of 0x71180 |
Jesse Barnes | 382b093 | 2010-10-07 16:01:25 -0700 | [diff] [blame] | 8553 | */ |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8554 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 8555 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 8556 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 8557 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 8558 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 8559 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
| 8560 | I915_WRITE(ILK_DSPCLK_GATE, |
| 8561 | I915_READ(ILK_DSPCLK_GATE) | |
| 8562 | ILK_DPARB_CLK_GATE | |
| 8563 | ILK_DPFD_CLK_GATE); |
Jesse Barnes | 382b093 | 2010-10-07 16:01:25 -0700 | [diff] [blame] | 8564 | |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 8565 | for_each_pipe(pipe) { |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8566 | I915_WRITE(DSPCNTR(pipe), |
| 8567 | I915_READ(DSPCNTR(pipe)) | |
| 8568 | DISPPLANE_TRICKLE_FEED_DISABLE); |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 8569 | intel_flush_display_plane(dev_priv, pipe); |
| 8570 | } |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8571 | } |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8572 | |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8573 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
| 8574 | { |
| 8575 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8576 | int pipe; |
| 8577 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8578 | |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8579 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8580 | |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8581 | I915_WRITE(WM3_LP_ILK, 0); |
| 8582 | I915_WRITE(WM2_LP_ILK, 0); |
| 8583 | I915_WRITE(WM1_LP_ILK, 0); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8584 | |
Eugeni Dodonov | eae66b5 | 2012-02-08 12:53:49 -0800 | [diff] [blame] | 8585 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
| 8586 | * This implements the WaDisableRCZUnitClockGating workaround. |
| 8587 | */ |
| 8588 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
| 8589 | |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8590 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
Eric Anholt | de6e2ea | 2010-11-06 14:53:32 -0700 | [diff] [blame] | 8591 | |
Eric Anholt | 116ac8d | 2011-12-21 10:31:09 -0800 | [diff] [blame] | 8592 | I915_WRITE(IVB_CHICKEN3, |
| 8593 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 8594 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 8595 | |
Kenneth Graunke | d71de14 | 2012-02-08 12:53:52 -0800 | [diff] [blame] | 8596 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
| 8597 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 8598 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 8599 | |
Eugeni Dodonov | e4e0c05 | 2012-02-08 12:53:50 -0800 | [diff] [blame] | 8600 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
| 8601 | I915_WRITE(GEN7_L3CNTLREG1, |
| 8602 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 8603 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
| 8604 | GEN7_WA_L3_CHICKEN_MODE); |
| 8605 | |
Eugeni Dodonov | db099c8 | 2012-02-08 12:53:51 -0800 | [diff] [blame] | 8606 | /* This is required by WaCatErrorRejectionIssue */ |
| 8607 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 8608 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 8609 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 8610 | |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 8611 | for_each_pipe(pipe) { |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8612 | I915_WRITE(DSPCNTR(pipe), |
| 8613 | I915_READ(DSPCNTR(pipe)) | |
| 8614 | DISPPLANE_TRICKLE_FEED_DISABLE); |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 8615 | intel_flush_display_plane(dev_priv, pipe); |
| 8616 | } |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8617 | } |
Eric Anholt | 67e92af | 2010-11-06 14:53:33 -0700 | [diff] [blame] | 8618 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8619 | static void g4x_init_clock_gating(struct drm_device *dev) |
| 8620 | { |
| 8621 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8622 | uint32_t dspclk_gate; |
Chris Wilson | 8fd2685 | 2010-12-08 18:40:43 +0000 | [diff] [blame] | 8623 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8624 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 8625 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 8626 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 8627 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 8628 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 8629 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 8630 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 8631 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 8632 | if (IS_GM45(dev)) |
| 8633 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 8634 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
| 8635 | } |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 8636 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8637 | static void crestline_init_clock_gating(struct drm_device *dev) |
| 8638 | { |
| 8639 | struct drm_i915_private *dev_priv = dev->dev_private; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 8640 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8641 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 8642 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 8643 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 8644 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 8645 | I915_WRITE16(DEUC, 0); |
| 8646 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8647 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8648 | static void broadwater_init_clock_gating(struct drm_device *dev) |
| 8649 | { |
| 8650 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8651 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8652 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 8653 | I965_RCC_CLOCK_GATE_DISABLE | |
| 8654 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 8655 | I965_ISC_CLOCK_GATE_DISABLE | |
| 8656 | I965_FBC_CLOCK_GATE_DISABLE); |
| 8657 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 8658 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8659 | |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8660 | static void gen3_init_clock_gating(struct drm_device *dev) |
| 8661 | { |
| 8662 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8663 | u32 dstate = I915_READ(D_STATE); |
| 8664 | |
| 8665 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 8666 | DSTATE_DOT_CLOCK_GATING; |
| 8667 | I915_WRITE(D_STATE, dstate); |
| 8668 | } |
| 8669 | |
| 8670 | static void i85x_init_clock_gating(struct drm_device *dev) |
| 8671 | { |
| 8672 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8673 | |
| 8674 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 8675 | } |
| 8676 | |
| 8677 | static void i830_init_clock_gating(struct drm_device *dev) |
| 8678 | { |
| 8679 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8680 | |
| 8681 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8682 | } |
| 8683 | |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 8684 | static void ibx_init_clock_gating(struct drm_device *dev) |
| 8685 | { |
| 8686 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8687 | |
| 8688 | /* |
| 8689 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 8690 | * gating for the panel power sequencer or it will fail to |
| 8691 | * start up when no ports are active. |
| 8692 | */ |
| 8693 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 8694 | } |
| 8695 | |
| 8696 | static void cpt_init_clock_gating(struct drm_device *dev) |
| 8697 | { |
| 8698 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 3bcf603 | 2011-07-27 11:51:40 -0700 | [diff] [blame] | 8699 | int pipe; |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 8700 | |
| 8701 | /* |
| 8702 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 8703 | * gating for the panel power sequencer or it will fail to |
| 8704 | * start up when no ports are active. |
| 8705 | */ |
| 8706 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 8707 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 8708 | DPLS_EDP_PPS_FIX_DIS); |
Jesse Barnes | 3bcf603 | 2011-07-27 11:51:40 -0700 | [diff] [blame] | 8709 | /* Without this, mode sets may fail silently on FDI */ |
| 8710 | for_each_pipe(pipe) |
| 8711 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8712 | } |
| 8713 | |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8714 | static void ironlake_teardown_rc6(struct drm_device *dev) |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 8715 | { |
| 8716 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8717 | |
| 8718 | if (dev_priv->renderctx) { |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8719 | i915_gem_object_unpin(dev_priv->renderctx); |
| 8720 | drm_gem_object_unreference(&dev_priv->renderctx->base); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 8721 | dev_priv->renderctx = NULL; |
| 8722 | } |
| 8723 | |
| 8724 | if (dev_priv->pwrctx) { |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8725 | i915_gem_object_unpin(dev_priv->pwrctx); |
| 8726 | drm_gem_object_unreference(&dev_priv->pwrctx->base); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 8727 | dev_priv->pwrctx = NULL; |
| 8728 | } |
| 8729 | } |
| 8730 | |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8731 | static void ironlake_disable_rc6(struct drm_device *dev) |
| 8732 | { |
| 8733 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8734 | |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8735 | if (I915_READ(PWRCTXA)) { |
| 8736 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
| 8737 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
| 8738 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
| 8739 | 50); |
| 8740 | |
| 8741 | I915_WRITE(PWRCTXA, 0); |
| 8742 | POSTING_READ(PWRCTXA); |
| 8743 | |
| 8744 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
| 8745 | POSTING_READ(RSTDBYCTL); |
| 8746 | } |
| 8747 | |
Chris Wilson | 9950730 | 2011-02-24 09:42:52 +0000 | [diff] [blame] | 8748 | ironlake_teardown_rc6(dev); |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8749 | } |
| 8750 | |
| 8751 | static int ironlake_setup_rc6(struct drm_device *dev) |
| 8752 | { |
| 8753 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8754 | |
| 8755 | if (dev_priv->renderctx == NULL) |
| 8756 | dev_priv->renderctx = intel_alloc_context_page(dev); |
| 8757 | if (!dev_priv->renderctx) |
| 8758 | return -ENOMEM; |
| 8759 | |
| 8760 | if (dev_priv->pwrctx == NULL) |
| 8761 | dev_priv->pwrctx = intel_alloc_context_page(dev); |
| 8762 | if (!dev_priv->pwrctx) { |
| 8763 | ironlake_teardown_rc6(dev); |
| 8764 | return -ENOMEM; |
| 8765 | } |
| 8766 | |
| 8767 | return 0; |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8768 | } |
| 8769 | |
| 8770 | void ironlake_enable_rc6(struct drm_device *dev) |
| 8771 | { |
| 8772 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8773 | int ret; |
| 8774 | |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8775 | /* rc6 disabled by default due to repeated reports of hanging during |
| 8776 | * boot and resume. |
| 8777 | */ |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 8778 | if (!intel_enable_rc6(dev)) |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8779 | return; |
| 8780 | |
Ben Widawsky | 2c34b85 | 2011-03-19 18:14:26 -0700 | [diff] [blame] | 8781 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8782 | ret = ironlake_setup_rc6(dev); |
Ben Widawsky | 2c34b85 | 2011-03-19 18:14:26 -0700 | [diff] [blame] | 8783 | if (ret) { |
| 8784 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8785 | return; |
Ben Widawsky | 2c34b85 | 2011-03-19 18:14:26 -0700 | [diff] [blame] | 8786 | } |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8787 | |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8788 | /* |
| 8789 | * GPU can automatically power down the render unit if given a page |
| 8790 | * to save state. |
| 8791 | */ |
| 8792 | ret = BEGIN_LP_RING(6); |
| 8793 | if (ret) { |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8794 | ironlake_teardown_rc6(dev); |
Ben Widawsky | 2c34b85 | 2011-03-19 18:14:26 -0700 | [diff] [blame] | 8795 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8796 | return; |
| 8797 | } |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8798 | |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8799 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
| 8800 | OUT_RING(MI_SET_CONTEXT); |
| 8801 | OUT_RING(dev_priv->renderctx->gtt_offset | |
| 8802 | MI_MM_SPACE_GTT | |
| 8803 | MI_SAVE_EXT_STATE_EN | |
| 8804 | MI_RESTORE_EXT_STATE_EN | |
| 8805 | MI_RESTORE_INHIBIT); |
| 8806 | OUT_RING(MI_SUSPEND_FLUSH); |
| 8807 | OUT_RING(MI_NOOP); |
| 8808 | OUT_RING(MI_FLUSH); |
| 8809 | ADVANCE_LP_RING(); |
| 8810 | |
Ben Widawsky | 4a246cf | 2011-03-19 18:14:28 -0700 | [diff] [blame] | 8811 | /* |
| 8812 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
| 8813 | * does an implicit flush, combined with MI_FLUSH above, it should be |
| 8814 | * safe to assume that renderctx is valid |
| 8815 | */ |
| 8816 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); |
| 8817 | if (ret) { |
| 8818 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
| 8819 | ironlake_teardown_rc6(dev); |
| 8820 | mutex_unlock(&dev->struct_mutex); |
| 8821 | return; |
| 8822 | } |
| 8823 | |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8824 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
| 8825 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
Ben Widawsky | 2c34b85 | 2011-03-19 18:14:26 -0700 | [diff] [blame] | 8826 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 8827 | } |
| 8828 | |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 8829 | void intel_init_clock_gating(struct drm_device *dev) |
| 8830 | { |
| 8831 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8832 | |
| 8833 | dev_priv->display.init_clock_gating(dev); |
| 8834 | |
| 8835 | if (dev_priv->display.init_pch_clock_gating) |
| 8836 | dev_priv->display.init_pch_clock_gating(dev); |
| 8837 | } |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 8838 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8839 | /* Set up chip specific display functions */ |
| 8840 | static void intel_init_display(struct drm_device *dev) |
| 8841 | { |
| 8842 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8843 | |
| 8844 | /* We always want a DPMS function */ |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8845 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 8846 | dev_priv->display.dpms = ironlake_crtc_dpms; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8847 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 8848 | dev_priv->display.update_plane = ironlake_update_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8849 | } else { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8850 | dev_priv->display.dpms = i9xx_crtc_dpms; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8851 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 8852 | dev_priv->display.update_plane = i9xx_update_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8853 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8854 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 8855 | if (I915_HAS_FBC(dev)) { |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 8856 | if (HAS_PCH_SPLIT(dev)) { |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 8857 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
| 8858 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
| 8859 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 8860 | } else if (IS_GM45(dev)) { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 8861 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 8862 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 8863 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 8864 | } else if (IS_CRESTLINE(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8865 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 8866 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 8867 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
| 8868 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 8869 | /* 855GM needs testing */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8870 | } |
| 8871 | |
| 8872 | /* Returns the core display clock speed */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 8873 | if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8874 | dev_priv->display.get_display_clock_speed = |
| 8875 | i945_get_display_clock_speed; |
| 8876 | else if (IS_I915G(dev)) |
| 8877 | dev_priv->display.get_display_clock_speed = |
| 8878 | i915_get_display_clock_speed; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 8879 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8880 | dev_priv->display.get_display_clock_speed = |
| 8881 | i9xx_misc_get_display_clock_speed; |
| 8882 | else if (IS_I915GM(dev)) |
| 8883 | dev_priv->display.get_display_clock_speed = |
| 8884 | i915gm_get_display_clock_speed; |
| 8885 | else if (IS_I865G(dev)) |
| 8886 | dev_priv->display.get_display_clock_speed = |
| 8887 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 8888 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8889 | dev_priv->display.get_display_clock_speed = |
| 8890 | i855_get_display_clock_speed; |
| 8891 | else /* 852, 830 */ |
| 8892 | dev_priv->display.get_display_clock_speed = |
| 8893 | i830_get_display_clock_speed; |
| 8894 | |
| 8895 | /* For FIFO watermark updates */ |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8896 | if (HAS_PCH_SPLIT(dev)) { |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 8897 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; |
| 8898 | dev_priv->display.force_wake_put = __gen6_gt_force_wake_put; |
| 8899 | |
| 8900 | /* IVB configs may use multi-threaded forcewake */ |
| 8901 | if (IS_IVYBRIDGE(dev)) { |
| 8902 | u32 ecobus; |
| 8903 | |
Keith Packard | c7dffff | 2011-12-09 11:33:00 -0800 | [diff] [blame] | 8904 | /* A small trick here - if the bios hasn't configured MT forcewake, |
| 8905 | * and if the device is in RC6, then force_wake_mt_get will not wake |
| 8906 | * the device and the ECOBUS read will return zero. Which will be |
| 8907 | * (correctly) interpreted by the test below as MT forcewake being |
| 8908 | * disabled. |
| 8909 | */ |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 8910 | mutex_lock(&dev->struct_mutex); |
| 8911 | __gen6_gt_force_wake_mt_get(dev_priv); |
Keith Packard | c7dffff | 2011-12-09 11:33:00 -0800 | [diff] [blame] | 8912 | ecobus = I915_READ_NOTRACE(ECOBUS); |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 8913 | __gen6_gt_force_wake_mt_put(dev_priv); |
| 8914 | mutex_unlock(&dev->struct_mutex); |
| 8915 | |
| 8916 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 8917 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); |
| 8918 | dev_priv->display.force_wake_get = |
| 8919 | __gen6_gt_force_wake_mt_get; |
| 8920 | dev_priv->display.force_wake_put = |
| 8921 | __gen6_gt_force_wake_mt_put; |
| 8922 | } |
| 8923 | } |
| 8924 | |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 8925 | if (HAS_PCH_IBX(dev)) |
| 8926 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; |
| 8927 | else if (HAS_PCH_CPT(dev)) |
| 8928 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; |
| 8929 | |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 8930 | if (IS_GEN5(dev)) { |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8931 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
| 8932 | dev_priv->display.update_wm = ironlake_update_wm; |
| 8933 | else { |
| 8934 | DRM_DEBUG_KMS("Failed to get proper latency. " |
| 8935 | "Disable CxSR\n"); |
| 8936 | dev_priv->display.update_wm = NULL; |
| 8937 | } |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 8938 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8939 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8940 | dev_priv->display.write_eld = ironlake_write_eld; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 8941 | } else if (IS_GEN6(dev)) { |
| 8942 | if (SNB_READ_WM0_LATENCY()) { |
| 8943 | dev_priv->display.update_wm = sandybridge_update_wm; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 8944 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 8945 | } else { |
| 8946 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 8947 | "Disable CxSR\n"); |
| 8948 | dev_priv->display.update_wm = NULL; |
| 8949 | } |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 8950 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8951 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8952 | dev_priv->display.write_eld = ironlake_write_eld; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 8953 | } else if (IS_IVYBRIDGE(dev)) { |
| 8954 | /* FIXME: detect B0+ stepping and use auto training */ |
| 8955 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
Jesse Barnes | fe100d4 | 2011-04-28 14:29:45 -0700 | [diff] [blame] | 8956 | if (SNB_READ_WM0_LATENCY()) { |
| 8957 | dev_priv->display.update_wm = sandybridge_update_wm; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 8958 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
Jesse Barnes | fe100d4 | 2011-04-28 14:29:45 -0700 | [diff] [blame] | 8959 | } else { |
| 8960 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 8961 | "Disable CxSR\n"); |
| 8962 | dev_priv->display.update_wm = NULL; |
| 8963 | } |
Jesse Barnes | 28963a3 | 2011-05-11 09:42:30 -0700 | [diff] [blame] | 8964 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8965 | dev_priv->display.write_eld = ironlake_write_eld; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 8966 | } else |
| 8967 | dev_priv->display.update_wm = NULL; |
| 8968 | } else if (IS_PINEVIEW(dev)) { |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 8969 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 8970 | dev_priv->is_ddr3, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 8971 | dev_priv->fsb_freq, |
| 8972 | dev_priv->mem_freq)) { |
| 8973 | DRM_INFO("failed to find known CxSR latency " |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 8974 | "(found ddr%s fsb freq %d, mem freq %d), " |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 8975 | "disabling CxSR\n", |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 8976 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 8977 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 8978 | /* Disable CxSR and never update its watermark again */ |
| 8979 | pineview_disable_cxsr(dev); |
| 8980 | dev_priv->display.update_wm = NULL; |
| 8981 | } else |
| 8982 | dev_priv->display.update_wm = pineview_update_wm; |
Jason Stubbs | 95e0ee9 | 2011-05-28 14:26:48 +1000 | [diff] [blame] | 8983 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8984 | } else if (IS_G4X(dev)) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8985 | dev_priv->display.write_eld = g4x_write_eld; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8986 | dev_priv->display.update_wm = g4x_update_wm; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8987 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 8988 | } else if (IS_GEN4(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8989 | dev_priv->display.update_wm = i965_update_wm; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8990 | if (IS_CRESTLINE(dev)) |
| 8991 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 8992 | else if (IS_BROADWATER(dev)) |
| 8993 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 8994 | } else if (IS_GEN3(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 8995 | dev_priv->display.update_wm = i9xx_update_wm; |
| 8996 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 8997 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 8998 | } else if (IS_I865G(dev)) { |
| 8999 | dev_priv->display.update_wm = i830_update_wm; |
| 9000 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 9001 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 9002 | } else if (IS_I85X(dev)) { |
| 9003 | dev_priv->display.update_wm = i9xx_update_wm; |
| 9004 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 9005 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 9006 | } else { |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 9007 | dev_priv->display.update_wm = i830_update_wm; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 9008 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 9009 | if (IS_845G(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 9010 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
| 9011 | else |
| 9012 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 9013 | } |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9014 | |
| 9015 | /* Default just returns -ENODEV to indicate unsupported */ |
| 9016 | dev_priv->display.queue_flip = intel_default_queue_flip; |
| 9017 | |
| 9018 | switch (INTEL_INFO(dev)->gen) { |
| 9019 | case 2: |
| 9020 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 9021 | break; |
| 9022 | |
| 9023 | case 3: |
| 9024 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 9025 | break; |
| 9026 | |
| 9027 | case 4: |
| 9028 | case 5: |
| 9029 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 9030 | break; |
| 9031 | |
| 9032 | case 6: |
| 9033 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 9034 | break; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9035 | case 7: |
| 9036 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 9037 | break; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9038 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 9039 | } |
| 9040 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9041 | /* |
| 9042 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 9043 | * resume, or other times. This quirk makes sure that's the case for |
| 9044 | * affected systems. |
| 9045 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 9046 | static void quirk_pipea_force(struct drm_device *dev) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9047 | { |
| 9048 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9049 | |
| 9050 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
| 9051 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); |
| 9052 | } |
| 9053 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 9054 | /* |
| 9055 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 9056 | */ |
| 9057 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 9058 | { |
| 9059 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9060 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
| 9061 | } |
| 9062 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9063 | struct intel_quirk { |
| 9064 | int device; |
| 9065 | int subsystem_vendor; |
| 9066 | int subsystem_device; |
| 9067 | void (*hook)(struct drm_device *dev); |
| 9068 | }; |
| 9069 | |
| 9070 | struct intel_quirk intel_quirks[] = { |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9071 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 9072 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9073 | |
| 9074 | /* Thinkpad R31 needs pipe A force quirk */ |
| 9075 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, |
| 9076 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 9077 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 9078 | |
| 9079 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ |
| 9080 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, |
| 9081 | /* ThinkPad X40 needs pipe A force quirk */ |
| 9082 | |
| 9083 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 9084 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 9085 | |
| 9086 | /* 855 & before need to leave pipe A & dpll A up */ |
| 9087 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 9088 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 9089 | |
| 9090 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 9091 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Michel Alexandre Salim | 070d329 | 2011-07-28 18:52:06 +0200 | [diff] [blame] | 9092 | |
| 9093 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 9094 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9095 | }; |
| 9096 | |
| 9097 | static void intel_init_quirks(struct drm_device *dev) |
| 9098 | { |
| 9099 | struct pci_dev *d = dev->pdev; |
| 9100 | int i; |
| 9101 | |
| 9102 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 9103 | struct intel_quirk *q = &intel_quirks[i]; |
| 9104 | |
| 9105 | if (d->device == q->device && |
| 9106 | (d->subsystem_vendor == q->subsystem_vendor || |
| 9107 | q->subsystem_vendor == PCI_ANY_ID) && |
| 9108 | (d->subsystem_device == q->subsystem_device || |
| 9109 | q->subsystem_device == PCI_ANY_ID)) |
| 9110 | q->hook(dev); |
| 9111 | } |
| 9112 | } |
| 9113 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 9114 | /* Disable the VGA plane that we never use */ |
| 9115 | static void i915_disable_vga(struct drm_device *dev) |
| 9116 | { |
| 9117 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9118 | u8 sr1; |
| 9119 | u32 vga_reg; |
| 9120 | |
| 9121 | if (HAS_PCH_SPLIT(dev)) |
| 9122 | vga_reg = CPU_VGACNTRL; |
| 9123 | else |
| 9124 | vga_reg = VGACNTRL; |
| 9125 | |
| 9126 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 9127 | outb(1, VGA_SR_INDEX); |
| 9128 | sr1 = inb(VGA_SR_DATA); |
| 9129 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 9130 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 9131 | udelay(300); |
| 9132 | |
| 9133 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 9134 | POSTING_READ(vga_reg); |
| 9135 | } |
| 9136 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9137 | void intel_modeset_init(struct drm_device *dev) |
| 9138 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9139 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 9140 | int i, ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9141 | |
| 9142 | drm_mode_config_init(dev); |
| 9143 | |
| 9144 | dev->mode_config.min_width = 0; |
| 9145 | dev->mode_config.min_height = 0; |
| 9146 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 9147 | dev->mode_config.preferred_depth = 24; |
| 9148 | dev->mode_config.prefer_shadow = 1; |
| 9149 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9150 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
| 9151 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 9152 | intel_init_quirks(dev); |
| 9153 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 9154 | intel_init_display(dev); |
| 9155 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 9156 | if (IS_GEN2(dev)) { |
| 9157 | dev->mode_config.max_width = 2048; |
| 9158 | dev->mode_config.max_height = 2048; |
| 9159 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 9160 | dev->mode_config.max_width = 4096; |
| 9161 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9162 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 9163 | dev->mode_config.max_width = 8192; |
| 9164 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9165 | } |
Chris Wilson | 35c3047 | 2010-12-22 14:07:12 +0000 | [diff] [blame] | 9166 | dev->mode_config.fb_base = dev->agp->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9167 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 9168 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 9169 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9170 | |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 9171 | for (i = 0; i < dev_priv->num_pipe; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9172 | intel_crtc_init(dev, i); |
Jesse Barnes | 00c2064b | 2012-01-13 15:48:39 -0800 | [diff] [blame] | 9173 | ret = intel_plane_init(dev, i); |
| 9174 | if (ret) |
| 9175 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9176 | } |
| 9177 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 9178 | /* Just disable it once at startup */ |
| 9179 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9180 | intel_setup_outputs(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9181 | |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 9182 | intel_init_clock_gating(dev); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 9183 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 9184 | if (IS_IRONLAKE_M(dev)) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 9185 | ironlake_enable_drps(dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 9186 | intel_init_emon(dev); |
| 9187 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 9188 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 9189 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 9190 | gen6_enable_rps(dev_priv); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 9191 | gen6_update_ring_freq(dev_priv); |
| 9192 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 9193 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9194 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
| 9195 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
| 9196 | (unsigned long)dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 9197 | } |
| 9198 | |
| 9199 | void intel_modeset_gem_init(struct drm_device *dev) |
| 9200 | { |
| 9201 | if (IS_IRONLAKE_M(dev)) |
| 9202 | ironlake_enable_rc6(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 9203 | |
| 9204 | intel_setup_overlay(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9205 | } |
| 9206 | |
| 9207 | void intel_modeset_cleanup(struct drm_device *dev) |
| 9208 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9209 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9210 | struct drm_crtc *crtc; |
| 9211 | struct intel_crtc *intel_crtc; |
| 9212 | |
Keith Packard | f87ea76 | 2010-10-03 19:36:26 -0700 | [diff] [blame] | 9213 | drm_kms_helper_poll_fini(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9214 | mutex_lock(&dev->struct_mutex); |
| 9215 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 9216 | intel_unregister_dsm_handler(); |
| 9217 | |
| 9218 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9219 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 9220 | /* Skip inactive CRTCs */ |
| 9221 | if (!crtc->fb) |
| 9222 | continue; |
| 9223 | |
| 9224 | intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 9225 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9226 | } |
| 9227 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 9228 | intel_disable_fbc(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 9229 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 9230 | if (IS_IRONLAKE_M(dev)) |
| 9231 | ironlake_disable_drps(dev); |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 9232 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 9233 | gen6_disable_rps(dev); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 9234 | |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 9235 | if (IS_IRONLAKE_M(dev)) |
| 9236 | ironlake_disable_rc6(dev); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 9237 | |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 9238 | mutex_unlock(&dev->struct_mutex); |
| 9239 | |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 9240 | /* Disable the irq before mode object teardown, for the irq might |
| 9241 | * enqueue unpin/hotplug work. */ |
| 9242 | drm_irq_uninstall(dev); |
| 9243 | cancel_work_sync(&dev_priv->hotplug_work); |
Daniel Vetter | 6fdd4d9 | 2011-09-08 14:00:22 +0200 | [diff] [blame] | 9244 | cancel_work_sync(&dev_priv->rps_work); |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 9245 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 9246 | /* flush any delayed tasks or pending work */ |
| 9247 | flush_scheduled_work(); |
| 9248 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 9249 | /* Shut off idle work before the crtcs get freed. */ |
| 9250 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 9251 | intel_crtc = to_intel_crtc(crtc); |
| 9252 | del_timer_sync(&intel_crtc->idle_timer); |
| 9253 | } |
| 9254 | del_timer_sync(&dev_priv->idle_timer); |
| 9255 | cancel_work_sync(&dev_priv->idle_work); |
| 9256 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9257 | drm_mode_config_cleanup(dev); |
| 9258 | } |
| 9259 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 9260 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 9261 | * Return which encoder is currently attached for connector. |
| 9262 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 9263 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9264 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 9265 | return &intel_attached_encoder(connector)->base; |
| 9266 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9267 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 9268 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 9269 | struct intel_encoder *encoder) |
| 9270 | { |
| 9271 | connector->encoder = encoder; |
| 9272 | drm_mode_connector_attach_encoder(&connector->base, |
| 9273 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9274 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 9275 | |
| 9276 | /* |
| 9277 | * set vga decode state - true == enable VGA decode |
| 9278 | */ |
| 9279 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 9280 | { |
| 9281 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9282 | u16 gmch_ctrl; |
| 9283 | |
| 9284 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
| 9285 | if (state) |
| 9286 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 9287 | else |
| 9288 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 9289 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
| 9290 | return 0; |
| 9291 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 9292 | |
| 9293 | #ifdef CONFIG_DEBUG_FS |
| 9294 | #include <linux/seq_file.h> |
| 9295 | |
| 9296 | struct intel_display_error_state { |
| 9297 | struct intel_cursor_error_state { |
| 9298 | u32 control; |
| 9299 | u32 position; |
| 9300 | u32 base; |
| 9301 | u32 size; |
| 9302 | } cursor[2]; |
| 9303 | |
| 9304 | struct intel_pipe_error_state { |
| 9305 | u32 conf; |
| 9306 | u32 source; |
| 9307 | |
| 9308 | u32 htotal; |
| 9309 | u32 hblank; |
| 9310 | u32 hsync; |
| 9311 | u32 vtotal; |
| 9312 | u32 vblank; |
| 9313 | u32 vsync; |
| 9314 | } pipe[2]; |
| 9315 | |
| 9316 | struct intel_plane_error_state { |
| 9317 | u32 control; |
| 9318 | u32 stride; |
| 9319 | u32 size; |
| 9320 | u32 pos; |
| 9321 | u32 addr; |
| 9322 | u32 surface; |
| 9323 | u32 tile_offset; |
| 9324 | } plane[2]; |
| 9325 | }; |
| 9326 | |
| 9327 | struct intel_display_error_state * |
| 9328 | intel_display_capture_error_state(struct drm_device *dev) |
| 9329 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 9330 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 9331 | struct intel_display_error_state *error; |
| 9332 | int i; |
| 9333 | |
| 9334 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 9335 | if (error == NULL) |
| 9336 | return NULL; |
| 9337 | |
| 9338 | for (i = 0; i < 2; i++) { |
| 9339 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 9340 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 9341 | error->cursor[i].base = I915_READ(CURBASE(i)); |
| 9342 | |
| 9343 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 9344 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
| 9345 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 9346 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 9347 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
| 9348 | if (INTEL_INFO(dev)->gen >= 4) { |
| 9349 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 9350 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 9351 | } |
| 9352 | |
| 9353 | error->pipe[i].conf = I915_READ(PIPECONF(i)); |
| 9354 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
| 9355 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); |
| 9356 | error->pipe[i].hblank = I915_READ(HBLANK(i)); |
| 9357 | error->pipe[i].hsync = I915_READ(HSYNC(i)); |
| 9358 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); |
| 9359 | error->pipe[i].vblank = I915_READ(VBLANK(i)); |
| 9360 | error->pipe[i].vsync = I915_READ(VSYNC(i)); |
| 9361 | } |
| 9362 | |
| 9363 | return error; |
| 9364 | } |
| 9365 | |
| 9366 | void |
| 9367 | intel_display_print_error_state(struct seq_file *m, |
| 9368 | struct drm_device *dev, |
| 9369 | struct intel_display_error_state *error) |
| 9370 | { |
| 9371 | int i; |
| 9372 | |
| 9373 | for (i = 0; i < 2; i++) { |
| 9374 | seq_printf(m, "Pipe [%d]:\n", i); |
| 9375 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); |
| 9376 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); |
| 9377 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); |
| 9378 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); |
| 9379 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); |
| 9380 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); |
| 9381 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); |
| 9382 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); |
| 9383 | |
| 9384 | seq_printf(m, "Plane [%d]:\n", i); |
| 9385 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 9386 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
| 9387 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 9388 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
| 9389 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
| 9390 | if (INTEL_INFO(dev)->gen >= 4) { |
| 9391 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 9392 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
| 9393 | } |
| 9394 | |
| 9395 | seq_printf(m, "Cursor [%d]:\n", i); |
| 9396 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 9397 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 9398 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); |
| 9399 | } |
| 9400 | } |
| 9401 | #endif |