Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 3 | /include/ "tegra20.dtsi" |
| 4 | |
| 5 | / { |
| 6 | model = "NVIDIA Seaboard"; |
| 7 | compatible = "nvidia,seaboard", "nvidia,tegra20"; |
| 8 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 9 | memory { |
| 10 | device_type = "memory"; |
| 11 | reg = < 0x00000000 0x40000000 >; |
| 12 | }; |
| 13 | |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 14 | pinmux@70000000 { |
| 15 | pinctrl-names = "default"; |
| 16 | pinctrl-0 = <&state_default>; |
| 17 | |
| 18 | state_default: pinmux { |
| 19 | ata { |
| 20 | nvidia,pins = "ata"; |
| 21 | nvidia,function = "ide"; |
| 22 | }; |
| 23 | atb { |
| 24 | nvidia,pins = "atb", "gma", "gme"; |
| 25 | nvidia,function = "sdio4"; |
| 26 | }; |
| 27 | atc { |
| 28 | nvidia,pins = "atc"; |
| 29 | nvidia,function = "nand"; |
| 30 | }; |
| 31 | atd { |
| 32 | nvidia,pins = "atd", "ate", "gmb", "spia", |
| 33 | "spib", "spic"; |
| 34 | nvidia,function = "gmi"; |
| 35 | }; |
| 36 | cdev1 { |
| 37 | nvidia,pins = "cdev1"; |
| 38 | nvidia,function = "plla_out"; |
| 39 | }; |
| 40 | cdev2 { |
| 41 | nvidia,pins = "cdev2"; |
| 42 | nvidia,function = "pllp_out4"; |
| 43 | }; |
| 44 | crtp { |
| 45 | nvidia,pins = "crtp", "lm1"; |
| 46 | nvidia,function = "crt"; |
| 47 | }; |
| 48 | csus { |
| 49 | nvidia,pins = "csus"; |
| 50 | nvidia,function = "vi_sensor_clk"; |
| 51 | }; |
| 52 | dap1 { |
| 53 | nvidia,pins = "dap1"; |
| 54 | nvidia,function = "dap1"; |
| 55 | }; |
| 56 | dap2 { |
| 57 | nvidia,pins = "dap2"; |
| 58 | nvidia,function = "dap2"; |
| 59 | }; |
| 60 | dap3 { |
| 61 | nvidia,pins = "dap3"; |
| 62 | nvidia,function = "dap3"; |
| 63 | }; |
| 64 | dap4 { |
| 65 | nvidia,pins = "dap4"; |
| 66 | nvidia,function = "dap4"; |
| 67 | }; |
| 68 | ddc { |
| 69 | nvidia,pins = "ddc", "owc", "spdi", "spdo", |
| 70 | "uac"; |
| 71 | nvidia,function = "rsvd2"; |
| 72 | }; |
| 73 | dta { |
| 74 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 75 | nvidia,function = "vi"; |
| 76 | }; |
| 77 | dtf { |
| 78 | nvidia,pins = "dtf"; |
| 79 | nvidia,function = "i2c3"; |
| 80 | }; |
| 81 | gmc { |
| 82 | nvidia,pins = "gmc"; |
| 83 | nvidia,function = "uartd"; |
| 84 | }; |
| 85 | gmd { |
| 86 | nvidia,pins = "gmd"; |
| 87 | nvidia,function = "sflash"; |
| 88 | }; |
| 89 | gpu { |
| 90 | nvidia,pins = "gpu"; |
| 91 | nvidia,function = "pwm"; |
| 92 | }; |
| 93 | gpu7 { |
| 94 | nvidia,pins = "gpu7"; |
| 95 | nvidia,function = "rtck"; |
| 96 | }; |
| 97 | gpv { |
| 98 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 99 | nvidia,function = "pcie"; |
| 100 | }; |
| 101 | hdint { |
| 102 | nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", |
| 103 | "lsck", "lsda", "pta"; |
| 104 | nvidia,function = "hdmi"; |
| 105 | }; |
| 106 | i2cp { |
| 107 | nvidia,pins = "i2cp"; |
| 108 | nvidia,function = "i2cp"; |
| 109 | }; |
| 110 | irrx { |
| 111 | nvidia,pins = "irrx", "irtx"; |
| 112 | nvidia,function = "uartb"; |
| 113 | }; |
| 114 | kbca { |
| 115 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 116 | "kbce", "kbcf"; |
| 117 | nvidia,function = "kbc"; |
| 118 | }; |
| 119 | lcsn { |
| 120 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", |
| 121 | "lsdi", "lvp0"; |
| 122 | nvidia,function = "rsvd4"; |
| 123 | }; |
| 124 | ld0 { |
| 125 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 126 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 127 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 128 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 129 | "lhp1", "lhp2", "lhs", "lpp", "lsc0", |
| 130 | "lspi", "lvp1", "lvs"; |
| 131 | nvidia,function = "displaya"; |
| 132 | }; |
| 133 | pmc { |
| 134 | nvidia,pins = "pmc"; |
| 135 | nvidia,function = "pwr_on"; |
| 136 | }; |
| 137 | rm { |
| 138 | nvidia,pins = "rm"; |
| 139 | nvidia,function = "i2c1"; |
| 140 | }; |
| 141 | sdb { |
| 142 | nvidia,pins = "sdb", "sdc", "sdd"; |
| 143 | nvidia,function = "sdio3"; |
| 144 | }; |
| 145 | sdio1 { |
| 146 | nvidia,pins = "sdio1"; |
| 147 | nvidia,function = "sdio1"; |
| 148 | }; |
| 149 | slxc { |
| 150 | nvidia,pins = "slxc", "slxd"; |
| 151 | nvidia,function = "spdif"; |
| 152 | }; |
| 153 | spid { |
| 154 | nvidia,pins = "spid", "spie", "spif"; |
| 155 | nvidia,function = "spi1"; |
| 156 | }; |
| 157 | spig { |
| 158 | nvidia,pins = "spig", "spih"; |
| 159 | nvidia,function = "spi2_alt"; |
| 160 | }; |
| 161 | uaa { |
| 162 | nvidia,pins = "uaa", "uab", "uda"; |
| 163 | nvidia,function = "ulpi"; |
| 164 | }; |
| 165 | uad { |
| 166 | nvidia,pins = "uad"; |
| 167 | nvidia,function = "irda"; |
| 168 | }; |
| 169 | uca { |
| 170 | nvidia,pins = "uca", "ucb"; |
| 171 | nvidia,function = "uartc"; |
| 172 | }; |
| 173 | conf_ata { |
| 174 | nvidia,pins = "ata", "atb", "atc", "atd", |
| 175 | "cdev1", "cdev2", "dap1", "dap2", |
| 176 | "dap4", "dtf", "gma", "gmc", "gmd", |
| 177 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
| 178 | "irtx", "pta", "rm", "sdc", "sdd", |
| 179 | "slxd", "slxk", "spdi", "spdo", "uac", |
| 180 | "uad", "uca", "ucb", "uda"; |
| 181 | nvidia,pull = <0>; |
| 182 | nvidia,tristate = <0>; |
| 183 | }; |
| 184 | conf_ate { |
| 185 | nvidia,pins = "ate", "csus", "dap3", "ddc", |
| 186 | "gpv", "owc", "slxc", "spib", "spid", |
| 187 | "spie"; |
| 188 | nvidia,pull = <0>; |
| 189 | nvidia,tristate = <1>; |
| 190 | }; |
| 191 | conf_ck32 { |
| 192 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 193 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
| 194 | nvidia,pull = <0>; |
| 195 | }; |
| 196 | conf_crtp { |
| 197 | nvidia,pins = "crtp", "gmb", "slxa", "spia", |
| 198 | "spig", "spih"; |
| 199 | nvidia,pull = <2>; |
| 200 | nvidia,tristate = <1>; |
| 201 | }; |
| 202 | conf_dta { |
| 203 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; |
| 204 | nvidia,pull = <1>; |
| 205 | nvidia,tristate = <0>; |
| 206 | }; |
| 207 | conf_dte { |
| 208 | nvidia,pins = "dte", "spif"; |
| 209 | nvidia,pull = <1>; |
| 210 | nvidia,tristate = <1>; |
| 211 | }; |
| 212 | conf_hdint { |
| 213 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 214 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
| 215 | "lvp0"; |
| 216 | nvidia,tristate = <1>; |
| 217 | }; |
| 218 | conf_kbca { |
| 219 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 220 | "kbce", "kbcf", "sdio1", "spic", "uaa", |
| 221 | "uab"; |
| 222 | nvidia,pull = <2>; |
| 223 | nvidia,tristate = <0>; |
| 224 | }; |
| 225 | conf_lc { |
| 226 | nvidia,pins = "lc", "ls"; |
| 227 | nvidia,pull = <2>; |
| 228 | }; |
| 229 | conf_ld0 { |
| 230 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 231 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 232 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 233 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 234 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 235 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
| 236 | "lvs", "pmc", "sdb"; |
| 237 | nvidia,tristate = <0>; |
| 238 | }; |
| 239 | conf_ld17_0 { |
| 240 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 241 | "ld23_22"; |
| 242 | nvidia,pull = <1>; |
| 243 | }; |
| 244 | drive_sdio1 { |
| 245 | nvidia,pins = "drive_sdio1"; |
| 246 | nvidia,high-speed-mode = <0>; |
| 247 | nvidia,schmitt = <0>; |
| 248 | nvidia,low-power-mode = <3>; |
| 249 | nvidia,pull-down-strength = <31>; |
| 250 | nvidia,pull-up-strength = <31>; |
| 251 | nvidia,slew-rate-rising = <3>; |
| 252 | nvidia,slew-rate-falling = <3>; |
| 253 | }; |
| 254 | }; |
| 255 | }; |
| 256 | |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 257 | i2c@7000c000 { |
| 258 | clock-frequency = <400000>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 259 | |
| 260 | wm8903: wm8903@1a { |
| 261 | compatible = "wlf,wm8903"; |
| 262 | reg = <0x1a>; |
| 263 | interrupt-parent = <&gpio>; |
| 264 | interrupts = < 187 0x04 >; |
| 265 | |
| 266 | gpio-controller; |
| 267 | #gpio-cells = <2>; |
| 268 | |
| 269 | micdet-cfg = <0>; |
| 270 | micdet-delay = <100>; |
| 271 | gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; |
| 272 | }; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 273 | }; |
| 274 | |
| 275 | i2c@7000c400 { |
| 276 | clock-frequency = <400000>; |
| 277 | }; |
| 278 | |
| 279 | i2c@7000c500 { |
| 280 | clock-frequency = <400000>; |
| 281 | }; |
| 282 | |
| 283 | i2c@7000d000 { |
| 284 | clock-frequency = <400000>; |
Stephen Warren | 401c9a5 | 2011-12-17 23:29:32 -0700 | [diff] [blame] | 285 | |
| 286 | adt7461@4c { |
| 287 | compatible = "adt7461"; |
| 288 | reg = <0x4c>; |
| 289 | }; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 290 | }; |
| 291 | |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 292 | i2s@70002a00 { |
| 293 | status = "disable"; |
| 294 | }; |
| 295 | |
| 296 | sound { |
| 297 | compatible = "nvidia,tegra-audio-wm8903-seaboard", |
| 298 | "nvidia,tegra-audio-wm8903"; |
| 299 | nvidia,model = "NVIDIA Tegra Seaboard"; |
| 300 | |
| 301 | nvidia,audio-routing = |
| 302 | "Headphone Jack", "HPOUTR", |
| 303 | "Headphone Jack", "HPOUTL", |
| 304 | "Int Spk", "ROP", |
| 305 | "Int Spk", "RON", |
| 306 | "Int Spk", "LOP", |
| 307 | "Int Spk", "LON", |
| 308 | "Mic Jack", "MICBIAS", |
| 309 | "IN1R", "Mic Jack"; |
| 310 | |
| 311 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 312 | nvidia,audio-codec = <&wm8903>; |
| 313 | |
| 314 | nvidia,spkr-en-gpios = <&wm8903 2 0>; |
| 315 | nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ |
| 316 | }; |
| 317 | |
Stephen Warren | 31c1ec9 | 2011-11-21 14:44:10 -0700 | [diff] [blame] | 318 | serial@70006000 { |
| 319 | status = "disable"; |
| 320 | }; |
| 321 | |
| 322 | serial@70006040 { |
| 323 | status = "disable"; |
| 324 | }; |
| 325 | |
| 326 | serial@70006200 { |
| 327 | status = "disable"; |
| 328 | }; |
| 329 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 330 | serial@70006300 { |
| 331 | clock-frequency = < 216000000 >; |
| 332 | }; |
| 333 | |
Stephen Warren | 31c1ec9 | 2011-11-21 14:44:10 -0700 | [diff] [blame] | 334 | serial@70006400 { |
| 335 | status = "disable"; |
| 336 | }; |
| 337 | |
Stephen Warren | 1292c12 | 2011-11-21 14:44:11 -0700 | [diff] [blame] | 338 | sdhci@c8000000 { |
| 339 | status = "disable"; |
| 340 | }; |
| 341 | |
| 342 | sdhci@c8000200 { |
| 343 | status = "disable"; |
| 344 | }; |
| 345 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 346 | sdhci@c8000400 { |
Stephen Warren | a0638eb | 2011-09-20 10:46:25 -0600 | [diff] [blame] | 347 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ |
| 348 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 349 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 350 | }; |
Stephen Warren | 6111d50 | 2011-09-20 10:46:26 -0600 | [diff] [blame] | 351 | |
| 352 | sdhci@c8000600 { |
| 353 | support-8bit; |
| 354 | }; |
Olof Johansson | c27317c | 2011-11-04 09:12:39 +0000 | [diff] [blame] | 355 | |
| 356 | usb@c5000000 { |
| 357 | nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ |
Simon Glass | 0a42803 | 2012-03-06 21:04:34 -0800 | [diff] [blame] | 358 | dr_mode = "otg"; |
Olof Johansson | c27317c | 2011-11-04 09:12:39 +0000 | [diff] [blame] | 359 | }; |
Stephen Warren | f0d1430 | 2011-12-17 22:18:23 -0700 | [diff] [blame] | 360 | |
| 361 | gpio-keys { |
| 362 | compatible = "gpio-keys"; |
| 363 | |
| 364 | power { |
| 365 | label = "Power"; |
| 366 | gpios = <&gpio 170 1>; /* gpio PV2, active low */ |
| 367 | linux,code = <116>; /* KEY_POWER */ |
| 368 | gpio-key,wakeup; |
| 369 | }; |
| 370 | |
| 371 | lid { |
| 372 | label = "Lid"; |
| 373 | gpios = <&gpio 23 0>; /* gpio PC7 */ |
| 374 | linux,input-type = <5>; /* EV_SW */ |
| 375 | linux,code = <0>; /* SW_LID */ |
| 376 | debounce-interval = <1>; |
| 377 | gpio-key,wakeup; |
| 378 | }; |
| 379 | }; |
Olof Johansson | d8017a9 | 2011-10-18 11:06:06 -0700 | [diff] [blame] | 380 | |
| 381 | emc@7000f400 { |
| 382 | emc-table@190000 { |
| 383 | reg = < 190000 >; |
| 384 | compatible = "nvidia,tegra20-emc-table"; |
| 385 | clock-frequency = < 190000 >; |
| 386 | nvidia,emc-registers = < 0x0000000c 0x00000026 |
| 387 | 0x00000009 0x00000003 0x00000004 0x00000004 |
| 388 | 0x00000002 0x0000000c 0x00000003 0x00000003 |
| 389 | 0x00000002 0x00000001 0x00000004 0x00000005 |
| 390 | 0x00000004 0x00000009 0x0000000d 0x0000059f |
| 391 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 392 | 0x00000003 0x00000001 0x0000000b 0x000000c8 |
| 393 | 0x00000003 0x00000007 0x00000004 0x0000000f |
| 394 | 0x00000002 0x00000000 0x00000000 0x00000002 |
| 395 | 0x00000000 0x00000000 0x00000083 0xa06204ae |
| 396 | 0x007dc010 0x00000000 0x00000000 0x00000000 |
| 397 | 0x00000000 0x00000000 0x00000000 0x00000000 >; |
| 398 | }; |
| 399 | |
| 400 | emc-table@380000 { |
| 401 | reg = < 380000 >; |
| 402 | compatible = "nvidia,tegra20-emc-table"; |
| 403 | clock-frequency = < 380000 >; |
| 404 | nvidia,emc-registers = < 0x00000017 0x0000004b |
| 405 | 0x00000012 0x00000006 0x00000004 0x00000005 |
| 406 | 0x00000003 0x0000000c 0x00000006 0x00000006 |
| 407 | 0x00000003 0x00000001 0x00000004 0x00000005 |
| 408 | 0x00000004 0x00000009 0x0000000d 0x00000b5f |
| 409 | 0x00000000 0x00000003 0x00000003 0x00000006 |
| 410 | 0x00000006 0x00000001 0x00000011 0x000000c8 |
| 411 | 0x00000003 0x0000000e 0x00000007 0x0000000f |
| 412 | 0x00000002 0x00000000 0x00000000 0x00000002 |
| 413 | 0x00000000 0x00000000 0x00000083 0xe044048b |
| 414 | 0x007d8010 0x00000000 0x00000000 0x00000000 |
| 415 | 0x00000000 0x00000000 0x00000000 0x00000000 >; |
| 416 | }; |
| 417 | }; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame^] | 418 | |
| 419 | usb@c5004000 { |
| 420 | nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ |
| 421 | }; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 422 | }; |