Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
Sujith | cee075a | 2009-03-13 09:07:23 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
| 18 | #include <asm/unaligned.h> |
| 19 | |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 20 | #include "hw.h" |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 21 | #include "rc.h" |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 22 | #include "initvals.h" |
| 23 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 24 | #define ATH9K_CLOCK_RATE_CCK 22 |
| 25 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
| 26 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 27 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 28 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 29 | static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 30 | static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 31 | struct ar5416_eeprom_def *pEepData, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 32 | u32 reg, u32 value); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 33 | |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 34 | MODULE_AUTHOR("Atheros Communications"); |
| 35 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); |
| 36 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); |
| 37 | MODULE_LICENSE("Dual BSD/GPL"); |
| 38 | |
| 39 | static int __init ath9k_init(void) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
| 43 | module_init(ath9k_init); |
| 44 | |
| 45 | static void __exit ath9k_exit(void) |
| 46 | { |
| 47 | return; |
| 48 | } |
| 49 | module_exit(ath9k_exit); |
| 50 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 51 | /********************/ |
| 52 | /* Helper Functions */ |
| 53 | /********************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 54 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 55 | static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 56 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 57 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 58 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 59 | if (!ah->curchan) /* should really check for CCK instead */ |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 60 | return clks / ATH9K_CLOCK_RATE_CCK; |
| 61 | if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 62 | return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 63 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 64 | return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 65 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 66 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 67 | static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 68 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 69 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 70 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 71 | if (conf_is_ht40(conf)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 72 | return ath9k_hw_mac_usec(ah, clks) / 2; |
| 73 | else |
| 74 | return ath9k_hw_mac_usec(ah, clks); |
| 75 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 76 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 77 | static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 78 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 79 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 80 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 81 | if (!ah->curchan) /* should really check for CCK instead */ |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 82 | return usecs *ATH9K_CLOCK_RATE_CCK; |
| 83 | if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 84 | return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; |
| 85 | return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 86 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 87 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 88 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 89 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 90 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 91 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 92 | if (conf_is_ht40(conf)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 93 | return ath9k_hw_mac_clks(ah, usecs) * 2; |
| 94 | else |
| 95 | return ath9k_hw_mac_clks(ah, usecs); |
| 96 | } |
| 97 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 98 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 99 | { |
| 100 | int i; |
| 101 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 102 | BUG_ON(timeout < AH_TIME_QUANTUM); |
| 103 | |
| 104 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 105 | if ((REG_READ(ah, reg) & mask) == val) |
| 106 | return true; |
| 107 | |
| 108 | udelay(AH_TIME_QUANTUM); |
| 109 | } |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 110 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 111 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, |
| 112 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
| 113 | timeout, reg, REG_READ(ah, reg), mask, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 114 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 115 | return false; |
| 116 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 117 | EXPORT_SYMBOL(ath9k_hw_wait); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 118 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 119 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
| 120 | { |
| 121 | u32 retval; |
| 122 | int i; |
| 123 | |
| 124 | for (i = 0, retval = 0; i < n; i++) { |
| 125 | retval = (retval << 1) | (val & 1); |
| 126 | val >>= 1; |
| 127 | } |
| 128 | return retval; |
| 129 | } |
| 130 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 131 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 132 | u16 flags, u16 *low, |
| 133 | u16 *high) |
| 134 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 135 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 136 | |
| 137 | if (flags & CHANNEL_5GHZ) { |
| 138 | *low = pCap->low_5ghz_chan; |
| 139 | *high = pCap->high_5ghz_chan; |
| 140 | return true; |
| 141 | } |
| 142 | if ((flags & CHANNEL_2GHZ)) { |
| 143 | *low = pCap->low_2ghz_chan; |
| 144 | *high = pCap->high_2ghz_chan; |
| 145 | return true; |
| 146 | } |
| 147 | return false; |
| 148 | } |
| 149 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 150 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 151 | u8 phy, int kbps, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 152 | u32 frameLen, u16 rateix, |
| 153 | bool shortPreamble) |
| 154 | { |
| 155 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 156 | |
| 157 | if (kbps == 0) |
| 158 | return 0; |
| 159 | |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 160 | switch (phy) { |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 161 | case WLAN_RC_PHY_CCK: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 162 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 163 | if (shortPreamble) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 164 | phyTime >>= 1; |
| 165 | numBits = frameLen << 3; |
| 166 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); |
| 167 | break; |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 168 | case WLAN_RC_PHY_OFDM: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 169 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 170 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
| 171 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 172 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 173 | txTime = OFDM_SIFS_TIME_QUARTER |
| 174 | + OFDM_PREAMBLE_TIME_QUARTER |
| 175 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 176 | } else if (ah->curchan && |
| 177 | IS_CHAN_HALF_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 178 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
| 179 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 180 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 181 | txTime = OFDM_SIFS_TIME_HALF + |
| 182 | OFDM_PREAMBLE_TIME_HALF |
| 183 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); |
| 184 | } else { |
| 185 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; |
| 186 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 187 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 188 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME |
| 189 | + (numSymbols * OFDM_SYMBOL_TIME); |
| 190 | } |
| 191 | break; |
| 192 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 193 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 194 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 195 | txTime = 0; |
| 196 | break; |
| 197 | } |
| 198 | |
| 199 | return txTime; |
| 200 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 201 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 202 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 203 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 204 | struct ath9k_channel *chan, |
| 205 | struct chan_centers *centers) |
| 206 | { |
| 207 | int8_t extoff; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 208 | |
| 209 | if (!IS_CHAN_HT40(chan)) { |
| 210 | centers->ctl_center = centers->ext_center = |
| 211 | centers->synth_center = chan->channel; |
| 212 | return; |
| 213 | } |
| 214 | |
| 215 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
| 216 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { |
| 217 | centers->synth_center = |
| 218 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; |
| 219 | extoff = 1; |
| 220 | } else { |
| 221 | centers->synth_center = |
| 222 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; |
| 223 | extoff = -1; |
| 224 | } |
| 225 | |
| 226 | centers->ctl_center = |
| 227 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 228 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 229 | centers->ext_center = |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 230 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | /******************/ |
| 234 | /* Chip Revisions */ |
| 235 | /******************/ |
| 236 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 237 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 238 | { |
| 239 | u32 val; |
| 240 | |
| 241 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
| 242 | |
| 243 | if (val == 0xFF) { |
| 244 | val = REG_READ(ah, AR_SREV); |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 245 | ah->hw_version.macVersion = |
| 246 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; |
| 247 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 248 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 249 | } else { |
| 250 | if (!AR_SREV_9100(ah)) |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 251 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 252 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 253 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 254 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 255 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 256 | ah->is_pciexpress = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 257 | } |
| 258 | } |
| 259 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 260 | static int ath9k_hw_get_radiorev(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 261 | { |
| 262 | u32 val; |
| 263 | int i; |
| 264 | |
| 265 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
| 266 | |
| 267 | for (i = 0; i < 8; i++) |
| 268 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); |
| 269 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; |
| 270 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); |
| 271 | |
| 272 | return ath9k_hw_reverse_bits(val, 8); |
| 273 | } |
| 274 | |
| 275 | /************************************/ |
| 276 | /* HW Attach, Detach, Init Routines */ |
| 277 | /************************************/ |
| 278 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 279 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 280 | { |
Sujith | feed029 | 2009-01-29 11:37:35 +0530 | [diff] [blame] | 281 | if (AR_SREV_9100(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 282 | return; |
| 283 | |
| 284 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 285 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 286 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); |
| 287 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); |
| 288 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); |
| 289 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); |
| 290 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 291 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); |
| 293 | |
| 294 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 295 | } |
| 296 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 297 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 298 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 299 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 300 | u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; |
| 301 | u32 regHold[2]; |
| 302 | u32 patternData[4] = { 0x55555555, |
| 303 | 0xaaaaaaaa, |
| 304 | 0x66666666, |
| 305 | 0x99999999 }; |
| 306 | int i, j; |
| 307 | |
| 308 | for (i = 0; i < 2; i++) { |
| 309 | u32 addr = regAddr[i]; |
| 310 | u32 wrData, rdData; |
| 311 | |
| 312 | regHold[i] = REG_READ(ah, addr); |
| 313 | for (j = 0; j < 0x100; j++) { |
| 314 | wrData = (j << 16) | j; |
| 315 | REG_WRITE(ah, addr, wrData); |
| 316 | rdData = REG_READ(ah, addr); |
| 317 | if (rdData != wrData) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 318 | ath_print(common, ATH_DBG_FATAL, |
| 319 | "address test failed " |
| 320 | "addr: 0x%08x - wr:0x%08x != " |
| 321 | "rd:0x%08x\n", |
| 322 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 323 | return false; |
| 324 | } |
| 325 | } |
| 326 | for (j = 0; j < 4; j++) { |
| 327 | wrData = patternData[j]; |
| 328 | REG_WRITE(ah, addr, wrData); |
| 329 | rdData = REG_READ(ah, addr); |
| 330 | if (wrData != rdData) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 331 | ath_print(common, ATH_DBG_FATAL, |
| 332 | "address test failed " |
| 333 | "addr: 0x%08x - wr:0x%08x != " |
| 334 | "rd:0x%08x\n", |
| 335 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 336 | return false; |
| 337 | } |
| 338 | } |
| 339 | REG_WRITE(ah, regAddr[i], regHold[i]); |
| 340 | } |
| 341 | udelay(100); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 342 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 343 | return true; |
| 344 | } |
| 345 | |
| 346 | static const char *ath9k_hw_devname(u16 devid) |
| 347 | { |
| 348 | switch (devid) { |
| 349 | case AR5416_DEVID_PCI: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 350 | return "Atheros 5416"; |
Benoit PAPILLAULT | 392dff8 | 2008-11-06 22:26:49 +0100 | [diff] [blame] | 351 | case AR5416_DEVID_PCIE: |
| 352 | return "Atheros 5418"; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 353 | case AR9160_DEVID_PCI: |
| 354 | return "Atheros 9160"; |
Gabor Juhos | 0c1aa49 | 2009-01-14 20:17:12 +0100 | [diff] [blame] | 355 | case AR5416_AR9100_DEVID: |
| 356 | return "Atheros 9100"; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 357 | case AR9280_DEVID_PCI: |
| 358 | case AR9280_DEVID_PCIE: |
| 359 | return "Atheros 9280"; |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 360 | case AR9285_DEVID_PCIE: |
| 361 | return "Atheros 9285"; |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 362 | case AR5416_DEVID_AR9287_PCI: |
| 363 | case AR5416_DEVID_AR9287_PCIE: |
| 364 | return "Atheros 9287"; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | return NULL; |
| 368 | } |
| 369 | |
Luis R. Rodriguez | b8b0f37 | 2009-08-03 12:24:43 -0700 | [diff] [blame] | 370 | static void ath9k_hw_init_config(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 371 | { |
| 372 | int i; |
| 373 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 374 | ah->config.dma_beacon_response_time = 2; |
| 375 | ah->config.sw_beacon_response_time = 10; |
| 376 | ah->config.additional_swba_backoff = 0; |
| 377 | ah->config.ack_6mb = 0x0; |
| 378 | ah->config.cwm_ignore_extcca = 0; |
| 379 | ah->config.pcie_powersave_enable = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 380 | ah->config.pcie_clock_req = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 381 | ah->config.pcie_waen = 0; |
| 382 | ah->config.analog_shiftreg = 1; |
| 383 | ah->config.ht_enable = 1; |
| 384 | ah->config.ofdm_trig_low = 200; |
| 385 | ah->config.ofdm_trig_high = 500; |
| 386 | ah->config.cck_trig_high = 200; |
| 387 | ah->config.cck_trig_low = 100; |
| 388 | ah->config.enable_ani = 1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 389 | |
| 390 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 391 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
| 392 | ah->config.spurchans[i][1] = AR_NO_SPUR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 393 | } |
| 394 | |
Sujith | 0ef1f16 | 2009-03-30 15:28:35 +0530 | [diff] [blame] | 395 | ah->config.intr_mitigation = true; |
Luis R. Rodriguez | 6158425 | 2009-03-12 18:18:49 -0400 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) |
| 399 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). |
| 400 | * This means we use it for all AR5416 devices, and the few |
| 401 | * minor PCI AR9280 devices out there. |
| 402 | * |
| 403 | * Serialization is required because these devices do not handle |
| 404 | * well the case of two concurrent reads/writes due to the latency |
| 405 | * involved. During one read/write another read/write can be issued |
| 406 | * on another CPU while the previous read/write may still be working |
| 407 | * on our hardware, if we hit this case the hardware poops in a loop. |
| 408 | * We prevent this by serializing reads and writes. |
| 409 | * |
| 410 | * This issue is not present on PCI-Express devices or pre-AR5416 |
| 411 | * devices (legacy, 802.11abg). |
| 412 | */ |
| 413 | if (num_possible_cpus() > 1) |
David S. Miller | 2d6a5e9 | 2009-03-17 15:01:30 -0700 | [diff] [blame] | 414 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 415 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 416 | EXPORT_SYMBOL(ath9k_hw_init); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 417 | |
Luis R. Rodriguez | 50aca25 | 2009-08-03 12:24:42 -0700 | [diff] [blame] | 418 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 419 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 420 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 421 | |
| 422 | regulatory->country_code = CTRY_DEFAULT; |
| 423 | regulatory->power_limit = MAX_RATE_POWER; |
| 424 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; |
| 425 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 426 | ah->hw_version.magic = AR5416_MAGIC; |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 427 | ah->hw_version.subvendorid = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 428 | |
| 429 | ah->ah_flags = 0; |
Luis R. Rodriguez | 8df5d1b | 2009-08-03 12:24:37 -0700 | [diff] [blame] | 430 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 431 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 432 | if (!AR_SREV_9100(ah)) |
| 433 | ah->ah_flags = AH_USE_EEPROM; |
| 434 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 435 | ah->atim_window = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 436 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; |
| 437 | ah->beacon_interval = 100; |
| 438 | ah->enable_32kHz_clock = DONT_USE_32KHZ; |
| 439 | ah->slottime = (u32) -1; |
| 440 | ah->acktimeout = (u32) -1; |
| 441 | ah->ctstimeout = (u32) -1; |
| 442 | ah->globaltxtimeout = (u32) -1; |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 443 | ah->power_mode = ATH9K_PM_UNDEFINED; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 444 | } |
| 445 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 446 | static int ath9k_hw_rf_claim(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 447 | { |
| 448 | u32 val; |
| 449 | |
| 450 | REG_WRITE(ah, AR_PHY(0), 0x00000007); |
| 451 | |
| 452 | val = ath9k_hw_get_radiorev(ah); |
| 453 | switch (val & AR_RADIO_SREV_MAJOR) { |
| 454 | case 0: |
| 455 | val = AR_RAD5133_SREV_MAJOR; |
| 456 | break; |
| 457 | case AR_RAD5133_SREV_MAJOR: |
| 458 | case AR_RAD5122_SREV_MAJOR: |
| 459 | case AR_RAD2133_SREV_MAJOR: |
| 460 | case AR_RAD2122_SREV_MAJOR: |
| 461 | break; |
| 462 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 463 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 464 | "Radio Chip Rev 0x%02X not supported\n", |
| 465 | val & AR_RADIO_SREV_MAJOR); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 466 | return -EOPNOTSUPP; |
| 467 | } |
| 468 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 469 | ah->hw_version.analog5GhzRev = val; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 474 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 475 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 476 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 477 | u32 sum; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 478 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 479 | u16 eeval; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 480 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 481 | sum = 0; |
| 482 | for (i = 0; i < 3; i++) { |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 483 | eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 484 | sum += eeval; |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 485 | common->macaddr[2 * i] = eeval >> 8; |
| 486 | common->macaddr[2 * i + 1] = eeval & 0xff; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 487 | } |
Sujith | d8baa93 | 2009-03-30 15:28:25 +0530 | [diff] [blame] | 488 | if (sum == 0 || sum == 0xffff * 3) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 489 | return -EADDRNOTAVAIL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 490 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 491 | return 0; |
| 492 | } |
| 493 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 494 | static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 495 | { |
| 496 | u32 rxgain_type; |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 497 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 498 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { |
| 499 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 500 | |
| 501 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 502 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 503 | ar9280Modes_backoff_13db_rxgain_9280_2, |
| 504 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); |
| 505 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 506 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 507 | ar9280Modes_backoff_23db_rxgain_9280_2, |
| 508 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); |
| 509 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 510 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 511 | ar9280Modes_original_rxgain_9280_2, |
| 512 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 513 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 514 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 515 | ar9280Modes_original_rxgain_9280_2, |
| 516 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 517 | } |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 518 | } |
| 519 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 520 | static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 521 | { |
| 522 | u32 txgain_type; |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 523 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 524 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { |
| 525 | txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 526 | |
| 527 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 528 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 529 | ar9280Modes_high_power_tx_gain_9280_2, |
| 530 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); |
| 531 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 532 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 533 | ar9280Modes_original_tx_gain_9280_2, |
| 534 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 535 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 536 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 537 | ar9280Modes_original_tx_gain_9280_2, |
| 538 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 539 | } |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 540 | } |
| 541 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 542 | static int ath9k_hw_post_init(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 543 | { |
| 544 | int ecode; |
| 545 | |
Sujith | d8baa93 | 2009-03-30 15:28:25 +0530 | [diff] [blame] | 546 | if (!ath9k_hw_chip_test(ah)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 547 | return -ENODEV; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 548 | |
| 549 | ecode = ath9k_hw_rf_claim(ah); |
| 550 | if (ecode != 0) |
| 551 | return ecode; |
| 552 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 553 | ecode = ath9k_hw_eeprom_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 554 | if (ecode != 0) |
| 555 | return ecode; |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 556 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 557 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
| 558 | "Eeprom VER: %d, REV: %d\n", |
| 559 | ah->eep_ops->get_eeprom_ver(ah), |
| 560 | ah->eep_ops->get_eeprom_rev(ah)); |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 561 | |
Luis R. Rodriguez | 574d6b1 | 2009-10-19 02:33:37 -0400 | [diff] [blame] | 562 | if (!AR_SREV_9280_10_OR_LATER(ah)) { |
| 563 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
| 564 | if (ecode) { |
| 565 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 566 | "Failed allocating banks for " |
| 567 | "external radio\n"); |
| 568 | return ecode; |
| 569 | } |
| 570 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 571 | |
| 572 | if (!AR_SREV_9100(ah)) { |
| 573 | ath9k_hw_ani_setup(ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 574 | ath9k_hw_ani_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 575 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 576 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 577 | return 0; |
| 578 | } |
| 579 | |
Luis R. Rodriguez | ee2bb46 | 2009-08-03 12:24:39 -0700 | [diff] [blame] | 580 | static bool ath9k_hw_devid_supported(u16 devid) |
| 581 | { |
| 582 | switch (devid) { |
| 583 | case AR5416_DEVID_PCI: |
| 584 | case AR5416_DEVID_PCIE: |
| 585 | case AR5416_AR9100_DEVID: |
| 586 | case AR9160_DEVID_PCI: |
| 587 | case AR9280_DEVID_PCI: |
| 588 | case AR9280_DEVID_PCIE: |
| 589 | case AR9285_DEVID_PCIE: |
| 590 | case AR5416_DEVID_AR9287_PCI: |
| 591 | case AR5416_DEVID_AR9287_PCIE: |
Luis R. Rodriguez | 7976b42 | 2009-09-23 23:07:02 -0400 | [diff] [blame] | 592 | case AR9271_USB: |
Luis R. Rodriguez | ee2bb46 | 2009-08-03 12:24:39 -0700 | [diff] [blame] | 593 | return true; |
| 594 | default: |
| 595 | break; |
| 596 | } |
| 597 | return false; |
| 598 | } |
| 599 | |
Luis R. Rodriguez | f9d4a66 | 2009-08-03 12:24:41 -0700 | [diff] [blame] | 600 | static bool ath9k_hw_macversion_supported(u32 macversion) |
| 601 | { |
| 602 | switch (macversion) { |
| 603 | case AR_SREV_VERSION_5416_PCI: |
| 604 | case AR_SREV_VERSION_5416_PCIE: |
| 605 | case AR_SREV_VERSION_9160: |
| 606 | case AR_SREV_VERSION_9100: |
| 607 | case AR_SREV_VERSION_9280: |
| 608 | case AR_SREV_VERSION_9285: |
| 609 | case AR_SREV_VERSION_9287: |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 610 | case AR_SREV_VERSION_9271: |
Luis R. Rodriguez | 7976b42 | 2009-09-23 23:07:02 -0400 | [diff] [blame] | 611 | return true; |
Luis R. Rodriguez | f9d4a66 | 2009-08-03 12:24:41 -0700 | [diff] [blame] | 612 | default: |
| 613 | break; |
| 614 | } |
| 615 | return false; |
| 616 | } |
| 617 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 618 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 619 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 620 | if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 621 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 622 | ah->iq_caldata.calData = &iq_cal_single_sample; |
| 623 | ah->adcgain_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 624 | &adc_gain_cal_single_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 625 | ah->adcdc_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 626 | &adc_dc_cal_single_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 627 | ah->adcdc_calinitdata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 628 | &adc_init_dc_cal; |
| 629 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 630 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
| 631 | ah->adcgain_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 632 | &adc_gain_cal_multi_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 633 | ah->adcdc_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 634 | &adc_dc_cal_multi_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 635 | ah->adcdc_calinitdata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 636 | &adc_init_dc_cal; |
| 637 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 638 | ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 639 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 640 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 641 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 642 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) |
| 643 | { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 644 | if (AR_SREV_9271(ah)) { |
Luis R. Rodriguez | 8564328 | 2009-10-19 02:33:33 -0400 | [diff] [blame] | 645 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
| 646 | ARRAY_SIZE(ar9271Modes_9271), 6); |
| 647 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, |
| 648 | ARRAY_SIZE(ar9271Common_9271), 2); |
| 649 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
| 650 | ar9271Modes_9271_1_0_only, |
| 651 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 652 | return; |
| 653 | } |
| 654 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 655 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 656 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, |
| 657 | ARRAY_SIZE(ar9287Modes_9287_1_1), 6); |
| 658 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, |
| 659 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); |
| 660 | if (ah->config.pcie_clock_req) |
| 661 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 662 | ar9287PciePhy_clkreq_off_L1_9287_1_1, |
| 663 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); |
| 664 | else |
| 665 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 666 | ar9287PciePhy_clkreq_always_on_L1_9287_1_1, |
| 667 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), |
| 668 | 2); |
| 669 | } else if (AR_SREV_9287_10_OR_LATER(ah)) { |
| 670 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0, |
| 671 | ARRAY_SIZE(ar9287Modes_9287_1_0), 6); |
| 672 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0, |
| 673 | ARRAY_SIZE(ar9287Common_9287_1_0), 2); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 674 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 675 | if (ah->config.pcie_clock_req) |
| 676 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 677 | ar9287PciePhy_clkreq_off_L1_9287_1_0, |
| 678 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2); |
| 679 | else |
| 680 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 681 | ar9287PciePhy_clkreq_always_on_L1_9287_1_0, |
| 682 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0), |
| 683 | 2); |
| 684 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
| 685 | |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 686 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 687 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 688 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 689 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 690 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
| 691 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 692 | if (ah->config.pcie_clock_req) { |
| 693 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 694 | ar9285PciePhy_clkreq_off_L1_9285_1_2, |
| 695 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); |
| 696 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 697 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 698 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, |
| 699 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), |
| 700 | 2); |
| 701 | } |
| 702 | } else if (AR_SREV_9285_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 703 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 704 | ARRAY_SIZE(ar9285Modes_9285), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 705 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 706 | ARRAY_SIZE(ar9285Common_9285), 2); |
| 707 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 708 | if (ah->config.pcie_clock_req) { |
| 709 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 710 | ar9285PciePhy_clkreq_off_L1_9285, |
| 711 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); |
| 712 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 713 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 714 | ar9285PciePhy_clkreq_always_on_L1_9285, |
| 715 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); |
| 716 | } |
| 717 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 718 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 719 | ARRAY_SIZE(ar9280Modes_9280_2), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 720 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 721 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
| 722 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 723 | if (ah->config.pcie_clock_req) { |
| 724 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 725 | ar9280PciePhy_clkreq_off_L1_9280, |
| 726 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 727 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 728 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 729 | ar9280PciePhy_clkreq_always_on_L1_9280, |
| 730 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 731 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 732 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 733 | ar9280Modes_fast_clock_9280_2, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 734 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 735 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 736 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 737 | ARRAY_SIZE(ar9280Modes_9280), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 738 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 739 | ARRAY_SIZE(ar9280Common_9280), 2); |
| 740 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 741 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 742 | ARRAY_SIZE(ar5416Modes_9160), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 743 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 744 | ARRAY_SIZE(ar5416Common_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 745 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 746 | ARRAY_SIZE(ar5416Bank0_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 747 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 748 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 749 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 750 | ARRAY_SIZE(ar5416Bank1_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 751 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 752 | ARRAY_SIZE(ar5416Bank2_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 753 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 754 | ARRAY_SIZE(ar5416Bank3_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 755 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 756 | ARRAY_SIZE(ar5416Bank6_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 757 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 758 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 759 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 760 | ARRAY_SIZE(ar5416Bank7_9160), 2); |
| 761 | if (AR_SREV_9160_11(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 762 | INIT_INI_ARRAY(&ah->iniAddac, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 763 | ar5416Addac_91601_1, |
| 764 | ARRAY_SIZE(ar5416Addac_91601_1), 2); |
| 765 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 766 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 767 | ARRAY_SIZE(ar5416Addac_9160), 2); |
| 768 | } |
| 769 | } else if (AR_SREV_9100_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 770 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 771 | ARRAY_SIZE(ar5416Modes_9100), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 772 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 773 | ARRAY_SIZE(ar5416Common_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 774 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 775 | ARRAY_SIZE(ar5416Bank0_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 776 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 777 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 778 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 779 | ARRAY_SIZE(ar5416Bank1_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 780 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 781 | ARRAY_SIZE(ar5416Bank2_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 782 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 783 | ARRAY_SIZE(ar5416Bank3_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 784 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 785 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 786 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 787 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 788 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 789 | ARRAY_SIZE(ar5416Bank7_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 790 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 791 | ARRAY_SIZE(ar5416Addac_9100), 2); |
| 792 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 793 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 794 | ARRAY_SIZE(ar5416Modes), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 795 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 796 | ARRAY_SIZE(ar5416Common), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 797 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 798 | ARRAY_SIZE(ar5416Bank0), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 799 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 800 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 801 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 802 | ARRAY_SIZE(ar5416Bank1), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 803 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 804 | ARRAY_SIZE(ar5416Bank2), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 805 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 806 | ARRAY_SIZE(ar5416Bank3), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 807 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 808 | ARRAY_SIZE(ar5416Bank6), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 809 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 810 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 811 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 812 | ARRAY_SIZE(ar5416Bank7), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 813 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 814 | ARRAY_SIZE(ar5416Addac), 2); |
| 815 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 816 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 817 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 818 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 819 | { |
Vivek Natarajan | b37fa87 | 2009-09-23 16:27:27 +0530 | [diff] [blame] | 820 | if (AR_SREV_9287_11_OR_LATER(ah)) |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 821 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 822 | ar9287Modes_rx_gain_9287_1_1, |
| 823 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); |
| 824 | else if (AR_SREV_9287_10(ah)) |
| 825 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 826 | ar9287Modes_rx_gain_9287_1_0, |
| 827 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6); |
| 828 | else if (AR_SREV_9280_20(ah)) |
| 829 | ath9k_hw_init_rxgain_ini(ah); |
| 830 | |
Vivek Natarajan | b37fa87 | 2009-09-23 16:27:27 +0530 | [diff] [blame] | 831 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 832 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 833 | ar9287Modes_tx_gain_9287_1_1, |
| 834 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); |
| 835 | } else if (AR_SREV_9287_10(ah)) { |
| 836 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 837 | ar9287Modes_tx_gain_9287_1_0, |
| 838 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6); |
| 839 | } else if (AR_SREV_9280_20(ah)) { |
| 840 | ath9k_hw_init_txgain_ini(ah); |
| 841 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 842 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
| 843 | |
| 844 | /* txgain table */ |
| 845 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { |
| 846 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 847 | ar9285Modes_high_power_tx_gain_9285_1_2, |
| 848 | ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6); |
| 849 | } else { |
| 850 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 851 | ar9285Modes_original_tx_gain_9285_1_2, |
| 852 | ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6); |
| 853 | } |
| 854 | |
| 855 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 856 | } |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 857 | |
Felix Fietkau | aa8bc9e | 2010-01-23 20:04:18 +0100 | [diff] [blame^] | 858 | static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 859 | { |
| 860 | u32 i, j; |
Sujith | 06d0f06 | 2009-02-12 10:06:45 +0530 | [diff] [blame] | 861 | |
Felix Fietkau | aa8bc9e | 2010-01-23 20:04:18 +0100 | [diff] [blame^] | 862 | if (ah->hw_version.devid == AR9280_DEVID_PCI) { |
Sujith | 06d0f06 | 2009-02-12 10:06:45 +0530 | [diff] [blame] | 863 | |
| 864 | /* EEPROM Fixup */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 865 | for (i = 0; i < ah->iniModes.ia_rows; i++) { |
| 866 | u32 reg = INI_RA(&ah->iniModes, i, 0); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 867 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 868 | for (j = 1; j < ah->iniModes.ia_columns; j++) { |
| 869 | u32 val = INI_RA(&ah->iniModes, i, j); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 870 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 871 | INI_RA(&ah->iniModes, i, j) = |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 872 | ath9k_hw_ini_fixup(ah, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 873 | &ah->eeprom.def, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 874 | reg, val); |
| 875 | } |
| 876 | } |
| 877 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 878 | } |
| 879 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 880 | int ath9k_hw_init(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 881 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 882 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 883 | int r = 0; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 884 | |
Luis R. Rodriguez | 3ca3403 | 2009-09-23 23:07:01 -0400 | [diff] [blame] | 885 | if (!ath9k_hw_devid_supported(ah->hw_version.devid)) { |
| 886 | ath_print(common, ATH_DBG_FATAL, |
| 887 | "Unsupported device ID: 0x%0x\n", |
| 888 | ah->hw_version.devid); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 889 | return -EOPNOTSUPP; |
Luis R. Rodriguez | 3ca3403 | 2009-09-23 23:07:01 -0400 | [diff] [blame] | 890 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 891 | |
| 892 | ath9k_hw_init_defaults(ah); |
| 893 | ath9k_hw_init_config(ah); |
| 894 | |
| 895 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 896 | ath_print(common, ATH_DBG_FATAL, |
| 897 | "Couldn't reset chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 898 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 899 | } |
| 900 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 901 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 902 | ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 903 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { |
| 907 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || |
| 908 | (AR_SREV_9280(ah) && !ah->is_pciexpress)) { |
| 909 | ah->config.serialize_regmode = |
| 910 | SER_REG_MODE_ON; |
| 911 | } else { |
| 912 | ah->config.serialize_regmode = |
| 913 | SER_REG_MODE_OFF; |
| 914 | } |
| 915 | } |
| 916 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 917 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 918 | ah->config.serialize_regmode); |
| 919 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 920 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 921 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; |
| 922 | else |
| 923 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; |
| 924 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 925 | if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 926 | ath_print(common, ATH_DBG_FATAL, |
| 927 | "Mac Chip Rev 0x%02x.%x is not supported by " |
| 928 | "this driver\n", ah->hw_version.macVersion, |
| 929 | ah->hw_version.macRev); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 930 | return -EOPNOTSUPP; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 931 | } |
| 932 | |
| 933 | if (AR_SREV_9100(ah)) { |
| 934 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
| 935 | ah->supp_cals = IQ_MISMATCH_CAL; |
| 936 | ah->is_pciexpress = false; |
| 937 | } |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 938 | |
| 939 | if (AR_SREV_9271(ah)) |
| 940 | ah->is_pciexpress = false; |
| 941 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 942 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
| 943 | |
| 944 | ath9k_hw_init_cal_settings(ah); |
| 945 | |
| 946 | ah->ani_function = ATH9K_ANI_ALL; |
Luis R. Rodriguez | e68a060 | 2009-10-19 02:33:41 -0400 | [diff] [blame] | 947 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 948 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
Luis R. Rodriguez | e68a060 | 2009-10-19 02:33:41 -0400 | [diff] [blame] | 949 | ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel; |
Luis R. Rodriguez | ae478cf | 2009-10-19 02:33:43 -0400 | [diff] [blame] | 950 | ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate; |
| 951 | } else { |
Luis R. Rodriguez | e68a060 | 2009-10-19 02:33:41 -0400 | [diff] [blame] | 952 | ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel; |
Luis R. Rodriguez | ae478cf | 2009-10-19 02:33:43 -0400 | [diff] [blame] | 953 | ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate; |
| 954 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 955 | |
| 956 | ath9k_hw_init_mode_regs(ah); |
| 957 | |
| 958 | if (ah->is_pciexpress) |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 959 | ath9k_hw_configpcipowersave(ah, 0, 0); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 960 | else |
| 961 | ath9k_hw_disablepcie(ah); |
| 962 | |
Sujith | 193cd45 | 2009-09-18 15:04:07 +0530 | [diff] [blame] | 963 | /* Support for Japan ch.14 (2484) spread */ |
| 964 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 965 | INIT_INI_ARRAY(&ah->iniCckfirNormal, |
| 966 | ar9287Common_normal_cck_fir_coeff_92871_1, |
| 967 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); |
| 968 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 969 | ar9287Common_japan_2484_cck_fir_coeff_92871_1, |
| 970 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); |
| 971 | } |
| 972 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 973 | r = ath9k_hw_post_init(ah); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 974 | if (r) |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 975 | return r; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 976 | |
| 977 | ath9k_hw_init_mode_gain_regs(ah); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 978 | r = ath9k_hw_fill_cap_info(ah); |
| 979 | if (r) |
| 980 | return r; |
| 981 | |
Felix Fietkau | aa8bc9e | 2010-01-23 20:04:18 +0100 | [diff] [blame^] | 982 | ath9k_hw_init_eeprom_fix(ah); |
Sujith | f6688cd | 2008-12-07 21:43:10 +0530 | [diff] [blame] | 983 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 984 | r = ath9k_hw_init_macaddr(ah); |
| 985 | if (r) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 986 | ath_print(common, ATH_DBG_FATAL, |
| 987 | "Failed to initialize MAC address\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 988 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 989 | } |
| 990 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 991 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 992 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 993 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 994 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 995 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 996 | ath9k_init_nfcal_hist_buffer(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 997 | |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 998 | common->state = ATH_HW_INITIALIZED; |
| 999 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 1000 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1001 | } |
| 1002 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1003 | static void ath9k_hw_init_bb(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1004 | struct ath9k_channel *chan) |
| 1005 | { |
| 1006 | u32 synthDelay; |
| 1007 | |
| 1008 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
Sujith | 788a3d6 | 2008-11-18 09:09:54 +0530 | [diff] [blame] | 1009 | if (IS_CHAN_B(chan)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1010 | synthDelay = (4 * synthDelay) / 22; |
| 1011 | else |
| 1012 | synthDelay /= 10; |
| 1013 | |
| 1014 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
| 1015 | |
| 1016 | udelay(synthDelay + BASE_ACTIVATE_DELAY); |
| 1017 | } |
| 1018 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1019 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1020 | { |
| 1021 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
| 1022 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); |
| 1023 | |
| 1024 | REG_WRITE(ah, AR_QOS_NO_ACK, |
| 1025 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | |
| 1026 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | |
| 1027 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); |
| 1028 | |
| 1029 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); |
| 1030 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); |
| 1031 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); |
| 1032 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); |
| 1033 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
| 1034 | } |
| 1035 | |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 1036 | static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud) |
| 1037 | { |
| 1038 | u32 lcr; |
| 1039 | u32 baud_divider = freq * 1000 * 1000 / 16 / baud; |
| 1040 | |
| 1041 | lcr = REG_READ(ah , 0x5100c); |
| 1042 | lcr |= 0x80; |
| 1043 | |
| 1044 | REG_WRITE(ah, 0x5100c, lcr); |
| 1045 | REG_WRITE(ah, 0x51004, (baud_divider >> 8)); |
| 1046 | REG_WRITE(ah, 0x51000, (baud_divider & 0xff)); |
| 1047 | |
| 1048 | lcr &= ~0x80; |
| 1049 | REG_WRITE(ah, 0x5100c, lcr); |
| 1050 | } |
| 1051 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1052 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1053 | struct ath9k_channel *chan) |
| 1054 | { |
| 1055 | u32 pll; |
| 1056 | |
| 1057 | if (AR_SREV_9100(ah)) { |
| 1058 | if (chan && IS_CHAN_5GHZ(chan)) |
| 1059 | pll = 0x1450; |
| 1060 | else |
| 1061 | pll = 0x1458; |
| 1062 | } else { |
| 1063 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
| 1064 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); |
| 1065 | |
| 1066 | if (chan && IS_CHAN_HALF_RATE(chan)) |
| 1067 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); |
| 1068 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) |
| 1069 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); |
| 1070 | |
| 1071 | if (chan && IS_CHAN_5GHZ(chan)) { |
| 1072 | pll |= SM(0x28, AR_RTC_9160_PLL_DIV); |
| 1073 | |
| 1074 | |
| 1075 | if (AR_SREV_9280_20(ah)) { |
| 1076 | if (((chan->channel % 20) == 0) |
| 1077 | || ((chan->channel % 10) == 0)) |
| 1078 | pll = 0x2850; |
| 1079 | else |
| 1080 | pll = 0x142c; |
| 1081 | } |
| 1082 | } else { |
| 1083 | pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); |
| 1084 | } |
| 1085 | |
| 1086 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 1087 | |
| 1088 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); |
| 1089 | |
| 1090 | if (chan && IS_CHAN_HALF_RATE(chan)) |
| 1091 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); |
| 1092 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) |
| 1093 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); |
| 1094 | |
| 1095 | if (chan && IS_CHAN_5GHZ(chan)) |
| 1096 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); |
| 1097 | else |
| 1098 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); |
| 1099 | } else { |
| 1100 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; |
| 1101 | |
| 1102 | if (chan && IS_CHAN_HALF_RATE(chan)) |
| 1103 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); |
| 1104 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) |
| 1105 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); |
| 1106 | |
| 1107 | if (chan && IS_CHAN_5GHZ(chan)) |
| 1108 | pll |= SM(0xa, AR_RTC_PLL_DIV); |
| 1109 | else |
| 1110 | pll |= SM(0xb, AR_RTC_PLL_DIV); |
| 1111 | } |
| 1112 | } |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1113 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1114 | |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 1115 | /* Switch the core clock for ar9271 to 117Mhz */ |
| 1116 | if (AR_SREV_9271(ah)) { |
| 1117 | if ((pll == 0x142c) || (pll == 0x2850) ) { |
| 1118 | udelay(500); |
| 1119 | /* set CLKOBS to output AHB clock */ |
| 1120 | REG_WRITE(ah, 0x7020, 0xe); |
| 1121 | /* |
| 1122 | * 0x304: 117Mhz, ahb_ratio: 1x1 |
| 1123 | * 0x306: 40Mhz, ahb_ratio: 1x1 |
| 1124 | */ |
| 1125 | REG_WRITE(ah, 0x50040, 0x304); |
| 1126 | /* |
| 1127 | * makes adjustments for the baud dividor to keep the |
| 1128 | * targetted baud rate based on the used core clock. |
| 1129 | */ |
| 1130 | ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK, |
| 1131 | AR9271_TARGET_BAUD_RATE); |
| 1132 | } |
| 1133 | } |
| 1134 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1135 | udelay(RTC_PLL_SETTLE_DELAY); |
| 1136 | |
| 1137 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
| 1138 | } |
| 1139 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1140 | static void ath9k_hw_init_chain_masks(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1141 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1142 | int rx_chainmask, tx_chainmask; |
| 1143 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1144 | rx_chainmask = ah->rxchainmask; |
| 1145 | tx_chainmask = ah->txchainmask; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1146 | |
| 1147 | switch (rx_chainmask) { |
| 1148 | case 0x5: |
| 1149 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, |
| 1150 | AR_PHY_SWAP_ALT_CHAIN); |
| 1151 | case 0x3: |
Sujith | cb53a15 | 2009-11-16 11:40:57 +0530 | [diff] [blame] | 1152 | if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1153 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); |
| 1154 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); |
| 1155 | break; |
| 1156 | } |
| 1157 | case 0x1: |
| 1158 | case 0x2: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1159 | case 0x7: |
| 1160 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); |
| 1161 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); |
| 1162 | break; |
| 1163 | default: |
| 1164 | break; |
| 1165 | } |
| 1166 | |
| 1167 | REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); |
| 1168 | if (tx_chainmask == 0x5) { |
| 1169 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, |
| 1170 | AR_PHY_SWAP_ALT_CHAIN); |
| 1171 | } |
| 1172 | if (AR_SREV_9100(ah)) |
| 1173 | REG_WRITE(ah, AR_PHY_ANALOG_SWAP, |
| 1174 | REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); |
| 1175 | } |
| 1176 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1177 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1178 | enum nl80211_iftype opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1179 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1180 | ah->mask_reg = AR_IMR_TXERR | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1181 | AR_IMR_TXURN | |
| 1182 | AR_IMR_RXERR | |
| 1183 | AR_IMR_RXORN | |
| 1184 | AR_IMR_BCNMISC; |
| 1185 | |
Sujith | 0ef1f16 | 2009-03-30 15:28:35 +0530 | [diff] [blame] | 1186 | if (ah->config.intr_mitigation) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1187 | ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1188 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1189 | ah->mask_reg |= AR_IMR_RXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1190 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1191 | ah->mask_reg |= AR_IMR_TXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1192 | |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1193 | if (opmode == NL80211_IFTYPE_AP) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1194 | ah->mask_reg |= AR_IMR_MIB; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1195 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1196 | REG_WRITE(ah, AR_IMR, ah->mask_reg); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1197 | REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); |
| 1198 | |
| 1199 | if (!AR_SREV_9100(ah)) { |
| 1200 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); |
| 1201 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); |
| 1202 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
| 1203 | } |
| 1204 | } |
| 1205 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1206 | static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1207 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1208 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1209 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1210 | "bad ack timeout %u\n", us); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1211 | ah->acktimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1212 | return false; |
| 1213 | } else { |
| 1214 | REG_RMW_FIELD(ah, AR_TIME_OUT, |
| 1215 | AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1216 | ah->acktimeout = us; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1217 | return true; |
| 1218 | } |
| 1219 | } |
| 1220 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1221 | static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1222 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1223 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1224 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1225 | "bad cts timeout %u\n", us); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1226 | ah->ctstimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1227 | return false; |
| 1228 | } else { |
| 1229 | REG_RMW_FIELD(ah, AR_TIME_OUT, |
| 1230 | AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1231 | ah->ctstimeout = us; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1232 | return true; |
| 1233 | } |
| 1234 | } |
| 1235 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1236 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1237 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1238 | if (tu > 0xFFFF) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1239 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, |
| 1240 | "bad global tx timeout %u\n", tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1241 | ah->globaltxtimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1242 | return false; |
| 1243 | } else { |
| 1244 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1245 | ah->globaltxtimeout = tu; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1246 | return true; |
| 1247 | } |
| 1248 | } |
| 1249 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1250 | static void ath9k_hw_init_user_settings(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1251 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1252 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
| 1253 | ah->misc_mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1254 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1255 | if (ah->misc_mode != 0) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1256 | REG_WRITE(ah, AR_PCU_MISC, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1257 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
| 1258 | if (ah->slottime != (u32) -1) |
| 1259 | ath9k_hw_setslottime(ah, ah->slottime); |
| 1260 | if (ah->acktimeout != (u32) -1) |
| 1261 | ath9k_hw_set_ack_timeout(ah, ah->acktimeout); |
| 1262 | if (ah->ctstimeout != (u32) -1) |
| 1263 | ath9k_hw_set_cts_timeout(ah, ah->ctstimeout); |
| 1264 | if (ah->globaltxtimeout != (u32) -1) |
| 1265 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | const char *ath9k_hw_probe(u16 vendorid, u16 devid) |
| 1269 | { |
| 1270 | return vendorid == ATHEROS_VENDOR_ID ? |
| 1271 | ath9k_hw_devname(devid) : NULL; |
| 1272 | } |
| 1273 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1274 | void ath9k_hw_detach(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1275 | { |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 1276 | struct ath_common *common = ath9k_hw_common(ah); |
| 1277 | |
| 1278 | if (common->state <= ATH_HW_INITIALIZED) |
| 1279 | goto free_hw; |
| 1280 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1281 | if (!AR_SREV_9100(ah)) |
Luis R. Rodriguez | e70c0cf | 2009-08-03 12:24:51 -0700 | [diff] [blame] | 1282 | ath9k_hw_ani_disable(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1283 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1284 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 1285 | |
| 1286 | free_hw: |
Luis R. Rodriguez | dc51dd5 | 2009-10-19 02:33:39 -0400 | [diff] [blame] | 1287 | if (!AR_SREV_9280_10_OR_LATER(ah)) |
| 1288 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1289 | kfree(ah); |
Luis R. Rodriguez | 9db6b6a | 2009-08-03 12:24:52 -0700 | [diff] [blame] | 1290 | ah = NULL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1291 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1292 | EXPORT_SYMBOL(ath9k_hw_detach); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1293 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1294 | /*******/ |
| 1295 | /* INI */ |
| 1296 | /*******/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1297 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1298 | static void ath9k_hw_override_ini(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1299 | struct ath9k_channel *chan) |
| 1300 | { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1301 | u32 val; |
| 1302 | |
| 1303 | if (AR_SREV_9271(ah)) { |
| 1304 | /* |
| 1305 | * Enable spectral scan to solution for issues with stuck |
| 1306 | * beacons on AR9271 1.0. The beacon stuck issue is not seeon on |
| 1307 | * AR9271 1.1 |
| 1308 | */ |
| 1309 | if (AR_SREV_9271_10(ah)) { |
Luis R. Rodriguez | ec11bb8 | 2009-10-27 12:59:36 -0400 | [diff] [blame] | 1310 | val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | |
| 1311 | AR_PHY_SPECTRAL_SCAN_ENABLE; |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1312 | REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); |
| 1313 | } |
| 1314 | else if (AR_SREV_9271_11(ah)) |
| 1315 | /* |
| 1316 | * change AR_PHY_RF_CTL3 setting to fix MAC issue |
| 1317 | * present on AR9271 1.1 |
| 1318 | */ |
| 1319 | REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001); |
| 1320 | return; |
| 1321 | } |
| 1322 | |
Senthil Balasubramanian | 8aa15e1 | 2008-12-08 19:43:50 +0530 | [diff] [blame] | 1323 | /* |
| 1324 | * Set the RX_ABORT and RX_DIS and clear if off only after |
| 1325 | * RXE is set for MAC. This prevents frames with corrupted |
| 1326 | * descriptor status. |
| 1327 | */ |
| 1328 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
| 1329 | |
Vasanthakumar Thiagarajan | 204d794 | 2009-09-17 09:26:14 +0530 | [diff] [blame] | 1330 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
| 1331 | val = REG_READ(ah, AR_PCU_MISC_MODE2) & |
| 1332 | (~AR_PCU_MISC_MODE2_HWWAR1); |
| 1333 | |
| 1334 | if (AR_SREV_9287_10_OR_LATER(ah)) |
| 1335 | val = val & (~AR_PCU_MISC_MODE2_HWWAR2); |
| 1336 | |
| 1337 | REG_WRITE(ah, AR_PCU_MISC_MODE2, val); |
| 1338 | } |
Senthil Balasubramanian | 8aa15e1 | 2008-12-08 19:43:50 +0530 | [diff] [blame] | 1339 | |
Gabor Juhos | a8c96d3 | 2009-03-06 09:08:51 +0100 | [diff] [blame] | 1340 | if (!AR_SREV_5416_20_OR_LATER(ah) || |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1341 | AR_SREV_9280_10_OR_LATER(ah)) |
| 1342 | return; |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1343 | /* |
| 1344 | * Disable BB clock gating |
| 1345 | * Necessary to avoid issues on AR5416 2.0 |
| 1346 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1347 | REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); |
| 1348 | } |
| 1349 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1350 | static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1351 | struct ar5416_eeprom_def *pEepData, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1352 | u32 reg, u32 value) |
| 1353 | { |
| 1354 | struct base_eep_header *pBase = &(pEepData->baseEepHeader); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1355 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1356 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 1357 | switch (ah->hw_version.devid) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1358 | case AR9280_DEVID_PCI: |
| 1359 | if (reg == 0x7894) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1360 | ath_print(common, ATH_DBG_EEPROM, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1361 | "ini VAL: %x EEPROM: %x\n", value, |
| 1362 | (pBase->version & 0xff)); |
| 1363 | |
| 1364 | if ((pBase->version & 0xff) > 0x0a) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1365 | ath_print(common, ATH_DBG_EEPROM, |
| 1366 | "PWDCLKIND: %d\n", |
| 1367 | pBase->pwdclkind); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1368 | value &= ~AR_AN_TOP2_PWDCLKIND; |
| 1369 | value |= AR_AN_TOP2_PWDCLKIND & |
| 1370 | (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); |
| 1371 | } else { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1372 | ath_print(common, ATH_DBG_EEPROM, |
| 1373 | "PWDCLKIND Earlier Rev\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1374 | } |
| 1375 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1376 | ath_print(common, ATH_DBG_EEPROM, |
| 1377 | "final ini VAL: %x\n", value); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1378 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1379 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1380 | } |
| 1381 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1382 | return value; |
| 1383 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1384 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1385 | static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1386 | struct ar5416_eeprom_def *pEepData, |
| 1387 | u32 reg, u32 value) |
| 1388 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1389 | if (ah->eep_map == EEP_MAP_4KBITS) |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1390 | return value; |
| 1391 | else |
| 1392 | return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); |
| 1393 | } |
| 1394 | |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1395 | static void ath9k_olc_init(struct ath_hw *ah) |
| 1396 | { |
| 1397 | u32 i; |
| 1398 | |
Vivek Natarajan | db91f2e | 2009-08-14 11:27:16 +0530 | [diff] [blame] | 1399 | if (OLC_FOR_AR9287_10_LATER) { |
| 1400 | REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, |
| 1401 | AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); |
| 1402 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, |
| 1403 | AR9287_AN_TXPC0_TXPCMODE, |
| 1404 | AR9287_AN_TXPC0_TXPCMODE_S, |
| 1405 | AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); |
| 1406 | udelay(100); |
| 1407 | } else { |
| 1408 | for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) |
| 1409 | ah->originalGain[i] = |
| 1410 | MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), |
| 1411 | AR_PHY_TX_GAIN); |
| 1412 | ah->PDADCdelta = 0; |
| 1413 | } |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1414 | } |
| 1415 | |
Bob Copeland | 3a702e4 | 2009-03-30 22:30:29 -0400 | [diff] [blame] | 1416 | static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, |
| 1417 | struct ath9k_channel *chan) |
| 1418 | { |
| 1419 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); |
| 1420 | |
| 1421 | if (IS_CHAN_B(chan)) |
| 1422 | ctl |= CTL_11B; |
| 1423 | else if (IS_CHAN_G(chan)) |
| 1424 | ctl |= CTL_11G; |
| 1425 | else |
| 1426 | ctl |= CTL_11A; |
| 1427 | |
| 1428 | return ctl; |
| 1429 | } |
| 1430 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1431 | static int ath9k_hw_process_ini(struct ath_hw *ah, |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1432 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1433 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1434 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1435 | int i, regWrites = 0; |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1436 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1437 | u32 modesIndex, freqIndex; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1438 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1439 | switch (chan->chanmode) { |
| 1440 | case CHANNEL_A: |
| 1441 | case CHANNEL_A_HT20: |
| 1442 | modesIndex = 1; |
| 1443 | freqIndex = 1; |
| 1444 | break; |
| 1445 | case CHANNEL_A_HT40PLUS: |
| 1446 | case CHANNEL_A_HT40MINUS: |
| 1447 | modesIndex = 2; |
| 1448 | freqIndex = 1; |
| 1449 | break; |
| 1450 | case CHANNEL_G: |
| 1451 | case CHANNEL_G_HT20: |
| 1452 | case CHANNEL_B: |
| 1453 | modesIndex = 4; |
| 1454 | freqIndex = 2; |
| 1455 | break; |
| 1456 | case CHANNEL_G_HT40PLUS: |
| 1457 | case CHANNEL_G_HT40MINUS: |
| 1458 | modesIndex = 3; |
| 1459 | freqIndex = 2; |
| 1460 | break; |
| 1461 | |
| 1462 | default: |
| 1463 | return -EINVAL; |
| 1464 | } |
| 1465 | |
| 1466 | REG_WRITE(ah, AR_PHY(0), 0x00000007); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1467 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1468 | ah->eep_ops->set_addac(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1469 | |
Gabor Juhos | a8c96d3 | 2009-03-06 09:08:51 +0100 | [diff] [blame] | 1470 | if (AR_SREV_5416_22_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1471 | REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1472 | } else { |
| 1473 | struct ar5416IniArray temp; |
| 1474 | u32 addacSize = |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1475 | sizeof(u32) * ah->iniAddac.ia_rows * |
| 1476 | ah->iniAddac.ia_columns; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1477 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1478 | memcpy(ah->addac5416_21, |
| 1479 | ah->iniAddac.ia_array, addacSize); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1480 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1481 | (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1482 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1483 | temp.ia_array = ah->addac5416_21; |
| 1484 | temp.ia_columns = ah->iniAddac.ia_columns; |
| 1485 | temp.ia_rows = ah->iniAddac.ia_rows; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1486 | REG_WRITE_ARRAY(&temp, 1, regWrites); |
| 1487 | } |
| 1488 | |
| 1489 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); |
| 1490 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1491 | for (i = 0; i < ah->iniModes.ia_rows; i++) { |
| 1492 | u32 reg = INI_RA(&ah->iniModes, i, 0); |
| 1493 | u32 val = INI_RA(&ah->iniModes, i, modesIndex); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1494 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1495 | REG_WRITE(ah, reg, val); |
| 1496 | |
| 1497 | if (reg >= 0x7800 && reg < 0x78a0 |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1498 | && ah->config.analog_shiftreg) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1499 | udelay(100); |
| 1500 | } |
| 1501 | |
| 1502 | DO_DELAY(regWrites); |
| 1503 | } |
| 1504 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1505 | if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1506 | REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 1507 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1508 | if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || |
| 1509 | AR_SREV_9287_10_OR_LATER(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1510 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 1511 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1512 | for (i = 0; i < ah->iniCommon.ia_rows; i++) { |
| 1513 | u32 reg = INI_RA(&ah->iniCommon, i, 0); |
| 1514 | u32 val = INI_RA(&ah->iniCommon, i, 1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1515 | |
| 1516 | REG_WRITE(ah, reg, val); |
| 1517 | |
| 1518 | if (reg >= 0x7800 && reg < 0x78a0 |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1519 | && ah->config.analog_shiftreg) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1520 | udelay(100); |
| 1521 | } |
| 1522 | |
| 1523 | DO_DELAY(regWrites); |
| 1524 | } |
| 1525 | |
Luis R. Rodriguez | 896ff26 | 2009-10-19 02:33:44 -0400 | [diff] [blame] | 1526 | ath9k_hw_write_regs(ah, freqIndex, regWrites); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1527 | |
Luis R. Rodriguez | 8564328 | 2009-10-19 02:33:33 -0400 | [diff] [blame] | 1528 | if (AR_SREV_9271_10(ah)) |
| 1529 | REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only, |
| 1530 | modesIndex, regWrites); |
| 1531 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1532 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1533 | REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1534 | regWrites); |
| 1535 | } |
| 1536 | |
| 1537 | ath9k_hw_override_ini(ah, chan); |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1538 | ath9k_hw_set_regs(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1539 | ath9k_hw_init_chain_masks(ah); |
| 1540 | |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1541 | if (OLC_FOR_AR9280_20_LATER) |
| 1542 | ath9k_olc_init(ah); |
| 1543 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1544 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1545 | ath9k_regd_get_ctl(regulatory, chan), |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1546 | channel->max_antenna_gain * 2, |
| 1547 | channel->max_power * 2, |
| 1548 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1549 | (u32) regulatory->power_limit)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1550 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1551 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1552 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 1553 | "ar5416SetRfRegs failed\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1554 | return -EIO; |
| 1555 | } |
| 1556 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1557 | return 0; |
| 1558 | } |
| 1559 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1560 | /****************************************/ |
| 1561 | /* Reset and Channel Switching Routines */ |
| 1562 | /****************************************/ |
| 1563 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1564 | static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1565 | { |
| 1566 | u32 rfMode = 0; |
| 1567 | |
| 1568 | if (chan == NULL) |
| 1569 | return; |
| 1570 | |
| 1571 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) |
| 1572 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; |
| 1573 | |
| 1574 | if (!AR_SREV_9280_10_OR_LATER(ah)) |
| 1575 | rfMode |= (IS_CHAN_5GHZ(chan)) ? |
| 1576 | AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; |
| 1577 | |
| 1578 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) |
| 1579 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); |
| 1580 | |
| 1581 | REG_WRITE(ah, AR_PHY_MODE, rfMode); |
| 1582 | } |
| 1583 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1584 | static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1585 | { |
| 1586 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); |
| 1587 | } |
| 1588 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1589 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1590 | { |
| 1591 | u32 regval; |
| 1592 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1593 | /* |
| 1594 | * set AHB_MODE not to do cacheline prefetches |
| 1595 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1596 | regval = REG_READ(ah, AR_AHB_MODE); |
| 1597 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); |
| 1598 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1599 | /* |
| 1600 | * let mac dma reads be in 128 byte chunks |
| 1601 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1602 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
| 1603 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); |
| 1604 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1605 | /* |
| 1606 | * Restore TX Trigger Level to its pre-reset value. |
| 1607 | * The initial value depends on whether aggregation is enabled, and is |
| 1608 | * adjusted whenever underruns are detected. |
| 1609 | */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1610 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1611 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1612 | /* |
| 1613 | * let mac dma writes be in 128 byte chunks |
| 1614 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1615 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
| 1616 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); |
| 1617 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1618 | /* |
| 1619 | * Setup receive FIFO threshold to hold off TX activities |
| 1620 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1621 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
| 1622 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1623 | /* |
| 1624 | * reduce the number of usable entries in PCU TXBUF to avoid |
| 1625 | * wrap around issues. |
| 1626 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1627 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1628 | /* For AR9285 the number of Fifos are reduced to half. |
| 1629 | * So set the usable tx buf size also to half to |
| 1630 | * avoid data/delimiter underruns |
| 1631 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1632 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 1633 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1634 | } else if (!AR_SREV_9271(ah)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1635 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 1636 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
| 1637 | } |
| 1638 | } |
| 1639 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1640 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1641 | { |
| 1642 | u32 val; |
| 1643 | |
| 1644 | val = REG_READ(ah, AR_STA_ID1); |
| 1645 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); |
| 1646 | switch (opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1647 | case NL80211_IFTYPE_AP: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1648 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
| 1649 | | AR_STA_ID1_KSRCH_MODE); |
| 1650 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 1651 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1652 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 1653 | case NL80211_IFTYPE_MESH_POINT: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1654 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
| 1655 | | AR_STA_ID1_KSRCH_MODE); |
| 1656 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 1657 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1658 | case NL80211_IFTYPE_STATION: |
| 1659 | case NL80211_IFTYPE_MONITOR: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1660 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
| 1661 | break; |
| 1662 | } |
| 1663 | } |
| 1664 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1665 | static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1666 | u32 coef_scaled, |
| 1667 | u32 *coef_mantissa, |
| 1668 | u32 *coef_exponent) |
| 1669 | { |
| 1670 | u32 coef_exp, coef_man; |
| 1671 | |
| 1672 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
| 1673 | if ((coef_scaled >> coef_exp) & 0x1) |
| 1674 | break; |
| 1675 | |
| 1676 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); |
| 1677 | |
| 1678 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); |
| 1679 | |
| 1680 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); |
| 1681 | *coef_exponent = coef_exp - 16; |
| 1682 | } |
| 1683 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1684 | static void ath9k_hw_set_delta_slope(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1685 | struct ath9k_channel *chan) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1686 | { |
| 1687 | u32 coef_scaled, ds_coef_exp, ds_coef_man; |
| 1688 | u32 clockMhzScaled = 0x64000000; |
| 1689 | struct chan_centers centers; |
| 1690 | |
| 1691 | if (IS_CHAN_HALF_RATE(chan)) |
| 1692 | clockMhzScaled = clockMhzScaled >> 1; |
| 1693 | else if (IS_CHAN_QUARTER_RATE(chan)) |
| 1694 | clockMhzScaled = clockMhzScaled >> 2; |
| 1695 | |
| 1696 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
| 1697 | coef_scaled = clockMhzScaled / centers.synth_center; |
| 1698 | |
| 1699 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, |
| 1700 | &ds_coef_exp); |
| 1701 | |
| 1702 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, |
| 1703 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); |
| 1704 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, |
| 1705 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); |
| 1706 | |
| 1707 | coef_scaled = (9 * coef_scaled) / 10; |
| 1708 | |
| 1709 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, |
| 1710 | &ds_coef_exp); |
| 1711 | |
| 1712 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, |
| 1713 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); |
| 1714 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, |
| 1715 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); |
| 1716 | } |
| 1717 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1718 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1719 | { |
| 1720 | u32 rst_flags; |
| 1721 | u32 tmpReg; |
| 1722 | |
Sujith | 7076849 | 2009-02-16 13:23:12 +0530 | [diff] [blame] | 1723 | if (AR_SREV_9100(ah)) { |
| 1724 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 1725 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; |
| 1726 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); |
| 1727 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); |
| 1728 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 1729 | } |
| 1730 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1731 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1732 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1733 | |
| 1734 | if (AR_SREV_9100(ah)) { |
| 1735 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | |
| 1736 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; |
| 1737 | } else { |
| 1738 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 1739 | if (tmpReg & |
| 1740 | (AR_INTR_SYNC_LOCAL_TIMEOUT | |
| 1741 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
| 1742 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
| 1743 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 1744 | } else { |
| 1745 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
| 1746 | } |
| 1747 | |
| 1748 | rst_flags = AR_RTC_RC_MAC_WARM; |
| 1749 | if (type == ATH9K_RESET_COLD) |
| 1750 | rst_flags |= AR_RTC_RC_MAC_COLD; |
| 1751 | } |
| 1752 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1753 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1754 | udelay(50); |
| 1755 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1756 | REG_WRITE(ah, AR_RTC_RC, 0); |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1757 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1758 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1759 | "RTC stuck in MAC reset\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1760 | return false; |
| 1761 | } |
| 1762 | |
| 1763 | if (!AR_SREV_9100(ah)) |
| 1764 | REG_WRITE(ah, AR_RC, 0); |
| 1765 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1766 | if (AR_SREV_9100(ah)) |
| 1767 | udelay(50); |
| 1768 | |
| 1769 | return true; |
| 1770 | } |
| 1771 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1772 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1773 | { |
| 1774 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1775 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1776 | |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1777 | if (!AR_SREV_9100(ah)) |
| 1778 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
| 1779 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1780 | REG_WRITE(ah, AR_RTC_RESET, 0); |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1781 | udelay(2); |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1782 | |
| 1783 | if (!AR_SREV_9100(ah)) |
| 1784 | REG_WRITE(ah, AR_RC, 0); |
| 1785 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1786 | REG_WRITE(ah, AR_RTC_RESET, 1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1787 | |
| 1788 | if (!ath9k_hw_wait(ah, |
| 1789 | AR_RTC_STATUS, |
| 1790 | AR_RTC_STATUS_M, |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1791 | AR_RTC_STATUS_ON, |
| 1792 | AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1793 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1794 | "RTC not waking up\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1795 | return false; |
| 1796 | } |
| 1797 | |
| 1798 | ath9k_hw_read_revisions(ah); |
| 1799 | |
| 1800 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
| 1801 | } |
| 1802 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1803 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1804 | { |
| 1805 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1806 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
| 1807 | |
| 1808 | switch (type) { |
| 1809 | case ATH9K_RESET_POWER_ON: |
| 1810 | return ath9k_hw_set_reset_power_on(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1811 | case ATH9K_RESET_WARM: |
| 1812 | case ATH9K_RESET_COLD: |
| 1813 | return ath9k_hw_set_reset(ah, type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1814 | default: |
| 1815 | return false; |
| 1816 | } |
| 1817 | } |
| 1818 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1819 | static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1820 | { |
| 1821 | u32 phymode; |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1822 | u32 enableDacFifo = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1823 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1824 | if (AR_SREV_9285_10_OR_LATER(ah)) |
| 1825 | enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & |
| 1826 | AR_PHY_FC_ENABLE_DAC_FIFO); |
| 1827 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1828 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1829 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1830 | |
| 1831 | if (IS_CHAN_HT40(chan)) { |
| 1832 | phymode |= AR_PHY_FC_DYN2040_EN; |
| 1833 | |
| 1834 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
| 1835 | (chan->chanmode == CHANNEL_G_HT40PLUS)) |
| 1836 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; |
| 1837 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1838 | } |
| 1839 | REG_WRITE(ah, AR_PHY_TURBO, phymode); |
| 1840 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1841 | ath9k_hw_set11nmac2040(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1842 | |
| 1843 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); |
| 1844 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); |
| 1845 | } |
| 1846 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1847 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1848 | struct ath9k_channel *chan) |
| 1849 | { |
Vivek Natarajan | 42abfbe | 2009-09-17 09:27:59 +0530 | [diff] [blame] | 1850 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1851 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
| 1852 | return false; |
| 1853 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1854 | return false; |
| 1855 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1856 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1857 | return false; |
| 1858 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1859 | ah->chip_fullsleep = false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1860 | ath9k_hw_init_pll(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1861 | ath9k_hw_set_rfmode(ah, chan); |
| 1862 | |
| 1863 | return true; |
| 1864 | } |
| 1865 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1866 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1867 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1868 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1869 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1870 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1871 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1872 | u32 synthDelay, qnum; |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1873 | int r; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1874 | |
| 1875 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
| 1876 | if (ath9k_hw_numtxpending(ah, qnum)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1877 | ath_print(common, ATH_DBG_QUEUE, |
| 1878 | "Transmit frames pending on " |
| 1879 | "queue %d\n", qnum); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1880 | return false; |
| 1881 | } |
| 1882 | } |
| 1883 | |
| 1884 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); |
| 1885 | if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1886 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1887 | ath_print(common, ATH_DBG_FATAL, |
| 1888 | "Could not kill baseband RX\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1889 | return false; |
| 1890 | } |
| 1891 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1892 | ath9k_hw_set_regs(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1893 | |
Luis R. Rodriguez | e68a060 | 2009-10-19 02:33:41 -0400 | [diff] [blame] | 1894 | r = ah->ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1895 | if (r) { |
| 1896 | ath_print(common, ATH_DBG_FATAL, |
| 1897 | "Failed to set channel\n"); |
| 1898 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1899 | } |
| 1900 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1901 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1902 | ath9k_regd_get_ctl(regulatory, chan), |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1903 | channel->max_antenna_gain * 2, |
| 1904 | channel->max_power * 2, |
| 1905 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1906 | (u32) regulatory->power_limit)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1907 | |
| 1908 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
Sujith | 788a3d6 | 2008-11-18 09:09:54 +0530 | [diff] [blame] | 1909 | if (IS_CHAN_B(chan)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1910 | synthDelay = (4 * synthDelay) / 22; |
| 1911 | else |
| 1912 | synthDelay /= 10; |
| 1913 | |
| 1914 | udelay(synthDelay + BASE_ACTIVATE_DELAY); |
| 1915 | |
| 1916 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); |
| 1917 | |
| 1918 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1919 | ath9k_hw_set_delta_slope(ah, chan); |
| 1920 | |
Luis R. Rodriguez | ae478cf | 2009-10-19 02:33:43 -0400 | [diff] [blame] | 1921 | ah->ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1922 | |
| 1923 | if (!chan->oneTimeCalsDone) |
| 1924 | chan->oneTimeCalsDone = true; |
| 1925 | |
| 1926 | return true; |
| 1927 | } |
| 1928 | |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1929 | static void ath9k_enable_rfkill(struct ath_hw *ah) |
| 1930 | { |
| 1931 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, |
| 1932 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); |
| 1933 | |
| 1934 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, |
| 1935 | AR_GPIO_INPUT_MUX2_RFSILENT); |
| 1936 | |
| 1937 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); |
| 1938 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); |
| 1939 | } |
| 1940 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1941 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1942 | bool bChannelChange) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1943 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1944 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1945 | u32 saveLedState; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1946 | struct ath9k_channel *curchan = ah->curchan; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1947 | u32 saveDefAntenna; |
| 1948 | u32 macStaId1; |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1949 | u64 tsf = 0; |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1950 | int i, rx_chainmask, r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1951 | |
Luis R. Rodriguez | 43c2761 | 2009-09-13 21:07:07 -0700 | [diff] [blame] | 1952 | ah->txchainmask = common->tx_chainmask; |
| 1953 | ah->rxchainmask = common->rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1954 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1955 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1956 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1957 | |
Vasanthakumar Thiagarajan | 9ebef799 | 2009-09-17 09:26:44 +0530 | [diff] [blame] | 1958 | if (curchan && !ah->chip_fullsleep) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1959 | ath9k_hw_getnf(ah, curchan); |
| 1960 | |
| 1961 | if (bChannelChange && |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1962 | (ah->chip_fullsleep != true) && |
| 1963 | (ah->curchan != NULL) && |
| 1964 | (chan->channel != ah->curchan->channel) && |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1965 | ((chan->channelFlags & CHANNEL_ALL) == |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1966 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
Vasanthakumar Thiagarajan | 0a475cc | 2009-09-17 09:27:10 +0530 | [diff] [blame] | 1967 | !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || |
| 1968 | IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1969 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1970 | if (ath9k_hw_channel_change(ah, chan)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1971 | ath9k_hw_loadnf(ah, ah->curchan); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1972 | ath9k_hw_start_nfcal(ah); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1973 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1974 | } |
| 1975 | } |
| 1976 | |
| 1977 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
| 1978 | if (saveDefAntenna == 0) |
| 1979 | saveDefAntenna = 1; |
| 1980 | |
| 1981 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; |
| 1982 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1983 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
| 1984 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
| 1985 | tsf = ath9k_hw_gettsf64(ah); |
| 1986 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1987 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
| 1988 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | |
| 1989 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); |
| 1990 | |
| 1991 | ath9k_hw_mark_phy_inactive(ah); |
| 1992 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1993 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1994 | REG_WRITE(ah, |
| 1995 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1996 | AR9271_RADIO_RF_RST); |
| 1997 | udelay(50); |
| 1998 | } |
| 1999 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2000 | if (!ath9k_hw_chip_reset(ah, chan)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2001 | ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 2002 | return -EINVAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2003 | } |
| 2004 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2005 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 2006 | ah->htc_reset_init = false; |
| 2007 | REG_WRITE(ah, |
| 2008 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 2009 | AR9271_GATE_MAC_CTL); |
| 2010 | udelay(50); |
| 2011 | } |
| 2012 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 2013 | /* Restore TSF */ |
| 2014 | if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
| 2015 | ath9k_hw_settsf64(ah, tsf); |
| 2016 | |
Vasanthakumar Thiagarajan | 369391d | 2009-01-21 19:24:13 +0530 | [diff] [blame] | 2017 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 2018 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2019 | |
Vivek Natarajan | 326bebb | 2009-08-14 11:33:36 +0530 | [diff] [blame] | 2020 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 2021 | /* Enable ASYNC FIFO */ |
| 2022 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 2023 | AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); |
| 2024 | REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); |
| 2025 | REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 2026 | AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
| 2027 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 2028 | AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
| 2029 | } |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2030 | r = ath9k_hw_process_ini(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 2031 | if (r) |
| 2032 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2033 | |
Jouni Malinen | 0ced0e1 | 2009-01-08 13:32:13 +0200 | [diff] [blame] | 2034 | /* Setup MFP options for CCMP */ |
| 2035 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 2036 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt |
| 2037 | * frames when constructing CCMP AAD. */ |
| 2038 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, |
| 2039 | 0xc7ff); |
| 2040 | ah->sw_mgmt_crypto = false; |
| 2041 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 2042 | /* Disable hardware crypto for management frames */ |
| 2043 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, |
| 2044 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); |
| 2045 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 2046 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); |
| 2047 | ah->sw_mgmt_crypto = true; |
| 2048 | } else |
| 2049 | ah->sw_mgmt_crypto = true; |
| 2050 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2051 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 2052 | ath9k_hw_set_delta_slope(ah, chan); |
| 2053 | |
Luis R. Rodriguez | ae478cf | 2009-10-19 02:33:43 -0400 | [diff] [blame] | 2054 | ah->ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | d650915 | 2009-03-13 08:56:05 +0530 | [diff] [blame] | 2055 | ah->eep_ops->set_board_values(ah, chan); |
Luis R. Rodriguez | a776582 | 2009-10-19 02:33:45 -0400 | [diff] [blame] | 2056 | |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 2057 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
| 2058 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2059 | | macStaId1 |
| 2060 | | AR_STA_ID1_RTS_USE_DEF |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2061 | | (ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2062 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2063 | | ah->sta_id1_defaults); |
| 2064 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2065 | |
Luis R. Rodriguez | 13b8155 | 2009-09-10 17:52:45 -0700 | [diff] [blame] | 2066 | ath_hw_setbssidmask(common); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2067 | |
| 2068 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
| 2069 | |
Luis R. Rodriguez | 3453ad8 | 2009-09-10 08:57:00 -0700 | [diff] [blame] | 2070 | ath9k_hw_write_associd(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2071 | |
| 2072 | REG_WRITE(ah, AR_ISR, ~0); |
| 2073 | |
| 2074 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
| 2075 | |
Luis R. Rodriguez | e68a060 | 2009-10-19 02:33:41 -0400 | [diff] [blame] | 2076 | r = ah->ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 2077 | if (r) |
| 2078 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2079 | |
| 2080 | for (i = 0; i < AR_NUM_DCU; i++) |
| 2081 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); |
| 2082 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2083 | ah->intr_txqs = 0; |
| 2084 | for (i = 0; i < ah->caps.total_queues; i++) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2085 | ath9k_hw_resettxqueue(ah, i); |
| 2086 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2087 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2088 | ath9k_hw_init_qos(ah); |
| 2089 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2090 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
Vasanthakumar Thiagarajan | 500c064 | 2008-09-10 18:50:17 +0530 | [diff] [blame] | 2091 | ath9k_enable_rfkill(ah); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 2092 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2093 | ath9k_hw_init_user_settings(ah); |
| 2094 | |
Vivek Natarajan | 326bebb | 2009-08-14 11:33:36 +0530 | [diff] [blame] | 2095 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 2096 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, |
| 2097 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); |
| 2098 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, |
| 2099 | AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); |
| 2100 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, |
| 2101 | AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); |
| 2102 | |
| 2103 | REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); |
| 2104 | REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); |
| 2105 | |
| 2106 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, |
| 2107 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); |
| 2108 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, |
| 2109 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); |
| 2110 | } |
Vivek Natarajan | 326bebb | 2009-08-14 11:33:36 +0530 | [diff] [blame] | 2111 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 2112 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 2113 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); |
| 2114 | } |
| 2115 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2116 | REG_WRITE(ah, AR_STA_ID1, |
| 2117 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); |
| 2118 | |
| 2119 | ath9k_hw_set_dma(ah); |
| 2120 | |
| 2121 | REG_WRITE(ah, AR_OBS, 8); |
| 2122 | |
Sujith | 0ef1f16 | 2009-03-30 15:28:35 +0530 | [diff] [blame] | 2123 | if (ah->config.intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2124 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
| 2125 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); |
| 2126 | } |
| 2127 | |
| 2128 | ath9k_hw_init_bb(ah, chan); |
| 2129 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 2130 | if (!ath9k_hw_init_cal(ah, chan)) |
Joe Perches | 6badaaf | 2009-06-28 09:26:32 -0700 | [diff] [blame] | 2131 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2132 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2133 | rx_chainmask = ah->rxchainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2134 | if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { |
| 2135 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); |
| 2136 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); |
| 2137 | } |
| 2138 | |
| 2139 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
| 2140 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2141 | /* |
| 2142 | * For big endian systems turn on swapping for descriptors |
| 2143 | */ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2144 | if (AR_SREV_9100(ah)) { |
| 2145 | u32 mask; |
| 2146 | mask = REG_READ(ah, AR_CFG); |
| 2147 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2148 | ath_print(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 2149 | "CFG Byte Swap Set 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2150 | } else { |
| 2151 | mask = |
| 2152 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
| 2153 | REG_WRITE(ah, AR_CFG, mask); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2154 | ath_print(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 2155 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2156 | } |
| 2157 | } else { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2158 | /* Configure AR9271 target WLAN */ |
| 2159 | if (AR_SREV_9271(ah)) |
| 2160 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2161 | #ifdef __BIG_ENDIAN |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2162 | else |
| 2163 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2164 | #endif |
| 2165 | } |
| 2166 | |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2167 | if (ah->btcoex_hw.enabled) |
Vasanthakumar Thiagarajan | 42cc41e | 2009-08-26 21:08:45 +0530 | [diff] [blame] | 2168 | ath9k_hw_btcoex_enable(ah); |
| 2169 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 2170 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2171 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2172 | EXPORT_SYMBOL(ath9k_hw_reset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2173 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2174 | /************************/ |
| 2175 | /* Key Cache Management */ |
| 2176 | /************************/ |
| 2177 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2178 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2179 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2180 | u32 keyType; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2181 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2182 | if (entry >= ah->caps.keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2183 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 2184 | "keychache entry %u out of range\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2185 | return false; |
| 2186 | } |
| 2187 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2188 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2189 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2190 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
| 2191 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); |
| 2192 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); |
| 2193 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); |
| 2194 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); |
| 2195 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); |
| 2196 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); |
| 2197 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); |
| 2198 | |
| 2199 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
| 2200 | u16 micentry = entry + 64; |
| 2201 | |
| 2202 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
| 2203 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); |
| 2204 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); |
| 2205 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); |
| 2206 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2207 | } |
| 2208 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2209 | return true; |
| 2210 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2211 | EXPORT_SYMBOL(ath9k_hw_keyreset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2212 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2213 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2214 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2215 | u32 macHi, macLo; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2216 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2217 | if (entry >= ah->caps.keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2218 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 2219 | "keychache entry %u out of range\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2220 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2221 | } |
| 2222 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2223 | if (mac != NULL) { |
| 2224 | macHi = (mac[5] << 8) | mac[4]; |
| 2225 | macLo = (mac[3] << 24) | |
| 2226 | (mac[2] << 16) | |
| 2227 | (mac[1] << 8) | |
| 2228 | mac[0]; |
| 2229 | macLo >>= 1; |
| 2230 | macLo |= (macHi & 1) << 31; |
| 2231 | macHi >>= 1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2232 | } else { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2233 | macLo = macHi = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2234 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2235 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
| 2236 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2237 | |
| 2238 | return true; |
| 2239 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2240 | EXPORT_SYMBOL(ath9k_hw_keysetmac); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2241 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2242 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2243 | const struct ath9k_keyval *k, |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 2244 | const u8 *mac) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2245 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2246 | const struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2247 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2248 | u32 key0, key1, key2, key3, key4; |
| 2249 | u32 keyType; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2250 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2251 | if (entry >= pCap->keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2252 | ath_print(common, ATH_DBG_FATAL, |
| 2253 | "keycache entry %u out of range\n", entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2254 | return false; |
| 2255 | } |
| 2256 | |
| 2257 | switch (k->kv_type) { |
| 2258 | case ATH9K_CIPHER_AES_OCB: |
| 2259 | keyType = AR_KEYTABLE_TYPE_AES; |
| 2260 | break; |
| 2261 | case ATH9K_CIPHER_AES_CCM: |
| 2262 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2263 | ath_print(common, ATH_DBG_ANY, |
| 2264 | "AES-CCM not supported by mac rev 0x%x\n", |
| 2265 | ah->hw_version.macRev); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2266 | return false; |
| 2267 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2268 | keyType = AR_KEYTABLE_TYPE_CCM; |
| 2269 | break; |
| 2270 | case ATH9K_CIPHER_TKIP: |
| 2271 | keyType = AR_KEYTABLE_TYPE_TKIP; |
| 2272 | if (ATH9K_IS_MIC_ENABLED(ah) |
| 2273 | && entry + 64 >= pCap->keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2274 | ath_print(common, ATH_DBG_ANY, |
| 2275 | "entry %u inappropriate for TKIP\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2276 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2277 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2278 | break; |
| 2279 | case ATH9K_CIPHER_WEP: |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 2280 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2281 | ath_print(common, ATH_DBG_ANY, |
| 2282 | "WEP key length %u too small\n", k->kv_len); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2283 | return false; |
| 2284 | } |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 2285 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2286 | keyType = AR_KEYTABLE_TYPE_40; |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 2287 | else if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2288 | keyType = AR_KEYTABLE_TYPE_104; |
| 2289 | else |
| 2290 | keyType = AR_KEYTABLE_TYPE_128; |
| 2291 | break; |
| 2292 | case ATH9K_CIPHER_CLR: |
| 2293 | keyType = AR_KEYTABLE_TYPE_CLR; |
| 2294 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2295 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2296 | ath_print(common, ATH_DBG_FATAL, |
| 2297 | "cipher %u not supported\n", k->kv_type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2298 | return false; |
| 2299 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2300 | |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 2301 | key0 = get_unaligned_le32(k->kv_val + 0); |
| 2302 | key1 = get_unaligned_le16(k->kv_val + 4); |
| 2303 | key2 = get_unaligned_le32(k->kv_val + 6); |
| 2304 | key3 = get_unaligned_le16(k->kv_val + 10); |
| 2305 | key4 = get_unaligned_le32(k->kv_val + 12); |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 2306 | if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2307 | key4 &= 0xff; |
| 2308 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2309 | /* |
| 2310 | * Note: Key cache registers access special memory area that requires |
| 2311 | * two 32-bit writes to actually update the values in the internal |
| 2312 | * memory. Consequently, the exact order and pairs used here must be |
| 2313 | * maintained. |
| 2314 | */ |
| 2315 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2316 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
| 2317 | u16 micentry = entry + 64; |
| 2318 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2319 | /* |
| 2320 | * Write inverted key[47:0] first to avoid Michael MIC errors |
| 2321 | * on frames that could be sent or received at the same time. |
| 2322 | * The correct key will be written in the end once everything |
| 2323 | * else is ready. |
| 2324 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2325 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
| 2326 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2327 | |
| 2328 | /* Write key[95:48] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2329 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
| 2330 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2331 | |
| 2332 | /* Write key[127:96] and key type */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2333 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
| 2334 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2335 | |
| 2336 | /* Write MAC address for the entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2337 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
| 2338 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2339 | if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2340 | /* |
| 2341 | * TKIP uses two key cache entries: |
| 2342 | * Michael MIC TX/RX keys in the same key cache entry |
| 2343 | * (idx = main index + 64): |
| 2344 | * key0 [31:0] = RX key [31:0] |
| 2345 | * key1 [15:0] = TX key [31:16] |
| 2346 | * key1 [31:16] = reserved |
| 2347 | * key2 [31:0] = RX key [63:32] |
| 2348 | * key3 [15:0] = TX key [15:0] |
| 2349 | * key3 [31:16] = reserved |
| 2350 | * key4 [31:0] = TX key [63:32] |
| 2351 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2352 | u32 mic0, mic1, mic2, mic3, mic4; |
| 2353 | |
| 2354 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
| 2355 | mic2 = get_unaligned_le32(k->kv_mic + 4); |
| 2356 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; |
| 2357 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; |
| 2358 | mic4 = get_unaligned_le32(k->kv_txmic + 4); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2359 | |
| 2360 | /* Write RX[31:0] and TX[31:16] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2361 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
| 2362 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2363 | |
| 2364 | /* Write RX[63:32] and TX[15:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2365 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
| 2366 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2367 | |
| 2368 | /* Write TX[63:32] and keyType(reserved) */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2369 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); |
| 2370 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), |
| 2371 | AR_KEYTABLE_TYPE_CLR); |
| 2372 | |
| 2373 | } else { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2374 | /* |
| 2375 | * TKIP uses four key cache entries (two for group |
| 2376 | * keys): |
| 2377 | * Michael MIC TX/RX keys are in different key cache |
| 2378 | * entries (idx = main index + 64 for TX and |
| 2379 | * main index + 32 + 96 for RX): |
| 2380 | * key0 [31:0] = TX/RX MIC key [31:0] |
| 2381 | * key1 [31:0] = reserved |
| 2382 | * key2 [31:0] = TX/RX MIC key [63:32] |
| 2383 | * key3 [31:0] = reserved |
| 2384 | * key4 [31:0] = reserved |
| 2385 | * |
| 2386 | * Upper layer code will call this function separately |
| 2387 | * for TX and RX keys when these registers offsets are |
| 2388 | * used. |
| 2389 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2390 | u32 mic0, mic2; |
| 2391 | |
| 2392 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
| 2393 | mic2 = get_unaligned_le32(k->kv_mic + 4); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2394 | |
| 2395 | /* Write MIC key[31:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2396 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
| 2397 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2398 | |
| 2399 | /* Write MIC key[63:32] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2400 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
| 2401 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2402 | |
| 2403 | /* Write TX[63:32] and keyType(reserved) */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2404 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); |
| 2405 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), |
| 2406 | AR_KEYTABLE_TYPE_CLR); |
| 2407 | } |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2408 | |
| 2409 | /* MAC address registers are reserved for the MIC entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2410 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); |
| 2411 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2412 | |
| 2413 | /* |
| 2414 | * Write the correct (un-inverted) key[47:0] last to enable |
| 2415 | * TKIP now that all other registers are set with correct |
| 2416 | * values. |
| 2417 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2418 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
| 2419 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
| 2420 | } else { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2421 | /* Write key[47:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2422 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
| 2423 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2424 | |
| 2425 | /* Write key[95:48] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2426 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
| 2427 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2428 | |
| 2429 | /* Write key[127:96] and key type */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2430 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
| 2431 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
| 2432 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 2433 | /* Write MAC address for the entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2434 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
| 2435 | } |
| 2436 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2437 | return true; |
| 2438 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2439 | EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2440 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2441 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2442 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2443 | if (entry < ah->caps.keycache_size) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2444 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
| 2445 | if (val & AR_KEYTABLE_VALID) |
| 2446 | return true; |
| 2447 | } |
| 2448 | return false; |
| 2449 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2450 | EXPORT_SYMBOL(ath9k_hw_keyisvalid); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2451 | |
| 2452 | /******************************/ |
| 2453 | /* Power Management (Chipset) */ |
| 2454 | /******************************/ |
| 2455 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2456 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2457 | { |
| 2458 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 2459 | if (setChip) { |
| 2460 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2461 | AR_RTC_FORCE_WAKE_EN); |
| 2462 | if (!AR_SREV_9100(ah)) |
| 2463 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 2464 | |
Sujith | 4921be8 | 2009-09-18 15:04:27 +0530 | [diff] [blame] | 2465 | if(!AR_SREV_5416(ah)) |
| 2466 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
| 2467 | AR_RTC_RESET_EN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2468 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2469 | } |
| 2470 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2471 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2472 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2473 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 2474 | if (setChip) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2475 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2476 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2477 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
| 2478 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 2479 | AR_RTC_FORCE_WAKE_ON_INT); |
| 2480 | } else { |
| 2481 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2482 | AR_RTC_FORCE_WAKE_EN); |
| 2483 | } |
| 2484 | } |
| 2485 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2486 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2487 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2488 | { |
| 2489 | u32 val; |
| 2490 | int i; |
| 2491 | |
| 2492 | if (setChip) { |
| 2493 | if ((REG_READ(ah, AR_RTC_STATUS) & |
| 2494 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { |
| 2495 | if (ath9k_hw_set_reset_reg(ah, |
| 2496 | ATH9K_RESET_POWER_ON) != true) { |
| 2497 | return false; |
| 2498 | } |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2499 | ath9k_hw_init_pll(ah, NULL); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2500 | } |
| 2501 | if (AR_SREV_9100(ah)) |
| 2502 | REG_SET_BIT(ah, AR_RTC_RESET, |
| 2503 | AR_RTC_RESET_EN); |
| 2504 | |
| 2505 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2506 | AR_RTC_FORCE_WAKE_EN); |
| 2507 | udelay(50); |
| 2508 | |
| 2509 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
| 2510 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; |
| 2511 | if (val == AR_RTC_STATUS_ON) |
| 2512 | break; |
| 2513 | udelay(50); |
| 2514 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2515 | AR_RTC_FORCE_WAKE_EN); |
| 2516 | } |
| 2517 | if (i == 0) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2518 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 2519 | "Failed to wakeup in %uus\n", |
| 2520 | POWER_UP_TIME / 20); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2521 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2522 | } |
| 2523 | } |
| 2524 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2525 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 2526 | |
| 2527 | return true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2528 | } |
| 2529 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 2530 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2531 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2532 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2533 | int status = true, setChip = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2534 | static const char *modes[] = { |
| 2535 | "AWAKE", |
| 2536 | "FULL-SLEEP", |
| 2537 | "NETWORK SLEEP", |
| 2538 | "UNDEFINED" |
| 2539 | }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2540 | |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 2541 | if (ah->power_mode == mode) |
| 2542 | return status; |
| 2543 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2544 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", |
| 2545 | modes[ah->power_mode], modes[mode]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2546 | |
| 2547 | switch (mode) { |
| 2548 | case ATH9K_PM_AWAKE: |
| 2549 | status = ath9k_hw_set_power_awake(ah, setChip); |
| 2550 | break; |
| 2551 | case ATH9K_PM_FULL_SLEEP: |
| 2552 | ath9k_set_power_sleep(ah, setChip); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2553 | ah->chip_fullsleep = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2554 | break; |
| 2555 | case ATH9K_PM_NETWORK_SLEEP: |
| 2556 | ath9k_set_power_network_sleep(ah, setChip); |
| 2557 | break; |
| 2558 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2559 | ath_print(common, ATH_DBG_FATAL, |
| 2560 | "Unknown power mode %u\n", mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2561 | return false; |
| 2562 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2563 | ah->power_mode = mode; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2564 | |
| 2565 | return status; |
| 2566 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2567 | EXPORT_SYMBOL(ath9k_hw_setpower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2568 | |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2569 | /* |
| 2570 | * Helper for ASPM support. |
| 2571 | * |
| 2572 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 2573 | * This power saving option must be enabled through the SerDes. |
| 2574 | * |
| 2575 | * Programming the SerDes must go through the same 288 bit serial shift |
| 2576 | * register as the other analog registers. Hence the 9 writes. |
| 2577 | */ |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2578 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2579 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2580 | u8 i; |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2581 | u32 val; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2582 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2583 | if (ah->is_pciexpress != true) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2584 | return; |
| 2585 | |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2586 | /* Do not touch SerDes registers */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2587 | if (ah->config.pcie_powersave_enable == 2) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2588 | return; |
| 2589 | |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2590 | /* Nothing to do on restore for 11N */ |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2591 | if (!restore) { |
| 2592 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 2593 | /* |
| 2594 | * AR9280 2.0 or later chips use SerDes values from the |
| 2595 | * initvals.h initialized depending on chipset during |
| 2596 | * ath9k_hw_init() |
| 2597 | */ |
| 2598 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
| 2599 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), |
| 2600 | INI_RA(&ah->iniPcieSerdes, i, 1)); |
| 2601 | } |
| 2602 | } else if (AR_SREV_9280(ah) && |
| 2603 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { |
| 2604 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); |
| 2605 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2606 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2607 | /* RX shut off when elecidle is asserted */ |
| 2608 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); |
| 2609 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); |
| 2610 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); |
| 2611 | |
| 2612 | /* Shut off CLKREQ active in L1 */ |
| 2613 | if (ah->config.pcie_clock_req) |
| 2614 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); |
| 2615 | else |
| 2616 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); |
| 2617 | |
| 2618 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 2619 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 2620 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); |
| 2621 | |
| 2622 | /* Load the new settings */ |
| 2623 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 2624 | |
| 2625 | } else { |
| 2626 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 2627 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 2628 | |
| 2629 | /* RX shut off when elecidle is asserted */ |
| 2630 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
| 2631 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); |
| 2632 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); |
| 2633 | |
| 2634 | /* |
| 2635 | * Ignore ah->ah_config.pcie_clock_req setting for |
| 2636 | * pre-AR9280 11n |
| 2637 | */ |
| 2638 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); |
| 2639 | |
| 2640 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 2641 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 2642 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); |
| 2643 | |
| 2644 | /* Load the new settings */ |
| 2645 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2646 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2647 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2648 | udelay(1000); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2649 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2650 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 2651 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2652 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2653 | /* Several PCIe massages to ensure proper behaviour */ |
| 2654 | if (ah->config.pcie_waen) { |
| 2655 | val = ah->config.pcie_waen; |
| 2656 | if (!power_off) |
| 2657 | val &= (~AR_WA_D3_L1_DISABLE); |
| 2658 | } else { |
| 2659 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || |
| 2660 | AR_SREV_9287(ah)) { |
| 2661 | val = AR9285_WA_DEFAULT; |
| 2662 | if (!power_off) |
| 2663 | val &= (~AR_WA_D3_L1_DISABLE); |
| 2664 | } else if (AR_SREV_9280(ah)) { |
| 2665 | /* |
| 2666 | * On AR9280 chips bit 22 of 0x4004 needs to be |
| 2667 | * set otherwise card may disappear. |
| 2668 | */ |
| 2669 | val = AR9280_WA_DEFAULT; |
| 2670 | if (!power_off) |
| 2671 | val &= (~AR_WA_D3_L1_DISABLE); |
| 2672 | } else |
| 2673 | val = AR_WA_DEFAULT; |
| 2674 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2675 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2676 | REG_WRITE(ah, AR_WA, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2677 | } |
| 2678 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2679 | if (power_off) { |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2680 | /* |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2681 | * Set PCIe workaround bits |
| 2682 | * bit 14 in WA register (disable L1) should only |
| 2683 | * be set when device enters D3 and be cleared |
| 2684 | * when device comes back to D0. |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2685 | */ |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2686 | if (ah->config.pcie_waen) { |
| 2687 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) |
| 2688 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); |
| 2689 | } else { |
| 2690 | if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || |
| 2691 | AR_SREV_9287(ah)) && |
| 2692 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || |
| 2693 | (AR_SREV_9280(ah) && |
| 2694 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { |
| 2695 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); |
| 2696 | } |
| 2697 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2698 | } |
| 2699 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2700 | EXPORT_SYMBOL(ath9k_hw_configpcipowersave); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2701 | |
| 2702 | /**********************/ |
| 2703 | /* Interrupt Handling */ |
| 2704 | /**********************/ |
| 2705 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2706 | bool ath9k_hw_intrpend(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2707 | { |
| 2708 | u32 host_isr; |
| 2709 | |
| 2710 | if (AR_SREV_9100(ah)) |
| 2711 | return true; |
| 2712 | |
| 2713 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); |
| 2714 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) |
| 2715 | return true; |
| 2716 | |
| 2717 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 2718 | if ((host_isr & AR_INTR_SYNC_DEFAULT) |
| 2719 | && (host_isr != AR_INTR_SPURIOUS)) |
| 2720 | return true; |
| 2721 | |
| 2722 | return false; |
| 2723 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2724 | EXPORT_SYMBOL(ath9k_hw_intrpend); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2725 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2726 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2727 | { |
| 2728 | u32 isr = 0; |
| 2729 | u32 mask2 = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2730 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2731 | u32 sync_cause = 0; |
| 2732 | bool fatal_int = false; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2733 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2734 | |
| 2735 | if (!AR_SREV_9100(ah)) { |
| 2736 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { |
| 2737 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) |
| 2738 | == AR_RTC_STATUS_ON) { |
| 2739 | isr = REG_READ(ah, AR_ISR); |
| 2740 | } |
| 2741 | } |
| 2742 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2743 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & |
| 2744 | AR_INTR_SYNC_DEFAULT; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2745 | |
| 2746 | *masked = 0; |
| 2747 | |
| 2748 | if (!isr && !sync_cause) |
| 2749 | return false; |
| 2750 | } else { |
| 2751 | *masked = 0; |
| 2752 | isr = REG_READ(ah, AR_ISR); |
| 2753 | } |
| 2754 | |
| 2755 | if (isr) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2756 | if (isr & AR_ISR_BCNMISC) { |
| 2757 | u32 isr2; |
| 2758 | isr2 = REG_READ(ah, AR_ISR_S2); |
| 2759 | if (isr2 & AR_ISR_S2_TIM) |
| 2760 | mask2 |= ATH9K_INT_TIM; |
| 2761 | if (isr2 & AR_ISR_S2_DTIM) |
| 2762 | mask2 |= ATH9K_INT_DTIM; |
| 2763 | if (isr2 & AR_ISR_S2_DTIMSYNC) |
| 2764 | mask2 |= ATH9K_INT_DTIMSYNC; |
| 2765 | if (isr2 & (AR_ISR_S2_CABEND)) |
| 2766 | mask2 |= ATH9K_INT_CABEND; |
| 2767 | if (isr2 & AR_ISR_S2_GTT) |
| 2768 | mask2 |= ATH9K_INT_GTT; |
| 2769 | if (isr2 & AR_ISR_S2_CST) |
| 2770 | mask2 |= ATH9K_INT_CST; |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 2771 | if (isr2 & AR_ISR_S2_TSFOOR) |
| 2772 | mask2 |= ATH9K_INT_TSFOOR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2773 | } |
| 2774 | |
| 2775 | isr = REG_READ(ah, AR_ISR_RAC); |
| 2776 | if (isr == 0xffffffff) { |
| 2777 | *masked = 0; |
| 2778 | return false; |
| 2779 | } |
| 2780 | |
| 2781 | *masked = isr & ATH9K_INT_COMMON; |
| 2782 | |
Sujith | 0ef1f16 | 2009-03-30 15:28:35 +0530 | [diff] [blame] | 2783 | if (ah->config.intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2784 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
| 2785 | *masked |= ATH9K_INT_RX; |
| 2786 | } |
| 2787 | |
| 2788 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) |
| 2789 | *masked |= ATH9K_INT_RX; |
| 2790 | if (isr & |
| 2791 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | |
| 2792 | AR_ISR_TXEOL)) { |
| 2793 | u32 s0_s, s1_s; |
| 2794 | |
| 2795 | *masked |= ATH9K_INT_TX; |
| 2796 | |
| 2797 | s0_s = REG_READ(ah, AR_ISR_S0_S); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2798 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); |
| 2799 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2800 | |
| 2801 | s1_s = REG_READ(ah, AR_ISR_S1_S); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2802 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); |
| 2803 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2804 | } |
| 2805 | |
| 2806 | if (isr & AR_ISR_RXORN) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2807 | ath_print(common, ATH_DBG_INTERRUPT, |
| 2808 | "receive FIFO overrun interrupt\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2809 | } |
| 2810 | |
| 2811 | if (!AR_SREV_9100(ah)) { |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2812 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2813 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); |
| 2814 | if (isr5 & AR_ISR_S5_TIM_TIMER) |
| 2815 | *masked |= ATH9K_INT_TIM_TIMER; |
| 2816 | } |
| 2817 | } |
| 2818 | |
| 2819 | *masked |= mask2; |
| 2820 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2821 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2822 | if (AR_SREV_9100(ah)) |
| 2823 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2824 | |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2825 | if (isr & AR_ISR_GENTMR) { |
| 2826 | u32 s5_s; |
| 2827 | |
| 2828 | s5_s = REG_READ(ah, AR_ISR_S5_S); |
| 2829 | if (isr & AR_ISR_GENTMR) { |
| 2830 | ah->intr_gen_timer_trigger = |
| 2831 | MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); |
| 2832 | |
| 2833 | ah->intr_gen_timer_thresh = |
| 2834 | MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); |
| 2835 | |
| 2836 | if (ah->intr_gen_timer_trigger) |
| 2837 | *masked |= ATH9K_INT_GENTIMER; |
| 2838 | |
| 2839 | } |
| 2840 | } |
| 2841 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2842 | if (sync_cause) { |
| 2843 | fatal_int = |
| 2844 | (sync_cause & |
| 2845 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) |
| 2846 | ? true : false; |
| 2847 | |
| 2848 | if (fatal_int) { |
| 2849 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2850 | ath_print(common, ATH_DBG_ANY, |
| 2851 | "received PCI FATAL interrupt\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2852 | } |
| 2853 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2854 | ath_print(common, ATH_DBG_ANY, |
| 2855 | "received PCI PERR interrupt\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2856 | } |
Steven Luo | a89bff9 | 2009-04-12 02:57:54 -0700 | [diff] [blame] | 2857 | *masked |= ATH9K_INT_FATAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2858 | } |
| 2859 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2860 | ath_print(common, ATH_DBG_INTERRUPT, |
| 2861 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2862 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
| 2863 | REG_WRITE(ah, AR_RC, 0); |
| 2864 | *masked |= ATH9K_INT_FATAL; |
| 2865 | } |
| 2866 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2867 | ath_print(common, ATH_DBG_INTERRUPT, |
| 2868 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2869 | } |
| 2870 | |
| 2871 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); |
| 2872 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); |
| 2873 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2874 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2875 | return true; |
| 2876 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2877 | EXPORT_SYMBOL(ath9k_hw_getisr); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2878 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2879 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2880 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2881 | u32 omask = ah->mask_reg; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2882 | u32 mask, mask2; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2883 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2884 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2885 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2886 | ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2887 | |
| 2888 | if (omask & ATH9K_INT_GLOBAL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2889 | ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2890 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
| 2891 | (void) REG_READ(ah, AR_IER); |
| 2892 | if (!AR_SREV_9100(ah)) { |
| 2893 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); |
| 2894 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); |
| 2895 | |
| 2896 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
| 2897 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); |
| 2898 | } |
| 2899 | } |
| 2900 | |
| 2901 | mask = ints & ATH9K_INT_COMMON; |
| 2902 | mask2 = 0; |
| 2903 | |
| 2904 | if (ints & ATH9K_INT_TX) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2905 | if (ah->txok_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2906 | mask |= AR_IMR_TXOK; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2907 | if (ah->txdesc_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2908 | mask |= AR_IMR_TXDESC; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2909 | if (ah->txerr_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2910 | mask |= AR_IMR_TXERR; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2911 | if (ah->txeol_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2912 | mask |= AR_IMR_TXEOL; |
| 2913 | } |
| 2914 | if (ints & ATH9K_INT_RX) { |
| 2915 | mask |= AR_IMR_RXERR; |
Sujith | 0ef1f16 | 2009-03-30 15:28:35 +0530 | [diff] [blame] | 2916 | if (ah->config.intr_mitigation) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2917 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
| 2918 | else |
| 2919 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2920 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2921 | mask |= AR_IMR_GENTMR; |
| 2922 | } |
| 2923 | |
| 2924 | if (ints & (ATH9K_INT_BMISC)) { |
| 2925 | mask |= AR_IMR_BCNMISC; |
| 2926 | if (ints & ATH9K_INT_TIM) |
| 2927 | mask2 |= AR_IMR_S2_TIM; |
| 2928 | if (ints & ATH9K_INT_DTIM) |
| 2929 | mask2 |= AR_IMR_S2_DTIM; |
| 2930 | if (ints & ATH9K_INT_DTIMSYNC) |
| 2931 | mask2 |= AR_IMR_S2_DTIMSYNC; |
| 2932 | if (ints & ATH9K_INT_CABEND) |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 2933 | mask2 |= AR_IMR_S2_CABEND; |
| 2934 | if (ints & ATH9K_INT_TSFOOR) |
| 2935 | mask2 |= AR_IMR_S2_TSFOOR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2936 | } |
| 2937 | |
| 2938 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { |
| 2939 | mask |= AR_IMR_BCNMISC; |
| 2940 | if (ints & ATH9K_INT_GTT) |
| 2941 | mask2 |= AR_IMR_S2_GTT; |
| 2942 | if (ints & ATH9K_INT_CST) |
| 2943 | mask2 |= AR_IMR_S2_CST; |
| 2944 | } |
| 2945 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2946 | ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2947 | REG_WRITE(ah, AR_IMR, mask); |
| 2948 | mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | |
| 2949 | AR_IMR_S2_DTIM | |
| 2950 | AR_IMR_S2_DTIMSYNC | |
| 2951 | AR_IMR_S2_CABEND | |
| 2952 | AR_IMR_S2_CABTO | |
| 2953 | AR_IMR_S2_TSFOOR | |
| 2954 | AR_IMR_S2_GTT | AR_IMR_S2_CST); |
| 2955 | REG_WRITE(ah, AR_IMR_S2, mask | mask2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2956 | ah->mask_reg = ints; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2957 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2958 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2959 | if (ints & ATH9K_INT_TIM_TIMER) |
| 2960 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
| 2961 | else |
| 2962 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
| 2963 | } |
| 2964 | |
| 2965 | if (ints & ATH9K_INT_GLOBAL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2966 | ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2967 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
| 2968 | if (!AR_SREV_9100(ah)) { |
| 2969 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, |
| 2970 | AR_INTR_MAC_IRQ); |
| 2971 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); |
| 2972 | |
| 2973 | |
| 2974 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, |
| 2975 | AR_INTR_SYNC_DEFAULT); |
| 2976 | REG_WRITE(ah, AR_INTR_SYNC_MASK, |
| 2977 | AR_INTR_SYNC_DEFAULT); |
| 2978 | } |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2979 | ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
| 2980 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2981 | } |
| 2982 | |
| 2983 | return omask; |
| 2984 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2985 | EXPORT_SYMBOL(ath9k_hw_set_interrupts); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2986 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2987 | /*******************/ |
| 2988 | /* Beacon Handling */ |
| 2989 | /*******************/ |
| 2990 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2991 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2992 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2993 | int flags = 0; |
| 2994 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2995 | ah->beacon_interval = beacon_period; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2996 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2997 | switch (ah->opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 2998 | case NL80211_IFTYPE_STATION: |
| 2999 | case NL80211_IFTYPE_MONITOR: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3000 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 3001 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); |
| 3002 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); |
| 3003 | flags |= AR_TBTT_TIMER_EN; |
| 3004 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 3005 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 3006 | case NL80211_IFTYPE_MESH_POINT: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3007 | REG_SET_BIT(ah, AR_TXCFG, |
| 3008 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); |
| 3009 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, |
| 3010 | TU_TO_USEC(next_beacon + |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3011 | (ah->atim_window ? ah-> |
| 3012 | atim_window : 1))); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3013 | flags |= AR_NDP_TIMER_EN; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 3014 | case NL80211_IFTYPE_AP: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3015 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 3016 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, |
| 3017 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3018 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 3019 | dma_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3020 | REG_WRITE(ah, AR_NEXT_SWBA, |
| 3021 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3022 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 3023 | sw_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3024 | flags |= |
| 3025 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; |
| 3026 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 3027 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3028 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, |
| 3029 | "%s: unsupported opmode: %d\n", |
| 3030 | __func__, ah->opmode); |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 3031 | return; |
| 3032 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3033 | } |
| 3034 | |
| 3035 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 3036 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 3037 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); |
| 3038 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); |
| 3039 | |
| 3040 | beacon_period &= ~ATH9K_BEACON_ENA; |
| 3041 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3042 | ath9k_hw_reset_tsf(ah); |
| 3043 | } |
| 3044 | |
| 3045 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
| 3046 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3047 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3048 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3049 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3050 | const struct ath9k_beacon_state *bs) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3051 | { |
| 3052 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3053 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3054 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3055 | |
| 3056 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
| 3057 | |
| 3058 | REG_WRITE(ah, AR_BEACON_PERIOD, |
| 3059 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 3060 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, |
| 3061 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 3062 | |
| 3063 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
| 3064 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); |
| 3065 | |
| 3066 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; |
| 3067 | |
| 3068 | if (bs->bs_sleepduration > beaconintval) |
| 3069 | beaconintval = bs->bs_sleepduration; |
| 3070 | |
| 3071 | dtimperiod = bs->bs_dtimperiod; |
| 3072 | if (bs->bs_sleepduration > dtimperiod) |
| 3073 | dtimperiod = bs->bs_sleepduration; |
| 3074 | |
| 3075 | if (beaconintval == dtimperiod) |
| 3076 | nextTbtt = bs->bs_nextdtim; |
| 3077 | else |
| 3078 | nextTbtt = bs->bs_nexttbtt; |
| 3079 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3080 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
| 3081 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); |
| 3082 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); |
| 3083 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3084 | |
| 3085 | REG_WRITE(ah, AR_NEXT_DTIM, |
| 3086 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); |
| 3087 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); |
| 3088 | |
| 3089 | REG_WRITE(ah, AR_SLEEP1, |
| 3090 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) |
| 3091 | | AR_SLEEP1_ASSUME_DTIM); |
| 3092 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 3093 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3094 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); |
| 3095 | else |
| 3096 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; |
| 3097 | |
| 3098 | REG_WRITE(ah, AR_SLEEP2, |
| 3099 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); |
| 3100 | |
| 3101 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
| 3102 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); |
| 3103 | |
| 3104 | REG_SET_BIT(ah, AR_TIMER_MODE, |
| 3105 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | |
| 3106 | AR_DTIM_TIMER_EN); |
| 3107 | |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 3108 | /* TSF Out of Range Threshold */ |
| 3109 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3110 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3111 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3112 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3113 | /*******************/ |
| 3114 | /* HW Capabilities */ |
| 3115 | /*******************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3116 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 3117 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3118 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3119 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3120 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3121 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 3122 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3123 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3124 | u16 capField = 0, eeval; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3125 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3126 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3127 | regulatory->current_rd = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3128 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3129 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
Sujith | fec0de1 | 2009-02-12 10:06:43 +0530 | [diff] [blame] | 3130 | if (AR_SREV_9285_10_OR_LATER(ah)) |
| 3131 | eeval |= AR9285_RDEXT_DEFAULT; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3132 | regulatory->current_rd_ext = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3133 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3134 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3135 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3136 | if (ah->opmode != NL80211_IFTYPE_AP && |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 3137 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3138 | if (regulatory->current_rd == 0x64 || |
| 3139 | regulatory->current_rd == 0x65) |
| 3140 | regulatory->current_rd += 5; |
| 3141 | else if (regulatory->current_rd == 0x41) |
| 3142 | regulatory->current_rd = 0x43; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3143 | ath_print(common, ATH_DBG_REGULATORY, |
| 3144 | "regdomain mapped to 0x%x\n", regulatory->current_rd); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3145 | } |
Sujith | dc2222a | 2008-08-14 13:26:55 +0530 | [diff] [blame] | 3146 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3147 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 3148 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
| 3149 | ath_print(common, ATH_DBG_FATAL, |
| 3150 | "no band has been marked as supported in EEPROM.\n"); |
| 3151 | return -EINVAL; |
| 3152 | } |
| 3153 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3154 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3155 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3156 | if (eeval & AR5416_OPFLAGS_11A) { |
| 3157 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3158 | if (ah->config.ht_enable) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3159 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) |
| 3160 | set_bit(ATH9K_MODE_11NA_HT20, |
| 3161 | pCap->wireless_modes); |
| 3162 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { |
| 3163 | set_bit(ATH9K_MODE_11NA_HT40PLUS, |
| 3164 | pCap->wireless_modes); |
| 3165 | set_bit(ATH9K_MODE_11NA_HT40MINUS, |
| 3166 | pCap->wireless_modes); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3167 | } |
| 3168 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3169 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3170 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3171 | if (eeval & AR5416_OPFLAGS_11G) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3172 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3173 | if (ah->config.ht_enable) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3174 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) |
| 3175 | set_bit(ATH9K_MODE_11NG_HT20, |
| 3176 | pCap->wireless_modes); |
| 3177 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { |
| 3178 | set_bit(ATH9K_MODE_11NG_HT40PLUS, |
| 3179 | pCap->wireless_modes); |
| 3180 | set_bit(ATH9K_MODE_11NG_HT40MINUS, |
| 3181 | pCap->wireless_modes); |
| 3182 | } |
| 3183 | } |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 3184 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3185 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3186 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 3187 | /* |
| 3188 | * For AR9271 we will temporarilly uses the rx chainmax as read from |
| 3189 | * the EEPROM. |
| 3190 | */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 3191 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 3192 | !(eeval & AR5416_OPFLAGS_11A) && |
| 3193 | !(AR_SREV_9271(ah))) |
| 3194 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 3195 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
| 3196 | else |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 3197 | /* Use rx_chainmask from EEPROM. */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 3198 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3199 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 3200 | if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3201 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3202 | |
| 3203 | pCap->low_2ghz_chan = 2312; |
| 3204 | pCap->high_2ghz_chan = 2732; |
| 3205 | |
| 3206 | pCap->low_5ghz_chan = 4920; |
| 3207 | pCap->high_5ghz_chan = 6100; |
| 3208 | |
| 3209 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
| 3210 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; |
| 3211 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; |
| 3212 | |
| 3213 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
| 3214 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; |
| 3215 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; |
| 3216 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3217 | if (ah->config.ht_enable) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3218 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
| 3219 | else |
| 3220 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; |
| 3221 | |
| 3222 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
| 3223 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; |
| 3224 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; |
| 3225 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; |
| 3226 | |
| 3227 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
| 3228 | pCap->total_queues = |
| 3229 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); |
| 3230 | else |
| 3231 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; |
| 3232 | |
| 3233 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
| 3234 | pCap->keycache_size = |
| 3235 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); |
| 3236 | else |
| 3237 | pCap->keycache_size = AR_KEYTABLE_SIZE; |
| 3238 | |
| 3239 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 3240 | |
| 3241 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 3242 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; |
| 3243 | else |
| 3244 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3245 | |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 3246 | if (AR_SREV_9285_10_OR_LATER(ah)) |
| 3247 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
| 3248 | else if (AR_SREV_9280_10_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3249 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
| 3250 | else |
| 3251 | pCap->num_gpio_pins = AR_NUM_GPIO; |
| 3252 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3253 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
| 3254 | pCap->hw_caps |= ATH9K_HW_CAP_CST; |
| 3255 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
| 3256 | } else { |
| 3257 | pCap->rts_aggr_limit = (8 * 1024); |
| 3258 | } |
| 3259 | |
| 3260 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
| 3261 | |
Senthil Balasubramanian | e97275c | 2008-11-13 18:00:02 +0530 | [diff] [blame] | 3262 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3263 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
| 3264 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { |
| 3265 | ah->rfkill_gpio = |
| 3266 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); |
| 3267 | ah->rfkill_polarity = |
| 3268 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3269 | |
| 3270 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; |
| 3271 | } |
| 3272 | #endif |
| 3273 | |
Vivek Natarajan | a3ca95fb | 2009-09-17 09:29:07 +0530 | [diff] [blame] | 3274 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3275 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 3276 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3277 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 3278 | else |
| 3279 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 3280 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3281 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3282 | pCap->reg_cap = |
| 3283 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 3284 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | |
| 3285 | AR_EEPROM_EEREGCAP_EN_KK_U2 | |
| 3286 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; |
| 3287 | } else { |
| 3288 | pCap->reg_cap = |
| 3289 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 3290 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; |
| 3291 | } |
| 3292 | |
Senthil Balasubramanian | ebb90cf | 2009-09-18 15:07:33 +0530 | [diff] [blame] | 3293 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
| 3294 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && |
| 3295 | AR_SREV_5416(ah)) |
| 3296 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3297 | |
| 3298 | pCap->num_antcfg_5ghz = |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3299 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3300 | pCap->num_antcfg_2ghz = |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 3301 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3302 | |
Vasanthakumar Thiagarajan | fe12946 | 2009-09-09 15:25:50 +0530 | [diff] [blame] | 3303 | if (AR_SREV_9280_10_OR_LATER(ah) && |
Luis R. Rodriguez | a36cfbc | 2009-09-09 16:05:32 -0700 | [diff] [blame] | 3304 | ath9k_hw_btcoex_supported(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 3305 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
| 3306 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 3307 | |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 3308 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 3309 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
| 3310 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 3311 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 3312 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 3313 | } |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 3314 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 3315 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
Vasanthakumar Thiagarajan | c97c92d | 2009-01-02 15:35:46 +0530 | [diff] [blame] | 3316 | } |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 3317 | |
| 3318 | return 0; |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 3319 | } |
| 3320 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3321 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3322 | u32 capability, u32 *result) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3323 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3324 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3325 | switch (type) { |
| 3326 | case ATH9K_CAP_CIPHER: |
| 3327 | switch (capability) { |
| 3328 | case ATH9K_CIPHER_AES_CCM: |
| 3329 | case ATH9K_CIPHER_AES_OCB: |
| 3330 | case ATH9K_CIPHER_TKIP: |
| 3331 | case ATH9K_CIPHER_WEP: |
| 3332 | case ATH9K_CIPHER_MIC: |
| 3333 | case ATH9K_CIPHER_CLR: |
| 3334 | return true; |
| 3335 | default: |
| 3336 | return false; |
| 3337 | } |
| 3338 | case ATH9K_CAP_TKIP_MIC: |
| 3339 | switch (capability) { |
| 3340 | case 0: |
| 3341 | return true; |
| 3342 | case 1: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3343 | return (ah->sta_id1_defaults & |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3344 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : |
| 3345 | false; |
| 3346 | } |
| 3347 | case ATH9K_CAP_TKIP_SPLIT: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3348 | return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3349 | false : true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3350 | case ATH9K_CAP_DIVERSITY: |
| 3351 | return (REG_READ(ah, AR_PHY_CCK_DETECT) & |
| 3352 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? |
| 3353 | true : false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3354 | case ATH9K_CAP_MCAST_KEYSRCH: |
| 3355 | switch (capability) { |
| 3356 | case 0: |
| 3357 | return true; |
| 3358 | case 1: |
| 3359 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { |
| 3360 | return false; |
| 3361 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3362 | return (ah->sta_id1_defaults & |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3363 | AR_STA_ID1_MCAST_KSRCH) ? true : |
| 3364 | false; |
| 3365 | } |
| 3366 | } |
| 3367 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3368 | case ATH9K_CAP_TXPOW: |
| 3369 | switch (capability) { |
| 3370 | case 0: |
| 3371 | return 0; |
| 3372 | case 1: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3373 | *result = regulatory->power_limit; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3374 | return 0; |
| 3375 | case 2: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3376 | *result = regulatory->max_power_level; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3377 | return 0; |
| 3378 | case 3: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3379 | *result = regulatory->tp_scale; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3380 | return 0; |
| 3381 | } |
| 3382 | return false; |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 3383 | case ATH9K_CAP_DS: |
| 3384 | return (AR_SREV_9280_20_OR_LATER(ah) && |
| 3385 | (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) |
| 3386 | ? false : true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3387 | default: |
| 3388 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3389 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3390 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3391 | EXPORT_SYMBOL(ath9k_hw_getcapability); |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 3392 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3393 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3394 | u32 capability, u32 setting, int *status) |
| 3395 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3396 | u32 v; |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 3397 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3398 | switch (type) { |
| 3399 | case ATH9K_CAP_TKIP_MIC: |
| 3400 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3401 | ah->sta_id1_defaults |= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3402 | AR_STA_ID1_CRPT_MIC_ENABLE; |
| 3403 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3404 | ah->sta_id1_defaults &= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3405 | ~AR_STA_ID1_CRPT_MIC_ENABLE; |
| 3406 | return true; |
| 3407 | case ATH9K_CAP_DIVERSITY: |
| 3408 | v = REG_READ(ah, AR_PHY_CCK_DETECT); |
| 3409 | if (setting) |
| 3410 | v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; |
| 3411 | else |
| 3412 | v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; |
| 3413 | REG_WRITE(ah, AR_PHY_CCK_DETECT, v); |
| 3414 | return true; |
| 3415 | case ATH9K_CAP_MCAST_KEYSRCH: |
| 3416 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3417 | ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3418 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3419 | ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3420 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3421 | default: |
| 3422 | return false; |
| 3423 | } |
| 3424 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3425 | EXPORT_SYMBOL(ath9k_hw_setcapability); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3426 | |
| 3427 | /****************************/ |
| 3428 | /* GPIO / RFKILL / Antennae */ |
| 3429 | /****************************/ |
| 3430 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3431 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3432 | u32 gpio, u32 type) |
| 3433 | { |
| 3434 | int addr; |
| 3435 | u32 gpio_shift, tmp; |
| 3436 | |
| 3437 | if (gpio > 11) |
| 3438 | addr = AR_GPIO_OUTPUT_MUX3; |
| 3439 | else if (gpio > 5) |
| 3440 | addr = AR_GPIO_OUTPUT_MUX2; |
| 3441 | else |
| 3442 | addr = AR_GPIO_OUTPUT_MUX1; |
| 3443 | |
| 3444 | gpio_shift = (gpio % 6) * 5; |
| 3445 | |
| 3446 | if (AR_SREV_9280_20_OR_LATER(ah) |
| 3447 | || (addr != AR_GPIO_OUTPUT_MUX1)) { |
| 3448 | REG_RMW(ah, addr, (type << gpio_shift), |
| 3449 | (0x1f << gpio_shift)); |
| 3450 | } else { |
| 3451 | tmp = REG_READ(ah, addr); |
| 3452 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); |
| 3453 | tmp &= ~(0x1f << gpio_shift); |
| 3454 | tmp |= (type << gpio_shift); |
| 3455 | REG_WRITE(ah, addr, tmp); |
| 3456 | } |
| 3457 | } |
| 3458 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3459 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3460 | { |
| 3461 | u32 gpio_shift; |
| 3462 | |
Luis R. Rodriguez | 9680e8a | 2009-09-13 23:28:00 -0700 | [diff] [blame] | 3463 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3464 | |
| 3465 | gpio_shift = gpio << 1; |
| 3466 | |
| 3467 | REG_RMW(ah, |
| 3468 | AR_GPIO_OE_OUT, |
| 3469 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), |
| 3470 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 3471 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3472 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3473 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3474 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3475 | { |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 3476 | #define MS_REG_READ(x, y) \ |
| 3477 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) |
| 3478 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3479 | if (gpio >= ah->caps.num_gpio_pins) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3480 | return 0xffffffff; |
| 3481 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 3482 | if (AR_SREV_9287_10_OR_LATER(ah)) |
| 3483 | return MS_REG_READ(AR9287, gpio) != 0; |
| 3484 | else if (AR_SREV_9285_10_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 3485 | return MS_REG_READ(AR9285, gpio) != 0; |
| 3486 | else if (AR_SREV_9280_10_OR_LATER(ah)) |
| 3487 | return MS_REG_READ(AR928X, gpio) != 0; |
| 3488 | else |
| 3489 | return MS_REG_READ(AR, gpio) != 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3490 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3491 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3492 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3493 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3494 | u32 ah_signal_type) |
| 3495 | { |
| 3496 | u32 gpio_shift; |
| 3497 | |
| 3498 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
| 3499 | |
| 3500 | gpio_shift = 2 * gpio; |
| 3501 | |
| 3502 | REG_RMW(ah, |
| 3503 | AR_GPIO_OE_OUT, |
| 3504 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), |
| 3505 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 3506 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3507 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3508 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3509 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3510 | { |
| 3511 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
| 3512 | AR_GPIO_BIT(gpio)); |
| 3513 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3514 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3515 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3516 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3517 | { |
| 3518 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
| 3519 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3520 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3521 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3522 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3523 | { |
| 3524 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
| 3525 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3526 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3527 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3528 | /*********************/ |
| 3529 | /* General Operation */ |
| 3530 | /*********************/ |
| 3531 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3532 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3533 | { |
| 3534 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
| 3535 | u32 phybits = REG_READ(ah, AR_PHY_ERR); |
| 3536 | |
| 3537 | if (phybits & AR_PHY_ERR_RADAR) |
| 3538 | bits |= ATH9K_RX_FILTER_PHYRADAR; |
| 3539 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) |
| 3540 | bits |= ATH9K_RX_FILTER_PHYERR; |
| 3541 | |
| 3542 | return bits; |
| 3543 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3544 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3545 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3546 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3547 | { |
| 3548 | u32 phybits; |
| 3549 | |
Sujith | 7ea310b | 2009-09-03 12:08:43 +0530 | [diff] [blame] | 3550 | REG_WRITE(ah, AR_RX_FILTER, bits); |
| 3551 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3552 | phybits = 0; |
| 3553 | if (bits & ATH9K_RX_FILTER_PHYRADAR) |
| 3554 | phybits |= AR_PHY_ERR_RADAR; |
| 3555 | if (bits & ATH9K_RX_FILTER_PHYERR) |
| 3556 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; |
| 3557 | REG_WRITE(ah, AR_PHY_ERR, phybits); |
| 3558 | |
| 3559 | if (phybits) |
| 3560 | REG_WRITE(ah, AR_RXCFG, |
| 3561 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); |
| 3562 | else |
| 3563 | REG_WRITE(ah, AR_RXCFG, |
| 3564 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); |
| 3565 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3566 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3567 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3568 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3569 | { |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 3570 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
| 3571 | return false; |
| 3572 | |
| 3573 | ath9k_hw_init_pll(ah, NULL); |
| 3574 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3575 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3576 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3577 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3578 | bool ath9k_hw_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3579 | { |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 3580 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3581 | return false; |
| 3582 | |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 3583 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
| 3584 | return false; |
| 3585 | |
| 3586 | ath9k_hw_init_pll(ah, NULL); |
| 3587 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3588 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3589 | EXPORT_SYMBOL(ath9k_hw_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3590 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 3591 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3592 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3593 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3594 | struct ath9k_channel *chan = ah->curchan; |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 3595 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3596 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3597 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3598 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 3599 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3600 | ath9k_regd_get_ctl(regulatory, chan), |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 3601 | channel->max_antenna_gain * 2, |
| 3602 | channel->max_power * 2, |
| 3603 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3604 | (u32) regulatory->power_limit)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3605 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3606 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3607 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3608 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3609 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 3610 | memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3611 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3612 | EXPORT_SYMBOL(ath9k_hw_setmac); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3613 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3614 | void ath9k_hw_setopmode(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3615 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3616 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3617 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3618 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3619 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3620 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3621 | { |
| 3622 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
| 3623 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); |
| 3624 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3625 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3626 | |
Luis R. Rodriguez | f2b2143 | 2009-09-10 08:50:20 -0700 | [diff] [blame] | 3627 | void ath9k_hw_write_associd(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3628 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 3629 | struct ath_common *common = ath9k_hw_common(ah); |
| 3630 | |
| 3631 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); |
| 3632 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | |
| 3633 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3634 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3635 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3636 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3637 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3638 | { |
| 3639 | u64 tsf; |
| 3640 | |
| 3641 | tsf = REG_READ(ah, AR_TSF_U32); |
| 3642 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); |
| 3643 | |
| 3644 | return tsf; |
| 3645 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3646 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3647 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3648 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3649 | { |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3650 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
Alina Friedrichsen | b9a1619 | 2009-03-02 23:28:38 +0100 | [diff] [blame] | 3651 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3652 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3653 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3654 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3655 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3656 | { |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 3657 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
| 3658 | AH_TSF_WRITE_TIMEOUT)) |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3659 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 3660 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 3661 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3662 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3663 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3664 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3665 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 3666 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3667 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3668 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3669 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3670 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3671 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3672 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3673 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3674 | |
Luis R. Rodriguez | 30cbd42 | 2009-11-03 16:10:46 -0800 | [diff] [blame] | 3675 | /* |
| 3676 | * Extend 15-bit time stamp from rx descriptor to |
| 3677 | * a full 64-bit TSF using the current h/w TSF. |
| 3678 | */ |
| 3679 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) |
| 3680 | { |
| 3681 | u64 tsf; |
| 3682 | |
| 3683 | tsf = ath9k_hw_gettsf64(ah); |
| 3684 | if ((tsf & 0x7fff) < rstamp) |
| 3685 | tsf -= 0x8000; |
| 3686 | return (tsf & ~0x7fff) | rstamp; |
| 3687 | } |
| 3688 | EXPORT_SYMBOL(ath9k_hw_extend_tsf); |
| 3689 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3690 | bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3691 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3692 | if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3693 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 3694 | "bad slot time %u\n", us); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3695 | ah->slottime = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3696 | return false; |
| 3697 | } else { |
| 3698 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3699 | ah->slottime = us; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3700 | return true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3701 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3702 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3703 | EXPORT_SYMBOL(ath9k_hw_setslottime); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3704 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 3705 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3706 | { |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 3707 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3708 | u32 macmode; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3709 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 3710 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3711 | macmode = AR_2040_JOINED_RX_CLEAR; |
| 3712 | else |
| 3713 | macmode = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3714 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3715 | REG_WRITE(ah, AR_2040_MODE, macmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3716 | } |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3717 | |
| 3718 | /* HW Generic timers configuration */ |
| 3719 | |
| 3720 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = |
| 3721 | { |
| 3722 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3723 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3724 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3725 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3726 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3727 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3728 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3729 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3730 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, |
| 3731 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, |
| 3732 | AR_NDP2_TIMER_MODE, 0x0002}, |
| 3733 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, |
| 3734 | AR_NDP2_TIMER_MODE, 0x0004}, |
| 3735 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, |
| 3736 | AR_NDP2_TIMER_MODE, 0x0008}, |
| 3737 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, |
| 3738 | AR_NDP2_TIMER_MODE, 0x0010}, |
| 3739 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, |
| 3740 | AR_NDP2_TIMER_MODE, 0x0020}, |
| 3741 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, |
| 3742 | AR_NDP2_TIMER_MODE, 0x0040}, |
| 3743 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, |
| 3744 | AR_NDP2_TIMER_MODE, 0x0080} |
| 3745 | }; |
| 3746 | |
| 3747 | /* HW generic timer primitives */ |
| 3748 | |
| 3749 | /* compute and clear index of rightmost 1 */ |
| 3750 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) |
| 3751 | { |
| 3752 | u32 b; |
| 3753 | |
| 3754 | b = *mask; |
| 3755 | b &= (0-b); |
| 3756 | *mask &= ~b; |
| 3757 | b *= debruijn32; |
| 3758 | b >>= 27; |
| 3759 | |
| 3760 | return timer_table->gen_timer_index[b]; |
| 3761 | } |
| 3762 | |
Vasanthakumar Thiagarajan | 1773912 | 2009-08-26 21:08:50 +0530 | [diff] [blame] | 3763 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3764 | { |
| 3765 | return REG_READ(ah, AR_TSF_L32); |
| 3766 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3767 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3768 | |
| 3769 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
| 3770 | void (*trigger)(void *), |
| 3771 | void (*overflow)(void *), |
| 3772 | void *arg, |
| 3773 | u8 timer_index) |
| 3774 | { |
| 3775 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3776 | struct ath_gen_timer *timer; |
| 3777 | |
| 3778 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
| 3779 | |
| 3780 | if (timer == NULL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3781 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 3782 | "Failed to allocate memory" |
| 3783 | "for hw timer[%d]\n", timer_index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3784 | return NULL; |
| 3785 | } |
| 3786 | |
| 3787 | /* allocate a hardware generic timer slot */ |
| 3788 | timer_table->timers[timer_index] = timer; |
| 3789 | timer->index = timer_index; |
| 3790 | timer->trigger = trigger; |
| 3791 | timer->overflow = overflow; |
| 3792 | timer->arg = arg; |
| 3793 | |
| 3794 | return timer; |
| 3795 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3796 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3797 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 3798 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
| 3799 | struct ath_gen_timer *timer, |
| 3800 | u32 timer_next, |
| 3801 | u32 timer_period) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3802 | { |
| 3803 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3804 | u32 tsf; |
| 3805 | |
| 3806 | BUG_ON(!timer_period); |
| 3807 | |
| 3808 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); |
| 3809 | |
| 3810 | tsf = ath9k_hw_gettsf32(ah); |
| 3811 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3812 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
| 3813 | "curent tsf %x period %x" |
| 3814 | "timer_next %x\n", tsf, timer_period, timer_next); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3815 | |
| 3816 | /* |
| 3817 | * Pull timer_next forward if the current TSF already passed it |
| 3818 | * because of software latency |
| 3819 | */ |
| 3820 | if (timer_next < tsf) |
| 3821 | timer_next = tsf + timer_period; |
| 3822 | |
| 3823 | /* |
| 3824 | * Program generic timer registers |
| 3825 | */ |
| 3826 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, |
| 3827 | timer_next); |
| 3828 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, |
| 3829 | timer_period); |
| 3830 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 3831 | gen_tmr_configuration[timer->index].mode_mask); |
| 3832 | |
| 3833 | /* Enable both trigger and thresh interrupt masks */ |
| 3834 | REG_SET_BIT(ah, AR_IMR_S5, |
| 3835 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 3836 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3837 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3838 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3839 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 3840 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3841 | { |
| 3842 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3843 | |
| 3844 | if ((timer->index < AR_FIRST_NDP_TIMER) || |
| 3845 | (timer->index >= ATH_MAX_GEN_TIMER)) { |
| 3846 | return; |
| 3847 | } |
| 3848 | |
| 3849 | /* Clear generic timer enable bits. */ |
| 3850 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 3851 | gen_tmr_configuration[timer->index].mode_mask); |
| 3852 | |
| 3853 | /* Disable both trigger and thresh interrupt masks */ |
| 3854 | REG_CLR_BIT(ah, AR_IMR_S5, |
| 3855 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 3856 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
| 3857 | |
| 3858 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3859 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3860 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3861 | |
| 3862 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) |
| 3863 | { |
| 3864 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3865 | |
| 3866 | /* free the hardware generic timer slot */ |
| 3867 | timer_table->timers[timer->index] = NULL; |
| 3868 | kfree(timer); |
| 3869 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3870 | EXPORT_SYMBOL(ath_gen_timer_free); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3871 | |
| 3872 | /* |
| 3873 | * Generic Timer Interrupts handling |
| 3874 | */ |
| 3875 | void ath_gen_timer_isr(struct ath_hw *ah) |
| 3876 | { |
| 3877 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3878 | struct ath_gen_timer *timer; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3879 | struct ath_common *common = ath9k_hw_common(ah); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3880 | u32 trigger_mask, thresh_mask, index; |
| 3881 | |
| 3882 | /* get hardware generic timer interrupt status */ |
| 3883 | trigger_mask = ah->intr_gen_timer_trigger; |
| 3884 | thresh_mask = ah->intr_gen_timer_thresh; |
| 3885 | trigger_mask &= timer_table->timer_mask.val; |
| 3886 | thresh_mask &= timer_table->timer_mask.val; |
| 3887 | |
| 3888 | trigger_mask &= ~thresh_mask; |
| 3889 | |
| 3890 | while (thresh_mask) { |
| 3891 | index = rightmost_index(timer_table, &thresh_mask); |
| 3892 | timer = timer_table->timers[index]; |
| 3893 | BUG_ON(!timer); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3894 | ath_print(common, ATH_DBG_HWTIMER, |
| 3895 | "TSF overflow for Gen timer %d\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3896 | timer->overflow(timer->arg); |
| 3897 | } |
| 3898 | |
| 3899 | while (trigger_mask) { |
| 3900 | index = rightmost_index(timer_table, &trigger_mask); |
| 3901 | timer = timer_table->timers[index]; |
| 3902 | BUG_ON(!timer); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3903 | ath_print(common, ATH_DBG_HWTIMER, |
| 3904 | "Gen timer[%d] trigger\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3905 | timer->trigger(timer->arg); |
| 3906 | } |
| 3907 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3908 | EXPORT_SYMBOL(ath_gen_timer_isr); |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3909 | |
| 3910 | static struct { |
| 3911 | u32 version; |
| 3912 | const char * name; |
| 3913 | } ath_mac_bb_names[] = { |
| 3914 | /* Devices with external radios */ |
| 3915 | { AR_SREV_VERSION_5416_PCI, "5416" }, |
| 3916 | { AR_SREV_VERSION_5416_PCIE, "5418" }, |
| 3917 | { AR_SREV_VERSION_9100, "9100" }, |
| 3918 | { AR_SREV_VERSION_9160, "9160" }, |
| 3919 | /* Single-chip solutions */ |
| 3920 | { AR_SREV_VERSION_9280, "9280" }, |
| 3921 | { AR_SREV_VERSION_9285, "9285" }, |
Luis R. Rodriguez | 1115847 | 2009-10-27 12:59:35 -0400 | [diff] [blame] | 3922 | { AR_SREV_VERSION_9287, "9287" }, |
| 3923 | { AR_SREV_VERSION_9271, "9271" }, |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3924 | }; |
| 3925 | |
| 3926 | /* For devices with external radios */ |
| 3927 | static struct { |
| 3928 | u16 version; |
| 3929 | const char * name; |
| 3930 | } ath_rf_names[] = { |
| 3931 | { 0, "5133" }, |
| 3932 | { AR_RAD5133_SREV_MAJOR, "5133" }, |
| 3933 | { AR_RAD5122_SREV_MAJOR, "5122" }, |
| 3934 | { AR_RAD2133_SREV_MAJOR, "2133" }, |
| 3935 | { AR_RAD2122_SREV_MAJOR, "2122" } |
| 3936 | }; |
| 3937 | |
| 3938 | /* |
| 3939 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. |
| 3940 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 3941 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3942 | { |
| 3943 | int i; |
| 3944 | |
| 3945 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { |
| 3946 | if (ath_mac_bb_names[i].version == mac_bb_version) { |
| 3947 | return ath_mac_bb_names[i].name; |
| 3948 | } |
| 3949 | } |
| 3950 | |
| 3951 | return "????"; |
| 3952 | } |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3953 | |
| 3954 | /* |
| 3955 | * Return the RF name. "????" is returned if the RF is unknown. |
| 3956 | * Used for devices with external radios. |
| 3957 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 3958 | static const char *ath9k_hw_rf_name(u16 rf_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3959 | { |
| 3960 | int i; |
| 3961 | |
| 3962 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { |
| 3963 | if (ath_rf_names[i].version == rf_version) { |
| 3964 | return ath_rf_names[i].name; |
| 3965 | } |
| 3966 | } |
| 3967 | |
| 3968 | return "????"; |
| 3969 | } |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 3970 | |
| 3971 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) |
| 3972 | { |
| 3973 | int used; |
| 3974 | |
| 3975 | /* chipsets >= AR9280 are single-chip */ |
| 3976 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
| 3977 | used = snprintf(hw_name, len, |
| 3978 | "Atheros AR%s Rev:%x", |
| 3979 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 3980 | ah->hw_version.macRev); |
| 3981 | } |
| 3982 | else { |
| 3983 | used = snprintf(hw_name, len, |
| 3984 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", |
| 3985 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 3986 | ah->hw_version.macRev, |
| 3987 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & |
| 3988 | AR_RADIO_SREV_MAJOR)), |
| 3989 | ah->hw_version.phyRev); |
| 3990 | } |
| 3991 | |
| 3992 | hw_name[used] = '\0'; |
| 3993 | } |
| 3994 | EXPORT_SYMBOL(ath9k_hw_name); |