Stephen Boyd | dd15ab8 | 2011-11-08 10:34:05 -0800 | [diff] [blame] | 1 | /* |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Copyright (C) 2007 Google, Inc. |
Kumar Gala | 3f8e8ce | 2014-01-29 16:17:30 -0600 | [diff] [blame] | 4 | * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved. |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and |
| 8 | * may be copied, distributed, and modified under those terms. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
Stephen Boyd | 4a18407 | 2011-11-08 10:34:04 -0800 | [diff] [blame] | 17 | #include <linux/clocksource.h> |
| 18 | #include <linux/clockchips.h> |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 19 | #include <linux/cpu.h> |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 20 | #include <linux/init.h> |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/irq.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | #include <linux/of_address.h> |
| 26 | #include <linux/of_irq.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 27 | #include <linux/sched_clock.h> |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 28 | |
Stephen Boyd | 013be5a | 2014-05-13 16:01:00 -0700 | [diff] [blame] | 29 | #include <asm/delay.h> |
| 30 | |
Stephen Boyd | e25e3d1 | 2013-03-14 20:31:39 -0700 | [diff] [blame] | 31 | #define TIMER_MATCH_VAL 0x0000 |
| 32 | #define TIMER_COUNT_VAL 0x0004 |
| 33 | #define TIMER_ENABLE 0x0008 |
| 34 | #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) |
| 35 | #define TIMER_ENABLE_EN BIT(0) |
| 36 | #define TIMER_CLEAR 0x000C |
| 37 | #define DGT_CLK_CTL 0x10 |
| 38 | #define DGT_CLK_CTL_DIV_4 0x3 |
| 39 | #define TIMER_STS_GPT0_CLR_PEND BIT(10) |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 40 | |
| 41 | #define GPT_HZ 32768 |
Jeff Ohlstein | 672039f | 2010-10-05 15:23:57 -0700 | [diff] [blame] | 42 | |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 43 | static void __iomem *event_base; |
Stephen Boyd | e25e3d1 | 2013-03-14 20:31:39 -0700 | [diff] [blame] | 44 | static void __iomem *sts_base; |
Stephen Boyd | a850c3f | 2011-11-08 10:34:06 -0800 | [diff] [blame] | 45 | |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 46 | static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) |
| 47 | { |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 48 | struct clock_event_device *evt = dev_id; |
Stephen Boyd | a850c3f | 2011-11-08 10:34:06 -0800 | [diff] [blame] | 49 | /* Stop the timer tick */ |
Viresh Kumar | 736b2df | 2015-06-18 16:24:31 +0530 | [diff] [blame] | 50 | if (clockevent_state_oneshot(evt)) { |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 51 | u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); |
Stephen Boyd | a850c3f | 2011-11-08 10:34:06 -0800 | [diff] [blame] | 52 | ctrl &= ~TIMER_ENABLE_EN; |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 53 | writel_relaxed(ctrl, event_base + TIMER_ENABLE); |
Stephen Boyd | a850c3f | 2011-11-08 10:34:06 -0800 | [diff] [blame] | 54 | } |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 55 | evt->event_handler(evt); |
| 56 | return IRQ_HANDLED; |
| 57 | } |
| 58 | |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 59 | static int msm_timer_set_next_event(unsigned long cycles, |
| 60 | struct clock_event_device *evt) |
| 61 | { |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 62 | u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 63 | |
Stephen Boyd | 4080d2d | 2013-03-14 20:31:37 -0700 | [diff] [blame] | 64 | ctrl &= ~TIMER_ENABLE_EN; |
| 65 | writel_relaxed(ctrl, event_base + TIMER_ENABLE); |
| 66 | |
| 67 | writel_relaxed(ctrl, event_base + TIMER_CLEAR); |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 68 | writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); |
Stephen Boyd | e25e3d1 | 2013-03-14 20:31:39 -0700 | [diff] [blame] | 69 | |
| 70 | if (sts_base) |
| 71 | while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND) |
| 72 | cpu_relax(); |
| 73 | |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 74 | writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 75 | return 0; |
| 76 | } |
| 77 | |
Viresh Kumar | 736b2df | 2015-06-18 16:24:31 +0530 | [diff] [blame] | 78 | static int msm_timer_shutdown(struct clock_event_device *evt) |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 79 | { |
Stephen Boyd | a850c3f | 2011-11-08 10:34:06 -0800 | [diff] [blame] | 80 | u32 ctrl; |
| 81 | |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 82 | ctrl = readl_relaxed(event_base + TIMER_ENABLE); |
Stephen Boyd | a850c3f | 2011-11-08 10:34:06 -0800 | [diff] [blame] | 83 | ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN); |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 84 | writel_relaxed(ctrl, event_base + TIMER_ENABLE); |
Viresh Kumar | 736b2df | 2015-06-18 16:24:31 +0530 | [diff] [blame] | 85 | return 0; |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 86 | } |
| 87 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 88 | static struct clock_event_device __percpu *msm_evt; |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 89 | |
| 90 | static void __iomem *source_base; |
| 91 | |
Stephen Boyd | f8e56c4 | 2012-02-22 01:39:37 +0000 | [diff] [blame] | 92 | static notrace cycle_t msm_read_timer_count(struct clocksource *cs) |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 93 | { |
Stephen Boyd | 2081a6b | 2011-11-08 10:34:08 -0800 | [diff] [blame] | 94 | return readl_relaxed(source_base + TIMER_COUNT_VAL); |
| 95 | } |
| 96 | |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 97 | static struct clocksource msm_clocksource = { |
| 98 | .name = "dg_timer", |
| 99 | .rating = 300, |
| 100 | .read = msm_read_timer_count, |
Stephen Boyd | 2081a6b | 2011-11-08 10:34:08 -0800 | [diff] [blame] | 101 | .mask = CLOCKSOURCE_MASK(32), |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 102 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 103 | }; |
| 104 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 105 | static int msm_timer_irq; |
| 106 | static int msm_timer_has_ppi; |
| 107 | |
Richard Cochran | b040416 | 2016-07-13 17:16:43 +0000 | [diff] [blame] | 108 | static int msm_local_timer_starting_cpu(unsigned int cpu) |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 109 | { |
Richard Cochran | b040416 | 2016-07-13 17:16:43 +0000 | [diff] [blame] | 110 | struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu); |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 111 | int err; |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 112 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 113 | evt->irq = msm_timer_irq; |
| 114 | evt->name = "msm_timer"; |
| 115 | evt->features = CLOCK_EVT_FEAT_ONESHOT; |
| 116 | evt->rating = 200; |
Viresh Kumar | 736b2df | 2015-06-18 16:24:31 +0530 | [diff] [blame] | 117 | evt->set_state_shutdown = msm_timer_shutdown; |
| 118 | evt->set_state_oneshot = msm_timer_shutdown; |
| 119 | evt->tick_resume = msm_timer_shutdown; |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 120 | evt->set_next_event = msm_timer_set_next_event; |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 121 | evt->cpumask = cpumask_of(cpu); |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 122 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 123 | clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff); |
| 124 | |
| 125 | if (msm_timer_has_ppi) { |
| 126 | enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); |
| 127 | } else { |
| 128 | err = request_irq(evt->irq, msm_timer_interrupt, |
| 129 | IRQF_TIMER | IRQF_NOBALANCING | |
| 130 | IRQF_TRIGGER_RISING, "gp_timer", evt); |
| 131 | if (err) |
| 132 | pr_err("request_irq failed\n"); |
| 133 | } |
| 134 | |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 135 | return 0; |
| 136 | } |
| 137 | |
Richard Cochran | b040416 | 2016-07-13 17:16:43 +0000 | [diff] [blame] | 138 | static int msm_local_timer_dying_cpu(unsigned int cpu) |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 139 | { |
Richard Cochran | b040416 | 2016-07-13 17:16:43 +0000 | [diff] [blame] | 140 | struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu); |
| 141 | |
Viresh Kumar | 736b2df | 2015-06-18 16:24:31 +0530 | [diff] [blame] | 142 | evt->set_state_shutdown(evt); |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 143 | disable_percpu_irq(evt->irq); |
Richard Cochran | b040416 | 2016-07-13 17:16:43 +0000 | [diff] [blame] | 144 | return 0; |
Marc Zyngier | 5ca709c | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 145 | } |
| 146 | |
Stephen Boyd | 6aa16a2 | 2013-11-15 15:26:16 -0800 | [diff] [blame] | 147 | static u64 notrace msm_sched_clock_read(void) |
Stephen Boyd | f8e56c4 | 2012-02-22 01:39:37 +0000 | [diff] [blame] | 148 | { |
| 149 | return msm_clocksource.read(&msm_clocksource); |
| 150 | } |
| 151 | |
Stephen Boyd | 013be5a | 2014-05-13 16:01:00 -0700 | [diff] [blame] | 152 | static unsigned long msm_read_current_timer(void) |
| 153 | { |
| 154 | return msm_clocksource.read(&msm_clocksource); |
| 155 | } |
| 156 | |
| 157 | static struct delay_timer msm_delay_timer = { |
| 158 | .read_current_timer = msm_read_current_timer, |
| 159 | }; |
| 160 | |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 161 | static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, |
Stephen Boyd | 4312a7e | 2012-09-05 12:28:52 -0700 | [diff] [blame] | 162 | bool percpu) |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 163 | { |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 164 | struct clocksource *cs = &msm_clocksource; |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 165 | int res = 0; |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 166 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 167 | msm_timer_irq = irq; |
| 168 | msm_timer_has_ppi = percpu; |
David Brown | 8c27e6f | 2011-01-07 10:20:49 -0800 | [diff] [blame] | 169 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 170 | msm_evt = alloc_percpu(struct clock_event_device); |
| 171 | if (!msm_evt) { |
| 172 | pr_err("memory allocation failed for clockevents\n"); |
| 173 | goto err; |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 174 | } |
Stephen Boyd | dd15ab8 | 2011-11-08 10:34:05 -0800 | [diff] [blame] | 175 | |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 176 | if (percpu) |
| 177 | res = request_percpu_irq(irq, msm_timer_interrupt, |
| 178 | "gp_timer", msm_evt); |
| 179 | |
| 180 | if (res) { |
| 181 | pr_err("request_percpu_irq failed\n"); |
| 182 | } else { |
Richard Cochran | b040416 | 2016-07-13 17:16:43 +0000 | [diff] [blame] | 183 | /* Install and invoke hotplug callbacks */ |
| 184 | res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING, |
| 185 | "AP_QCOM_TIMER_STARTING", |
| 186 | msm_local_timer_starting_cpu, |
| 187 | msm_local_timer_dying_cpu); |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 188 | if (res) { |
| 189 | free_percpu_irq(irq, msm_evt); |
| 190 | goto err; |
| 191 | } |
Stephen Boyd | 4d70c59 | 2013-02-15 17:31:31 -0800 | [diff] [blame] | 192 | } |
| 193 | |
Stephen Boyd | dd15ab8 | 2011-11-08 10:34:05 -0800 | [diff] [blame] | 194 | err: |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 195 | writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); |
Stephen Boyd | 2081a6b | 2011-11-08 10:34:08 -0800 | [diff] [blame] | 196 | res = clocksource_register_hz(cs, dgt_hz); |
Stephen Boyd | dd15ab8 | 2011-11-08 10:34:05 -0800 | [diff] [blame] | 197 | if (res) |
Stephen Boyd | 2a00c10 | 2011-11-08 10:34:07 -0800 | [diff] [blame] | 198 | pr_err("clocksource_register failed\n"); |
Stephen Boyd | 6aa16a2 | 2013-11-15 15:26:16 -0800 | [diff] [blame] | 199 | sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); |
Stephen Boyd | 013be5a | 2014-05-13 16:01:00 -0700 | [diff] [blame] | 200 | msm_delay_timer.freq = dgt_hz; |
| 201 | register_current_timer_delay(&msm_delay_timer); |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 202 | |
| 203 | return res; |
Arve Hjønnevåg | 3e4ea37 | 2007-11-26 04:11:58 -0800 | [diff] [blame] | 204 | } |
| 205 | |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 206 | static int __init msm_dt_timer_init(struct device_node *np) |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 207 | { |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 208 | u32 freq; |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 209 | int irq, ret; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 210 | struct resource res; |
| 211 | u32 percpu_offset; |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 212 | void __iomem *base; |
| 213 | void __iomem *cpu0_base; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 214 | |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 215 | base = of_iomap(np, 0); |
| 216 | if (!base) { |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 217 | pr_err("Failed to map event base\n"); |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 218 | return -ENXIO; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 219 | } |
| 220 | |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 221 | /* We use GPT0 for the clockevent */ |
| 222 | irq = irq_of_parse_and_map(np, 1); |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 223 | if (irq <= 0) { |
| 224 | pr_err("Can't get irq\n"); |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 225 | return -EINVAL; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 226 | } |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 227 | |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 228 | /* We use CPU0's DGT for the clocksource */ |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 229 | if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) |
| 230 | percpu_offset = 0; |
| 231 | |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 232 | ret = of_address_to_resource(np, 0, &res); |
| 233 | if (ret) { |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 234 | pr_err("Failed to parse DGT resource\n"); |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 235 | return ret; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 236 | } |
| 237 | |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 238 | cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res)); |
| 239 | if (!cpu0_base) { |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 240 | pr_err("Failed to map source base\n"); |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 241 | return -EINVAL; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 242 | } |
| 243 | |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 244 | if (of_property_read_u32(np, "clock-frequency", &freq)) { |
| 245 | pr_err("Unknown frequency\n"); |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 246 | return -EINVAL; |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 247 | } |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 248 | |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 249 | event_base = base + 0x4; |
Stephen Boyd | e25e3d1 | 2013-03-14 20:31:39 -0700 | [diff] [blame] | 250 | sts_base = base + 0x88; |
Stephen Boyd | eebdb0c | 2013-03-14 20:31:38 -0700 | [diff] [blame] | 251 | source_base = cpu0_base + 0x24; |
| 252 | freq /= 4; |
| 253 | writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); |
| 254 | |
Daniel Lezcano | ab51189 | 2016-06-06 17:58:43 +0200 | [diff] [blame] | 255 | return msm_timer_init(freq, 32, irq, !!percpu_offset); |
Stephen Boyd | 6e33216 | 2012-09-05 12:28:53 -0700 | [diff] [blame] | 256 | } |
Daniel Lezcano | 177cf6e | 2016-06-07 00:27:44 +0200 | [diff] [blame] | 257 | CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); |
| 258 | CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); |