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Vladimir Barinov3e062b02007-06-05 16:36:55 +01001/*
2 * TI DaVinci clock definitions
3 *
Kevin Hilmanc5b736d2009-03-20 17:29:01 -07004 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
Vladimir Barinov3e062b02007-06-05 16:36:55 +01006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13#define __ARCH_ARM_DAVINCI_CLOCK_H
14
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070015#define DAVINCI_PLL1_BASE 0x01c40800
16#define DAVINCI_PLL2_BASE 0x01c40c00
17#define MAX_PLL 2
18
19/* PLL/Reset register offsets */
20#define PLLCTL 0x100
21#define PLLCTL_PLLEN BIT(0)
Sekhar Norid6a61562009-08-31 15:48:03 +053022#define PLLCTL_PLLPWRDN BIT(1)
23#define PLLCTL_PLLRST BIT(3)
24#define PLLCTL_PLLDIS BIT(4)
25#define PLLCTL_PLLENSRC BIT(5)
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070026#define PLLCTL_CLKMODE BIT(8)
27
28#define PLLM 0x110
29#define PLLM_PLLM_MASK 0xff
30
31#define PREDIV 0x114
32#define PLLDIV1 0x118
33#define PLLDIV2 0x11c
34#define PLLDIV3 0x120
35#define POSTDIV 0x128
36#define BPDIV 0x12c
37#define PLLCMD 0x138
38#define PLLSTAT 0x13c
39#define PLLALNCTL 0x140
40#define PLLDCHANGE 0x144
41#define PLLCKEN 0x148
42#define PLLCKSTAT 0x14c
43#define PLLSYSTAT 0x150
44#define PLLDIV4 0x160
45#define PLLDIV5 0x164
46#define PLLDIV6 0x168
47#define PLLDIV7 0x16c
48#define PLLDIV8 0x170
49#define PLLDIV9 0x174
50#define PLLDIV_EN BIT(15)
51#define PLLDIV_RATIO_MASK 0x1f
52
Sekhar Nori9a219a92009-11-16 17:21:33 +053053/*
54 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
55 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
56 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
57 * is ~25MHz. Units are micro seconds.
58 */
59#define PLL_BYPASS_TIME 1
60/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
61#define PLL_RESET_TIME 1
62/*
63 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
64 * Units are micro seconds.
65 */
66#define PLL_LOCK_TIME 20
67
Sekhar Norie2da3aa2009-11-16 17:21:36 +053068#ifndef __ASSEMBLER__
69
70#include <linux/list.h>
71#include <asm/clkdev.h>
72
Sekhar Norib39639b2010-07-20 16:46:49 +053073#define PLLSTAT_GOSTAT BIT(0)
74#define PLLCMD_GOSET BIT(0)
75
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070076struct pll_data {
77 u32 phys_base;
78 void __iomem *base;
79 u32 num;
80 u32 flags;
81 u32 input_rate;
Cyril Chemparathyd6961e62010-04-14 14:44:49 -040082 u32 div_ratio_mask;
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070083};
84#define PLL_HAS_PREDIV 0x01
85#define PLL_HAS_POSTDIV 0x02
86
Vladimir Barinov3e062b02007-06-05 16:36:55 +010087struct clk {
88 struct list_head node;
89 struct module *owner;
90 const char *name;
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070091 unsigned long rate;
Sekhar Norib39639b2010-07-20 16:46:49 +053092 unsigned long maxrate; /* H/W supported max rate */
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070093 u8 usecount;
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070094 u8 lpsc;
Sergei Shtylyov789a7852009-09-30 19:48:03 +040095 u8 gpsc;
Sekhar Nori5d36a332009-08-31 15:48:05 +053096 u32 flags;
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070097 struct clk *parent;
Sekhar Norif02bf3b2009-08-31 15:48:01 +053098 struct list_head children; /* list of children */
99 struct list_head childnode; /* parent's child list node */
Kevin Hilmanc5b736d2009-03-20 17:29:01 -0700100 struct pll_data *pll_data;
101 u32 div_reg;
Sekhar Noride381a92009-08-31 15:48:02 +0530102 unsigned long (*recalc) (struct clk *);
Sekhar Norid6a61562009-08-31 15:48:03 +0530103 int (*set_rate) (struct clk *clk, unsigned long rate);
104 int (*round_rate) (struct clk *clk, unsigned long rate);
Vladimir Barinov3e062b02007-06-05 16:36:55 +0100105};
106
Sekhar Nori5d36a332009-08-31 15:48:05 +0530107/* Clock flags: SoC-specific flags start at BIT(16) */
Kevin Hilmanc5b736d2009-03-20 17:29:01 -0700108#define ALWAYS_ENABLED BIT(1)
Cyril Chemparathy52958be2010-03-25 17:43:47 -0400109#define CLK_PSC BIT(2)
110#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
Kevin Hilmanc5b736d2009-03-20 17:29:01 -0700111#define CLK_PLL BIT(4) /* PLL-derived clock */
Cyril Chemparathy52958be2010-03-25 17:43:47 -0400112#define PRE_PLL BIT(5) /* source is before PLL mult/div */
113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
Vladimir Barinov3e062b02007-06-05 16:36:55 +0100114
Kevin Hilman08aca082010-01-11 08:22:23 -0800115#define CLK(dev, con, ck) \
116 { \
117 .dev_id = dev, \
118 .con_id = con, \
119 .clk = ck, \
120 } \
Kevin Hilmanc5b736d2009-03-20 17:29:01 -0700121
Kevin Hilman08aca082010-01-11 08:22:23 -0800122int davinci_clk_init(struct clk_lookup *clocks);
Sekhar Norid6a61562009-08-31 15:48:03 +0530123int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
124 unsigned int mult, unsigned int postdiv);
Sekhar Norib39639b2010-07-20 16:46:49 +0530125int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
Kevin Hilmanfb631382009-04-29 16:23:59 -0700126
127extern struct platform_device davinci_wdt_device;
Cyril Chemparathyc78a5bc2010-05-01 18:38:28 -0400128extern void davinci_watchdog_reset(struct platform_device *);
Kevin Hilmanfb631382009-04-29 16:23:59 -0700129
Vladimir Barinov3e062b02007-06-05 16:36:55 +0100130#endif
Sekhar Norie2da3aa2009-11-16 17:21:36 +0530131
132#endif