blob: a2e6e7205d7e082b79a2428a35b406059fa59c3e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/video/sa1100fb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas
5 * Based on acornfb.c Copyright (C) Russell King.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * StrongARM 1100 LCD Controller Frame Buffer Driver
12 *
13 * Please direct your questions and comments on this driver to the following
14 * email address:
15 *
16 * linux-arm-kernel@lists.arm.linux.org.uk
17 *
18 * Clean patches should be sent to the ARM Linux Patch System. Please see the
19 * following web page for more information:
20 *
21 * http://www.arm.linux.org.uk/developer/patches/info.shtml
22 *
23 * Thank you.
24 *
25 * Known problems:
26 * - With the Neponset plugged into an Assabet, LCD powerdown
27 * doesn't work (LCD stays powered up). Therefore we shouldn't
28 * blank the screen.
29 * - We don't limit the CPU clock rate nor the mode selection
30 * according to the available SDRAM bandwidth.
31 *
32 * Other notes:
33 * - Linear grayscale palettes and the kernel.
34 * Such code does not belong in the kernel. The kernel frame buffer
35 * drivers do not expect a linear colourmap, but a colourmap based on
36 * the VT100 standard mapping.
37 *
38 * If your _userspace_ requires a linear colourmap, then the setup of
39 * such a colourmap belongs _in userspace_, not in the kernel. Code
40 * to set the colourmap correctly from user space has been sent to
41 * David Neuer. It's around 8 lines of C code, plus another 4 to
42 * detect if we are using grayscale.
43 *
44 * - The following must never be specified in a panel definition:
45 * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
46 *
47 * - The following should be specified:
48 * either LCCR0_Color or LCCR0_Mono
49 * either LCCR0_Sngl or LCCR0_Dual
50 * either LCCR0_Act or LCCR0_Pas
51 * either LCCR3_OutEnH or LCCD3_OutEnL
52 * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
53 * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
54 *
55 * Code Status:
56 * 1999/04/01:
57 * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
58 * resolutions are working, but only the 8bpp mode is supported.
59 * Changes need to be made to the palette encode and decode routines
60 * to support 4 and 16 bpp modes.
61 * Driver is not designed to be a module. The FrameBuffer is statically
62 * allocated since dynamic allocation of a 300k buffer cannot be
63 * guaranteed.
64 *
65 * 1999/06/17:
66 * - FrameBuffer memory is now allocated at run-time when the
67 * driver is initialized.
68 *
69 * 2000/04/10: Nicolas Pitre <nico@cam.org>
70 * - Big cleanup for dynamic selection of machine type at run time.
71 *
72 * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
73 * - Support for Bitsy aka Compaq iPAQ H3600 added.
74 *
75 * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
76 * Jeff Sutherland <jsutherland@accelent.com>
77 * - Resolved an issue caused by a change made to the Assabet's PLD
78 * earlier this year which broke the framebuffer driver for newer
79 * Phase 4 Assabets. Some other parameters were changed to optimize
80 * for the Sharp display.
81 *
82 * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
83 * - XP860 support added
84 *
85 * 2000/08/19: Mark Huang <mhuang@livetoy.com>
86 * - Allows standard options to be passed on the kernel command line
87 * for most common passive displays.
88 *
89 * 2000/08/29:
90 * - s/save_flags_cli/local_irq_save/
91 * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
92 *
93 * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
94 * - Updated LART stuff. Fixed some minor bugs.
95 *
96 * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
97 * - Pangolin support added
98 *
99 * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
100 * - Huw Webpanel support added
101 *
102 * 2000/11/23: Eric Peng <ericpeng@coventive.com>
103 * - Freebird add
104 *
105 * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
106 * Cliff Brake <cbrake@accelent.com>
107 * - Added PM callback
108 *
109 * 2001/05/26: <rmk@arm.linux.org.uk>
110 * - Fix 16bpp so that (a) we use the right colours rather than some
111 * totally random colour depending on what was in page 0, and (b)
112 * we don't de-reference a NULL pointer.
113 * - remove duplicated implementation of consistent_alloc()
114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial
117 * memzero.
118 * - remove allow_modeset (acornfb idea does not belong here)
119 *
120 * 2001/05/28: <rmk@arm.linux.org.uk>
121 * - massive cleanup - move machine dependent data into structures
122 * - I've left various #warnings in - if you see one, and know
123 * the hardware concerned, please get in contact with me.
124 *
125 * 2001/05/31: <rmk@arm.linux.org.uk>
126 * - Fix LCCR1 HSW value, fix all machine type specifications to
127 * keep values in line. (Please check your machine type specs)
128 *
129 * 2001/06/10: <rmk@arm.linux.org.uk>
130 * - Fiddle with the LCD controller from task context only; mainly
131 * so that we can run with interrupts on, and sleep.
132 * - Convert #warnings into #errors. No pain, no gain. ;)
133 *
134 * 2001/06/14: <rmk@arm.linux.org.uk>
135 * - Make the palette BPS value for 12bpp come out correctly.
136 * - Take notice of "greyscale" on any colour depth.
137 * - Make truecolor visuals use the RGB channel encoding information.
138 *
139 * 2001/07/02: <rmk@arm.linux.org.uk>
140 * - Fix colourmap problems.
141 *
142 * 2001/07/13: <abraham@2d3d.co.za>
143 * - Added support for the ICP LCD-Kit01 on LART. This LCD is
144 * manufactured by Prime View, model no V16C6448AB
145 *
146 * 2001/07/23: <rmk@arm.linux.org.uk>
147 * - Hand merge version from handhelds.org CVS tree. See patch
148 * notes for 595/1 for more information.
149 * - Drop 12bpp (it's 16bpp with different colour register mappings).
150 * - This hardware can not do direct colour. Therefore we don't
151 * support it.
152 *
153 * 2001/07/27: <rmk@arm.linux.org.uk>
154 * - Halve YRES on dual scan LCDs.
155 *
156 * 2001/08/22: <rmk@arm.linux.org.uk>
157 * - Add b/w iPAQ pixclock value.
158 *
159 * 2001/10/12: <rmk@arm.linux.org.uk>
160 * - Add patch 681/1 and clean up stork definitions.
161 */
162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163#include <linux/module.h>
164#include <linux/kernel.h>
165#include <linux/sched.h>
166#include <linux/errno.h>
167#include <linux/string.h>
168#include <linux/interrupt.h>
169#include <linux/slab.h>
170#include <linux/fb.h>
171#include <linux/delay.h>
172#include <linux/init.h>
173#include <linux/ioport.h>
174#include <linux/cpufreq.h>
Russell Kingd052d1b2005-10-29 19:07:23 +0100175#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176#include <linux/dma-mapping.h>
177
178#include <asm/hardware.h>
179#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180#include <asm/mach-types.h>
181#include <asm/uaccess.h>
182#include <asm/arch/assabet.h>
183#include <asm/arch/shannon.h>
184
185/*
186 * debugging?
187 */
188#define DEBUG 0
189/*
190 * Complain if VAR is out of range.
191 */
192#define DEBUG_VAR 1
193
194#undef ASSABET_PAL_VIDEO
195
196#include "sa1100fb.h"
197
198extern void (*sa1100fb_backlight_power)(int on);
199extern void (*sa1100fb_lcd_power)(int on);
200
201/*
202 * IMHO this looks wrong. In 8BPP, length should be 8.
203 */
204static struct sa1100fb_rgb rgb_8 = {
205 .red = { .offset = 0, .length = 4, },
206 .green = { .offset = 0, .length = 4, },
207 .blue = { .offset = 0, .length = 4, },
208 .transp = { .offset = 0, .length = 0, },
209};
210
211static struct sa1100fb_rgb def_rgb_16 = {
212 .red = { .offset = 11, .length = 5, },
213 .green = { .offset = 5, .length = 6, },
214 .blue = { .offset = 0, .length = 5, },
215 .transp = { .offset = 0, .length = 0, },
216};
217
218#ifdef CONFIG_SA1100_ASSABET
219#ifndef ASSABET_PAL_VIDEO
220/*
221 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
222 * takes an RGB666 signal, but we provide it with an RGB565 signal
223 * instead (def_rgb_16).
224 */
225static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
226 .pixclock = 171521, .bpp = 16,
227 .xres = 320, .yres = 240,
228
229 .hsync_len = 5, .vsync_len = 1,
230 .left_margin = 61, .upper_margin = 3,
231 .right_margin = 9, .lower_margin = 0,
232
233 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
234
235 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
236 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
237};
238#else
239static struct sa1100fb_mach_info pal_info __initdata = {
240 .pixclock = 67797, .bpp = 16,
241 .xres = 640, .yres = 512,
242
243 .hsync_len = 64, .vsync_len = 6,
244 .left_margin = 125, .upper_margin = 70,
245 .right_margin = 115, .lower_margin = 36,
246
247 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
248 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
249};
250#endif
251#endif
252
253#ifdef CONFIG_SA1100_H3800
254static struct sa1100fb_mach_info h3800_info __initdata = {
255 .pixclock = 174757, .bpp = 16,
256 .xres = 320, .yres = 240,
257
258 .hsync_len = 3, .vsync_len = 3,
259 .left_margin = 12, .upper_margin = 10,
260 .right_margin = 17, .lower_margin = 1,
261
262 .cmap_static = 1,
263
264 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
265 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
266};
267#endif
268
269#ifdef CONFIG_SA1100_H3600
270static struct sa1100fb_mach_info h3600_info __initdata = {
271 .pixclock = 174757, .bpp = 16,
272 .xres = 320, .yres = 240,
273
274 .hsync_len = 3, .vsync_len = 3,
275 .left_margin = 12, .upper_margin = 10,
276 .right_margin = 17, .lower_margin = 1,
277
278 .cmap_static = 1,
279
280 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
281 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
282};
283
284static struct sa1100fb_rgb h3600_rgb_16 = {
285 .red = { .offset = 12, .length = 4, },
286 .green = { .offset = 7, .length = 4, },
287 .blue = { .offset = 1, .length = 4, },
288 .transp = { .offset = 0, .length = 0, },
289};
290#endif
291
292#ifdef CONFIG_SA1100_H3100
293static struct sa1100fb_mach_info h3100_info __initdata = {
294 .pixclock = 406977, .bpp = 4,
295 .xres = 320, .yres = 240,
296
297 .hsync_len = 26, .vsync_len = 41,
298 .left_margin = 4, .upper_margin = 0,
299 .right_margin = 4, .lower_margin = 0,
300
301 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
302 .cmap_greyscale = 1,
303 .cmap_inverse = 1,
304
305 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
306 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
307};
308#endif
309
310#ifdef CONFIG_SA1100_COLLIE
311static struct sa1100fb_mach_info collie_info __initdata = {
312 .pixclock = 171521, .bpp = 16,
313 .xres = 320, .yres = 240,
314
315 .hsync_len = 5, .vsync_len = 1,
316 .left_margin = 11, .upper_margin = 2,
317 .right_margin = 30, .lower_margin = 0,
318
319 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
320
321 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
322 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
323};
324#endif
325
326#ifdef LART_GREY_LCD
327static struct sa1100fb_mach_info lart_grey_info __initdata = {
328 .pixclock = 150000, .bpp = 4,
329 .xres = 320, .yres = 240,
330
331 .hsync_len = 1, .vsync_len = 1,
332 .left_margin = 4, .upper_margin = 0,
333 .right_margin = 2, .lower_margin = 0,
334
335 .cmap_greyscale = 1,
336 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
337
338 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
339 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
340};
341#endif
342#ifdef LART_COLOR_LCD
343static struct sa1100fb_mach_info lart_color_info __initdata = {
344 .pixclock = 150000, .bpp = 16,
345 .xres = 320, .yres = 240,
346
347 .hsync_len = 2, .vsync_len = 3,
348 .left_margin = 69, .upper_margin = 14,
349 .right_margin = 8, .lower_margin = 4,
350
351 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
352 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
353};
354#endif
355#ifdef LART_VIDEO_OUT
356static struct sa1100fb_mach_info lart_video_info __initdata = {
357 .pixclock = 39721, .bpp = 16,
358 .xres = 640, .yres = 480,
359
360 .hsync_len = 95, .vsync_len = 2,
361 .left_margin = 40, .upper_margin = 32,
362 .right_margin = 24, .lower_margin = 11,
363
364 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
365
366 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
367 .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
368};
369#endif
370
371#ifdef LART_KIT01_LCD
372static struct sa1100fb_mach_info lart_kit01_info __initdata = {
373 .pixclock = 63291, .bpp = 16,
374 .xres = 640, .yres = 480,
375
376 .hsync_len = 64, .vsync_len = 3,
377 .left_margin = 122, .upper_margin = 45,
378 .right_margin = 10, .lower_margin = 10,
379
380 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
381 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
382};
383#endif
384
385#ifdef CONFIG_SA1100_SHANNON
386static struct sa1100fb_mach_info shannon_info __initdata = {
387 .pixclock = 152500, .bpp = 8,
388 .xres = 640, .yres = 480,
389
390 .hsync_len = 4, .vsync_len = 3,
391 .left_margin = 2, .upper_margin = 0,
392 .right_margin = 1, .lower_margin = 0,
393
394 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
395
396 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
397 .lccr3 = LCCR3_ACBsDiv(512),
398};
399#endif
400
401
402
403static struct sa1100fb_mach_info * __init
404sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
405{
406 struct sa1100fb_mach_info *inf = NULL;
407
408 /*
409 * R G B T
410 * default {11,5}, { 5,6}, { 0,5}, { 0,0}
411 * h3600 {12,4}, { 7,4}, { 1,4}, { 0,0}
412 * freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
413 */
414#ifdef CONFIG_SA1100_ASSABET
415 if (machine_is_assabet()) {
416#ifndef ASSABET_PAL_VIDEO
417 inf = &lq039q2ds54_info;
418#else
419 inf = &pal_info;
420#endif
421 }
422#endif
423#ifdef CONFIG_SA1100_H3100
424 if (machine_is_h3100()) {
425 inf = &h3100_info;
426 }
427#endif
428#ifdef CONFIG_SA1100_H3600
429 if (machine_is_h3600()) {
430 inf = &h3600_info;
431 fbi->rgb[RGB_16] = &h3600_rgb_16;
432 }
433#endif
434#ifdef CONFIG_SA1100_H3800
435 if (machine_is_h3800()) {
436 inf = &h3800_info;
437 }
438#endif
439#ifdef CONFIG_SA1100_COLLIE
440 if (machine_is_collie()) {
441 inf = &collie_info;
442 }
443#endif
444#ifdef CONFIG_SA1100_LART
445 if (machine_is_lart()) {
446#ifdef LART_GREY_LCD
447 inf = &lart_grey_info;
448#endif
449#ifdef LART_COLOR_LCD
450 inf = &lart_color_info;
451#endif
452#ifdef LART_VIDEO_OUT
453 inf = &lart_video_info;
454#endif
455#ifdef LART_KIT01_LCD
456 inf = &lart_kit01_info;
457#endif
458 }
459#endif
460#ifdef CONFIG_SA1100_SHANNON
461 if (machine_is_shannon()) {
462 inf = &shannon_info;
463 }
464#endif
465 return inf;
466}
467
468static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
469static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
470
471static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
472{
473 unsigned long flags;
474
475 local_irq_save(flags);
476 /*
477 * We need to handle two requests being made at the same time.
478 * There are two important cases:
479 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
480 * We must perform the unblanking, which will do our REENABLE for us.
481 * 2. When we are blanking, but immediately unblank before we have
482 * blanked. We do the "REENABLE" thing here as well, just to be sure.
483 */
484 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
485 state = (u_int) -1;
486 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
487 state = C_REENABLE;
488
489 if (state != (u_int)-1) {
490 fbi->task_state = state;
491 schedule_work(&fbi->task);
492 }
493 local_irq_restore(flags);
494}
495
496static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
497{
498 chan &= 0xffff;
499 chan >>= 16 - bf->length;
500 return chan << bf->offset;
501}
502
503/*
504 * Convert bits-per-pixel to a hardware palette PBS value.
505 */
506static inline u_int palette_pbs(struct fb_var_screeninfo *var)
507{
508 int ret = 0;
509 switch (var->bits_per_pixel) {
510 case 4: ret = 0 << 12; break;
511 case 8: ret = 1 << 12; break;
512 case 16: ret = 2 << 12; break;
513 }
514 return ret;
515}
516
517static int
518sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
519 u_int trans, struct fb_info *info)
520{
521 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
522 u_int val, ret = 1;
523
524 if (regno < fbi->palette_size) {
525 val = ((red >> 4) & 0xf00);
526 val |= ((green >> 8) & 0x0f0);
527 val |= ((blue >> 12) & 0x00f);
528
529 if (regno == 0)
530 val |= palette_pbs(&fbi->fb.var);
531
532 fbi->palette_cpu[regno] = val;
533 ret = 0;
534 }
535 return ret;
536}
537
538static int
539sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
540 u_int trans, struct fb_info *info)
541{
542 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
543 unsigned int val;
544 int ret = 1;
545
546 /*
547 * If inverse mode was selected, invert all the colours
548 * rather than the register number. The register number
549 * is what you poke into the framebuffer to produce the
550 * colour you requested.
551 */
552 if (fbi->cmap_inverse) {
553 red = 0xffff - red;
554 green = 0xffff - green;
555 blue = 0xffff - blue;
556 }
557
558 /*
559 * If greyscale is true, then we convert the RGB value
560 * to greyscale no mater what visual we are using.
561 */
562 if (fbi->fb.var.grayscale)
563 red = green = blue = (19595 * red + 38470 * green +
564 7471 * blue) >> 16;
565
566 switch (fbi->fb.fix.visual) {
567 case FB_VISUAL_TRUECOLOR:
568 /*
569 * 12 or 16-bit True Colour. We encode the RGB value
570 * according to the RGB bitfield information.
571 */
572 if (regno < 16) {
573 u32 *pal = fbi->fb.pseudo_palette;
574
575 val = chan_to_field(red, &fbi->fb.var.red);
576 val |= chan_to_field(green, &fbi->fb.var.green);
577 val |= chan_to_field(blue, &fbi->fb.var.blue);
578
579 pal[regno] = val;
580 ret = 0;
581 }
582 break;
583
584 case FB_VISUAL_STATIC_PSEUDOCOLOR:
585 case FB_VISUAL_PSEUDOCOLOR:
586 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
587 break;
588 }
589
590 return ret;
591}
592
Pavel Machek6edb7462005-10-14 15:59:01 -0700593#ifdef CONFIG_CPU_FREQ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594/*
595 * sa1100fb_display_dma_period()
596 * Calculate the minimum period (in picoseconds) between two DMA
597 * requests for the LCD controller. If we hit this, it means we're
598 * doing nothing but LCD DMA.
599 */
Russell Kingfc1df372005-08-07 14:20:26 +0100600static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601{
602 /*
603 * Period = pixclock * bits_per_byte * bytes_per_transfer
604 * / memory_bits_per_pixel;
605 */
606 return var->pixclock * 8 * 16 / var->bits_per_pixel;
607}
Pavel Machek6edb7462005-10-14 15:59:01 -0700608#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609
610/*
611 * sa1100fb_check_var():
612 * Round up in the following order: bits_per_pixel, xres,
613 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
614 * bitfields, horizontal timing, vertical timing.
615 */
616static int
617sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
618{
619 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
620 int rgbidx;
621
622 if (var->xres < MIN_XRES)
623 var->xres = MIN_XRES;
624 if (var->yres < MIN_YRES)
625 var->yres = MIN_YRES;
626 if (var->xres > fbi->max_xres)
627 var->xres = fbi->max_xres;
628 if (var->yres > fbi->max_yres)
629 var->yres = fbi->max_yres;
630 var->xres_virtual = max(var->xres_virtual, var->xres);
631 var->yres_virtual = max(var->yres_virtual, var->yres);
632
633 DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
634 switch (var->bits_per_pixel) {
635 case 4:
636 rgbidx = RGB_8;
637 break;
638 case 8:
639 rgbidx = RGB_8;
640 break;
641 case 16:
642 rgbidx = RGB_16;
643 break;
644 default:
645 return -EINVAL;
646 }
647
648 /*
649 * Copy the RGB parameters for this display
650 * from the machine specific parameters.
651 */
652 var->red = fbi->rgb[rgbidx]->red;
653 var->green = fbi->rgb[rgbidx]->green;
654 var->blue = fbi->rgb[rgbidx]->blue;
655 var->transp = fbi->rgb[rgbidx]->transp;
656
657 DPRINTK("RGBT length = %d:%d:%d:%d\n",
658 var->red.length, var->green.length, var->blue.length,
659 var->transp.length);
660
661 DPRINTK("RGBT offset = %d:%d:%d:%d\n",
662 var->red.offset, var->green.offset, var->blue.offset,
663 var->transp.offset);
664
665#ifdef CONFIG_CPU_FREQ
666 printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
667 sa1100fb_display_dma_period(var),
668 cpufreq_get(smp_processor_id()));
669#endif
670
671 return 0;
672}
673
674static inline void sa1100fb_set_truecolor(u_int is_true_color)
675{
676 if (machine_is_assabet()) {
677#if 1 // phase 4 or newer Assabet's
678 if (is_true_color)
679 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
680 else
681 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
682#else
683 // older Assabet's
684 if (is_true_color)
685 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
686 else
687 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
688#endif
689 }
690}
691
692/*
693 * sa1100fb_set_par():
694 * Set the user defined part of the display for the specified console
695 */
696static int sa1100fb_set_par(struct fb_info *info)
697{
698 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
699 struct fb_var_screeninfo *var = &info->var;
700 unsigned long palette_mem_size;
701
702 DPRINTK("set_par\n");
703
704 if (var->bits_per_pixel == 16)
705 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
706 else if (!fbi->cmap_static)
707 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
708 else {
709 /*
710 * Some people have weird ideas about wanting static
711 * pseudocolor maps. I suspect their user space
712 * applications are broken.
713 */
714 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
715 }
716
717 fbi->fb.fix.line_length = var->xres_virtual *
718 var->bits_per_pixel / 8;
719 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
720
721 palette_mem_size = fbi->palette_size * sizeof(u16);
722
723 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
724
725 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
726 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
727
728 /*
729 * Set (any) board control register to handle new color depth
730 */
731 sa1100fb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
732 sa1100fb_activate_var(var, fbi);
733
734 return 0;
735}
736
737#if 0
738static int
739sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
740 struct fb_info *info)
741{
742 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
743
744 /*
745 * Make sure the user isn't doing something stupid.
746 */
747 if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->cmap_static))
748 return -EINVAL;
749
750 return gen_set_cmap(cmap, kspc, con, info);
751}
752#endif
753
754/*
755 * Formal definition of the VESA spec:
756 * On
757 * This refers to the state of the display when it is in full operation
758 * Stand-By
759 * This defines an optional operating state of minimal power reduction with
760 * the shortest recovery time
761 * Suspend
762 * This refers to a level of power management in which substantial power
763 * reduction is achieved by the display. The display can have a longer
764 * recovery time from this state than from the Stand-by state
765 * Off
766 * This indicates that the display is consuming the lowest level of power
767 * and is non-operational. Recovery from this state may optionally require
768 * the user to manually power on the monitor
769 *
770 * Now, the fbdev driver adds an additional state, (blank), where they
771 * turn off the video (maybe by colormap tricks), but don't mess with the
772 * video itself: think of it semantically between on and Stand-By.
773 *
774 * So here's what we should do in our fbdev blank routine:
775 *
776 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
777 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
778 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
779 * VESA_POWERDOWN (mode 3) Video off, front/back light off
780 *
781 * This will match the matrox implementation.
782 */
783/*
784 * sa1100fb_blank():
785 * Blank the display by setting all palette values to zero. Note, the
786 * 12 and 16 bpp modes don't really use the palette, so this will not
787 * blank the display in all modes.
788 */
789static int sa1100fb_blank(int blank, struct fb_info *info)
790{
791 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
792 int i;
793
794 DPRINTK("sa1100fb_blank: blank=%d\n", blank);
795
796 switch (blank) {
797 case FB_BLANK_POWERDOWN:
798 case FB_BLANK_VSYNC_SUSPEND:
799 case FB_BLANK_HSYNC_SUSPEND:
800 case FB_BLANK_NORMAL:
801 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
802 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
803 for (i = 0; i < fbi->palette_size; i++)
804 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
805 sa1100fb_schedule_work(fbi, C_DISABLE);
806 break;
807
808 case FB_BLANK_UNBLANK:
809 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
810 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
811 fb_set_cmap(&fbi->fb.cmap, info);
812 sa1100fb_schedule_work(fbi, C_ENABLE);
813 }
814 return 0;
815}
816
Christoph Hellwig216d5262006-01-14 13:21:25 -0800817static int sa1100fb_mmap(struct fb_info *info,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 struct vm_area_struct *vma)
819{
820 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
821 unsigned long start, len, off = vma->vm_pgoff << PAGE_SHIFT;
822
823 if (off < info->fix.smem_len) {
824 vma->vm_pgoff += 1; /* skip over the palette */
825 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
826 fbi->map_dma, fbi->map_size);
827 }
828
829 start = info->fix.mmio_start;
830 len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.mmio_len);
831
832 if ((vma->vm_end - vma->vm_start + off) > len)
833 return -EINVAL;
834
835 off += start & PAGE_MASK;
836 vma->vm_pgoff = off >> PAGE_SHIFT;
837 vma->vm_flags |= VM_IO;
838 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
839 return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
840 vma->vm_end - vma->vm_start,
841 vma->vm_page_prot);
842}
843
844static struct fb_ops sa1100fb_ops = {
845 .owner = THIS_MODULE,
846 .fb_check_var = sa1100fb_check_var,
847 .fb_set_par = sa1100fb_set_par,
848// .fb_set_cmap = sa1100fb_set_cmap,
849 .fb_setcolreg = sa1100fb_setcolreg,
850 .fb_fillrect = cfb_fillrect,
851 .fb_copyarea = cfb_copyarea,
852 .fb_imageblit = cfb_imageblit,
853 .fb_blank = sa1100fb_blank,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 .fb_mmap = sa1100fb_mmap,
855};
856
857/*
858 * Calculate the PCD value from the clock rate (in picoseconds).
859 * We take account of the PPCR clock setting.
860 */
861static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
862{
863 unsigned int pcd = cpuclock / 100;
864
865 pcd *= pixclock;
866 pcd /= 10000000;
867
868 return pcd + 1; /* make up for integer math truncations */
869}
870
871/*
872 * sa1100fb_activate_var():
873 * Configures LCD Controller based on entries in var parameter. Settings are
874 * only written to the controller if changes were made.
875 */
876static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
877{
878 struct sa1100fb_lcd_reg new_regs;
879 u_int half_screen_size, yres, pcd;
880 u_long flags;
881
882 DPRINTK("Configuring SA1100 LCD\n");
883
884 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
885 var->xres, var->hsync_len,
886 var->left_margin, var->right_margin);
887 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
888 var->yres, var->vsync_len,
889 var->upper_margin, var->lower_margin);
890
891#if DEBUG_VAR
892 if (var->xres < 16 || var->xres > 1024)
893 printk(KERN_ERR "%s: invalid xres %d\n",
894 fbi->fb.fix.id, var->xres);
895 if (var->hsync_len < 1 || var->hsync_len > 64)
896 printk(KERN_ERR "%s: invalid hsync_len %d\n",
897 fbi->fb.fix.id, var->hsync_len);
898 if (var->left_margin < 1 || var->left_margin > 255)
899 printk(KERN_ERR "%s: invalid left_margin %d\n",
900 fbi->fb.fix.id, var->left_margin);
901 if (var->right_margin < 1 || var->right_margin > 255)
902 printk(KERN_ERR "%s: invalid right_margin %d\n",
903 fbi->fb.fix.id, var->right_margin);
904 if (var->yres < 1 || var->yres > 1024)
905 printk(KERN_ERR "%s: invalid yres %d\n",
906 fbi->fb.fix.id, var->yres);
907 if (var->vsync_len < 1 || var->vsync_len > 64)
908 printk(KERN_ERR "%s: invalid vsync_len %d\n",
909 fbi->fb.fix.id, var->vsync_len);
910 if (var->upper_margin < 0 || var->upper_margin > 255)
911 printk(KERN_ERR "%s: invalid upper_margin %d\n",
912 fbi->fb.fix.id, var->upper_margin);
913 if (var->lower_margin < 0 || var->lower_margin > 255)
914 printk(KERN_ERR "%s: invalid lower_margin %d\n",
915 fbi->fb.fix.id, var->lower_margin);
916#endif
917
918 new_regs.lccr0 = fbi->lccr0 |
919 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
920 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
921
922 new_regs.lccr1 =
923 LCCR1_DisWdth(var->xres) +
924 LCCR1_HorSnchWdth(var->hsync_len) +
925 LCCR1_BegLnDel(var->left_margin) +
926 LCCR1_EndLnDel(var->right_margin);
927
928 /*
929 * If we have a dual scan LCD, then we need to halve
930 * the YRES parameter.
931 */
932 yres = var->yres;
933 if (fbi->lccr0 & LCCR0_Dual)
934 yres /= 2;
935
936 new_regs.lccr2 =
937 LCCR2_DisHght(yres) +
938 LCCR2_VrtSnchWdth(var->vsync_len) +
939 LCCR2_BegFrmDel(var->upper_margin) +
940 LCCR2_EndFrmDel(var->lower_margin);
941
942 pcd = get_pcd(var->pixclock, cpufreq_get(0));
943 new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 |
944 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
945 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
946
947 DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0);
948 DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1);
949 DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2);
950 DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3);
951
952 half_screen_size = var->bits_per_pixel;
953 half_screen_size = half_screen_size * var->xres * var->yres / 16;
954
955 /* Update shadow copy atomically */
956 local_irq_save(flags);
957 fbi->dbar1 = fbi->palette_dma;
958 fbi->dbar2 = fbi->screen_dma + half_screen_size;
959
960 fbi->reg_lccr0 = new_regs.lccr0;
961 fbi->reg_lccr1 = new_regs.lccr1;
962 fbi->reg_lccr2 = new_regs.lccr2;
963 fbi->reg_lccr3 = new_regs.lccr3;
964 local_irq_restore(flags);
965
966 /*
967 * Only update the registers if the controller is enabled
968 * and something has changed.
969 */
970 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
971 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
972 (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
973 sa1100fb_schedule_work(fbi, C_REENABLE);
974
975 return 0;
976}
977
978/*
979 * NOTE! The following functions are purely helpers for set_ctrlr_state.
980 * Do not call them directly; set_ctrlr_state does the correct serialisation
981 * to ensure that things happen in the right way 100% of time time.
982 * -- rmk
983 */
984static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
985{
986 DPRINTK("backlight o%s\n", on ? "n" : "ff");
987
988 if (sa1100fb_backlight_power)
989 sa1100fb_backlight_power(on);
990}
991
992static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
993{
994 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
995
996 if (sa1100fb_lcd_power)
997 sa1100fb_lcd_power(on);
998}
999
1000static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
1001{
1002 u_int mask = 0;
1003
1004 /*
1005 * Enable GPIO<9:2> for LCD use if:
1006 * 1. Active display, or
1007 * 2. Color Dual Passive display
1008 *
1009 * see table 11.8 on page 11-27 in the SA1100 manual
1010 * -- Erik.
1011 *
1012 * SA1110 spec update nr. 25 says we can and should
1013 * clear LDD15 to 12 for 4 or 8bpp modes with active
1014 * panels.
1015 */
1016 if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
1017 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
1018 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
1019
1020 if (fbi->fb.var.bits_per_pixel > 8 ||
1021 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
1022 mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
1023
1024 }
1025
1026 if (mask) {
1027 GPDR |= mask;
1028 GAFR |= mask;
1029 }
1030}
1031
1032static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
1033{
1034 DPRINTK("Enabling LCD controller\n");
1035
1036 /*
1037 * Make sure the mode bits are present in the first palette entry
1038 */
1039 fbi->palette_cpu[0] &= 0xcfff;
1040 fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
1041
1042 /* Sequence from 11.7.10 */
1043 LCCR3 = fbi->reg_lccr3;
1044 LCCR2 = fbi->reg_lccr2;
1045 LCCR1 = fbi->reg_lccr1;
1046 LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
1047 DBAR1 = fbi->dbar1;
1048 DBAR2 = fbi->dbar2;
1049 LCCR0 |= LCCR0_LEN;
1050
1051 if (machine_is_shannon()) {
1052 GPDR |= SHANNON_GPIO_DISP_EN;
1053 GPSR |= SHANNON_GPIO_DISP_EN;
1054 }
1055
1056 DPRINTK("DBAR1 = 0x%08x\n", DBAR1);
1057 DPRINTK("DBAR2 = 0x%08x\n", DBAR2);
1058 DPRINTK("LCCR0 = 0x%08x\n", LCCR0);
1059 DPRINTK("LCCR1 = 0x%08x\n", LCCR1);
1060 DPRINTK("LCCR2 = 0x%08x\n", LCCR2);
1061 DPRINTK("LCCR3 = 0x%08x\n", LCCR3);
1062}
1063
1064static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
1065{
1066 DECLARE_WAITQUEUE(wait, current);
1067
1068 DPRINTK("Disabling LCD controller\n");
1069
1070 if (machine_is_shannon()) {
1071 GPCR |= SHANNON_GPIO_DISP_EN;
1072 }
1073
1074 set_current_state(TASK_UNINTERRUPTIBLE);
1075 add_wait_queue(&fbi->ctrlr_wait, &wait);
1076
1077 LCSR = 0xffffffff; /* Clear LCD Status Register */
1078 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
1079 LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */
1080
1081 schedule_timeout(20 * HZ / 1000);
1082 remove_wait_queue(&fbi->ctrlr_wait, &wait);
1083}
1084
1085/*
1086 * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
1087 */
1088static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
1089{
1090 struct sa1100fb_info *fbi = dev_id;
1091 unsigned int lcsr = LCSR;
1092
1093 if (lcsr & LCSR_LDD) {
1094 LCCR0 |= LCCR0_LDM;
1095 wake_up(&fbi->ctrlr_wait);
1096 }
1097
1098 LCSR = lcsr;
1099 return IRQ_HANDLED;
1100}
1101
1102/*
1103 * This function must be called from task context only, since it will
1104 * sleep when disabling the LCD controller, or if we get two contending
1105 * processes trying to alter state.
1106 */
1107static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
1108{
1109 u_int old_state;
1110
1111 down(&fbi->ctrlr_sem);
1112
1113 old_state = fbi->state;
1114
1115 /*
1116 * Hack around fbcon initialisation.
1117 */
1118 if (old_state == C_STARTUP && state == C_REENABLE)
1119 state = C_ENABLE;
1120
1121 switch (state) {
1122 case C_DISABLE_CLKCHANGE:
1123 /*
1124 * Disable controller for clock change. If the
1125 * controller is already disabled, then do nothing.
1126 */
1127 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1128 fbi->state = state;
1129 sa1100fb_disable_controller(fbi);
1130 }
1131 break;
1132
1133 case C_DISABLE_PM:
1134 case C_DISABLE:
1135 /*
1136 * Disable controller
1137 */
1138 if (old_state != C_DISABLE) {
1139 fbi->state = state;
1140
1141 __sa1100fb_backlight_power(fbi, 0);
1142 if (old_state != C_DISABLE_CLKCHANGE)
1143 sa1100fb_disable_controller(fbi);
1144 __sa1100fb_lcd_power(fbi, 0);
1145 }
1146 break;
1147
1148 case C_ENABLE_CLKCHANGE:
1149 /*
1150 * Enable the controller after clock change. Only
1151 * do this if we were disabled for the clock change.
1152 */
1153 if (old_state == C_DISABLE_CLKCHANGE) {
1154 fbi->state = C_ENABLE;
1155 sa1100fb_enable_controller(fbi);
1156 }
1157 break;
1158
1159 case C_REENABLE:
1160 /*
1161 * Re-enable the controller only if it was already
1162 * enabled. This is so we reprogram the control
1163 * registers.
1164 */
1165 if (old_state == C_ENABLE) {
1166 sa1100fb_disable_controller(fbi);
1167 sa1100fb_setup_gpio(fbi);
1168 sa1100fb_enable_controller(fbi);
1169 }
1170 break;
1171
1172 case C_ENABLE_PM:
1173 /*
1174 * Re-enable the controller after PM. This is not
1175 * perfect - think about the case where we were doing
1176 * a clock change, and we suspended half-way through.
1177 */
1178 if (old_state != C_DISABLE_PM)
1179 break;
1180 /* fall through */
1181
1182 case C_ENABLE:
1183 /*
1184 * Power up the LCD screen, enable controller, and
1185 * turn on the backlight.
1186 */
1187 if (old_state != C_ENABLE) {
1188 fbi->state = C_ENABLE;
1189 sa1100fb_setup_gpio(fbi);
1190 __sa1100fb_lcd_power(fbi, 1);
1191 sa1100fb_enable_controller(fbi);
1192 __sa1100fb_backlight_power(fbi, 1);
1193 }
1194 break;
1195 }
1196 up(&fbi->ctrlr_sem);
1197}
1198
1199/*
1200 * Our LCD controller task (which is called when we blank or unblank)
1201 * via keventd.
1202 */
1203static void sa1100fb_task(void *dummy)
1204{
1205 struct sa1100fb_info *fbi = dummy;
1206 u_int state = xchg(&fbi->task_state, -1);
1207
1208 set_ctrlr_state(fbi, state);
1209}
1210
1211#ifdef CONFIG_CPU_FREQ
1212/*
1213 * Calculate the minimum DMA period over all displays that we own.
1214 * This, together with the SDRAM bandwidth defines the slowest CPU
1215 * frequency that can be selected.
1216 */
1217static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
1218{
1219#if 0
1220 unsigned int min_period = (unsigned int)-1;
1221 int i;
1222
1223 for (i = 0; i < MAX_NR_CONSOLES; i++) {
1224 struct display *disp = &fb_display[i];
1225 unsigned int period;
1226
1227 /*
1228 * Do we own this display?
1229 */
1230 if (disp->fb_info != &fbi->fb)
1231 continue;
1232
1233 /*
1234 * Ok, calculate its DMA period
1235 */
1236 period = sa1100fb_display_dma_period(&disp->var);
1237 if (period < min_period)
1238 min_period = period;
1239 }
1240
1241 return min_period;
1242#else
1243 /*
1244 * FIXME: we need to verify _all_ consoles.
1245 */
1246 return sa1100fb_display_dma_period(&fbi->fb.var);
1247#endif
1248}
1249
1250/*
1251 * CPU clock speed change handler. We need to adjust the LCD timing
1252 * parameters when the CPU clock is adjusted by the power management
1253 * subsystem.
1254 */
1255static int
1256sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
1257 void *data)
1258{
1259 struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
1260 struct cpufreq_freqs *f = data;
1261 u_int pcd;
1262
1263 switch (val) {
1264 case CPUFREQ_PRECHANGE:
1265 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1266 break;
1267
1268 case CPUFREQ_POSTCHANGE:
1269 pcd = get_pcd(fbi->fb.var.pixclock, f->new);
1270 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1271 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1272 break;
1273 }
1274 return 0;
1275}
1276
1277static int
1278sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
1279 void *data)
1280{
1281 struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
1282 struct cpufreq_policy *policy = data;
1283
1284 switch (val) {
1285 case CPUFREQ_ADJUST:
1286 case CPUFREQ_INCOMPATIBLE:
1287 printk(KERN_DEBUG "min dma period: %d ps, "
1288 "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
1289 policy->max);
1290 /* todo: fill in min/max values */
1291 break;
1292 case CPUFREQ_NOTIFY:
1293 do {} while(0);
1294 /* todo: panic if min/max values aren't fulfilled
1295 * [can't really happen unless there's a bug in the
1296 * CPU policy verififcation process *
1297 */
1298 break;
1299 }
1300 return 0;
1301}
1302#endif
1303
1304#ifdef CONFIG_PM
1305/*
1306 * Power management hooks. Note that we won't be called from IRQ context,
1307 * unlike the blank functions above, so we may sleep.
1308 */
Russell King3ae5eae2005-11-09 22:32:44 +00001309static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001310{
Russell King3ae5eae2005-11-09 22:32:44 +00001311 struct sa1100fb_info *fbi = platform_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001312
Russell King9480e302005-10-28 09:52:56 -07001313 set_ctrlr_state(fbi, C_DISABLE_PM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314 return 0;
1315}
1316
Russell King3ae5eae2005-11-09 22:32:44 +00001317static int sa1100fb_resume(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318{
Russell King3ae5eae2005-11-09 22:32:44 +00001319 struct sa1100fb_info *fbi = platform_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320
Russell King9480e302005-10-28 09:52:56 -07001321 set_ctrlr_state(fbi, C_ENABLE_PM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 return 0;
1323}
1324#else
1325#define sa1100fb_suspend NULL
1326#define sa1100fb_resume NULL
1327#endif
1328
1329/*
1330 * sa1100fb_map_video_memory():
1331 * Allocates the DRAM memory for the frame buffer. This buffer is
1332 * remapped into a non-cached, non-buffered, memory region to
1333 * allow palette and pixel writes to occur without flushing the
1334 * cache. Once this area is remapped, all virtual memory
1335 * access to the video memory should occur at the new region.
1336 */
1337static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
1338{
1339 /*
1340 * We reserve one page for the palette, plus the size
1341 * of the framebuffer.
1342 */
1343 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1344 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1345 &fbi->map_dma, GFP_KERNEL);
1346
1347 if (fbi->map_cpu) {
1348 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1349 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1350 /*
1351 * FIXME: this is actually the wrong thing to place in
1352 * smem_start. But fbdev suffers from the problem that
1353 * it needs an API which doesn't exist (in this case,
1354 * dma_writecombine_mmap)
1355 */
1356 fbi->fb.fix.smem_start = fbi->screen_dma;
1357 }
1358
1359 return fbi->map_cpu ? 0 : -ENOMEM;
1360}
1361
1362/* Fake monspecs to fill in fbinfo structure */
1363static struct fb_monspecs monspecs __initdata = {
1364 .hfmin = 30000,
1365 .hfmax = 70000,
1366 .vfmin = 50,
1367 .vfmax = 65,
1368};
1369
1370
1371static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev)
1372{
1373 struct sa1100fb_mach_info *inf;
1374 struct sa1100fb_info *fbi;
1375
1376 fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
1377 GFP_KERNEL);
1378 if (!fbi)
1379 return NULL;
1380
1381 memset(fbi, 0, sizeof(struct sa1100fb_info));
1382 fbi->dev = dev;
1383
1384 strcpy(fbi->fb.fix.id, SA1100_NAME);
1385
1386 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1387 fbi->fb.fix.type_aux = 0;
1388 fbi->fb.fix.xpanstep = 0;
1389 fbi->fb.fix.ypanstep = 0;
1390 fbi->fb.fix.ywrapstep = 0;
1391 fbi->fb.fix.accel = FB_ACCEL_NONE;
1392
1393 fbi->fb.var.nonstd = 0;
1394 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1395 fbi->fb.var.height = -1;
1396 fbi->fb.var.width = -1;
1397 fbi->fb.var.accel_flags = 0;
1398 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1399
1400 fbi->fb.fbops = &sa1100fb_ops;
1401 fbi->fb.flags = FBINFO_DEFAULT;
1402 fbi->fb.monspecs = monspecs;
1403 fbi->fb.pseudo_palette = (fbi + 1);
1404
1405 fbi->rgb[RGB_8] = &rgb_8;
1406 fbi->rgb[RGB_16] = &def_rgb_16;
1407
1408 inf = sa1100fb_get_machine_info(fbi);
1409
1410 /*
1411 * People just don't seem to get this. We don't support
1412 * anything but correct entries now, so panic if someone
1413 * does something stupid.
1414 */
1415 if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
1416 inf->pixclock == 0)
1417 panic("sa1100fb error: invalid LCCR3 fields set or zero "
1418 "pixclock.");
1419
1420 fbi->max_xres = inf->xres;
1421 fbi->fb.var.xres = inf->xres;
1422 fbi->fb.var.xres_virtual = inf->xres;
1423 fbi->max_yres = inf->yres;
1424 fbi->fb.var.yres = inf->yres;
1425 fbi->fb.var.yres_virtual = inf->yres;
1426 fbi->max_bpp = inf->bpp;
1427 fbi->fb.var.bits_per_pixel = inf->bpp;
1428 fbi->fb.var.pixclock = inf->pixclock;
1429 fbi->fb.var.hsync_len = inf->hsync_len;
1430 fbi->fb.var.left_margin = inf->left_margin;
1431 fbi->fb.var.right_margin = inf->right_margin;
1432 fbi->fb.var.vsync_len = inf->vsync_len;
1433 fbi->fb.var.upper_margin = inf->upper_margin;
1434 fbi->fb.var.lower_margin = inf->lower_margin;
1435 fbi->fb.var.sync = inf->sync;
1436 fbi->fb.var.grayscale = inf->cmap_greyscale;
1437 fbi->cmap_inverse = inf->cmap_inverse;
1438 fbi->cmap_static = inf->cmap_static;
1439 fbi->lccr0 = inf->lccr0;
1440 fbi->lccr3 = inf->lccr3;
1441 fbi->state = C_STARTUP;
1442 fbi->task_state = (u_char)-1;
1443 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1444 fbi->max_bpp / 8;
1445
1446 init_waitqueue_head(&fbi->ctrlr_wait);
1447 INIT_WORK(&fbi->task, sa1100fb_task, fbi);
1448 init_MUTEX(&fbi->ctrlr_sem);
1449
1450 return fbi;
1451}
1452
Russell King3ae5eae2005-11-09 22:32:44 +00001453static int __init sa1100fb_probe(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454{
1455 struct sa1100fb_info *fbi;
Russell Kinge9368f82006-01-09 13:56:42 +00001456 int ret, irq;
1457
1458 irq = platform_get_irq(pdev, 0);
David Vrabel48944732006-01-19 17:56:29 +00001459 if (irq < 0)
Russell Kinge9368f82006-01-09 13:56:42 +00001460 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461
1462 if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
1463 return -EBUSY;
1464
Russell King3ae5eae2005-11-09 22:32:44 +00001465 fbi = sa1100fb_init_fbinfo(&pdev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466 ret = -ENOMEM;
1467 if (!fbi)
1468 goto failed;
1469
1470 /* Initialize video memory */
1471 ret = sa1100fb_map_video_memory(fbi);
1472 if (ret)
1473 goto failed;
1474
Thomas Gleixner63a43392006-07-01 19:29:45 -07001475 ret = request_irq(irq, sa1100fb_handle_irq, IRQF_DISABLED,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 "LCD", fbi);
1477 if (ret) {
1478 printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
1479 goto failed;
1480 }
1481
1482#ifdef ASSABET_PAL_VIDEO
1483 if (machine_is_assabet())
1484 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
1485#endif
1486
1487 /*
1488 * This makes sure that our colour bitfield
1489 * descriptors are correctly initialised.
1490 */
1491 sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
1492
Russell King3ae5eae2005-11-09 22:32:44 +00001493 platform_set_drvdata(pdev, fbi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494
1495 ret = register_framebuffer(&fbi->fb);
1496 if (ret < 0)
Russell Kinge9368f82006-01-09 13:56:42 +00001497 goto err_free_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498
1499#ifdef CONFIG_CPU_FREQ
1500 fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
1501 fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
1502 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1503 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1504#endif
1505
1506 /* This driver cannot be unloaded at the moment */
1507 return 0;
1508
Russell Kinge9368f82006-01-09 13:56:42 +00001509 err_free_irq:
1510 free_irq(irq, fbi);
1511 failed:
Russell King3ae5eae2005-11-09 22:32:44 +00001512 platform_set_drvdata(pdev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513 kfree(fbi);
1514 release_mem_region(0xb0100000, 0x10000);
1515 return ret;
1516}
1517
Russell King3ae5eae2005-11-09 22:32:44 +00001518static struct platform_driver sa1100fb_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 .probe = sa1100fb_probe,
1520 .suspend = sa1100fb_suspend,
1521 .resume = sa1100fb_resume,
Russell King3ae5eae2005-11-09 22:32:44 +00001522 .driver = {
1523 .name = "sa11x0-fb",
1524 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525};
1526
1527int __init sa1100fb_init(void)
1528{
1529 if (fb_get_options("sa1100fb", NULL))
1530 return -ENODEV;
1531
Russell King3ae5eae2005-11-09 22:32:44 +00001532 return platform_driver_register(&sa1100fb_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533}
1534
1535int __init sa1100fb_setup(char *options)
1536{
1537#if 0
1538 char *this_opt;
1539
1540 if (!options || !*options)
1541 return 0;
1542
1543 while ((this_opt = strsep(&options, ",")) != NULL) {
1544
1545 if (!strncmp(this_opt, "bpp:", 4))
1546 current_par.max_bpp =
1547 simple_strtoul(this_opt + 4, NULL, 0);
1548
1549 if (!strncmp(this_opt, "lccr0:", 6))
1550 lcd_shadow.lccr0 =
1551 simple_strtoul(this_opt + 6, NULL, 0);
1552 if (!strncmp(this_opt, "lccr1:", 6)) {
1553 lcd_shadow.lccr1 =
1554 simple_strtoul(this_opt + 6, NULL, 0);
1555 current_par.max_xres =
1556 (lcd_shadow.lccr1 & 0x3ff) + 16;
1557 }
1558 if (!strncmp(this_opt, "lccr2:", 6)) {
1559 lcd_shadow.lccr2 =
1560 simple_strtoul(this_opt + 6, NULL, 0);
1561 current_par.max_yres =
1562 (lcd_shadow.
1563 lccr0 & LCCR0_SDS) ? ((lcd_shadow.
1564 lccr2 & 0x3ff) +
1565 1) *
1566 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
1567 }
1568 if (!strncmp(this_opt, "lccr3:", 6))
1569 lcd_shadow.lccr3 =
1570 simple_strtoul(this_opt + 6, NULL, 0);
1571 }
1572#endif
1573 return 0;
1574}
1575
1576module_init(sa1100fb_init);
1577MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
1578MODULE_LICENSE("GPL");