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Tero Kristo0a84a912011-12-16 14:36:58 -07001/*
2 * OMAP2+ common Power & Reset Management (PRM) IP block functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Tero Kristo <t-kristo@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *
12 * For historical purposes, the API used to configure the PRM
13 * interrupt handler refers to it as the "PRCM interrupt." The
14 * underlying registers are located in the PRM on OMAP3/4.
15 *
16 * XXX This code should eventually be moved to a PRM driver.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/interrupt.h>
25#include <linux/slab.h>
Tero Kristo943a63a2013-10-25 15:28:11 +030026#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/clk-provider.h>
29#include <linux/clk/ti.h>
Tero Kristo0a84a912011-12-16 14:36:58 -070030
Tony Lindgren30a69ef2013-10-10 15:45:13 -070031#include "soc.h"
Tero Kristo0a84a912011-12-16 14:36:58 -070032#include "prm2xxx_3xxx.h"
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -060033#include "prm2xxx.h"
34#include "prm3xxx.h"
Tero Kristoab7b2ff2014-11-20 15:02:59 +020035#include "prm33xx.h"
Tero Kristo0a84a912011-12-16 14:36:58 -070036#include "prm44xx.h"
Paul Walmsleyd9a16f92012-10-29 20:57:39 -060037#include "common.h"
Tero Kristo943a63a2013-10-25 15:28:11 +030038#include "clock.h"
Tero Kristo3dbb0482014-12-16 18:20:54 +020039#include "cm.h"
40#include "control.h"
Tero Kristo0a84a912011-12-16 14:36:58 -070041
42/*
43 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
44 * XXX this is technically not needed, since
45 * omap_prcm_register_chain_handler() could allocate this based on the
46 * actual amount of memory needed for the SoC
47 */
48#define OMAP_PRCM_MAX_NR_PENDING_REG 2
49
50/*
51 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
52 * by the PRCM interrupt handler code. There will be one 'chip' per
53 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
54 * one "chip" and OMAP4 will have two.)
55 */
56static struct irq_chip_generic **prcm_irq_chips;
57
58/*
59 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
60 * is currently running on. Defined and passed by initialization code
61 * that calls omap_prcm_register_chain_handler().
62 */
63static struct omap_prcm_irq_setup *prcm_irq_setup;
64
Paul Walmsleyd9a16f92012-10-29 20:57:39 -060065/* prm_base: base virtual address of the PRM IP block */
66void __iomem *prm_base;
67
Tero Kristo2541d152014-03-31 18:15:44 +030068u16 prm_features;
69
Paul Walmsleye24c3572012-10-21 01:01:11 -060070/*
71 * prm_ll_data: function pointers to SoC-specific implementations of
72 * common PRM functions
73 */
74static struct prm_ll_data null_prm_ll_data;
75static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
76
Tero Kristo0a84a912011-12-16 14:36:58 -070077/* Private functions */
78
79/*
80 * Move priority events from events to priority_events array
81 */
82static void omap_prcm_events_filter_priority(unsigned long *events,
83 unsigned long *priority_events)
84{
85 int i;
86
87 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
88 priority_events[i] =
89 events[i] & prcm_irq_setup->priority_mask[i];
90 events[i] ^= priority_events[i];
91 }
92}
93
94/*
95 * PRCM Interrupt Handler
96 *
97 * This is a common handler for the OMAP PRCM interrupts. Pending
98 * interrupts are detected by a call to prcm_pending_events and
99 * dispatched accordingly. Clearing of the wakeup events should be
100 * done by the SoC specific individual handlers.
101 */
102static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
103{
104 unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
105 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
106 struct irq_chip *chip = irq_desc_get_chip(desc);
107 unsigned int virtirq;
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530108 int nr_irq = prcm_irq_setup->nr_regs * 32;
Tero Kristo0a84a912011-12-16 14:36:58 -0700109
110 /*
Tero Kristo91285b62011-12-16 14:36:58 -0700111 * If we are suspended, mask all interrupts from PRCM level,
112 * this does not ack them, and they will be pending until we
113 * re-enable the interrupts, at which point the
114 * omap_prcm_irq_handler will be executed again. The
115 * _save_and_clear_irqen() function must ensure that the PRM
116 * write to disable all IRQs has reached the PRM before
117 * returning, or spurious PRCM interrupts may occur during
118 * suspend.
119 */
120 if (prcm_irq_setup->suspended) {
121 prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
122 prcm_irq_setup->suspend_save_flag = true;
123 }
124
125 /*
Tero Kristo0a84a912011-12-16 14:36:58 -0700126 * Loop until all pending irqs are handled, since
127 * generic_handle_irq() can cause new irqs to come
128 */
Tero Kristo91285b62011-12-16 14:36:58 -0700129 while (!prcm_irq_setup->suspended) {
Tero Kristo0a84a912011-12-16 14:36:58 -0700130 prcm_irq_setup->read_pending_irqs(pending);
131
132 /* No bit set, then all IRQs are handled */
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530133 if (find_first_bit(pending, nr_irq) >= nr_irq)
Tero Kristo0a84a912011-12-16 14:36:58 -0700134 break;
135
136 omap_prcm_events_filter_priority(pending, priority_pending);
137
138 /*
139 * Loop on all currently pending irqs so that new irqs
140 * cannot starve previously pending irqs
141 */
142
143 /* Serve priority events first */
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530144 for_each_set_bit(virtirq, priority_pending, nr_irq)
Tero Kristo0a84a912011-12-16 14:36:58 -0700145 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
146
147 /* Serve normal events next */
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530148 for_each_set_bit(virtirq, pending, nr_irq)
Tero Kristo0a84a912011-12-16 14:36:58 -0700149 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
150 }
151 if (chip->irq_ack)
152 chip->irq_ack(&desc->irq_data);
153 if (chip->irq_eoi)
154 chip->irq_eoi(&desc->irq_data);
155 chip->irq_unmask(&desc->irq_data);
156
157 prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
158}
159
160/* Public functions */
161
162/**
163 * omap_prcm_event_to_irq - given a PRCM event name, returns the
164 * corresponding IRQ on which the handler should be registered
165 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
166 *
167 * Returns the Linux internal IRQ ID corresponding to @name upon success,
168 * or -ENOENT upon failure.
169 */
170int omap_prcm_event_to_irq(const char *name)
171{
172 int i;
173
174 if (!prcm_irq_setup || !name)
175 return -ENOENT;
176
177 for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
178 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
179 return prcm_irq_setup->base_irq +
180 prcm_irq_setup->irqs[i].offset;
181
182 return -ENOENT;
183}
184
185/**
186 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
187 * done by omap_prcm_register_chain_handler()
188 *
189 * No return value.
190 */
191void omap_prcm_irq_cleanup(void)
192{
Marc Zyngier0fb22a82015-01-17 10:21:08 +0000193 unsigned int irq;
Tero Kristo0a84a912011-12-16 14:36:58 -0700194 int i;
195
196 if (!prcm_irq_setup) {
197 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
198 return;
199 }
200
201 if (prcm_irq_chips) {
202 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
203 if (prcm_irq_chips[i])
204 irq_remove_generic_chip(prcm_irq_chips[i],
205 0xffffffff, 0, 0);
206 prcm_irq_chips[i] = NULL;
207 }
208 kfree(prcm_irq_chips);
209 prcm_irq_chips = NULL;
210 }
211
Tero Kristo91285b62011-12-16 14:36:58 -0700212 kfree(prcm_irq_setup->saved_mask);
213 prcm_irq_setup->saved_mask = NULL;
214
Tero Kristo0a84a912011-12-16 14:36:58 -0700215 kfree(prcm_irq_setup->priority_mask);
216 prcm_irq_setup->priority_mask = NULL;
217
Marc Zyngier0fb22a82015-01-17 10:21:08 +0000218 if (prcm_irq_setup->xlate_irq)
219 irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq);
220 else
221 irq = prcm_irq_setup->irq;
222 irq_set_chained_handler(irq, NULL);
Tero Kristo0a84a912011-12-16 14:36:58 -0700223
224 if (prcm_irq_setup->base_irq > 0)
225 irq_free_descs(prcm_irq_setup->base_irq,
226 prcm_irq_setup->nr_regs * 32);
227 prcm_irq_setup->base_irq = 0;
228}
229
Tero Kristo91285b62011-12-16 14:36:58 -0700230void omap_prcm_irq_prepare(void)
231{
232 prcm_irq_setup->suspended = true;
233}
234
235void omap_prcm_irq_complete(void)
236{
237 prcm_irq_setup->suspended = false;
238
239 /* If we have not saved the masks, do not attempt to restore */
240 if (!prcm_irq_setup->suspend_save_flag)
241 return;
242
243 prcm_irq_setup->suspend_save_flag = false;
244
245 /*
246 * Re-enable all masked PRCM irq sources, this causes the PRCM
247 * interrupt to fire immediately if the events were masked
248 * previously in the chain handler
249 */
250 prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
251}
252
Tero Kristo0a84a912011-12-16 14:36:58 -0700253/**
254 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
255 * handler based on provided parameters
256 * @irq_setup: hardware data about the underlying PRM/PRCM
257 *
258 * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
259 * one generic IRQ chip per PRM interrupt status/enable register pair.
260 * Returns 0 upon success, -EINVAL if called twice or if invalid
261 * arguments are passed, or -ENOMEM on any other error.
262 */
263int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
264{
Paul Walmsleyeeb37112012-04-13 06:34:32 -0600265 int nr_regs;
Tero Kristo0a84a912011-12-16 14:36:58 -0700266 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
267 int offset, i;
268 struct irq_chip_generic *gc;
269 struct irq_chip_type *ct;
Marc Zyngier0fb22a82015-01-17 10:21:08 +0000270 unsigned int irq;
Tero Kristo0a84a912011-12-16 14:36:58 -0700271
272 if (!irq_setup)
273 return -EINVAL;
274
Paul Walmsleyeeb37112012-04-13 06:34:32 -0600275 nr_regs = irq_setup->nr_regs;
276
Tero Kristo0a84a912011-12-16 14:36:58 -0700277 if (prcm_irq_setup) {
278 pr_err("PRCM: already initialized; won't reinitialize\n");
279 return -EINVAL;
280 }
281
282 if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
283 pr_err("PRCM: nr_regs too large\n");
284 return -EINVAL;
285 }
286
287 prcm_irq_setup = irq_setup;
288
289 prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
Tero Kristo91285b62011-12-16 14:36:58 -0700290 prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
Tero Kristo0a84a912011-12-16 14:36:58 -0700291 prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
292 GFP_KERNEL);
293
Tero Kristo91285b62011-12-16 14:36:58 -0700294 if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
295 !prcm_irq_setup->priority_mask) {
Tero Kristo0a84a912011-12-16 14:36:58 -0700296 pr_err("PRCM: kzalloc failed\n");
297 goto err;
298 }
299
300 memset(mask, 0, sizeof(mask));
301
302 for (i = 0; i < irq_setup->nr_irqs; i++) {
303 offset = irq_setup->irqs[i].offset;
304 mask[offset >> 5] |= 1 << (offset & 0x1f);
305 if (irq_setup->irqs[i].priority)
306 irq_setup->priority_mask[offset >> 5] |=
307 1 << (offset & 0x1f);
308 }
309
Marc Zyngier0fb22a82015-01-17 10:21:08 +0000310 if (irq_setup->xlate_irq)
311 irq = irq_setup->xlate_irq(irq_setup->irq);
312 else
313 irq = irq_setup->irq;
314 irq_set_chained_handler(irq, omap_prcm_irq_handler);
Tero Kristo0a84a912011-12-16 14:36:58 -0700315
316 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
317 0);
318
319 if (irq_setup->base_irq < 0) {
320 pr_err("PRCM: failed to allocate irq descs: %d\n",
321 irq_setup->base_irq);
322 goto err;
323 }
324
Ming Lei4ba7c3c2012-03-22 09:23:37 +0800325 for (i = 0; i < irq_setup->nr_regs; i++) {
Tero Kristo0a84a912011-12-16 14:36:58 -0700326 gc = irq_alloc_generic_chip("PRCM", 1,
327 irq_setup->base_irq + i * 32, prm_base,
328 handle_level_irq);
329
330 if (!gc) {
331 pr_err("PRCM: failed to allocate generic chip\n");
332 goto err;
333 }
334 ct = gc->chip_types;
335 ct->chip.irq_ack = irq_gc_ack_set_bit;
336 ct->chip.irq_mask = irq_gc_mask_clr_bit;
337 ct->chip.irq_unmask = irq_gc_mask_set_bit;
338
339 ct->regs.ack = irq_setup->ack + i * 4;
340 ct->regs.mask = irq_setup->mask + i * 4;
341
342 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
343 prcm_irq_chips[i] = gc;
344 }
345
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700346 if (of_have_populated_dt()) {
347 int irq = omap_prcm_event_to_irq("io");
Tero Kristo81243652014-03-31 18:15:43 +0300348 omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700349 }
350
Tero Kristo0a84a912011-12-16 14:36:58 -0700351 return 0;
352
353err:
354 omap_prcm_irq_cleanup();
355 return -ENOMEM;
356}
R Sricharan3f4990f2012-07-04 05:04:00 -0600357
Paul Walmsleye24c3572012-10-21 01:01:11 -0600358/**
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600359 * omap2_set_globals_prm - set the PRM base address (for early use)
360 * @prm: PRM base virtual address
361 *
362 * XXX Will be replaced when the PRM/CM drivers are completed.
R Sricharan3f4990f2012-07-04 05:04:00 -0600363 */
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600364void __init omap2_set_globals_prm(void __iomem *prm)
R Sricharan3f4990f2012-07-04 05:04:00 -0600365{
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600366 prm_base = prm;
367}
368
369/**
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600370 * prm_read_reset_sources - return the sources of the SoC's last reset
371 *
372 * Return a u32 bitmask representing the reset sources that caused the
373 * SoC to reset. The low-level per-SoC functions called by this
374 * function remap the SoC-specific reset source bits into an
375 * OMAP-common set of reset source bits, defined in
376 * arch/arm/mach-omap2/prm.h. Returns the standardized reset source
377 * u32 bitmask from the hardware upon success, or returns (1 <<
378 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
379 * function was registered.
R Sricharan3f4990f2012-07-04 05:04:00 -0600380 */
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600381u32 prm_read_reset_sources(void)
R Sricharan3f4990f2012-07-04 05:04:00 -0600382{
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600383 u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
384
385 if (prm_ll_data->read_reset_sources)
386 ret = prm_ll_data->read_reset_sources();
387 else
388 WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
389
390 return ret;
391}
392
393/**
Rajendra Nayake6d3a8b2012-11-21 16:15:17 -0700394 * prm_was_any_context_lost_old - was device context lost? (old API)
395 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
396 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
397 * @idx: CONTEXT register offset
398 *
399 * Return 1 if any bits were set in the *_CONTEXT_* register
400 * identified by (@part, @inst, @idx), which means that some context
401 * was lost for that module; otherwise, return 0. XXX Deprecated;
402 * callers need to use a less-SoC-dependent way to identify hardware
403 * IP blocks.
404 */
405bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
406{
407 bool ret = true;
408
409 if (prm_ll_data->was_any_context_lost_old)
410 ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
411 else
412 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
413 __func__);
414
415 return ret;
416}
417
418/**
419 * prm_clear_context_lost_flags_old - clear context loss flags (old API)
420 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
421 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
422 * @idx: CONTEXT register offset
423 *
424 * Clear hardware context loss bits for the module identified by
425 * (@part, @inst, @idx). No return value. XXX Deprecated; callers
426 * need to use a less-SoC-dependent way to identify hardware IP
427 * blocks.
428 */
429void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
430{
431 if (prm_ll_data->clear_context_loss_flags_old)
432 prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
433 else
434 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
435 __func__);
436}
437
438/**
Tero Kristoefd44dc2014-10-27 08:39:24 -0700439 * omap_prm_assert_hardreset - assert hardreset for an IP block
440 * @shift: register bit shift corresponding to the reset line
441 * @part: PRM partition
442 * @prm_mod: PRM submodule base or instance offset
443 * @offset: register offset
444 *
445 * Asserts a hardware reset line for an IP block.
446 */
447int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
448{
449 if (!prm_ll_data->assert_hardreset) {
450 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
451 __func__);
452 return -EINVAL;
453 }
454
455 return prm_ll_data->assert_hardreset(shift, part, prm_mod, offset);
456}
457
458/**
Tero Kristo37fb59d2014-10-27 08:39:25 -0700459 * omap_prm_deassert_hardreset - deassert hardreset for an IP block
460 * @shift: register bit shift corresponding to the reset line
461 * @st_shift: reset status bit shift corresponding to the reset line
462 * @part: PRM partition
463 * @prm_mod: PRM submodule base or instance offset
464 * @offset: register offset
465 * @st_offset: status register offset
466 *
467 * Deasserts a hardware reset line for an IP block.
468 */
469int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
470 u16 offset, u16 st_offset)
471{
472 if (!prm_ll_data->deassert_hardreset) {
473 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
474 __func__);
475 return -EINVAL;
476 }
477
478 return prm_ll_data->deassert_hardreset(shift, st_shift, part, prm_mod,
479 offset, st_offset);
480}
481
482/**
Tero Kristo1bc28b32014-10-27 08:39:25 -0700483 * omap_prm_is_hardreset_asserted - check the hardreset status for an IP block
484 * @shift: register bit shift corresponding to the reset line
485 * @part: PRM partition
486 * @prm_mod: PRM submodule base or instance offset
487 * @offset: register offset
488 *
489 * Checks if a hardware reset line for an IP block is enabled or not.
490 */
491int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
492{
493 if (!prm_ll_data->is_hardreset_asserted) {
494 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
495 __func__);
496 return -EINVAL;
497 }
498
499 return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
500}
501
502/**
Tero Kristo4984eea2014-10-27 08:39:26 -0700503 * omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
504 *
505 * Clear any previously-latched I/O wakeup events and ensure that the
506 * I/O wakeup gates are aligned with the current mux settings.
507 * Calls SoC specific I/O chain reconfigure function if available,
508 * otherwise does nothing.
509 */
510void omap_prm_reconfigure_io_chain(void)
511{
512 if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
513 return;
514
515 prcm_irq_setup->reconfigure_io_chain();
516}
517
518/**
Tero Kristo61c86212014-10-27 08:39:26 -0700519 * omap_prm_reset_system - trigger global SW reset
520 *
521 * Triggers SoC specific global warm reset to reboot the device.
522 */
523void omap_prm_reset_system(void)
524{
525 if (!prm_ll_data->reset_system) {
526 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
527 __func__);
528 return;
529 }
530
531 prm_ll_data->reset_system();
532
533 while (1)
534 cpu_relax();
535}
536
537/**
Tero Kristo9cb6d362014-04-04 12:31:51 +0300538 * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
539 * @module: PRM module to clear wakeups from
540 * @regs: register to clear
541 * @wkst_mask: wkst bits to clear
542 *
543 * Clears any wakeup events for the module and register set defined.
544 * Uses SoC specific implementation to do the actual wakeup status
545 * clearing.
546 */
547int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
548{
549 if (!prm_ll_data->clear_mod_irqs) {
550 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
551 __func__);
552 return -EINVAL;
553 }
554
555 return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
556}
557
558/**
Tero Kristoe9f1ddc2014-04-04 15:52:01 +0300559 * omap_prm_vp_check_txdone - check voltage processor TX done status
560 *
561 * Checks if voltage processor transmission has been completed.
562 * Returns non-zero if a transmission has completed, 0 otherwise.
563 */
564u32 omap_prm_vp_check_txdone(u8 vp_id)
565{
566 if (!prm_ll_data->vp_check_txdone) {
567 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
568 __func__);
569 return 0;
570 }
571
572 return prm_ll_data->vp_check_txdone(vp_id);
573}
574
575/**
576 * omap_prm_vp_clear_txdone - clears voltage processor TX done status
577 *
578 * Clears the status bit for completed voltage processor transmission
579 * returned by prm_vp_check_txdone.
580 */
581void omap_prm_vp_clear_txdone(u8 vp_id)
582{
583 if (!prm_ll_data->vp_clear_txdone) {
584 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
585 __func__);
586 return;
587 }
588
589 prm_ll_data->vp_clear_txdone(vp_id);
590}
591
592/**
Paul Walmsleye24c3572012-10-21 01:01:11 -0600593 * prm_register - register per-SoC low-level data with the PRM
594 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
595 *
596 * Register per-SoC low-level OMAP PRM data and function pointers with
597 * the OMAP PRM common interface. The caller must keep the data
598 * pointed to by @pld valid until it calls prm_unregister() and
599 * it returns successfully. Returns 0 upon success, -EINVAL if @pld
600 * is NULL, or -EEXIST if prm_register() has already been called
601 * without an intervening prm_unregister().
602 */
603int prm_register(struct prm_ll_data *pld)
604{
605 if (!pld)
606 return -EINVAL;
607
608 if (prm_ll_data != &null_prm_ll_data)
609 return -EEXIST;
610
611 prm_ll_data = pld;
612
R Sricharan3f4990f2012-07-04 05:04:00 -0600613 return 0;
614}
615
Paul Walmsleye24c3572012-10-21 01:01:11 -0600616/**
617 * prm_unregister - unregister per-SoC low-level data & function pointers
618 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
619 *
620 * Unregister per-SoC low-level OMAP PRM data and function pointers
621 * that were previously registered with prm_register(). The
622 * caller may not destroy any of the data pointed to by @pld until
623 * this function returns successfully. Returns 0 upon success, or
624 * -EINVAL if @pld is NULL or if @pld does not match the struct
625 * prm_ll_data * previously registered by prm_register().
626 */
627int prm_unregister(struct prm_ll_data *pld)
R Sricharan3f4990f2012-07-04 05:04:00 -0600628{
Paul Walmsleye24c3572012-10-21 01:01:11 -0600629 if (!pld || prm_ll_data != pld)
630 return -EINVAL;
R Sricharan3f4990f2012-07-04 05:04:00 -0600631
Paul Walmsleye24c3572012-10-21 01:01:11 -0600632 prm_ll_data = &null_prm_ll_data;
633
R Sricharan3f4990f2012-07-04 05:04:00 -0600634 return 0;
635}
Tero Kristo943a63a2013-10-25 15:28:11 +0300636
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200637#ifdef CONFIG_ARCH_OMAP2
638static struct omap_prcm_init_data omap2_prm_data __initdata = {
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200639 .index = TI_CLKM_PRM,
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200640 .init = omap2xxx_prm_init,
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200641};
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200642#endif
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200643
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200644#ifdef CONFIG_ARCH_OMAP3
645static struct omap_prcm_init_data omap3_prm_data __initdata = {
Tero Kristoae521d4d2014-11-11 17:17:18 +0200646 .index = TI_CLKM_PRM,
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200647 .init = omap3xxx_prm_init,
Tero Kristoae521d4d2014-11-11 17:17:18 +0200648
649 /*
650 * IVA2 offset is a negative value, must offset the prm_base
651 * address by this to get it to positive
652 */
653 .offset = -OMAP3430_IVA2_MOD,
654};
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200655#endif
Tero Kristoae521d4d2014-11-11 17:17:18 +0200656
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200657#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
658static struct omap_prcm_init_data am3_prm_data __initdata = {
659 .index = TI_CLKM_PRM,
660 .init = am33xx_prm_init,
661};
662#endif
663
664#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
665 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
666static struct omap_prcm_init_data omap4_prm_data __initdata = {
667 .index = TI_CLKM_PRM,
668 .init = omap44xx_prm_init,
669};
670#endif
671
672#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
673static struct omap_prcm_init_data scrm_data __initdata = {
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200674 .index = TI_CLKM_SCRM,
675};
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200676#endif
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200677
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200678static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
679#ifdef CONFIG_SOC_AM33XX
680 { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
681#endif
682#ifdef CONFIG_SOC_AM43XX
683 { .compatible = "ti,am4-prcm", .data = &omap4_prm_data },
684#endif
685#ifdef CONFIG_SOC_TI81XX
686 { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
687 { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
688#endif
689#ifdef CONFIG_ARCH_OMAP2
690 { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
691#endif
692#ifdef CONFIG_ARCH_OMAP3
Tero Kristoae521d4d2014-11-11 17:17:18 +0200693 { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200694#endif
695#ifdef CONFIG_ARCH_OMAP4
696 { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200697 { .compatible = "ti,omap4-scrm", .data = &scrm_data },
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200698#endif
699#ifdef CONFIG_SOC_OMAP5
700 { .compatible = "ti,omap5-prm", .data = &omap4_prm_data },
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200701 { .compatible = "ti,omap5-scrm", .data = &scrm_data },
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200702#endif
703#ifdef CONFIG_SOC_DRA7XX
704 { .compatible = "ti,dra7-prm", .data = &omap4_prm_data },
705#endif
Tero Kristo943a63a2013-10-25 15:28:11 +0300706 { }
707};
708
Tero Kristo3a1a3882014-11-18 14:59:36 +0200709/**
Tero Kristoae521d4d2014-11-11 17:17:18 +0200710 * omap2_prm_base_init - initialize iomappings for the PRM driver
711 *
712 * Detects and initializes the iomappings for the PRM driver, based
713 * on the DT data. Returns 0 in success, negative error value
714 * otherwise.
715 */
716int __init omap2_prm_base_init(void)
717{
718 struct device_node *np;
719 const struct of_device_id *match;
720 struct omap_prcm_init_data *data;
721 void __iomem *mem;
722
723 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
724 data = (struct omap_prcm_init_data *)match->data;
725
726 mem = of_iomap(np, 0);
727 if (!mem)
728 return -ENOMEM;
729
730 if (data->index == TI_CLKM_PRM)
731 prm_base = mem + data->offset;
732
733 data->mem = mem;
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200734
735 data->np = np;
736
737 if (data->init)
738 data->init(data);
Tero Kristoae521d4d2014-11-11 17:17:18 +0200739 }
740
741 return 0;
742}
743
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200744int __init omap2_prcm_base_init(void)
745{
746 return omap2_prm_base_init();
747}
748
Tero Kristoae521d4d2014-11-11 17:17:18 +0200749/**
Tero Kristo3a1a3882014-11-18 14:59:36 +0200750 * omap_prcm_init - low level init for the PRCM drivers
751 *
752 * Initializes the low level clock infrastructure for PRCM drivers.
753 * Returns 0 in success, negative error value in failure.
754 */
755int __init omap_prcm_init(void)
Tero Kristo943a63a2013-10-25 15:28:11 +0300756{
757 struct device_node *np;
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200758 const struct of_device_id *match;
759 const struct omap_prcm_init_data *data;
Tero Kristo9f029b12014-10-22 15:15:36 +0300760 int ret;
Tero Kristo943a63a2013-10-25 15:28:11 +0300761
Tero Kristo3a3e1c82015-02-23 15:57:32 +0200762 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
763 data = match->data;
764
Tero Kristoae521d4d2014-11-11 17:17:18 +0200765 ret = omap2_clk_provider_init(np, data->index, data->mem);
Tero Kristo9f029b12014-10-22 15:15:36 +0300766 if (ret)
767 return ret;
Tero Kristo943a63a2013-10-25 15:28:11 +0300768 }
769
Tero Kristofe874142014-03-12 18:33:45 +0200770 omap_cm_init();
771
Tero Kristo943a63a2013-10-25 15:28:11 +0300772 return 0;
773}
Tero Kristob550e472014-03-31 18:15:45 +0300774
775static int __init prm_late_init(void)
776{
777 if (prm_ll_data->late_init)
778 return prm_ll_data->late_init();
779 return 0;
780}
781subsys_initcall(prm_late_init);