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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070016#include <linux/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/module.h>
18#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080019#include <linux/string.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090021#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -070023unsigned int pci_pm_d3_delay = 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
Atsushi Nemoto4516a612007-02-05 16:36:06 -080025#define DEFAULT_CARDBUS_IO_SIZE (256)
26#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
27/* pci=cbmemsize=nnM,cbiosize=nn can override this */
28unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
29unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
30
Linus Torvalds1da177e2005-04-16 15:20:36 -070031/**
32 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
33 * @bus: pointer to PCI bus structure to search
34 *
35 * Given a PCI bus, returns the highest PCI bus number present in the set
36 * including the given PCI bus and its list of child PCI buses.
37 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080038unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039{
40 struct list_head *tmp;
41 unsigned char max, n;
42
Kristen Accardib82db5c2006-01-17 16:56:56 -080043 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 list_for_each(tmp, &bus->children) {
45 n = pci_bus_max_busnr(pci_bus_b(tmp));
46 if(n > max)
47 max = n;
48 }
49 return max;
50}
Kristen Accardib82db5c2006-01-17 16:56:56 -080051EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Kristen Accardib82db5c2006-01-17 16:56:56 -080053#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070054/**
55 * pci_max_busnr - returns maximum PCI bus number
56 *
57 * Returns the highest PCI bus number present in the system global list of
58 * PCI buses.
59 */
60unsigned char __devinit
61pci_max_busnr(void)
62{
63 struct pci_bus *bus = NULL;
64 unsigned char max, n;
65
66 max = 0;
67 while ((bus = pci_find_next_bus(bus)) != NULL) {
68 n = pci_bus_max_busnr(bus);
69 if(n > max)
70 max = n;
71 }
72 return max;
73}
74
Adrian Bunk54c762f2005-12-22 01:08:52 +010075#endif /* 0 */
76
Michael Ellerman687d5fe2006-11-22 18:26:18 +110077#define PCI_FIND_CAP_TTL 48
78
79static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
80 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -070081{
82 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -070083
Michael Ellerman687d5fe2006-11-22 18:26:18 +110084 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -070085 pci_bus_read_config_byte(bus, devfn, pos, &pos);
86 if (pos < 0x40)
87 break;
88 pos &= ~3;
89 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
90 &id);
91 if (id == 0xff)
92 break;
93 if (id == cap)
94 return pos;
95 pos += PCI_CAP_LIST_NEXT;
96 }
97 return 0;
98}
99
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100100static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
101 u8 pos, int cap)
102{
103 int ttl = PCI_FIND_CAP_TTL;
104
105 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
106}
107
Roland Dreier24a4e372005-10-28 17:35:34 -0700108int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
109{
110 return __pci_find_next_cap(dev->bus, dev->devfn,
111 pos + PCI_CAP_LIST_NEXT, cap);
112}
113EXPORT_SYMBOL_GPL(pci_find_next_capability);
114
Michael Ellermand3bac112006-11-22 18:26:16 +1100115static int __pci_bus_find_cap_start(struct pci_bus *bus,
116 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117{
118 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
121 if (!(status & PCI_STATUS_CAP_LIST))
122 return 0;
123
124 switch (hdr_type) {
125 case PCI_HEADER_TYPE_NORMAL:
126 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100127 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100129 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 default:
131 return 0;
132 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100133
134 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135}
136
137/**
138 * pci_find_capability - query for devices' capabilities
139 * @dev: PCI device to query
140 * @cap: capability code
141 *
142 * Tell if a device supports a given PCI capability.
143 * Returns the address of the requested capability structure within the
144 * device's PCI configuration space or 0 in case the device does not
145 * support it. Possible values for @cap:
146 *
147 * %PCI_CAP_ID_PM Power Management
148 * %PCI_CAP_ID_AGP Accelerated Graphics Port
149 * %PCI_CAP_ID_VPD Vital Product Data
150 * %PCI_CAP_ID_SLOTID Slot Identification
151 * %PCI_CAP_ID_MSI Message Signalled Interrupts
152 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
153 * %PCI_CAP_ID_PCIX PCI-X
154 * %PCI_CAP_ID_EXP PCI Express
155 */
156int pci_find_capability(struct pci_dev *dev, int cap)
157{
Michael Ellermand3bac112006-11-22 18:26:16 +1100158 int pos;
159
160 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
161 if (pos)
162 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
163
164 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165}
166
167/**
168 * pci_bus_find_capability - query for devices' capabilities
169 * @bus: the PCI bus to query
170 * @devfn: PCI device to query
171 * @cap: capability code
172 *
173 * Like pci_find_capability() but works for pci devices that do not have a
174 * pci_dev structure set up yet.
175 *
176 * Returns the address of the requested capability structure within the
177 * device's PCI configuration space or 0 in case the device does not
178 * support it.
179 */
180int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
181{
Michael Ellermand3bac112006-11-22 18:26:16 +1100182 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 u8 hdr_type;
184
185 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
186
Michael Ellermand3bac112006-11-22 18:26:16 +1100187 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
188 if (pos)
189 pos = __pci_find_next_cap(bus, devfn, pos, cap);
190
191 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192}
193
194/**
195 * pci_find_ext_capability - Find an extended capability
196 * @dev: PCI device to query
197 * @cap: capability code
198 *
199 * Returns the address of the requested extended capability structure
200 * within the device's PCI configuration space or 0 if the device does
201 * not support it. Possible values for @cap:
202 *
203 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
204 * %PCI_EXT_CAP_ID_VC Virtual Channel
205 * %PCI_EXT_CAP_ID_DSN Device Serial Number
206 * %PCI_EXT_CAP_ID_PWR Power Budgeting
207 */
208int pci_find_ext_capability(struct pci_dev *dev, int cap)
209{
210 u32 header;
211 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
212 int pos = 0x100;
213
214 if (dev->cfg_size <= 256)
215 return 0;
216
217 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
218 return 0;
219
220 /*
221 * If we have no capabilities, this is indicated by cap ID,
222 * cap version and next pointer all being 0.
223 */
224 if (header == 0)
225 return 0;
226
227 while (ttl-- > 0) {
228 if (PCI_EXT_CAP_ID(header) == cap)
229 return pos;
230
231 pos = PCI_EXT_CAP_NEXT(header);
232 if (pos < 0x100)
233 break;
234
235 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
236 break;
237 }
238
239 return 0;
240}
Brice Goglin3a720d72006-05-23 06:10:01 -0400241EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100243static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
244{
245 int rc, ttl = PCI_FIND_CAP_TTL;
246 u8 cap, mask;
247
248 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
249 mask = HT_3BIT_CAP_MASK;
250 else
251 mask = HT_5BIT_CAP_MASK;
252
253 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
254 PCI_CAP_ID_HT, &ttl);
255 while (pos) {
256 rc = pci_read_config_byte(dev, pos + 3, &cap);
257 if (rc != PCIBIOS_SUCCESSFUL)
258 return 0;
259
260 if ((cap & mask) == ht_cap)
261 return pos;
262
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800263 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
264 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100265 PCI_CAP_ID_HT, &ttl);
266 }
267
268 return 0;
269}
270/**
271 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
272 * @dev: PCI device to query
273 * @pos: Position from which to continue searching
274 * @ht_cap: Hypertransport capability code
275 *
276 * To be used in conjunction with pci_find_ht_capability() to search for
277 * all capabilities matching @ht_cap. @pos should always be a value returned
278 * from pci_find_ht_capability().
279 *
280 * NB. To be 100% safe against broken PCI devices, the caller should take
281 * steps to avoid an infinite loop.
282 */
283int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
284{
285 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
286}
287EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
288
289/**
290 * pci_find_ht_capability - query a device's Hypertransport capabilities
291 * @dev: PCI device to query
292 * @ht_cap: Hypertransport capability code
293 *
294 * Tell if a device supports a given Hypertransport capability.
295 * Returns an address within the device's PCI configuration space
296 * or 0 in case the device does not support the request capability.
297 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
298 * which has a Hypertransport capability matching @ht_cap.
299 */
300int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
301{
302 int pos;
303
304 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
305 if (pos)
306 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
307
308 return pos;
309}
310EXPORT_SYMBOL_GPL(pci_find_ht_capability);
311
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312/**
313 * pci_find_parent_resource - return resource region of parent bus of given region
314 * @dev: PCI device structure contains resources to be searched
315 * @res: child resource record for which parent is sought
316 *
317 * For given resource region of given device, return the resource
318 * region of parent bus the given region is contained in or where
319 * it should be allocated from.
320 */
321struct resource *
322pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
323{
324 const struct pci_bus *bus = dev->bus;
325 int i;
326 struct resource *best = NULL;
327
328 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
329 struct resource *r = bus->resource[i];
330 if (!r)
331 continue;
332 if (res->start && !(res->start >= r->start && res->end <= r->end))
333 continue; /* Not contained */
334 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
335 continue; /* Wrong type */
336 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
337 return r; /* Exact match */
338 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
339 best = r; /* Approximating prefetchable by non-prefetchable */
340 }
341 return best;
342}
343
344/**
John W. Linville064b53db2005-07-27 10:19:44 -0400345 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
346 * @dev: PCI device to have its BARs restored
347 *
348 * Restore the BAR values for a given device, so as to make it
349 * accessible by its driver.
350 */
351void
352pci_restore_bars(struct pci_dev *dev)
353{
354 int i, numres;
355
356 switch (dev->hdr_type) {
357 case PCI_HEADER_TYPE_NORMAL:
358 numres = 6;
359 break;
360 case PCI_HEADER_TYPE_BRIDGE:
361 numres = 2;
362 break;
363 case PCI_HEADER_TYPE_CARDBUS:
364 numres = 1;
365 break;
366 default:
367 /* Should never get here, but just in case... */
368 return;
369 }
370
371 for (i = 0; i < numres; i ++)
372 pci_update_resource(dev, &dev->resource[i], i);
373}
374
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700375int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
376
John W. Linville064b53db2005-07-27 10:19:44 -0400377/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 * pci_set_power_state - Set the power state of a PCI device
379 * @dev: PCI device to be suspended
380 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
381 *
382 * Transition a device to a new power state, using the Power Management
383 * Capabilities in the device's config space.
384 *
385 * RETURN VALUE:
386 * -EINVAL if trying to enter a lower state than we're already in.
387 * 0 if we're already in the requested state.
388 * -EIO if device does not support PCI PM.
389 * 0 if we can successfully change the power state.
390 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391int
392pci_set_power_state(struct pci_dev *dev, pci_power_t state)
393{
John W. Linville064b53db2005-07-27 10:19:44 -0400394 int pm, need_restore = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 u16 pmcsr, pmc;
396
397 /* bound the state we're entering */
398 if (state > PCI_D3hot)
399 state = PCI_D3hot;
400
Pavel Macheke36c4552007-01-16 12:17:13 +0100401 /*
402 * If the device or the parent bridge can't support PCI PM, ignore
403 * the request if we're doing anything besides putting it into D0
404 * (which would only happen on boot).
405 */
406 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
407 return 0;
408
Andrew Lunncca03de2007-07-09 11:55:58 -0700409 /* find PCI PM capability in list */
410 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
411
412 /* abort if the device doesn't support PM capabilities */
413 if (!pm)
414 return -EIO;
415
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 /* Validate current state:
417 * Can enter D0 from any state, but if we can only go deeper
418 * to sleep if we're already in a low power state
419 */
Andrew Morton02669492006-03-23 01:38:34 -0800420 if (state != PCI_D0 && dev->current_state > state) {
421 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
422 __FUNCTION__, pci_name(dev), state, dev->current_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 return -EINVAL;
Andrew Morton02669492006-03-23 01:38:34 -0800424 } else if (dev->current_state == state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 return 0; /* we're already there */
426
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700427
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700429 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 printk(KERN_DEBUG
431 "PCI: %s has unsupported PM cap regs version (%u)\n",
432 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
433 return -EIO;
434 }
435
436 /* check if this device supports the desired state */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700437 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
438 return -EIO;
439 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
440 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441
John W. Linville064b53db2005-07-27 10:19:44 -0400442 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
443
John W. Linville32a36582005-09-14 09:52:42 -0400444 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 * This doesn't affect PME_Status, disables PME_En, and
446 * sets PowerState to 0.
447 */
John W. Linville32a36582005-09-14 09:52:42 -0400448 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400449 case PCI_D0:
450 case PCI_D1:
451 case PCI_D2:
452 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
453 pmcsr |= state;
454 break;
John W. Linville32a36582005-09-14 09:52:42 -0400455 case PCI_UNKNOWN: /* Boot-up */
456 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
457 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
John W. Linville064b53db2005-07-27 10:19:44 -0400458 need_restore = 1;
John W. Linville32a36582005-09-14 09:52:42 -0400459 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400460 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400461 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400462 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 }
464
465 /* enter specified state */
466 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
467
468 /* Mandatory power management transition delays */
469 /* see PCI PM 1.1 5.6.1 table 18 */
470 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700471 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 else if (state == PCI_D2 || dev->current_state == PCI_D2)
473 udelay(200);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
David Shaohua Lib9131002005-03-19 00:16:18 -0500475 /*
476 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
Andreas Mohrd6e05ed2006-06-26 18:35:02 +0200477 * Firmware method after native method ?
David Shaohua Lib9131002005-03-19 00:16:18 -0500478 */
479 if (platform_pci_set_power_state)
480 platform_pci_set_power_state(dev, state);
481
482 dev->current_state = state;
John W. Linville064b53db2005-07-27 10:19:44 -0400483
484 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
485 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
486 * from D3hot to D0 _may_ perform an internal reset, thereby
487 * going to "D0 Uninitialized" rather than "D0 Initialized".
488 * For example, at least some versions of the 3c905B and the
489 * 3c556B exhibit this behaviour.
490 *
491 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
492 * devices in a D3hot state at boot. Consequently, we need to
493 * restore at least the BARs so that the device will be
494 * accessible to its driver.
495 */
496 if (need_restore)
497 pci_restore_bars(dev);
498
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 return 0;
500}
501
Shaohua Liab826ca2007-07-20 10:03:22 +0800502pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
David Shaohua Li0f644742005-03-19 00:15:48 -0500503
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504/**
505 * pci_choose_state - Choose the power state of a PCI device
506 * @dev: PCI device to be suspended
507 * @state: target sleep state for the whole system. This is the value
508 * that is passed to suspend() function.
509 *
510 * Returns PCI power state suitable for given device and given system
511 * message.
512 */
513
514pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
515{
Shaohua Liab826ca2007-07-20 10:03:22 +0800516 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500517
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
519 return PCI_D0;
520
David Shaohua Li0f644742005-03-19 00:15:48 -0500521 if (platform_pci_choose_state) {
522 ret = platform_pci_choose_state(dev, state);
Shaohua Liab826ca2007-07-20 10:03:22 +0800523 if (ret != PCI_POWER_ERROR)
524 return ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500525 }
Pavel Machekca078ba2005-09-03 15:56:57 -0700526
527 switch (state.event) {
528 case PM_EVENT_ON:
529 return PCI_D0;
530 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700531 case PM_EVENT_PRETHAW:
532 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700533 case PM_EVENT_SUSPEND:
534 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535 default:
David Brownellb887d2e2006-08-14 23:11:05 -0700536 printk("Unrecognized suspend event %d\n", state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 BUG();
538 }
539 return PCI_D0;
540}
541
542EXPORT_SYMBOL(pci_choose_state);
543
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300544static int pci_save_pcie_state(struct pci_dev *dev)
545{
546 int pos, i = 0;
547 struct pci_cap_saved_state *save_state;
548 u16 *cap;
549
550 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
551 if (pos <= 0)
552 return 0;
553
Eric W. Biederman9f355752007-03-08 13:06:13 -0700554 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
555 if (!save_state)
556 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300557 if (!save_state) {
558 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
559 return -ENOMEM;
560 }
561 cap = (u16 *)&save_state->data[0];
562
563 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
564 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
565 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
566 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
567 pci_add_saved_cap(dev, save_state);
568 return 0;
569}
570
571static void pci_restore_pcie_state(struct pci_dev *dev)
572{
573 int i = 0, pos;
574 struct pci_cap_saved_state *save_state;
575 u16 *cap;
576
577 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
578 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
579 if (!save_state || pos <= 0)
580 return;
581 cap = (u16 *)&save_state->data[0];
582
583 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
584 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
585 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
586 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300587}
588
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800589
590static int pci_save_pcix_state(struct pci_dev *dev)
591{
592 int pos, i = 0;
593 struct pci_cap_saved_state *save_state;
594 u16 *cap;
595
596 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
597 if (pos <= 0)
598 return 0;
599
Eric W. Biederman9f355752007-03-08 13:06:13 -0700600 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
601 if (!save_state)
602 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800603 if (!save_state) {
604 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
605 return -ENOMEM;
606 }
607 cap = (u16 *)&save_state->data[0];
608
609 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
610 pci_add_saved_cap(dev, save_state);
611 return 0;
612}
613
614static void pci_restore_pcix_state(struct pci_dev *dev)
615{
616 int i = 0, pos;
617 struct pci_cap_saved_state *save_state;
618 u16 *cap;
619
620 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
621 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
622 if (!save_state || pos <= 0)
623 return;
624 cap = (u16 *)&save_state->data[0];
625
626 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800627}
628
629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630/**
631 * pci_save_state - save the PCI configuration space of a device before suspending
632 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 */
634int
635pci_save_state(struct pci_dev *dev)
636{
637 int i;
638 /* XXX: 100% dword access ok here? */
639 for (i = 0; i < 16; i++)
640 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300641 if ((i = pci_save_pcie_state(dev)) != 0)
642 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800643 if ((i = pci_save_pcix_state(dev)) != 0)
644 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 return 0;
646}
647
648/**
649 * pci_restore_state - Restore the saved state of a PCI device
650 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 */
652int
653pci_restore_state(struct pci_dev *dev)
654{
655 int i;
Dave Jones04d9c1a2006-04-18 21:06:51 -0700656 int val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300658 /* PCI Express register must be restored first */
659 pci_restore_pcie_state(dev);
660
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700661 /*
662 * The Base Address register should be programmed before the command
663 * register(s)
664 */
665 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700666 pci_read_config_dword(dev, i * 4, &val);
667 if (val != dev->saved_config_space[i]) {
668 printk(KERN_DEBUG "PM: Writing back config space on "
669 "device %s at offset %x (was %x, writing %x)\n",
670 pci_name(dev), i,
671 val, (int)dev->saved_config_space[i]);
672 pci_write_config_dword(dev,i * 4,
673 dev->saved_config_space[i]);
674 }
675 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800676 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800677 pci_restore_msi_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100678
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 return 0;
680}
681
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900682static int do_pci_enable_device(struct pci_dev *dev, int bars)
683{
684 int err;
685
686 err = pci_set_power_state(dev, PCI_D0);
687 if (err < 0 && err != -EIO)
688 return err;
689 err = pcibios_enable_device(dev, bars);
690 if (err < 0)
691 return err;
692 pci_fixup_device(pci_fixup_enable, dev);
693
694 return 0;
695}
696
697/**
698 * __pci_reenable_device - Resume abandoned device
699 * @dev: PCI device to be resumed
700 *
701 * Note this function is a backend of pci_default_resume and is not supposed
702 * to be called by normal code, write proper resume handler and use it instead.
703 */
704int
705__pci_reenable_device(struct pci_dev *dev)
706{
707 if (atomic_read(&dev->enable_cnt))
708 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
709 return 0;
710}
711
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712/**
713 * pci_enable_device_bars - Initialize some of a device for use
714 * @dev: PCI device to be initialized
715 * @bars: bitmask of BAR's that must be configured
716 *
717 * Initialize device before it's used by a driver. Ask low-level code
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900718 * to enable selected I/O and memory resources. Wake up the device if it
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 * was suspended. Beware, this function can fail.
720 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721int
722pci_enable_device_bars(struct pci_dev *dev, int bars)
723{
724 int err;
725
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900726 if (atomic_add_return(1, &dev->enable_cnt) > 1)
727 return 0; /* already enabled */
728
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900729 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700730 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900731 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900732 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733}
734
735/**
736 * pci_enable_device - Initialize device before it's used by a driver.
737 * @dev: PCI device to be initialized
738 *
739 * Initialize device before it's used by a driver. Ask low-level code
740 * to enable I/O and memory. Wake up the device if it was suspended.
741 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800742 *
743 * Note we don't actually enable the device many times if we call
744 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800746int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747{
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900748 return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749}
750
Tejun Heo9ac78492007-01-20 16:00:26 +0900751/*
752 * Managed PCI resources. This manages device on/off, intx/msi/msix
753 * on/off and BAR regions. pci_dev itself records msi/msix status, so
754 * there's no need to track it separately. pci_devres is initialized
755 * when a device is enabled using managed PCI device enable interface.
756 */
757struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -0800758 unsigned int enabled:1;
759 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900760 unsigned int orig_intx:1;
761 unsigned int restore_intx:1;
762 u32 region_mask;
763};
764
765static void pcim_release(struct device *gendev, void *res)
766{
767 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
768 struct pci_devres *this = res;
769 int i;
770
771 if (dev->msi_enabled)
772 pci_disable_msi(dev);
773 if (dev->msix_enabled)
774 pci_disable_msix(dev);
775
776 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
777 if (this->region_mask & (1 << i))
778 pci_release_region(dev, i);
779
780 if (this->restore_intx)
781 pci_intx(dev, this->orig_intx);
782
Tejun Heo7f375f32007-02-25 04:36:01 -0800783 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +0900784 pci_disable_device(dev);
785}
786
787static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
788{
789 struct pci_devres *dr, *new_dr;
790
791 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
792 if (dr)
793 return dr;
794
795 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
796 if (!new_dr)
797 return NULL;
798 return devres_get(&pdev->dev, new_dr, NULL, NULL);
799}
800
801static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
802{
803 if (pci_is_managed(pdev))
804 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
805 return NULL;
806}
807
808/**
809 * pcim_enable_device - Managed pci_enable_device()
810 * @pdev: PCI device to be initialized
811 *
812 * Managed pci_enable_device().
813 */
814int pcim_enable_device(struct pci_dev *pdev)
815{
816 struct pci_devres *dr;
817 int rc;
818
819 dr = get_pci_dr(pdev);
820 if (unlikely(!dr))
821 return -ENOMEM;
Tejun Heo7f375f32007-02-25 04:36:01 -0800822 WARN_ON(!!dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +0900823
824 rc = pci_enable_device(pdev);
825 if (!rc) {
826 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -0800827 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900828 }
829 return rc;
830}
831
832/**
833 * pcim_pin_device - Pin managed PCI device
834 * @pdev: PCI device to pin
835 *
836 * Pin managed PCI device @pdev. Pinned device won't be disabled on
837 * driver detach. @pdev must have been enabled with
838 * pcim_enable_device().
839 */
840void pcim_pin_device(struct pci_dev *pdev)
841{
842 struct pci_devres *dr;
843
844 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -0800845 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +0900846 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800847 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900848}
849
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850/**
851 * pcibios_disable_device - disable arch specific PCI resources for device dev
852 * @dev: the PCI device to disable
853 *
854 * Disables architecture specific PCI resources for the device. This
855 * is the default implementation. Architecture implementations can
856 * override this.
857 */
858void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
859
860/**
861 * pci_disable_device - Disable PCI device after use
862 * @dev: PCI device to be disabled
863 *
864 * Signal to the system that the PCI device is not in use by the system
865 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800866 *
867 * Note we don't actually disable the device until all callers of
868 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 */
870void
871pci_disable_device(struct pci_dev *dev)
872{
Tejun Heo9ac78492007-01-20 16:00:26 +0900873 struct pci_devres *dr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 u16 pci_command;
Shaohua Li99dc8042006-05-26 10:58:27 +0800875
Tejun Heo9ac78492007-01-20 16:00:26 +0900876 dr = find_pci_dr(dev);
877 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800878 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +0900879
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800880 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
881 return;
882
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
884 if (pci_command & PCI_COMMAND_MASTER) {
885 pci_command &= ~PCI_COMMAND_MASTER;
886 pci_write_config_word(dev, PCI_COMMAND, pci_command);
887 }
Kenji Kaneshigeceb43742005-04-08 14:53:31 +0900888 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889
890 pcibios_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891}
892
893/**
Brian Kingf7bdd122007-04-06 16:39:36 -0500894 * pcibios_set_pcie_reset_state - set reset state for device dev
895 * @dev: the PCI-E device reset
896 * @state: Reset state to enter into
897 *
898 *
899 * Sets the PCI-E reset state for the device. This is the default
900 * implementation. Architecture implementations can override this.
901 */
902int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
903 enum pcie_reset_state state)
904{
905 return -EINVAL;
906}
907
908/**
909 * pci_set_pcie_reset_state - set reset state for device dev
910 * @dev: the PCI-E device reset
911 * @state: Reset state to enter into
912 *
913 *
914 * Sets the PCI reset state for the device.
915 */
916int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
917{
918 return pcibios_set_pcie_reset_state(dev, state);
919}
920
921/**
David Brownell075c1772007-04-26 00:12:06 -0700922 * pci_enable_wake - enable PCI device as wakeup event source
923 * @dev: PCI device affected
924 * @state: PCI state from which device will issue wakeup events
925 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926 *
David Brownell075c1772007-04-26 00:12:06 -0700927 * This enables the device as a wakeup event source, or disables it.
928 * When such events involves platform-specific hooks, those hooks are
929 * called automatically by this routine.
930 *
931 * Devices with legacy power management (no standard PCI PM capabilities)
932 * always require such platform hooks. Depending on the platform, devices
933 * supporting the standard PCI PME# signal may require such platform hooks;
934 * they always update bits in config space to allow PME# generation.
935 *
936 * -EIO is returned if the device can't ever be a wakeup event source.
937 * -EINVAL is returned if the device can't generate wakeup events from
938 * the specified PCI state. Returns zero if the operation is successful.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 */
940int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
941{
942 int pm;
David Brownell075c1772007-04-26 00:12:06 -0700943 int status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 u16 value;
945
David Brownell075c1772007-04-26 00:12:06 -0700946 /* Note that drivers should verify device_may_wakeup(&dev->dev)
947 * before calling this function. Platform code should report
948 * errors when drivers try to enable wakeup on devices that
949 * can't issue wakeups, or on which wakeups were disabled by
950 * userspace updating the /sys/devices.../power/wakeup file.
951 */
952
953 status = call_platform_enable_wakeup(&dev->dev, enable);
954
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 /* find PCI PM capability in list */
956 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
957
David Brownell075c1772007-04-26 00:12:06 -0700958 /* If device doesn't support PM Capabilities, but caller wants to
959 * disable wake events, it's a NOP. Otherwise fail unless the
960 * platform hooks handled this legacy device already.
961 */
962 if (!pm)
963 return enable ? status : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964
965 /* Check device's ability to generate PME# */
966 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
967
968 value &= PCI_PM_CAP_PME_MASK;
969 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
970
971 /* Check if it can generate PME# from requested state. */
David Brownell075c1772007-04-26 00:12:06 -0700972 if (!value || !(value & (1 << state))) {
973 /* if it can't, revert what the platform hook changed,
974 * always reporting the base "EINVAL, can't PME#" error
975 */
976 if (enable)
977 call_platform_enable_wakeup(&dev->dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978 return enable ? -EINVAL : 0;
David Brownell075c1772007-04-26 00:12:06 -0700979 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980
981 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
982
983 /* Clear PME_Status by writing 1 to it and enable PME# */
984 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
985
986 if (!enable)
987 value &= ~PCI_PM_CTRL_PME_ENABLE;
988
989 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
David Brownell075c1772007-04-26 00:12:06 -0700990
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991 return 0;
992}
993
994int
995pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
996{
997 u8 pin;
998
Kristen Accardi514d2072005-11-02 16:24:39 -0800999 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 if (!pin)
1001 return -1;
1002 pin--;
1003 while (dev->bus->self) {
1004 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1005 dev = dev->bus->self;
1006 }
1007 *bridge = dev;
1008 return pin;
1009}
1010
1011/**
1012 * pci_release_region - Release a PCI bar
1013 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1014 * @bar: BAR to release
1015 *
1016 * Releases the PCI I/O and memory resources previously reserved by a
1017 * successful call to pci_request_region. Call this function only
1018 * after all use of the PCI regions has ceased.
1019 */
1020void pci_release_region(struct pci_dev *pdev, int bar)
1021{
Tejun Heo9ac78492007-01-20 16:00:26 +09001022 struct pci_devres *dr;
1023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 if (pci_resource_len(pdev, bar) == 0)
1025 return;
1026 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1027 release_region(pci_resource_start(pdev, bar),
1028 pci_resource_len(pdev, bar));
1029 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1030 release_mem_region(pci_resource_start(pdev, bar),
1031 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09001032
1033 dr = find_pci_dr(pdev);
1034 if (dr)
1035 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036}
1037
1038/**
1039 * pci_request_region - Reserved PCI I/O and memory resource
1040 * @pdev: PCI device whose resources are to be reserved
1041 * @bar: BAR to be reserved
1042 * @res_name: Name to be associated with resource.
1043 *
1044 * Mark the PCI region associated with PCI device @pdev BR @bar as
1045 * being reserved by owner @res_name. Do not access any
1046 * address inside the PCI regions unless this call returns
1047 * successfully.
1048 *
1049 * Returns 0 on success, or %EBUSY on error. A warning
1050 * message is also printed on failure.
1051 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001052int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053{
Tejun Heo9ac78492007-01-20 16:00:26 +09001054 struct pci_devres *dr;
1055
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 if (pci_resource_len(pdev, bar) == 0)
1057 return 0;
1058
1059 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1060 if (!request_region(pci_resource_start(pdev, bar),
1061 pci_resource_len(pdev, bar), res_name))
1062 goto err_out;
1063 }
1064 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1065 if (!request_mem_region(pci_resource_start(pdev, bar),
1066 pci_resource_len(pdev, bar), res_name))
1067 goto err_out;
1068 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001069
1070 dr = find_pci_dr(pdev);
1071 if (dr)
1072 dr->region_mask |= 1 << bar;
1073
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 return 0;
1075
1076err_out:
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -07001077 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1078 "for device %s\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1080 bar + 1, /* PCI BAR # */
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -07001081 (unsigned long long)pci_resource_len(pdev, bar),
1082 (unsigned long long)pci_resource_start(pdev, bar),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 pci_name(pdev));
1084 return -EBUSY;
1085}
1086
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001087/**
1088 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1089 * @pdev: PCI device whose resources were previously reserved
1090 * @bars: Bitmask of BARs to be released
1091 *
1092 * Release selected PCI I/O and memory resources previously reserved.
1093 * Call this function only after all use of the PCI regions has ceased.
1094 */
1095void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1096{
1097 int i;
1098
1099 for (i = 0; i < 6; i++)
1100 if (bars & (1 << i))
1101 pci_release_region(pdev, i);
1102}
1103
1104/**
1105 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1106 * @pdev: PCI device whose resources are to be reserved
1107 * @bars: Bitmask of BARs to be requested
1108 * @res_name: Name to be associated with resource
1109 */
1110int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1111 const char *res_name)
1112{
1113 int i;
1114
1115 for (i = 0; i < 6; i++)
1116 if (bars & (1 << i))
1117 if(pci_request_region(pdev, i, res_name))
1118 goto err_out;
1119 return 0;
1120
1121err_out:
1122 while(--i >= 0)
1123 if (bars & (1 << i))
1124 pci_release_region(pdev, i);
1125
1126 return -EBUSY;
1127}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
1129/**
1130 * pci_release_regions - Release reserved PCI I/O and memory resources
1131 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1132 *
1133 * Releases all PCI I/O and memory resources previously reserved by a
1134 * successful call to pci_request_regions. Call this function only
1135 * after all use of the PCI regions has ceased.
1136 */
1137
1138void pci_release_regions(struct pci_dev *pdev)
1139{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001140 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141}
1142
1143/**
1144 * pci_request_regions - Reserved PCI I/O and memory resources
1145 * @pdev: PCI device whose resources are to be reserved
1146 * @res_name: Name to be associated with resource.
1147 *
1148 * Mark all PCI regions associated with PCI device @pdev as
1149 * being reserved by owner @res_name. Do not access any
1150 * address inside the PCI regions unless this call returns
1151 * successfully.
1152 *
1153 * Returns 0 on success, or %EBUSY on error. A warning
1154 * message is also printed on failure.
1155 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001156int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001158 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159}
1160
1161/**
1162 * pci_set_master - enables bus-mastering for device dev
1163 * @dev: the PCI device to enable
1164 *
1165 * Enables bus-mastering on the device and calls pcibios_set_master()
1166 * to do the needed arch specific settings.
1167 */
1168void
1169pci_set_master(struct pci_dev *dev)
1170{
1171 u16 cmd;
1172
1173 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1174 if (! (cmd & PCI_COMMAND_MASTER)) {
1175 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1176 cmd |= PCI_COMMAND_MASTER;
1177 pci_write_config_word(dev, PCI_COMMAND, cmd);
1178 }
1179 dev->is_busmaster = 1;
1180 pcibios_set_master(dev);
1181}
1182
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001183#ifdef PCI_DISABLE_MWI
1184int pci_set_mwi(struct pci_dev *dev)
1185{
1186 return 0;
1187}
1188
Randy Dunlap694625c2007-07-09 11:55:54 -07001189int pci_try_set_mwi(struct pci_dev *dev)
1190{
1191 return 0;
1192}
1193
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001194void pci_clear_mwi(struct pci_dev *dev)
1195{
1196}
1197
1198#else
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001199
1200#ifndef PCI_CACHE_LINE_BYTES
1201#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1202#endif
1203
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204/* This can be overridden by arch code. */
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001205/* Don't forget this is measured in 32-bit words, not bytes */
1206u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207
1208/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001209 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1210 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001212 * Helper function for pci_set_mwi.
1213 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1215 *
1216 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1217 */
1218static int
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001219pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220{
1221 u8 cacheline_size;
1222
1223 if (!pci_cache_line_size)
1224 return -EINVAL; /* The system doesn't support MWI. */
1225
1226 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1227 equal to or multiple of the right value. */
1228 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1229 if (cacheline_size >= pci_cache_line_size &&
1230 (cacheline_size % pci_cache_line_size) == 0)
1231 return 0;
1232
1233 /* Write the correct value. */
1234 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1235 /* Read it back. */
1236 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1237 if (cacheline_size == pci_cache_line_size)
1238 return 0;
1239
1240 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1241 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1242
1243 return -EINVAL;
1244}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245
1246/**
1247 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1248 * @dev: the PCI device for which MWI is enabled
1249 *
Randy Dunlap694625c2007-07-09 11:55:54 -07001250 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251 *
1252 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1253 */
1254int
1255pci_set_mwi(struct pci_dev *dev)
1256{
1257 int rc;
1258 u16 cmd;
1259
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001260 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261 if (rc)
1262 return rc;
1263
1264 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1265 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Randy Dunlap694625c2007-07-09 11:55:54 -07001266 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1267 pci_name(dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 cmd |= PCI_COMMAND_INVALIDATE;
1269 pci_write_config_word(dev, PCI_COMMAND, cmd);
1270 }
1271
1272 return 0;
1273}
1274
1275/**
Randy Dunlap694625c2007-07-09 11:55:54 -07001276 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1277 * @dev: the PCI device for which MWI is enabled
1278 *
1279 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1280 * Callers are not required to check the return value.
1281 *
1282 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1283 */
1284int pci_try_set_mwi(struct pci_dev *dev)
1285{
1286 int rc = pci_set_mwi(dev);
1287 return rc;
1288}
1289
1290/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1292 * @dev: the PCI device to disable
1293 *
1294 * Disables PCI Memory-Write-Invalidate transaction on the device
1295 */
1296void
1297pci_clear_mwi(struct pci_dev *dev)
1298{
1299 u16 cmd;
1300
1301 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1302 if (cmd & PCI_COMMAND_INVALIDATE) {
1303 cmd &= ~PCI_COMMAND_INVALIDATE;
1304 pci_write_config_word(dev, PCI_COMMAND, cmd);
1305 }
1306}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001307#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308
Brett M Russa04ce0f2005-08-15 15:23:41 -04001309/**
1310 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001311 * @pdev: the PCI device to operate on
1312 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04001313 *
1314 * Enables/disables PCI INTx for device dev
1315 */
1316void
1317pci_intx(struct pci_dev *pdev, int enable)
1318{
1319 u16 pci_command, new;
1320
1321 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1322
1323 if (enable) {
1324 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1325 } else {
1326 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1327 }
1328
1329 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09001330 struct pci_devres *dr;
1331
Brett M Russ2fd9d742005-09-09 10:02:22 -07001332 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09001333
1334 dr = find_pci_dr(pdev);
1335 if (dr && !dr->restore_intx) {
1336 dr->restore_intx = 1;
1337 dr->orig_intx = !enable;
1338 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04001339 }
1340}
1341
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001342/**
1343 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07001344 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001345 *
1346 * If you want to use msi see pci_enable_msi and friends.
1347 * This is a lower level primitive that allows us to disable
1348 * msi operation at the device level.
1349 */
1350void pci_msi_off(struct pci_dev *dev)
1351{
1352 int pos;
1353 u16 control;
1354
1355 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1356 if (pos) {
1357 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1358 control &= ~PCI_MSI_FLAGS_ENABLE;
1359 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1360 }
1361 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1362 if (pos) {
1363 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1364 control &= ~PCI_MSIX_FLAGS_ENABLE;
1365 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1366 }
1367}
1368
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1370/*
1371 * These can be overridden by arch-specific implementations
1372 */
1373int
1374pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1375{
1376 if (!pci_dma_supported(dev, mask))
1377 return -EIO;
1378
1379 dev->dma_mask = mask;
1380
1381 return 0;
1382}
1383
1384int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1386{
1387 if (!pci_dma_supported(dev, mask))
1388 return -EIO;
1389
1390 dev->dev.coherent_dma_mask = mask;
1391
1392 return 0;
1393}
1394#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001395
1396/**
Peter Orubad556ad42007-05-15 13:59:13 +02001397 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1398 * @dev: PCI device to query
1399 *
1400 * Returns mmrbc: maximum designed memory read count in bytes
1401 * or appropriate error value.
1402 */
1403int pcix_get_max_mmrbc(struct pci_dev *dev)
1404{
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001405 int err, cap;
Peter Orubad556ad42007-05-15 13:59:13 +02001406 u32 stat;
1407
1408 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1409 if (!cap)
1410 return -EINVAL;
1411
1412 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1413 if (err)
1414 return -EINVAL;
1415
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001416 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
Peter Orubad556ad42007-05-15 13:59:13 +02001417}
1418EXPORT_SYMBOL(pcix_get_max_mmrbc);
1419
1420/**
1421 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1422 * @dev: PCI device to query
1423 *
1424 * Returns mmrbc: maximum memory read count in bytes
1425 * or appropriate error value.
1426 */
1427int pcix_get_mmrbc(struct pci_dev *dev)
1428{
1429 int ret, cap;
1430 u32 cmd;
1431
1432 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1433 if (!cap)
1434 return -EINVAL;
1435
1436 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1437 if (!ret)
1438 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1439
1440 return ret;
1441}
1442EXPORT_SYMBOL(pcix_get_mmrbc);
1443
1444/**
1445 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1446 * @dev: PCI device to query
1447 * @mmrbc: maximum memory read count in bytes
1448 * valid values are 512, 1024, 2048, 4096
1449 *
1450 * If possible sets maximum memory read byte count, some bridges have erratas
1451 * that prevent this.
1452 */
1453int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1454{
1455 int cap, err = -EINVAL;
1456 u32 stat, cmd, v, o;
1457
1458 if (mmrbc < 512 || mmrbc > 4096 || (mmrbc & (mmrbc-1)))
1459 goto out;
1460
1461 v = ffs(mmrbc) - 10;
1462
1463 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1464 if (!cap)
1465 goto out;
1466
1467 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1468 if (err)
1469 goto out;
1470
1471 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1472 return -E2BIG;
1473
1474 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1475 if (err)
1476 goto out;
1477
1478 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1479 if (o != v) {
1480 if (v > o && dev->bus &&
1481 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1482 return -EIO;
1483
1484 cmd &= ~PCI_X_CMD_MAX_READ;
1485 cmd |= v << 2;
1486 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1487 }
1488out:
1489 return err;
1490}
1491EXPORT_SYMBOL(pcix_set_mmrbc);
1492
1493/**
1494 * pcie_get_readrq - get PCI Express read request size
1495 * @dev: PCI device to query
1496 *
1497 * Returns maximum memory read request in bytes
1498 * or appropriate error value.
1499 */
1500int pcie_get_readrq(struct pci_dev *dev)
1501{
1502 int ret, cap;
1503 u16 ctl;
1504
1505 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1506 if (!cap)
1507 return -EINVAL;
1508
1509 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1510 if (!ret)
1511 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1512
1513 return ret;
1514}
1515EXPORT_SYMBOL(pcie_get_readrq);
1516
1517/**
1518 * pcie_set_readrq - set PCI Express maximum memory read request
1519 * @dev: PCI device to query
1520 * @count: maximum memory read count in bytes
1521 * valid values are 128, 256, 512, 1024, 2048, 4096
1522 *
1523 * If possible sets maximum read byte count
1524 */
1525int pcie_set_readrq(struct pci_dev *dev, int rq)
1526{
1527 int cap, err = -EINVAL;
1528 u16 ctl, v;
1529
1530 if (rq < 128 || rq > 4096 || (rq & (rq-1)))
1531 goto out;
1532
1533 v = (ffs(rq) - 8) << 12;
1534
1535 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1536 if (!cap)
1537 goto out;
1538
1539 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1540 if (err)
1541 goto out;
1542
1543 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1544 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1545 ctl |= v;
1546 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1547 }
1548
1549out:
1550 return err;
1551}
1552EXPORT_SYMBOL(pcie_set_readrq);
1553
1554/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001555 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08001556 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001557 * @flags: resource type mask to be selected
1558 *
1559 * This helper routine makes bar mask from the type of resource.
1560 */
1561int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1562{
1563 int i, bars = 0;
1564 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1565 if (pci_resource_flags(dev, i) & flags)
1566 bars |= (1 << i);
1567 return bars;
1568}
1569
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570static int __devinit pci_init(void)
1571{
1572 struct pci_dev *dev = NULL;
1573
1574 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1575 pci_fixup_device(pci_fixup_final, dev);
1576 }
1577 return 0;
1578}
1579
1580static int __devinit pci_setup(char *str)
1581{
1582 while (str) {
1583 char *k = strchr(str, ',');
1584 if (k)
1585 *k++ = 0;
1586 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001587 if (!strcmp(str, "nomsi")) {
1588 pci_no_msi();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08001589 } else if (!strncmp(str, "cbiosize=", 9)) {
1590 pci_cardbus_io_size = memparse(str + 9, &str);
1591 } else if (!strncmp(str, "cbmemsize=", 10)) {
1592 pci_cardbus_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001593 } else {
1594 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1595 str);
1596 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 }
1598 str = k;
1599 }
Andi Kleen0637a702006-09-26 10:52:41 +02001600 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601}
Andi Kleen0637a702006-09-26 10:52:41 +02001602early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603
1604device_initcall(pci_init);
1605
John W. Linville064b53db2005-07-27 10:19:44 -04001606EXPORT_SYMBOL_GPL(pci_restore_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607EXPORT_SYMBOL(pci_enable_device_bars);
1608EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001609EXPORT_SYMBOL(pcim_enable_device);
1610EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612EXPORT_SYMBOL(pci_find_capability);
1613EXPORT_SYMBOL(pci_bus_find_capability);
1614EXPORT_SYMBOL(pci_release_regions);
1615EXPORT_SYMBOL(pci_request_regions);
1616EXPORT_SYMBOL(pci_release_region);
1617EXPORT_SYMBOL(pci_request_region);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001618EXPORT_SYMBOL(pci_release_selected_regions);
1619EXPORT_SYMBOL(pci_request_selected_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620EXPORT_SYMBOL(pci_set_master);
1621EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07001622EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001623EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04001624EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1627EXPORT_SYMBOL(pci_assign_resource);
1628EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001629EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630
1631EXPORT_SYMBOL(pci_set_power_state);
1632EXPORT_SYMBOL(pci_save_state);
1633EXPORT_SYMBOL(pci_restore_state);
1634EXPORT_SYMBOL(pci_enable_wake);
Brian Kingf7bdd122007-04-06 16:39:36 -05001635EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001636