blob: f0ee6bde11af3b4e31d4566329c07004657414c1 [file] [log] [blame]
Georgi Djakov2b46cd22014-06-12 19:41:42 +03001/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/module.h>
17#include <linux/regmap.h>
18#include <linux/reset-controller.h>
19
20#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
22
23#include "common.h"
24#include "clk-regmap.h"
25#include "clk-pll.h"
26#include "clk-rcg.h"
27#include "clk-branch.h"
28#include "reset.h"
29
Georgi Djakov293d2e972015-03-20 18:30:26 +020030enum {
31 P_XO,
32 P_MMPLL0,
33 P_EDPLINK,
34 P_MMPLL1,
35 P_HDMIPLL,
36 P_GPLL0,
37 P_EDPVCO,
38 P_MMPLL4,
39 P_DSI0PLL,
40 P_DSI0PLL_BYTE,
41 P_MMPLL2,
42 P_MMPLL3,
43 P_GPLL1,
44 P_DSI1PLL,
45 P_DSI1PLL_BYTE,
46 P_MMSLEEP,
47};
Georgi Djakov2b46cd22014-06-12 19:41:42 +030048
Georgi Djakov293d2e972015-03-20 18:30:26 +020049static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
50 { P_XO, 0 },
51 { P_MMPLL0, 1 },
52 { P_MMPLL1, 2 },
53 { P_GPLL0, 5 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +030054};
55
Georgi Djakovadb11a42015-07-06 16:51:30 +030056static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +030057 "xo",
58 "mmpll0_vote",
59 "mmpll1_vote",
60 "mmss_gpll0_vote",
61};
62
Georgi Djakov293d2e972015-03-20 18:30:26 +020063static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
64 { P_XO, 0 },
65 { P_MMPLL0, 1 },
66 { P_HDMIPLL, 4 },
67 { P_GPLL0, 5 },
68 { P_DSI0PLL, 2 },
69 { P_DSI1PLL, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +030070};
71
Georgi Djakovadb11a42015-07-06 16:51:30 +030072static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +030073 "xo",
74 "mmpll0_vote",
75 "hdmipll",
76 "mmss_gpll0_vote",
77 "dsi0pll",
78 "dsi1pll",
79};
80
Georgi Djakov293d2e972015-03-20 18:30:26 +020081static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
82 { P_XO, 0 },
83 { P_MMPLL0, 1 },
84 { P_MMPLL1, 2 },
85 { P_GPLL0, 5 },
86 { P_MMPLL2, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +030087};
88
Georgi Djakovadb11a42015-07-06 16:51:30 +030089static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +030090 "xo",
91 "mmpll0_vote",
92 "mmpll1_vote",
93 "mmss_gpll0_vote",
94 "mmpll2",
95};
96
Georgi Djakov293d2e972015-03-20 18:30:26 +020097static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
98 { P_XO, 0 },
99 { P_MMPLL0, 1 },
100 { P_MMPLL1, 2 },
101 { P_GPLL0, 5 },
102 { P_MMPLL3, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300103};
104
Georgi Djakovadb11a42015-07-06 16:51:30 +0300105static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300106 "xo",
107 "mmpll0_vote",
108 "mmpll1_vote",
109 "mmss_gpll0_vote",
110 "mmpll3",
111};
112
Georgi Djakov293d2e972015-03-20 18:30:26 +0200113static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
114 { P_XO, 0 },
115 { P_EDPLINK, 4 },
116 { P_HDMIPLL, 3 },
117 { P_EDPVCO, 5 },
118 { P_DSI0PLL, 1 },
119 { P_DSI1PLL, 2 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300120};
121
Georgi Djakovadb11a42015-07-06 16:51:30 +0300122static const char * const mmcc_xo_dsi_hdmi_edp[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300123 "xo",
124 "edp_link_clk",
125 "hdmipll",
126 "edp_vco_div",
127 "dsi0pll",
128 "dsi1pll",
129};
130
Georgi Djakov293d2e972015-03-20 18:30:26 +0200131static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
132 { P_XO, 0 },
133 { P_EDPLINK, 4 },
134 { P_HDMIPLL, 3 },
135 { P_GPLL0, 5 },
136 { P_DSI0PLL, 1 },
137 { P_DSI1PLL, 2 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300138};
139
Georgi Djakovadb11a42015-07-06 16:51:30 +0300140static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300141 "xo",
142 "edp_link_clk",
143 "hdmipll",
144 "gpll0_vote",
145 "dsi0pll",
146 "dsi1pll",
147};
148
Georgi Djakov293d2e972015-03-20 18:30:26 +0200149static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
150 { P_XO, 0 },
151 { P_EDPLINK, 4 },
152 { P_HDMIPLL, 3 },
153 { P_GPLL0, 5 },
154 { P_DSI0PLL_BYTE, 1 },
155 { P_DSI1PLL_BYTE, 2 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300156};
157
Georgi Djakovadb11a42015-07-06 16:51:30 +0300158static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300159 "xo",
160 "edp_link_clk",
161 "hdmipll",
162 "gpll0_vote",
163 "dsi0pllbyte",
164 "dsi1pllbyte",
165};
166
Georgi Djakov293d2e972015-03-20 18:30:26 +0200167static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
168 { P_XO, 0 },
169 { P_MMPLL0, 1 },
170 { P_MMPLL1, 2 },
171 { P_GPLL0, 5 },
172 { P_MMPLL4, 3 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300173};
174
Georgi Djakovadb11a42015-07-06 16:51:30 +0300175static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300176 "xo",
177 "mmpll0",
178 "mmpll1",
179 "mmpll4",
180 "gpll0",
181};
182
Georgi Djakov293d2e972015-03-20 18:30:26 +0200183static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
184 { P_XO, 0 },
185 { P_MMPLL0, 1 },
186 { P_MMPLL1, 2 },
187 { P_MMPLL4, 3 },
188 { P_GPLL0, 5 },
189 { P_GPLL1, 4 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300190};
191
Georgi Djakovadb11a42015-07-06 16:51:30 +0300192static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300193 "xo",
194 "mmpll0",
195 "mmpll1",
196 "mmpll4",
197 "gpll1",
198 "gpll0",
199};
200
Georgi Djakov293d2e972015-03-20 18:30:26 +0200201static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
202 { P_XO, 0 },
203 { P_MMPLL0, 1 },
204 { P_MMPLL1, 2 },
205 { P_MMPLL4, 3 },
206 { P_GPLL0, 5 },
207 { P_GPLL1, 4 },
208 { P_MMSLEEP, 6 }
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300209};
210
Georgi Djakovadb11a42015-07-06 16:51:30 +0300211static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
Georgi Djakov2b46cd22014-06-12 19:41:42 +0300212 "xo",
213 "mmpll0",
214 "mmpll1",
215 "mmpll4",
216 "gpll1",
217 "gpll0",
218 "sleep_clk_src",
219};
220
221#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
222
223static struct clk_pll mmpll0 = {
224 .l_reg = 0x0004,
225 .m_reg = 0x0008,
226 .n_reg = 0x000c,
227 .config_reg = 0x0014,
228 .mode_reg = 0x0000,
229 .status_reg = 0x001c,
230 .status_bit = 17,
231 .clkr.hw.init = &(struct clk_init_data){
232 .name = "mmpll0",
233 .parent_names = (const char *[]){ "xo" },
234 .num_parents = 1,
235 .ops = &clk_pll_ops,
236 },
237};
238
239static struct clk_regmap mmpll0_vote = {
240 .enable_reg = 0x0100,
241 .enable_mask = BIT(0),
242 .hw.init = &(struct clk_init_data){
243 .name = "mmpll0_vote",
244 .parent_names = (const char *[]){ "mmpll0" },
245 .num_parents = 1,
246 .ops = &clk_pll_vote_ops,
247 },
248};
249
250static struct clk_pll mmpll1 = {
251 .l_reg = 0x0044,
252 .m_reg = 0x0048,
253 .n_reg = 0x004c,
254 .config_reg = 0x0050,
255 .mode_reg = 0x0040,
256 .status_reg = 0x005c,
257 .status_bit = 17,
258 .clkr.hw.init = &(struct clk_init_data){
259 .name = "mmpll1",
260 .parent_names = (const char *[]){ "xo" },
261 .num_parents = 1,
262 .ops = &clk_pll_ops,
263 },
264};
265
266static struct clk_regmap mmpll1_vote = {
267 .enable_reg = 0x0100,
268 .enable_mask = BIT(1),
269 .hw.init = &(struct clk_init_data){
270 .name = "mmpll1_vote",
271 .parent_names = (const char *[]){ "mmpll1" },
272 .num_parents = 1,
273 .ops = &clk_pll_vote_ops,
274 },
275};
276
277static struct clk_pll mmpll2 = {
278 .l_reg = 0x4104,
279 .m_reg = 0x4108,
280 .n_reg = 0x410c,
281 .config_reg = 0x4110,
282 .mode_reg = 0x4100,
283 .status_reg = 0x411c,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "mmpll2",
286 .parent_names = (const char *[]){ "xo" },
287 .num_parents = 1,
288 .ops = &clk_pll_ops,
289 },
290};
291
292static struct clk_pll mmpll3 = {
293 .l_reg = 0x0084,
294 .m_reg = 0x0088,
295 .n_reg = 0x008c,
296 .config_reg = 0x0090,
297 .mode_reg = 0x0080,
298 .status_reg = 0x009c,
299 .status_bit = 17,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "mmpll3",
302 .parent_names = (const char *[]){ "xo" },
303 .num_parents = 1,
304 .ops = &clk_pll_ops,
305 },
306};
307
308static struct clk_pll mmpll4 = {
309 .l_reg = 0x00a4,
310 .m_reg = 0x00a8,
311 .n_reg = 0x00ac,
312 .config_reg = 0x00b0,
313 .mode_reg = 0x0080,
314 .status_reg = 0x00bc,
315 .clkr.hw.init = &(struct clk_init_data){
316 .name = "mmpll4",
317 .parent_names = (const char *[]){ "xo" },
318 .num_parents = 1,
319 .ops = &clk_pll_ops,
320 },
321};
322
323static struct clk_rcg2 mmss_ahb_clk_src = {
324 .cmd_rcgr = 0x5000,
325 .hid_width = 5,
326 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
327 .clkr.hw.init = &(struct clk_init_data){
328 .name = "mmss_ahb_clk_src",
329 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
330 .num_parents = 4,
331 .ops = &clk_rcg2_ops,
332 },
333};
334
335static struct freq_tbl ftbl_mmss_axi_clk[] = {
336 F(19200000, P_XO, 1, 0, 0),
337 F(37500000, P_GPLL0, 16, 0, 0),
338 F(50000000, P_GPLL0, 12, 0, 0),
339 F(75000000, P_GPLL0, 8, 0, 0),
340 F(100000000, P_GPLL0, 6, 0, 0),
341 F(150000000, P_GPLL0, 4, 0, 0),
342 F(333430000, P_MMPLL1, 3.5, 0, 0),
343 F(400000000, P_MMPLL0, 2, 0, 0),
344 F(466800000, P_MMPLL1, 2.5, 0, 0),
345};
346
347static struct clk_rcg2 mmss_axi_clk_src = {
348 .cmd_rcgr = 0x5040,
349 .hid_width = 5,
350 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
351 .freq_tbl = ftbl_mmss_axi_clk,
352 .clkr.hw.init = &(struct clk_init_data){
353 .name = "mmss_axi_clk_src",
354 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
355 .num_parents = 4,
356 .ops = &clk_rcg2_ops,
357 },
358};
359
360static struct freq_tbl ftbl_ocmemnoc_clk[] = {
361 F(19200000, P_XO, 1, 0, 0),
362 F(37500000, P_GPLL0, 16, 0, 0),
363 F(50000000, P_GPLL0, 12, 0, 0),
364 F(75000000, P_GPLL0, 8, 0, 0),
365 F(109090000, P_GPLL0, 5.5, 0, 0),
366 F(150000000, P_GPLL0, 4, 0, 0),
367 F(228570000, P_MMPLL0, 3.5, 0, 0),
368 F(320000000, P_MMPLL0, 2.5, 0, 0),
369};
370
371static struct clk_rcg2 ocmemnoc_clk_src = {
372 .cmd_rcgr = 0x5090,
373 .hid_width = 5,
374 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
375 .freq_tbl = ftbl_ocmemnoc_clk,
376 .clkr.hw.init = &(struct clk_init_data){
377 .name = "ocmemnoc_clk_src",
378 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
379 .num_parents = 4,
380 .ops = &clk_rcg2_ops,
381 },
382};
383
384static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
385 F(100000000, P_GPLL0, 6, 0, 0),
386 F(200000000, P_MMPLL0, 4, 0, 0),
387 { }
388};
389
390static struct clk_rcg2 csi0_clk_src = {
391 .cmd_rcgr = 0x3090,
392 .hid_width = 5,
393 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
394 .freq_tbl = ftbl_camss_csi0_3_clk,
395 .clkr.hw.init = &(struct clk_init_data){
396 .name = "csi0_clk_src",
397 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
398 .num_parents = 5,
399 .ops = &clk_rcg2_ops,
400 },
401};
402
403static struct clk_rcg2 csi1_clk_src = {
404 .cmd_rcgr = 0x3100,
405 .hid_width = 5,
406 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
407 .freq_tbl = ftbl_camss_csi0_3_clk,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "csi1_clk_src",
410 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
411 .num_parents = 5,
412 .ops = &clk_rcg2_ops,
413 },
414};
415
416static struct clk_rcg2 csi2_clk_src = {
417 .cmd_rcgr = 0x3160,
418 .hid_width = 5,
419 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
420 .freq_tbl = ftbl_camss_csi0_3_clk,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "csi2_clk_src",
423 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
424 .num_parents = 5,
425 .ops = &clk_rcg2_ops,
426 },
427};
428
429static struct clk_rcg2 csi3_clk_src = {
430 .cmd_rcgr = 0x31c0,
431 .hid_width = 5,
432 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
433 .freq_tbl = ftbl_camss_csi0_3_clk,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "csi3_clk_src",
436 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
437 .num_parents = 5,
438 .ops = &clk_rcg2_ops,
439 },
440};
441
442static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
443 F(37500000, P_GPLL0, 16, 0, 0),
444 F(50000000, P_GPLL0, 12, 0, 0),
445 F(60000000, P_GPLL0, 10, 0, 0),
446 F(80000000, P_GPLL0, 7.5, 0, 0),
447 F(100000000, P_GPLL0, 6, 0, 0),
448 F(109090000, P_GPLL0, 5.5, 0, 0),
449 F(133330000, P_GPLL0, 4.5, 0, 0),
450 F(200000000, P_GPLL0, 3, 0, 0),
451 F(228570000, P_MMPLL0, 3.5, 0, 0),
452 F(266670000, P_MMPLL0, 3, 0, 0),
453 F(320000000, P_MMPLL0, 2.5, 0, 0),
454 F(465000000, P_MMPLL4, 2, 0, 0),
455 F(600000000, P_GPLL0, 1, 0, 0),
456 { }
457};
458
459static struct clk_rcg2 vfe0_clk_src = {
460 .cmd_rcgr = 0x3600,
461 .hid_width = 5,
462 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
463 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
464 .clkr.hw.init = &(struct clk_init_data){
465 .name = "vfe0_clk_src",
466 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
467 .num_parents = 5,
468 .ops = &clk_rcg2_ops,
469 },
470};
471
472static struct clk_rcg2 vfe1_clk_src = {
473 .cmd_rcgr = 0x3620,
474 .hid_width = 5,
475 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
476 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
477 .clkr.hw.init = &(struct clk_init_data){
478 .name = "vfe1_clk_src",
479 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
480 .num_parents = 5,
481 .ops = &clk_rcg2_ops,
482 },
483};
484
485static struct freq_tbl ftbl_mdss_mdp_clk[] = {
486 F(37500000, P_GPLL0, 16, 0, 0),
487 F(60000000, P_GPLL0, 10, 0, 0),
488 F(75000000, P_GPLL0, 8, 0, 0),
489 F(85710000, P_GPLL0, 7, 0, 0),
490 F(100000000, P_GPLL0, 6, 0, 0),
491 F(150000000, P_GPLL0, 4, 0, 0),
492 F(160000000, P_MMPLL0, 5, 0, 0),
493 F(200000000, P_MMPLL0, 4, 0, 0),
494 F(228570000, P_MMPLL0, 3.5, 0, 0),
495 F(300000000, P_GPLL0, 2, 0, 0),
496 F(320000000, P_MMPLL0, 2.5, 0, 0),
497 { }
498};
499
500static struct clk_rcg2 mdp_clk_src = {
501 .cmd_rcgr = 0x2040,
502 .hid_width = 5,
503 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
504 .freq_tbl = ftbl_mdss_mdp_clk,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "mdp_clk_src",
507 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
508 .num_parents = 6,
509 .ops = &clk_rcg2_ops,
510 },
511};
512
513static struct clk_rcg2 gfx3d_clk_src = {
514 .cmd_rcgr = 0x4000,
515 .hid_width = 5,
516 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "gfx3d_clk_src",
519 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
520 .num_parents = 5,
521 .ops = &clk_rcg2_ops,
522 },
523};
524
525static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
526 F(75000000, P_GPLL0, 8, 0, 0),
527 F(133330000, P_GPLL0, 4.5, 0, 0),
528 F(200000000, P_GPLL0, 3, 0, 0),
529 F(228570000, P_MMPLL0, 3.5, 0, 0),
530 F(266670000, P_MMPLL0, 3, 0, 0),
531 F(320000000, P_MMPLL0, 2.5, 0, 0),
532 { }
533};
534
535static struct clk_rcg2 jpeg0_clk_src = {
536 .cmd_rcgr = 0x3500,
537 .hid_width = 5,
538 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
539 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
540 .clkr.hw.init = &(struct clk_init_data){
541 .name = "jpeg0_clk_src",
542 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
543 .num_parents = 5,
544 .ops = &clk_rcg2_ops,
545 },
546};
547
548static struct clk_rcg2 jpeg1_clk_src = {
549 .cmd_rcgr = 0x3520,
550 .hid_width = 5,
551 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
552 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
553 .clkr.hw.init = &(struct clk_init_data){
554 .name = "jpeg1_clk_src",
555 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
556 .num_parents = 5,
557 .ops = &clk_rcg2_ops,
558 },
559};
560
561static struct clk_rcg2 jpeg2_clk_src = {
562 .cmd_rcgr = 0x3540,
563 .hid_width = 5,
564 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
565 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "jpeg2_clk_src",
568 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
569 .num_parents = 5,
570 .ops = &clk_rcg2_ops,
571 },
572};
573
574static struct freq_tbl pixel_freq_tbl[] = {
575 { .src = P_DSI0PLL },
576 { }
577};
578
579static struct clk_rcg2 pclk0_clk_src = {
580 .cmd_rcgr = 0x2000,
581 .mnd_width = 8,
582 .hid_width = 5,
583 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
584 .freq_tbl = pixel_freq_tbl,
585 .clkr.hw.init = &(struct clk_init_data){
586 .name = "pclk0_clk_src",
587 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
588 .num_parents = 6,
589 .ops = &clk_pixel_ops,
590 .flags = CLK_SET_RATE_PARENT,
591 },
592};
593
594static struct clk_rcg2 pclk1_clk_src = {
595 .cmd_rcgr = 0x2020,
596 .mnd_width = 8,
597 .hid_width = 5,
598 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
599 .freq_tbl = pixel_freq_tbl,
600 .clkr.hw.init = &(struct clk_init_data){
601 .name = "pclk1_clk_src",
602 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
603 .num_parents = 6,
604 .ops = &clk_pixel_ops,
605 .flags = CLK_SET_RATE_PARENT,
606 },
607};
608
609static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
610 F(50000000, P_GPLL0, 12, 0, 0),
611 F(100000000, P_GPLL0, 6, 0, 0),
612 F(133330000, P_GPLL0, 4.5, 0, 0),
613 F(200000000, P_MMPLL0, 4, 0, 0),
614 F(266670000, P_MMPLL0, 3, 0, 0),
615 F(465000000, P_MMPLL3, 2, 0, 0),
616 { }
617};
618
619static struct clk_rcg2 vcodec0_clk_src = {
620 .cmd_rcgr = 0x1000,
621 .mnd_width = 8,
622 .hid_width = 5,
623 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
624 .freq_tbl = ftbl_venus0_vcodec0_clk,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "vcodec0_clk_src",
627 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
628 .num_parents = 5,
629 .ops = &clk_rcg2_ops,
630 },
631};
632
633static struct freq_tbl ftbl_avsync_vp_clk[] = {
634 F(150000000, P_GPLL0, 4, 0, 0),
635 F(320000000, P_MMPLL0, 2.5, 0, 0),
636 { }
637};
638
639static struct clk_rcg2 vp_clk_src = {
640 .cmd_rcgr = 0x2430,
641 .hid_width = 5,
642 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
643 .freq_tbl = ftbl_avsync_vp_clk,
644 .clkr.hw.init = &(struct clk_init_data){
645 .name = "vp_clk_src",
646 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
647 .num_parents = 4,
648 .ops = &clk_rcg2_ops,
649 },
650};
651
652static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
653 F(19200000, P_XO, 1, 0, 0),
654 { }
655};
656
657static struct clk_rcg2 cci_clk_src = {
658 .cmd_rcgr = 0x3300,
659 .mnd_width = 8,
660 .hid_width = 5,
661 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
662 .freq_tbl = ftbl_camss_cci_cci_clk,
663 .clkr.hw.init = &(struct clk_init_data){
664 .name = "cci_clk_src",
665 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
666 .num_parents = 6,
667 .ops = &clk_rcg2_ops,
668 },
669};
670
671static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
672 F(10000, P_XO, 16, 1, 120),
673 F(24000, P_XO, 16, 1, 50),
674 F(6000000, P_GPLL0, 10, 1, 10),
675 F(12000000, P_GPLL0, 10, 1, 5),
676 F(13000000, P_GPLL0, 4, 13, 150),
677 F(24000000, P_GPLL0, 5, 1, 5),
678 { }
679};
680
681static struct clk_rcg2 camss_gp0_clk_src = {
682 .cmd_rcgr = 0x3420,
683 .mnd_width = 8,
684 .hid_width = 5,
685 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
686 .freq_tbl = ftbl_camss_gp0_1_clk,
687 .clkr.hw.init = &(struct clk_init_data){
688 .name = "camss_gp0_clk_src",
689 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
690 .num_parents = 7,
691 .ops = &clk_rcg2_ops,
692 },
693};
694
695static struct clk_rcg2 camss_gp1_clk_src = {
696 .cmd_rcgr = 0x3450,
697 .mnd_width = 8,
698 .hid_width = 5,
699 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
700 .freq_tbl = ftbl_camss_gp0_1_clk,
701 .clkr.hw.init = &(struct clk_init_data){
702 .name = "camss_gp1_clk_src",
703 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
704 .num_parents = 7,
705 .ops = &clk_rcg2_ops,
706 },
707};
708
709static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
710 F(4800000, P_XO, 4, 0, 0),
711 F(6000000, P_GPLL0, 10, 1, 10),
712 F(8000000, P_GPLL0, 15, 1, 5),
713 F(9600000, P_XO, 2, 0, 0),
714 F(16000000, P_MMPLL0, 10, 1, 5),
715 F(19200000, P_XO, 1, 0, 0),
716 F(24000000, P_GPLL0, 5, 1, 5),
717 F(32000000, P_MMPLL0, 5, 1, 5),
718 F(48000000, P_GPLL0, 12.5, 0, 0),
719 F(64000000, P_MMPLL0, 12.5, 0, 0),
720 { }
721};
722
723static struct clk_rcg2 mclk0_clk_src = {
724 .cmd_rcgr = 0x3360,
725 .mnd_width = 8,
726 .hid_width = 5,
727 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
728 .freq_tbl = ftbl_camss_mclk0_3_clk,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "mclk0_clk_src",
731 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
732 .num_parents = 6,
733 .ops = &clk_rcg2_ops,
734 },
735};
736
737static struct clk_rcg2 mclk1_clk_src = {
738 .cmd_rcgr = 0x3390,
739 .mnd_width = 8,
740 .hid_width = 5,
741 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
742 .freq_tbl = ftbl_camss_mclk0_3_clk,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "mclk1_clk_src",
745 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
746 .num_parents = 6,
747 .ops = &clk_rcg2_ops,
748 },
749};
750
751static struct clk_rcg2 mclk2_clk_src = {
752 .cmd_rcgr = 0x33c0,
753 .mnd_width = 8,
754 .hid_width = 5,
755 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
756 .freq_tbl = ftbl_camss_mclk0_3_clk,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "mclk2_clk_src",
759 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
760 .num_parents = 6,
761 .ops = &clk_rcg2_ops,
762 },
763};
764
765static struct clk_rcg2 mclk3_clk_src = {
766 .cmd_rcgr = 0x33f0,
767 .mnd_width = 8,
768 .hid_width = 5,
769 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
770 .freq_tbl = ftbl_camss_mclk0_3_clk,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "mclk3_clk_src",
773 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
774 .num_parents = 6,
775 .ops = &clk_rcg2_ops,
776 },
777};
778
779static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
780 F(100000000, P_GPLL0, 6, 0, 0),
781 F(200000000, P_MMPLL0, 4, 0, 0),
782 { }
783};
784
785static struct clk_rcg2 csi0phytimer_clk_src = {
786 .cmd_rcgr = 0x3000,
787 .hid_width = 5,
788 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
789 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
790 .clkr.hw.init = &(struct clk_init_data){
791 .name = "csi0phytimer_clk_src",
792 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
793 .num_parents = 5,
794 .ops = &clk_rcg2_ops,
795 },
796};
797
798static struct clk_rcg2 csi1phytimer_clk_src = {
799 .cmd_rcgr = 0x3030,
800 .hid_width = 5,
801 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
802 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
803 .clkr.hw.init = &(struct clk_init_data){
804 .name = "csi1phytimer_clk_src",
805 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
806 .num_parents = 5,
807 .ops = &clk_rcg2_ops,
808 },
809};
810
811static struct clk_rcg2 csi2phytimer_clk_src = {
812 .cmd_rcgr = 0x3060,
813 .hid_width = 5,
814 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
815 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
816 .clkr.hw.init = &(struct clk_init_data){
817 .name = "csi2phytimer_clk_src",
818 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
819 .num_parents = 5,
820 .ops = &clk_rcg2_ops,
821 },
822};
823
824static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
825 F(133330000, P_GPLL0, 4.5, 0, 0),
826 F(266670000, P_MMPLL0, 3, 0, 0),
827 F(320000000, P_MMPLL0, 2.5, 0, 0),
828 F(372000000, P_MMPLL4, 2.5, 0, 0),
829 F(465000000, P_MMPLL4, 2, 0, 0),
830 F(600000000, P_GPLL0, 1, 0, 0),
831 { }
832};
833
834static struct clk_rcg2 cpp_clk_src = {
835 .cmd_rcgr = 0x3640,
836 .hid_width = 5,
837 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
838 .freq_tbl = ftbl_camss_vfe_cpp_clk,
839 .clkr.hw.init = &(struct clk_init_data){
840 .name = "cpp_clk_src",
841 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
842 .num_parents = 5,
843 .ops = &clk_rcg2_ops,
844 },
845};
846
847static struct freq_tbl byte_freq_tbl[] = {
848 { .src = P_DSI0PLL_BYTE },
849 { }
850};
851
852static struct clk_rcg2 byte0_clk_src = {
853 .cmd_rcgr = 0x2120,
854 .hid_width = 5,
855 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
856 .freq_tbl = byte_freq_tbl,
857 .clkr.hw.init = &(struct clk_init_data){
858 .name = "byte0_clk_src",
859 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
860 .num_parents = 6,
861 .ops = &clk_byte_ops,
862 .flags = CLK_SET_RATE_PARENT,
863 },
864};
865
866static struct clk_rcg2 byte1_clk_src = {
867 .cmd_rcgr = 0x2140,
868 .hid_width = 5,
869 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
870 .freq_tbl = byte_freq_tbl,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "byte1_clk_src",
873 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
874 .num_parents = 6,
875 .ops = &clk_byte_ops,
876 .flags = CLK_SET_RATE_PARENT,
877 },
878};
879
880static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
881 F(19200000, P_XO, 1, 0, 0),
882 { }
883};
884
885static struct clk_rcg2 edpaux_clk_src = {
886 .cmd_rcgr = 0x20e0,
887 .hid_width = 5,
888 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
889 .freq_tbl = ftbl_mdss_edpaux_clk,
890 .clkr.hw.init = &(struct clk_init_data){
891 .name = "edpaux_clk_src",
892 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
893 .num_parents = 4,
894 .ops = &clk_rcg2_ops,
895 },
896};
897
898static struct freq_tbl ftbl_mdss_edplink_clk[] = {
899 F(135000000, P_EDPLINK, 2, 0, 0),
900 F(270000000, P_EDPLINK, 11, 0, 0),
901 { }
902};
903
904static struct clk_rcg2 edplink_clk_src = {
905 .cmd_rcgr = 0x20c0,
906 .hid_width = 5,
907 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
908 .freq_tbl = ftbl_mdss_edplink_clk,
909 .clkr.hw.init = &(struct clk_init_data){
910 .name = "edplink_clk_src",
911 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
912 .num_parents = 6,
913 .ops = &clk_rcg2_ops,
914 .flags = CLK_SET_RATE_PARENT,
915 },
916};
917
918static struct freq_tbl edp_pixel_freq_tbl[] = {
919 { .src = P_EDPVCO },
920 { }
921};
922
923static struct clk_rcg2 edppixel_clk_src = {
924 .cmd_rcgr = 0x20a0,
925 .mnd_width = 8,
926 .hid_width = 5,
927 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
928 .freq_tbl = edp_pixel_freq_tbl,
929 .clkr.hw.init = &(struct clk_init_data){
930 .name = "edppixel_clk_src",
931 .parent_names = mmcc_xo_dsi_hdmi_edp,
932 .num_parents = 6,
933 .ops = &clk_edp_pixel_ops,
934 },
935};
936
937static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
938 F(19200000, P_XO, 1, 0, 0),
939 { }
940};
941
942static struct clk_rcg2 esc0_clk_src = {
943 .cmd_rcgr = 0x2160,
944 .hid_width = 5,
945 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
946 .freq_tbl = ftbl_mdss_esc0_1_clk,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "esc0_clk_src",
949 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
950 .num_parents = 6,
951 .ops = &clk_rcg2_ops,
952 },
953};
954
955static struct clk_rcg2 esc1_clk_src = {
956 .cmd_rcgr = 0x2180,
957 .hid_width = 5,
958 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
959 .freq_tbl = ftbl_mdss_esc0_1_clk,
960 .clkr.hw.init = &(struct clk_init_data){
961 .name = "esc1_clk_src",
962 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
963 .num_parents = 6,
964 .ops = &clk_rcg2_ops,
965 },
966};
967
968static struct freq_tbl extpclk_freq_tbl[] = {
969 { .src = P_HDMIPLL },
970 { }
971};
972
973static struct clk_rcg2 extpclk_clk_src = {
974 .cmd_rcgr = 0x2060,
975 .hid_width = 5,
976 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
977 .freq_tbl = extpclk_freq_tbl,
978 .clkr.hw.init = &(struct clk_init_data){
979 .name = "extpclk_clk_src",
980 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
981 .num_parents = 6,
982 .ops = &clk_byte_ops,
983 .flags = CLK_SET_RATE_PARENT,
984 },
985};
986
987static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
988 F(19200000, P_XO, 1, 0, 0),
989 { }
990};
991
992static struct clk_rcg2 hdmi_clk_src = {
993 .cmd_rcgr = 0x2100,
994 .hid_width = 5,
995 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
996 .freq_tbl = ftbl_mdss_hdmi_clk,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "hdmi_clk_src",
999 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1000 .num_parents = 4,
1001 .ops = &clk_rcg2_ops,
1002 },
1003};
1004
1005static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1006 F(19200000, P_XO, 1, 0, 0),
1007 { }
1008};
1009
1010static struct clk_rcg2 vsync_clk_src = {
1011 .cmd_rcgr = 0x2080,
1012 .hid_width = 5,
1013 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1014 .freq_tbl = ftbl_mdss_vsync_clk,
1015 .clkr.hw.init = &(struct clk_init_data){
1016 .name = "vsync_clk_src",
1017 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1018 .num_parents = 4,
1019 .ops = &clk_rcg2_ops,
1020 },
1021};
1022
1023static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1024 F(50000000, P_GPLL0, 12, 0, 0),
1025 { }
1026};
1027
1028static struct clk_rcg2 rbcpr_clk_src = {
1029 .cmd_rcgr = 0x4060,
1030 .hid_width = 5,
1031 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1032 .freq_tbl = ftbl_mmss_rbcpr_clk,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "rbcpr_clk_src",
1035 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1036 .num_parents = 4,
1037 .ops = &clk_rcg2_ops,
1038 },
1039};
1040
1041static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1042 F(19200000, P_XO, 1, 0, 0),
1043 { }
1044};
1045
1046static struct clk_rcg2 rbbmtimer_clk_src = {
1047 .cmd_rcgr = 0x4090,
1048 .hid_width = 5,
1049 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1050 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "rbbmtimer_clk_src",
1053 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1054 .num_parents = 4,
1055 .ops = &clk_rcg2_ops,
1056 },
1057};
1058
1059static struct freq_tbl ftbl_vpu_maple_clk[] = {
1060 F(50000000, P_GPLL0, 12, 0, 0),
1061 F(100000000, P_GPLL0, 6, 0, 0),
1062 F(133330000, P_GPLL0, 4.5, 0, 0),
1063 F(200000000, P_MMPLL0, 4, 0, 0),
1064 F(266670000, P_MMPLL0, 3, 0, 0),
1065 F(465000000, P_MMPLL3, 2, 0, 0),
1066 { }
1067};
1068
1069static struct clk_rcg2 maple_clk_src = {
1070 .cmd_rcgr = 0x1320,
1071 .hid_width = 5,
1072 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1073 .freq_tbl = ftbl_vpu_maple_clk,
1074 .clkr.hw.init = &(struct clk_init_data){
1075 .name = "maple_clk_src",
1076 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1077 .num_parents = 4,
1078 .ops = &clk_rcg2_ops,
1079 },
1080};
1081
1082static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1083 F(50000000, P_GPLL0, 12, 0, 0),
1084 F(100000000, P_GPLL0, 6, 0, 0),
1085 F(200000000, P_MMPLL0, 4, 0, 0),
1086 F(320000000, P_MMPLL0, 2.5, 0, 0),
1087 F(400000000, P_MMPLL0, 2, 0, 0),
1088 { }
1089};
1090
1091static struct clk_rcg2 vdp_clk_src = {
1092 .cmd_rcgr = 0x1300,
1093 .hid_width = 5,
1094 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1095 .freq_tbl = ftbl_vpu_vdp_clk,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "vdp_clk_src",
1098 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1099 .num_parents = 4,
1100 .ops = &clk_rcg2_ops,
1101 },
1102};
1103
1104static struct freq_tbl ftbl_vpu_bus_clk[] = {
1105 F(40000000, P_GPLL0, 15, 0, 0),
1106 F(80000000, P_MMPLL0, 10, 0, 0),
1107 { }
1108};
1109
1110static struct clk_rcg2 vpu_bus_clk_src = {
1111 .cmd_rcgr = 0x1340,
1112 .hid_width = 5,
1113 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1114 .freq_tbl = ftbl_vpu_bus_clk,
1115 .clkr.hw.init = &(struct clk_init_data){
1116 .name = "vpu_bus_clk_src",
1117 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1118 .num_parents = 4,
1119 .ops = &clk_rcg2_ops,
1120 },
1121};
1122
1123static struct clk_branch mmss_cxo_clk = {
1124 .halt_reg = 0x5104,
1125 .clkr = {
1126 .enable_reg = 0x5104,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "mmss_cxo_clk",
1130 .parent_names = (const char *[]){ "xo" },
1131 .num_parents = 1,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136};
1137
1138static struct clk_branch mmss_sleepclk_clk = {
1139 .halt_reg = 0x5100,
1140 .clkr = {
1141 .enable_reg = 0x5100,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "mmss_sleepclk_clk",
1145 .parent_names = (const char *[]){
1146 "sleep_clk_src",
1147 },
1148 .num_parents = 1,
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1151 },
1152 },
1153};
1154
1155static struct clk_branch avsync_ahb_clk = {
1156 .halt_reg = 0x2414,
1157 .clkr = {
1158 .enable_reg = 0x2414,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "avsync_ahb_clk",
1162 .parent_names = (const char *[]){
1163 "mmss_ahb_clk_src",
1164 },
1165 .num_parents = 1,
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1168 },
1169 },
1170};
1171
1172static struct clk_branch avsync_edppixel_clk = {
1173 .halt_reg = 0x2418,
1174 .clkr = {
1175 .enable_reg = 0x2418,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "avsync_edppixel_clk",
1179 .parent_names = (const char *[]){
1180 "edppixel_clk_src",
1181 },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch avsync_extpclk_clk = {
1190 .halt_reg = 0x2410,
1191 .clkr = {
1192 .enable_reg = 0x2410,
1193 .enable_mask = BIT(0),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "avsync_extpclk_clk",
1196 .parent_names = (const char *[]){
1197 "extpclk_clk_src",
1198 },
1199 .num_parents = 1,
1200 .flags = CLK_SET_RATE_PARENT,
1201 .ops = &clk_branch2_ops,
1202 },
1203 },
1204};
1205
1206static struct clk_branch avsync_pclk0_clk = {
1207 .halt_reg = 0x241c,
1208 .clkr = {
1209 .enable_reg = 0x241c,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "avsync_pclk0_clk",
1213 .parent_names = (const char *[]){
1214 "pclk0_clk_src",
1215 },
1216 .num_parents = 1,
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1219 },
1220 },
1221};
1222
1223static struct clk_branch avsync_pclk1_clk = {
1224 .halt_reg = 0x2420,
1225 .clkr = {
1226 .enable_reg = 0x2420,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "avsync_pclk1_clk",
1230 .parent_names = (const char *[]){
1231 "pclk1_clk_src",
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238};
1239
1240static struct clk_branch avsync_vp_clk = {
1241 .halt_reg = 0x2404,
1242 .clkr = {
1243 .enable_reg = 0x2404,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "avsync_vp_clk",
1247 .parent_names = (const char *[]){
1248 "vp_clk_src",
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch camss_ahb_clk = {
1258 .halt_reg = 0x348c,
1259 .clkr = {
1260 .enable_reg = 0x348c,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "camss_ahb_clk",
1264 .parent_names = (const char *[]){
1265 "mmss_ahb_clk_src",
1266 },
1267 .num_parents = 1,
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1270 },
1271 },
1272};
1273
1274static struct clk_branch camss_cci_cci_ahb_clk = {
1275 .halt_reg = 0x3348,
1276 .clkr = {
1277 .enable_reg = 0x3348,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "camss_cci_cci_ahb_clk",
1281 .parent_names = (const char *[]){
1282 "mmss_ahb_clk_src",
1283 },
1284 .num_parents = 1,
1285 .ops = &clk_branch2_ops,
1286 },
1287 },
1288};
1289
1290static struct clk_branch camss_cci_cci_clk = {
1291 .halt_reg = 0x3344,
1292 .clkr = {
1293 .enable_reg = 0x3344,
1294 .enable_mask = BIT(0),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "camss_cci_cci_clk",
1297 .parent_names = (const char *[]){
1298 "cci_clk_src",
1299 },
1300 .num_parents = 1,
1301 .flags = CLK_SET_RATE_PARENT,
1302 .ops = &clk_branch2_ops,
1303 },
1304 },
1305};
1306
1307static struct clk_branch camss_csi0_ahb_clk = {
1308 .halt_reg = 0x30bc,
1309 .clkr = {
1310 .enable_reg = 0x30bc,
1311 .enable_mask = BIT(0),
1312 .hw.init = &(struct clk_init_data){
1313 .name = "camss_csi0_ahb_clk",
1314 .parent_names = (const char *[]){
1315 "mmss_ahb_clk_src",
1316 },
1317 .num_parents = 1,
1318 .ops = &clk_branch2_ops,
1319 },
1320 },
1321};
1322
1323static struct clk_branch camss_csi0_clk = {
1324 .halt_reg = 0x30b4,
1325 .clkr = {
1326 .enable_reg = 0x30b4,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "camss_csi0_clk",
1330 .parent_names = (const char *[]){
1331 "csi0_clk_src",
1332 },
1333 .num_parents = 1,
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1336 },
1337 },
1338};
1339
1340static struct clk_branch camss_csi0phy_clk = {
1341 .halt_reg = 0x30c4,
1342 .clkr = {
1343 .enable_reg = 0x30c4,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "camss_csi0phy_clk",
1347 .parent_names = (const char *[]){
1348 "csi0_clk_src",
1349 },
1350 .num_parents = 1,
1351 .flags = CLK_SET_RATE_PARENT,
1352 .ops = &clk_branch2_ops,
1353 },
1354 },
1355};
1356
1357static struct clk_branch camss_csi0pix_clk = {
1358 .halt_reg = 0x30e4,
1359 .clkr = {
1360 .enable_reg = 0x30e4,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "camss_csi0pix_clk",
1364 .parent_names = (const char *[]){
1365 "csi0_clk_src",
1366 },
1367 .num_parents = 1,
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1370 },
1371 },
1372};
1373
1374static struct clk_branch camss_csi0rdi_clk = {
1375 .halt_reg = 0x30d4,
1376 .clkr = {
1377 .enable_reg = 0x30d4,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "camss_csi0rdi_clk",
1381 .parent_names = (const char *[]){
1382 "csi0_clk_src",
1383 },
1384 .num_parents = 1,
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1387 },
1388 },
1389};
1390
1391static struct clk_branch camss_csi1_ahb_clk = {
1392 .halt_reg = 0x3128,
1393 .clkr = {
1394 .enable_reg = 0x3128,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "camss_csi1_ahb_clk",
1398 .parent_names = (const char *[]){
1399 "mmss_ahb_clk_src",
1400 },
1401 .num_parents = 1,
1402 .flags = CLK_SET_RATE_PARENT,
1403 .ops = &clk_branch2_ops,
1404 },
1405 },
1406};
1407
1408static struct clk_branch camss_csi1_clk = {
1409 .halt_reg = 0x3124,
1410 .clkr = {
1411 .enable_reg = 0x3124,
1412 .enable_mask = BIT(0),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "camss_csi1_clk",
1415 .parent_names = (const char *[]){
1416 "csi1_clk_src",
1417 },
1418 .num_parents = 1,
1419 .flags = CLK_SET_RATE_PARENT,
1420 .ops = &clk_branch2_ops,
1421 },
1422 },
1423};
1424
1425static struct clk_branch camss_csi1phy_clk = {
1426 .halt_reg = 0x3134,
1427 .clkr = {
1428 .enable_reg = 0x3134,
1429 .enable_mask = BIT(0),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "camss_csi1phy_clk",
1432 .parent_names = (const char *[]){
1433 "csi1_clk_src",
1434 },
1435 .num_parents = 1,
1436 .flags = CLK_SET_RATE_PARENT,
1437 .ops = &clk_branch2_ops,
1438 },
1439 },
1440};
1441
1442static struct clk_branch camss_csi1pix_clk = {
1443 .halt_reg = 0x3154,
1444 .clkr = {
1445 .enable_reg = 0x3154,
1446 .enable_mask = BIT(0),
1447 .hw.init = &(struct clk_init_data){
1448 .name = "camss_csi1pix_clk",
1449 .parent_names = (const char *[]){
1450 "csi1_clk_src",
1451 },
1452 .num_parents = 1,
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1455 },
1456 },
1457};
1458
1459static struct clk_branch camss_csi1rdi_clk = {
1460 .halt_reg = 0x3144,
1461 .clkr = {
1462 .enable_reg = 0x3144,
1463 .enable_mask = BIT(0),
1464 .hw.init = &(struct clk_init_data){
1465 .name = "camss_csi1rdi_clk",
1466 .parent_names = (const char *[]){
1467 "csi1_clk_src",
1468 },
1469 .num_parents = 1,
1470 .flags = CLK_SET_RATE_PARENT,
1471 .ops = &clk_branch2_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch camss_csi2_ahb_clk = {
1477 .halt_reg = 0x3188,
1478 .clkr = {
1479 .enable_reg = 0x3188,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "camss_csi2_ahb_clk",
1483 .parent_names = (const char *[]){
1484 "mmss_ahb_clk_src",
1485 },
1486 .num_parents = 1,
1487 .ops = &clk_branch2_ops,
1488 },
1489 },
1490};
1491
1492static struct clk_branch camss_csi2_clk = {
1493 .halt_reg = 0x3184,
1494 .clkr = {
1495 .enable_reg = 0x3184,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "camss_csi2_clk",
1499 .parent_names = (const char *[]){
1500 "csi2_clk_src",
1501 },
1502 .num_parents = 1,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1505 },
1506 },
1507};
1508
1509static struct clk_branch camss_csi2phy_clk = {
1510 .halt_reg = 0x3194,
1511 .clkr = {
1512 .enable_reg = 0x3194,
1513 .enable_mask = BIT(0),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "camss_csi2phy_clk",
1516 .parent_names = (const char *[]){
1517 "csi2_clk_src",
1518 },
1519 .num_parents = 1,
1520 .flags = CLK_SET_RATE_PARENT,
1521 .ops = &clk_branch2_ops,
1522 },
1523 },
1524};
1525
1526static struct clk_branch camss_csi2pix_clk = {
1527 .halt_reg = 0x31b4,
1528 .clkr = {
1529 .enable_reg = 0x31b4,
1530 .enable_mask = BIT(0),
1531 .hw.init = &(struct clk_init_data){
1532 .name = "camss_csi2pix_clk",
1533 .parent_names = (const char *[]){
1534 "csi2_clk_src",
1535 },
1536 .num_parents = 1,
1537 .flags = CLK_SET_RATE_PARENT,
1538 .ops = &clk_branch2_ops,
1539 },
1540 },
1541};
1542
1543static struct clk_branch camss_csi2rdi_clk = {
1544 .halt_reg = 0x31a4,
1545 .clkr = {
1546 .enable_reg = 0x31a4,
1547 .enable_mask = BIT(0),
1548 .hw.init = &(struct clk_init_data){
1549 .name = "camss_csi2rdi_clk",
1550 .parent_names = (const char *[]){
1551 "csi2_clk_src",
1552 },
1553 .num_parents = 1,
1554 .flags = CLK_SET_RATE_PARENT,
1555 .ops = &clk_branch2_ops,
1556 },
1557 },
1558};
1559
1560static struct clk_branch camss_csi3_ahb_clk = {
1561 .halt_reg = 0x31e8,
1562 .clkr = {
1563 .enable_reg = 0x31e8,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "camss_csi3_ahb_clk",
1567 .parent_names = (const char *[]){
1568 "mmss_ahb_clk_src",
1569 },
1570 .num_parents = 1,
1571 .ops = &clk_branch2_ops,
1572 },
1573 },
1574};
1575
1576static struct clk_branch camss_csi3_clk = {
1577 .halt_reg = 0x31e4,
1578 .clkr = {
1579 .enable_reg = 0x31e4,
1580 .enable_mask = BIT(0),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "camss_csi3_clk",
1583 .parent_names = (const char *[]){
1584 "csi3_clk_src",
1585 },
1586 .num_parents = 1,
1587 .flags = CLK_SET_RATE_PARENT,
1588 .ops = &clk_branch2_ops,
1589 },
1590 },
1591};
1592
1593static struct clk_branch camss_csi3phy_clk = {
1594 .halt_reg = 0x31f4,
1595 .clkr = {
1596 .enable_reg = 0x31f4,
1597 .enable_mask = BIT(0),
1598 .hw.init = &(struct clk_init_data){
1599 .name = "camss_csi3phy_clk",
1600 .parent_names = (const char *[]){
1601 "csi3_clk_src",
1602 },
1603 .num_parents = 1,
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1606 },
1607 },
1608};
1609
1610static struct clk_branch camss_csi3pix_clk = {
1611 .halt_reg = 0x3214,
1612 .clkr = {
1613 .enable_reg = 0x3214,
1614 .enable_mask = BIT(0),
1615 .hw.init = &(struct clk_init_data){
1616 .name = "camss_csi3pix_clk",
1617 .parent_names = (const char *[]){
1618 "csi3_clk_src",
1619 },
1620 .num_parents = 1,
1621 .flags = CLK_SET_RATE_PARENT,
1622 .ops = &clk_branch2_ops,
1623 },
1624 },
1625};
1626
1627static struct clk_branch camss_csi3rdi_clk = {
1628 .halt_reg = 0x3204,
1629 .clkr = {
1630 .enable_reg = 0x3204,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "camss_csi3rdi_clk",
1634 .parent_names = (const char *[]){
1635 "csi3_clk_src",
1636 },
1637 .num_parents = 1,
1638 .flags = CLK_SET_RATE_PARENT,
1639 .ops = &clk_branch2_ops,
1640 },
1641 },
1642};
1643
1644static struct clk_branch camss_csi_vfe0_clk = {
1645 .halt_reg = 0x3704,
1646 .clkr = {
1647 .enable_reg = 0x3704,
1648 .enable_mask = BIT(0),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "camss_csi_vfe0_clk",
1651 .parent_names = (const char *[]){
1652 "vfe0_clk_src",
1653 },
1654 .num_parents = 1,
1655 .flags = CLK_SET_RATE_PARENT,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch camss_csi_vfe1_clk = {
1662 .halt_reg = 0x3714,
1663 .clkr = {
1664 .enable_reg = 0x3714,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_csi_vfe1_clk",
1668 .parent_names = (const char *[]){
1669 "vfe1_clk_src",
1670 },
1671 .num_parents = 1,
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1674 },
1675 },
1676};
1677
1678static struct clk_branch camss_gp0_clk = {
1679 .halt_reg = 0x3444,
1680 .clkr = {
1681 .enable_reg = 0x3444,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "camss_gp0_clk",
1685 .parent_names = (const char *[]){
1686 "camss_gp0_clk_src",
1687 },
1688 .num_parents = 1,
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1691 },
1692 },
1693};
1694
1695static struct clk_branch camss_gp1_clk = {
1696 .halt_reg = 0x3474,
1697 .clkr = {
1698 .enable_reg = 0x3474,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "camss_gp1_clk",
1702 .parent_names = (const char *[]){
1703 "camss_gp1_clk_src",
1704 },
1705 .num_parents = 1,
1706 .flags = CLK_SET_RATE_PARENT,
1707 .ops = &clk_branch2_ops,
1708 },
1709 },
1710};
1711
1712static struct clk_branch camss_ispif_ahb_clk = {
1713 .halt_reg = 0x3224,
1714 .clkr = {
1715 .enable_reg = 0x3224,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "camss_ispif_ahb_clk",
1719 .parent_names = (const char *[]){
1720 "mmss_ahb_clk_src",
1721 },
1722 .num_parents = 1,
1723 .flags = CLK_SET_RATE_PARENT,
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727};
1728
1729static struct clk_branch camss_jpeg_jpeg0_clk = {
1730 .halt_reg = 0x35a8,
1731 .clkr = {
1732 .enable_reg = 0x35a8,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data){
1735 .name = "camss_jpeg_jpeg0_clk",
1736 .parent_names = (const char *[]){
1737 "jpeg0_clk_src",
1738 },
1739 .num_parents = 1,
1740 .flags = CLK_SET_RATE_PARENT,
1741 .ops = &clk_branch2_ops,
1742 },
1743 },
1744};
1745
1746static struct clk_branch camss_jpeg_jpeg1_clk = {
1747 .halt_reg = 0x35ac,
1748 .clkr = {
1749 .enable_reg = 0x35ac,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "camss_jpeg_jpeg1_clk",
1753 .parent_names = (const char *[]){
1754 "jpeg1_clk_src",
1755 },
1756 .num_parents = 1,
1757 .flags = CLK_SET_RATE_PARENT,
1758 .ops = &clk_branch2_ops,
1759 },
1760 },
1761};
1762
1763static struct clk_branch camss_jpeg_jpeg2_clk = {
1764 .halt_reg = 0x35b0,
1765 .clkr = {
1766 .enable_reg = 0x35b0,
1767 .enable_mask = BIT(0),
1768 .hw.init = &(struct clk_init_data){
1769 .name = "camss_jpeg_jpeg2_clk",
1770 .parent_names = (const char *[]){
1771 "jpeg2_clk_src",
1772 },
1773 .num_parents = 1,
1774 .flags = CLK_SET_RATE_PARENT,
1775 .ops = &clk_branch2_ops,
1776 },
1777 },
1778};
1779
1780static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1781 .halt_reg = 0x35b4,
1782 .clkr = {
1783 .enable_reg = 0x35b4,
1784 .enable_mask = BIT(0),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "camss_jpeg_jpeg_ahb_clk",
1787 .parent_names = (const char *[]){
1788 "mmss_ahb_clk_src",
1789 },
1790 .num_parents = 1,
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794};
1795
1796static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1797 .halt_reg = 0x35b8,
1798 .clkr = {
1799 .enable_reg = 0x35b8,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "camss_jpeg_jpeg_axi_clk",
1803 .parent_names = (const char *[]){
1804 "mmss_axi_clk_src",
1805 },
1806 .num_parents = 1,
1807 .ops = &clk_branch2_ops,
1808 },
1809 },
1810};
1811
1812static struct clk_branch camss_mclk0_clk = {
1813 .halt_reg = 0x3384,
1814 .clkr = {
1815 .enable_reg = 0x3384,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "camss_mclk0_clk",
1819 .parent_names = (const char *[]){
1820 "mclk0_clk_src",
1821 },
1822 .num_parents = 1,
1823 .flags = CLK_SET_RATE_PARENT,
1824 .ops = &clk_branch2_ops,
1825 },
1826 },
1827};
1828
1829static struct clk_branch camss_mclk1_clk = {
1830 .halt_reg = 0x33b4,
1831 .clkr = {
1832 .enable_reg = 0x33b4,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "camss_mclk1_clk",
1836 .parent_names = (const char *[]){
1837 "mclk1_clk_src",
1838 },
1839 .num_parents = 1,
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1842 },
1843 },
1844};
1845
1846static struct clk_branch camss_mclk2_clk = {
1847 .halt_reg = 0x33e4,
1848 .clkr = {
1849 .enable_reg = 0x33e4,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "camss_mclk2_clk",
1853 .parent_names = (const char *[]){
1854 "mclk2_clk_src",
1855 },
1856 .num_parents = 1,
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1859 },
1860 },
1861};
1862
1863static struct clk_branch camss_mclk3_clk = {
1864 .halt_reg = 0x3414,
1865 .clkr = {
1866 .enable_reg = 0x3414,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "camss_mclk3_clk",
1870 .parent_names = (const char *[]){
1871 "mclk3_clk_src",
1872 },
1873 .num_parents = 1,
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1876 },
1877 },
1878};
1879
1880static struct clk_branch camss_micro_ahb_clk = {
1881 .halt_reg = 0x3494,
1882 .clkr = {
1883 .enable_reg = 0x3494,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "camss_micro_ahb_clk",
1887 .parent_names = (const char *[]){
1888 "mmss_ahb_clk_src",
1889 },
1890 .num_parents = 1,
1891 .ops = &clk_branch2_ops,
1892 },
1893 },
1894};
1895
1896static struct clk_branch camss_phy0_csi0phytimer_clk = {
1897 .halt_reg = 0x3024,
1898 .clkr = {
1899 .enable_reg = 0x3024,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "camss_phy0_csi0phytimer_clk",
1903 .parent_names = (const char *[]){
1904 "csi0phytimer_clk_src",
1905 },
1906 .num_parents = 1,
1907 .flags = CLK_SET_RATE_PARENT,
1908 .ops = &clk_branch2_ops,
1909 },
1910 },
1911};
1912
1913static struct clk_branch camss_phy1_csi1phytimer_clk = {
1914 .halt_reg = 0x3054,
1915 .clkr = {
1916 .enable_reg = 0x3054,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "camss_phy1_csi1phytimer_clk",
1920 .parent_names = (const char *[]){
1921 "csi1phytimer_clk_src",
1922 },
1923 .num_parents = 1,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1926 },
1927 },
1928};
1929
1930static struct clk_branch camss_phy2_csi2phytimer_clk = {
1931 .halt_reg = 0x3084,
1932 .clkr = {
1933 .enable_reg = 0x3084,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "camss_phy2_csi2phytimer_clk",
1937 .parent_names = (const char *[]){
1938 "csi2phytimer_clk_src",
1939 },
1940 .num_parents = 1,
1941 .flags = CLK_SET_RATE_PARENT,
1942 .ops = &clk_branch2_ops,
1943 },
1944 },
1945};
1946
1947static struct clk_branch camss_top_ahb_clk = {
1948 .halt_reg = 0x3484,
1949 .clkr = {
1950 .enable_reg = 0x3484,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "camss_top_ahb_clk",
1954 .parent_names = (const char *[]){
1955 "mmss_ahb_clk_src",
1956 },
1957 .num_parents = 1,
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1960 },
1961 },
1962};
1963
1964static struct clk_branch camss_vfe_cpp_ahb_clk = {
1965 .halt_reg = 0x36b4,
1966 .clkr = {
1967 .enable_reg = 0x36b4,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "camss_vfe_cpp_ahb_clk",
1971 .parent_names = (const char *[]){
1972 "mmss_ahb_clk_src",
1973 },
1974 .num_parents = 1,
1975 .flags = CLK_SET_RATE_PARENT,
1976 .ops = &clk_branch2_ops,
1977 },
1978 },
1979};
1980
1981static struct clk_branch camss_vfe_cpp_clk = {
1982 .halt_reg = 0x36b0,
1983 .clkr = {
1984 .enable_reg = 0x36b0,
1985 .enable_mask = BIT(0),
1986 .hw.init = &(struct clk_init_data){
1987 .name = "camss_vfe_cpp_clk",
1988 .parent_names = (const char *[]){
1989 "cpp_clk_src",
1990 },
1991 .num_parents = 1,
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1994 },
1995 },
1996};
1997
1998static struct clk_branch camss_vfe_vfe0_clk = {
1999 .halt_reg = 0x36a8,
2000 .clkr = {
2001 .enable_reg = 0x36a8,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "camss_vfe_vfe0_clk",
2005 .parent_names = (const char *[]){
2006 "vfe0_clk_src",
2007 },
2008 .num_parents = 1,
2009 .flags = CLK_SET_RATE_PARENT,
2010 .ops = &clk_branch2_ops,
2011 },
2012 },
2013};
2014
2015static struct clk_branch camss_vfe_vfe1_clk = {
2016 .halt_reg = 0x36ac,
2017 .clkr = {
2018 .enable_reg = 0x36ac,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "camss_vfe_vfe1_clk",
2022 .parent_names = (const char *[]){
2023 "vfe1_clk_src",
2024 },
2025 .num_parents = 1,
2026 .flags = CLK_SET_RATE_PARENT,
2027 .ops = &clk_branch2_ops,
2028 },
2029 },
2030};
2031
2032static struct clk_branch camss_vfe_vfe_ahb_clk = {
2033 .halt_reg = 0x36b8,
2034 .clkr = {
2035 .enable_reg = 0x36b8,
2036 .enable_mask = BIT(0),
2037 .hw.init = &(struct clk_init_data){
2038 .name = "camss_vfe_vfe_ahb_clk",
2039 .parent_names = (const char *[]){
2040 "mmss_ahb_clk_src",
2041 },
2042 .num_parents = 1,
2043 .flags = CLK_SET_RATE_PARENT,
2044 .ops = &clk_branch2_ops,
2045 },
2046 },
2047};
2048
2049static struct clk_branch camss_vfe_vfe_axi_clk = {
2050 .halt_reg = 0x36bc,
2051 .clkr = {
2052 .enable_reg = 0x36bc,
2053 .enable_mask = BIT(0),
2054 .hw.init = &(struct clk_init_data){
2055 .name = "camss_vfe_vfe_axi_clk",
2056 .parent_names = (const char *[]){
2057 "mmss_axi_clk_src",
2058 },
2059 .num_parents = 1,
2060 .flags = CLK_SET_RATE_PARENT,
2061 .ops = &clk_branch2_ops,
2062 },
2063 },
2064};
2065
2066static struct clk_branch mdss_ahb_clk = {
2067 .halt_reg = 0x2308,
2068 .clkr = {
2069 .enable_reg = 0x2308,
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "mdss_ahb_clk",
2073 .parent_names = (const char *[]){
2074 "mmss_ahb_clk_src",
2075 },
2076 .num_parents = 1,
2077 .flags = CLK_SET_RATE_PARENT,
2078 .ops = &clk_branch2_ops,
2079 },
2080 },
2081};
2082
2083static struct clk_branch mdss_axi_clk = {
2084 .halt_reg = 0x2310,
2085 .clkr = {
2086 .enable_reg = 0x2310,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "mdss_axi_clk",
2090 .parent_names = (const char *[]){
2091 "mmss_axi_clk_src",
2092 },
2093 .num_parents = 1,
2094 .flags = CLK_SET_RATE_PARENT,
2095 .ops = &clk_branch2_ops,
2096 },
2097 },
2098};
2099
2100static struct clk_branch mdss_byte0_clk = {
2101 .halt_reg = 0x233c,
2102 .clkr = {
2103 .enable_reg = 0x233c,
2104 .enable_mask = BIT(0),
2105 .hw.init = &(struct clk_init_data){
2106 .name = "mdss_byte0_clk",
2107 .parent_names = (const char *[]){
2108 "byte0_clk_src",
2109 },
2110 .num_parents = 1,
2111 .flags = CLK_SET_RATE_PARENT,
2112 .ops = &clk_branch2_ops,
2113 },
2114 },
2115};
2116
2117static struct clk_branch mdss_byte1_clk = {
2118 .halt_reg = 0x2340,
2119 .clkr = {
2120 .enable_reg = 0x2340,
2121 .enable_mask = BIT(0),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "mdss_byte1_clk",
2124 .parent_names = (const char *[]){
2125 "byte1_clk_src",
2126 },
2127 .num_parents = 1,
2128 .flags = CLK_SET_RATE_PARENT,
2129 .ops = &clk_branch2_ops,
2130 },
2131 },
2132};
2133
2134static struct clk_branch mdss_edpaux_clk = {
2135 .halt_reg = 0x2334,
2136 .clkr = {
2137 .enable_reg = 0x2334,
2138 .enable_mask = BIT(0),
2139 .hw.init = &(struct clk_init_data){
2140 .name = "mdss_edpaux_clk",
2141 .parent_names = (const char *[]){
2142 "edpaux_clk_src",
2143 },
2144 .num_parents = 1,
2145 .flags = CLK_SET_RATE_PARENT,
2146 .ops = &clk_branch2_ops,
2147 },
2148 },
2149};
2150
2151static struct clk_branch mdss_edplink_clk = {
2152 .halt_reg = 0x2330,
2153 .clkr = {
2154 .enable_reg = 0x2330,
2155 .enable_mask = BIT(0),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "mdss_edplink_clk",
2158 .parent_names = (const char *[]){
2159 "edplink_clk_src",
2160 },
2161 .num_parents = 1,
2162 .flags = CLK_SET_RATE_PARENT,
2163 .ops = &clk_branch2_ops,
2164 },
2165 },
2166};
2167
2168static struct clk_branch mdss_edppixel_clk = {
2169 .halt_reg = 0x232c,
2170 .clkr = {
2171 .enable_reg = 0x232c,
2172 .enable_mask = BIT(0),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "mdss_edppixel_clk",
2175 .parent_names = (const char *[]){
2176 "edppixel_clk_src",
2177 },
2178 .num_parents = 1,
2179 .flags = CLK_SET_RATE_PARENT,
2180 .ops = &clk_branch2_ops,
2181 },
2182 },
2183};
2184
2185static struct clk_branch mdss_esc0_clk = {
2186 .halt_reg = 0x2344,
2187 .clkr = {
2188 .enable_reg = 0x2344,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "mdss_esc0_clk",
2192 .parent_names = (const char *[]){
2193 "esc0_clk_src",
2194 },
2195 .num_parents = 1,
2196 .flags = CLK_SET_RATE_PARENT,
2197 .ops = &clk_branch2_ops,
2198 },
2199 },
2200};
2201
2202static struct clk_branch mdss_esc1_clk = {
2203 .halt_reg = 0x2348,
2204 .clkr = {
2205 .enable_reg = 0x2348,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "mdss_esc1_clk",
2209 .parent_names = (const char *[]){
2210 "esc1_clk_src",
2211 },
2212 .num_parents = 1,
2213 .flags = CLK_SET_RATE_PARENT,
2214 .ops = &clk_branch2_ops,
2215 },
2216 },
2217};
2218
2219static struct clk_branch mdss_extpclk_clk = {
2220 .halt_reg = 0x2324,
2221 .clkr = {
2222 .enable_reg = 0x2324,
2223 .enable_mask = BIT(0),
2224 .hw.init = &(struct clk_init_data){
2225 .name = "mdss_extpclk_clk",
2226 .parent_names = (const char *[]){
2227 "extpclk_clk_src",
2228 },
2229 .num_parents = 1,
2230 .flags = CLK_SET_RATE_PARENT,
2231 .ops = &clk_branch2_ops,
2232 },
2233 },
2234};
2235
2236static struct clk_branch mdss_hdmi_ahb_clk = {
2237 .halt_reg = 0x230c,
2238 .clkr = {
2239 .enable_reg = 0x230c,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "mdss_hdmi_ahb_clk",
2243 .parent_names = (const char *[]){
2244 "mmss_ahb_clk_src",
2245 },
2246 .num_parents = 1,
2247 .flags = CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2249 },
2250 },
2251};
2252
2253static struct clk_branch mdss_hdmi_clk = {
2254 .halt_reg = 0x2338,
2255 .clkr = {
2256 .enable_reg = 0x2338,
2257 .enable_mask = BIT(0),
2258 .hw.init = &(struct clk_init_data){
2259 .name = "mdss_hdmi_clk",
2260 .parent_names = (const char *[]){
2261 "hdmi_clk_src",
2262 },
2263 .num_parents = 1,
2264 .flags = CLK_SET_RATE_PARENT,
2265 .ops = &clk_branch2_ops,
2266 },
2267 },
2268};
2269
2270static struct clk_branch mdss_mdp_clk = {
2271 .halt_reg = 0x231c,
2272 .clkr = {
2273 .enable_reg = 0x231c,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "mdss_mdp_clk",
2277 .parent_names = (const char *[]){
2278 "mdp_clk_src",
2279 },
2280 .num_parents = 1,
2281 .flags = CLK_SET_RATE_PARENT,
2282 .ops = &clk_branch2_ops,
2283 },
2284 },
2285};
2286
2287static struct clk_branch mdss_mdp_lut_clk = {
2288 .halt_reg = 0x2320,
2289 .clkr = {
2290 .enable_reg = 0x2320,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "mdss_mdp_lut_clk",
2294 .parent_names = (const char *[]){
2295 "mdp_clk_src",
2296 },
2297 .num_parents = 1,
2298 .flags = CLK_SET_RATE_PARENT,
2299 .ops = &clk_branch2_ops,
2300 },
2301 },
2302};
2303
2304static struct clk_branch mdss_pclk0_clk = {
2305 .halt_reg = 0x2314,
2306 .clkr = {
2307 .enable_reg = 0x2314,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "mdss_pclk0_clk",
2311 .parent_names = (const char *[]){
2312 "pclk0_clk_src",
2313 },
2314 .num_parents = 1,
2315 .flags = CLK_SET_RATE_PARENT,
2316 .ops = &clk_branch2_ops,
2317 },
2318 },
2319};
2320
2321static struct clk_branch mdss_pclk1_clk = {
2322 .halt_reg = 0x2318,
2323 .clkr = {
2324 .enable_reg = 0x2318,
2325 .enable_mask = BIT(0),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "mdss_pclk1_clk",
2328 .parent_names = (const char *[]){
2329 "pclk1_clk_src",
2330 },
2331 .num_parents = 1,
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2334 },
2335 },
2336};
2337
2338static struct clk_branch mdss_vsync_clk = {
2339 .halt_reg = 0x2328,
2340 .clkr = {
2341 .enable_reg = 0x2328,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "mdss_vsync_clk",
2345 .parent_names = (const char *[]){
2346 "vsync_clk_src",
2347 },
2348 .num_parents = 1,
2349 .flags = CLK_SET_RATE_PARENT,
2350 .ops = &clk_branch2_ops,
2351 },
2352 },
2353};
2354
2355static struct clk_branch mmss_rbcpr_ahb_clk = {
2356 .halt_reg = 0x4088,
2357 .clkr = {
2358 .enable_reg = 0x4088,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "mmss_rbcpr_ahb_clk",
2362 .parent_names = (const char *[]){
2363 "mmss_ahb_clk_src",
2364 },
2365 .num_parents = 1,
2366 .flags = CLK_SET_RATE_PARENT,
2367 .ops = &clk_branch2_ops,
2368 },
2369 },
2370};
2371
2372static struct clk_branch mmss_rbcpr_clk = {
2373 .halt_reg = 0x4084,
2374 .clkr = {
2375 .enable_reg = 0x4084,
2376 .enable_mask = BIT(0),
2377 .hw.init = &(struct clk_init_data){
2378 .name = "mmss_rbcpr_clk",
2379 .parent_names = (const char *[]){
2380 "rbcpr_clk_src",
2381 },
2382 .num_parents = 1,
2383 .flags = CLK_SET_RATE_PARENT,
2384 .ops = &clk_branch2_ops,
2385 },
2386 },
2387};
2388
2389static struct clk_branch mmss_spdm_ahb_clk = {
2390 .halt_reg = 0x0230,
2391 .clkr = {
2392 .enable_reg = 0x0230,
2393 .enable_mask = BIT(0),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "mmss_spdm_ahb_clk",
2396 .parent_names = (const char *[]){
2397 "mmss_spdm_ahb_div_clk",
2398 },
2399 .num_parents = 1,
2400 .flags = CLK_SET_RATE_PARENT,
2401 .ops = &clk_branch2_ops,
2402 },
2403 },
2404};
2405
2406static struct clk_branch mmss_spdm_axi_clk = {
2407 .halt_reg = 0x0210,
2408 .clkr = {
2409 .enable_reg = 0x0210,
2410 .enable_mask = BIT(0),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "mmss_spdm_axi_clk",
2413 .parent_names = (const char *[]){
2414 "mmss_spdm_axi_div_clk",
2415 },
2416 .num_parents = 1,
2417 .flags = CLK_SET_RATE_PARENT,
2418 .ops = &clk_branch2_ops,
2419 },
2420 },
2421};
2422
2423static struct clk_branch mmss_spdm_csi0_clk = {
2424 .halt_reg = 0x023c,
2425 .clkr = {
2426 .enable_reg = 0x023c,
2427 .enable_mask = BIT(0),
2428 .hw.init = &(struct clk_init_data){
2429 .name = "mmss_spdm_csi0_clk",
2430 .parent_names = (const char *[]){
2431 "mmss_spdm_csi0_div_clk",
2432 },
2433 .num_parents = 1,
2434 .flags = CLK_SET_RATE_PARENT,
2435 .ops = &clk_branch2_ops,
2436 },
2437 },
2438};
2439
2440static struct clk_branch mmss_spdm_gfx3d_clk = {
2441 .halt_reg = 0x022c,
2442 .clkr = {
2443 .enable_reg = 0x022c,
2444 .enable_mask = BIT(0),
2445 .hw.init = &(struct clk_init_data){
2446 .name = "mmss_spdm_gfx3d_clk",
2447 .parent_names = (const char *[]){
2448 "mmss_spdm_gfx3d_div_clk",
2449 },
2450 .num_parents = 1,
2451 .flags = CLK_SET_RATE_PARENT,
2452 .ops = &clk_branch2_ops,
2453 },
2454 },
2455};
2456
2457static struct clk_branch mmss_spdm_jpeg0_clk = {
2458 .halt_reg = 0x0204,
2459 .clkr = {
2460 .enable_reg = 0x0204,
2461 .enable_mask = BIT(0),
2462 .hw.init = &(struct clk_init_data){
2463 .name = "mmss_spdm_jpeg0_clk",
2464 .parent_names = (const char *[]){
2465 "mmss_spdm_jpeg0_div_clk",
2466 },
2467 .num_parents = 1,
2468 .flags = CLK_SET_RATE_PARENT,
2469 .ops = &clk_branch2_ops,
2470 },
2471 },
2472};
2473
2474static struct clk_branch mmss_spdm_jpeg1_clk = {
2475 .halt_reg = 0x0208,
2476 .clkr = {
2477 .enable_reg = 0x0208,
2478 .enable_mask = BIT(0),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "mmss_spdm_jpeg1_clk",
2481 .parent_names = (const char *[]){
2482 "mmss_spdm_jpeg1_div_clk",
2483 },
2484 .num_parents = 1,
2485 .flags = CLK_SET_RATE_PARENT,
2486 .ops = &clk_branch2_ops,
2487 },
2488 },
2489};
2490
2491static struct clk_branch mmss_spdm_jpeg2_clk = {
2492 .halt_reg = 0x0224,
2493 .clkr = {
2494 .enable_reg = 0x0224,
2495 .enable_mask = BIT(0),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "mmss_spdm_jpeg2_clk",
2498 .parent_names = (const char *[]){
2499 "mmss_spdm_jpeg2_div_clk",
2500 },
2501 .num_parents = 1,
2502 .flags = CLK_SET_RATE_PARENT,
2503 .ops = &clk_branch2_ops,
2504 },
2505 },
2506};
2507
2508static struct clk_branch mmss_spdm_mdp_clk = {
2509 .halt_reg = 0x020c,
2510 .clkr = {
2511 .enable_reg = 0x020c,
2512 .enable_mask = BIT(0),
2513 .hw.init = &(struct clk_init_data){
2514 .name = "mmss_spdm_mdp_clk",
2515 .parent_names = (const char *[]){
2516 "mmss_spdm_mdp_div_clk",
2517 },
2518 .num_parents = 1,
2519 .flags = CLK_SET_RATE_PARENT,
2520 .ops = &clk_branch2_ops,
2521 },
2522 },
2523};
2524
2525static struct clk_branch mmss_spdm_pclk0_clk = {
2526 .halt_reg = 0x0234,
2527 .clkr = {
2528 .enable_reg = 0x0234,
2529 .enable_mask = BIT(0),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "mmss_spdm_pclk0_clk",
2532 .parent_names = (const char *[]){
2533 "mmss_spdm_pclk0_div_clk",
2534 },
2535 .num_parents = 1,
2536 .flags = CLK_SET_RATE_PARENT,
2537 .ops = &clk_branch2_ops,
2538 },
2539 },
2540};
2541
2542static struct clk_branch mmss_spdm_pclk1_clk = {
2543 .halt_reg = 0x0228,
2544 .clkr = {
2545 .enable_reg = 0x0228,
2546 .enable_mask = BIT(0),
2547 .hw.init = &(struct clk_init_data){
2548 .name = "mmss_spdm_pclk1_clk",
2549 .parent_names = (const char *[]){
2550 "mmss_spdm_pclk1_div_clk",
2551 },
2552 .num_parents = 1,
2553 .flags = CLK_SET_RATE_PARENT,
2554 .ops = &clk_branch2_ops,
2555 },
2556 },
2557};
2558
2559static struct clk_branch mmss_spdm_vcodec0_clk = {
2560 .halt_reg = 0x0214,
2561 .clkr = {
2562 .enable_reg = 0x0214,
2563 .enable_mask = BIT(0),
2564 .hw.init = &(struct clk_init_data){
2565 .name = "mmss_spdm_vcodec0_clk",
2566 .parent_names = (const char *[]){
2567 "mmss_spdm_vcodec0_div_clk",
2568 },
2569 .num_parents = 1,
2570 .flags = CLK_SET_RATE_PARENT,
2571 .ops = &clk_branch2_ops,
2572 },
2573 },
2574};
2575
2576static struct clk_branch mmss_spdm_vfe0_clk = {
2577 .halt_reg = 0x0218,
2578 .clkr = {
2579 .enable_reg = 0x0218,
2580 .enable_mask = BIT(0),
2581 .hw.init = &(struct clk_init_data){
2582 .name = "mmss_spdm_vfe0_clk",
2583 .parent_names = (const char *[]){
2584 "mmss_spdm_vfe0_div_clk",
2585 },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch mmss_spdm_vfe1_clk = {
2594 .halt_reg = 0x021c,
2595 .clkr = {
2596 .enable_reg = 0x021c,
2597 .enable_mask = BIT(0),
2598 .hw.init = &(struct clk_init_data){
2599 .name = "mmss_spdm_vfe1_clk",
2600 .parent_names = (const char *[]){
2601 "mmss_spdm_vfe1_div_clk",
2602 },
2603 .num_parents = 1,
2604 .flags = CLK_SET_RATE_PARENT,
2605 .ops = &clk_branch2_ops,
2606 },
2607 },
2608};
2609
2610static struct clk_branch mmss_spdm_rm_axi_clk = {
2611 .halt_reg = 0x0304,
2612 .clkr = {
2613 .enable_reg = 0x0304,
2614 .enable_mask = BIT(0),
2615 .hw.init = &(struct clk_init_data){
2616 .name = "mmss_spdm_rm_axi_clk",
2617 .parent_names = (const char *[]){
2618 "mmss_axi_clk_src",
2619 },
2620 .num_parents = 1,
2621 .flags = CLK_SET_RATE_PARENT,
2622 .ops = &clk_branch2_ops,
2623 },
2624 },
2625};
2626
2627static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2628 .halt_reg = 0x0308,
2629 .clkr = {
2630 .enable_reg = 0x0308,
2631 .enable_mask = BIT(0),
2632 .hw.init = &(struct clk_init_data){
2633 .name = "mmss_spdm_rm_ocmemnoc_clk",
2634 .parent_names = (const char *[]){
2635 "ocmemnoc_clk_src",
2636 },
2637 .num_parents = 1,
2638 .flags = CLK_SET_RATE_PARENT,
2639 .ops = &clk_branch2_ops,
2640 },
2641 },
2642};
2643
2644
2645static struct clk_branch mmss_misc_ahb_clk = {
2646 .halt_reg = 0x502c,
2647 .clkr = {
2648 .enable_reg = 0x502c,
2649 .enable_mask = BIT(0),
2650 .hw.init = &(struct clk_init_data){
2651 .name = "mmss_misc_ahb_clk",
2652 .parent_names = (const char *[]){
2653 "mmss_ahb_clk_src",
2654 },
2655 .num_parents = 1,
2656 .flags = CLK_SET_RATE_PARENT,
2657 .ops = &clk_branch2_ops,
2658 },
2659 },
2660};
2661
2662static struct clk_branch mmss_mmssnoc_ahb_clk = {
2663 .halt_reg = 0x5024,
2664 .clkr = {
2665 .enable_reg = 0x5024,
2666 .enable_mask = BIT(0),
2667 .hw.init = &(struct clk_init_data){
2668 .name = "mmss_mmssnoc_ahb_clk",
2669 .parent_names = (const char *[]){
2670 "mmss_ahb_clk_src",
2671 },
2672 .num_parents = 1,
2673 .ops = &clk_branch2_ops,
2674 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2675 },
2676 },
2677};
2678
2679static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2680 .halt_reg = 0x5028,
2681 .clkr = {
2682 .enable_reg = 0x5028,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "mmss_mmssnoc_bto_ahb_clk",
2686 .parent_names = (const char *[]){
2687 "mmss_ahb_clk_src",
2688 },
2689 .num_parents = 1,
2690 .ops = &clk_branch2_ops,
2691 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2692 },
2693 },
2694};
2695
2696static struct clk_branch mmss_mmssnoc_axi_clk = {
2697 .halt_reg = 0x506c,
2698 .clkr = {
2699 .enable_reg = 0x506c,
2700 .enable_mask = BIT(0),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "mmss_mmssnoc_axi_clk",
2703 .parent_names = (const char *[]){
2704 "mmss_axi_clk_src",
2705 },
2706 .num_parents = 1,
2707 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2708 .ops = &clk_branch2_ops,
2709 },
2710 },
2711};
2712
2713static struct clk_branch mmss_s0_axi_clk = {
2714 .halt_reg = 0x5064,
2715 .clkr = {
2716 .enable_reg = 0x5064,
2717 .enable_mask = BIT(0),
2718 .hw.init = &(struct clk_init_data){
2719 .name = "mmss_s0_axi_clk",
2720 .parent_names = (const char *[]){
2721 "mmss_axi_clk_src",
2722 },
2723 .num_parents = 1,
2724 .ops = &clk_branch2_ops,
2725 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2726 },
2727 },
2728};
2729
2730static struct clk_branch ocmemcx_ahb_clk = {
2731 .halt_reg = 0x405c,
2732 .clkr = {
2733 .enable_reg = 0x405c,
2734 .enable_mask = BIT(0),
2735 .hw.init = &(struct clk_init_data){
2736 .name = "ocmemcx_ahb_clk",
2737 .parent_names = (const char *[]){
2738 "mmss_ahb_clk_src",
2739 },
2740 .num_parents = 1,
2741 .flags = CLK_SET_RATE_PARENT,
2742 .ops = &clk_branch2_ops,
2743 },
2744 },
2745};
2746
2747static struct clk_branch ocmemcx_ocmemnoc_clk = {
2748 .halt_reg = 0x4058,
2749 .clkr = {
2750 .enable_reg = 0x4058,
2751 .enable_mask = BIT(0),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "ocmemcx_ocmemnoc_clk",
2754 .parent_names = (const char *[]){
2755 "ocmemnoc_clk_src",
2756 },
2757 .num_parents = 1,
2758 .flags = CLK_SET_RATE_PARENT,
2759 .ops = &clk_branch2_ops,
2760 },
2761 },
2762};
2763
2764static struct clk_branch oxili_ocmemgx_clk = {
2765 .halt_reg = 0x402c,
2766 .clkr = {
2767 .enable_reg = 0x402c,
2768 .enable_mask = BIT(0),
2769 .hw.init = &(struct clk_init_data){
2770 .name = "oxili_ocmemgx_clk",
2771 .parent_names = (const char *[]){
2772 "gfx3d_clk_src",
2773 },
2774 .num_parents = 1,
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2777 },
2778 },
2779};
2780
2781static struct clk_branch oxili_gfx3d_clk = {
2782 .halt_reg = 0x4028,
2783 .clkr = {
2784 .enable_reg = 0x4028,
2785 .enable_mask = BIT(0),
2786 .hw.init = &(struct clk_init_data){
2787 .name = "oxili_gfx3d_clk",
2788 .parent_names = (const char *[]){
2789 "gfx3d_clk_src",
2790 },
2791 .num_parents = 1,
2792 .flags = CLK_SET_RATE_PARENT,
2793 .ops = &clk_branch2_ops,
2794 },
2795 },
2796};
2797
2798static struct clk_branch oxili_rbbmtimer_clk = {
2799 .halt_reg = 0x40b0,
2800 .clkr = {
2801 .enable_reg = 0x40b0,
2802 .enable_mask = BIT(0),
2803 .hw.init = &(struct clk_init_data){
2804 .name = "oxili_rbbmtimer_clk",
2805 .parent_names = (const char *[]){
2806 "rbbmtimer_clk_src",
2807 },
2808 .num_parents = 1,
2809 .flags = CLK_SET_RATE_PARENT,
2810 .ops = &clk_branch2_ops,
2811 },
2812 },
2813};
2814
2815static struct clk_branch oxilicx_ahb_clk = {
2816 .halt_reg = 0x403c,
2817 .clkr = {
2818 .enable_reg = 0x403c,
2819 .enable_mask = BIT(0),
2820 .hw.init = &(struct clk_init_data){
2821 .name = "oxilicx_ahb_clk",
2822 .parent_names = (const char *[]){
2823 "mmss_ahb_clk_src",
2824 },
2825 .num_parents = 1,
2826 .flags = CLK_SET_RATE_PARENT,
2827 .ops = &clk_branch2_ops,
2828 },
2829 },
2830};
2831
2832static struct clk_branch venus0_ahb_clk = {
2833 .halt_reg = 0x1030,
2834 .clkr = {
2835 .enable_reg = 0x1030,
2836 .enable_mask = BIT(0),
2837 .hw.init = &(struct clk_init_data){
2838 .name = "venus0_ahb_clk",
2839 .parent_names = (const char *[]){
2840 "mmss_ahb_clk_src",
2841 },
2842 .num_parents = 1,
2843 .flags = CLK_SET_RATE_PARENT,
2844 .ops = &clk_branch2_ops,
2845 },
2846 },
2847};
2848
2849static struct clk_branch venus0_axi_clk = {
2850 .halt_reg = 0x1034,
2851 .clkr = {
2852 .enable_reg = 0x1034,
2853 .enable_mask = BIT(0),
2854 .hw.init = &(struct clk_init_data){
2855 .name = "venus0_axi_clk",
2856 .parent_names = (const char *[]){
2857 "mmss_axi_clk_src",
2858 },
2859 .num_parents = 1,
2860 .flags = CLK_SET_RATE_PARENT,
2861 .ops = &clk_branch2_ops,
2862 },
2863 },
2864};
2865
2866static struct clk_branch venus0_core0_vcodec_clk = {
2867 .halt_reg = 0x1048,
2868 .clkr = {
2869 .enable_reg = 0x1048,
2870 .enable_mask = BIT(0),
2871 .hw.init = &(struct clk_init_data){
2872 .name = "venus0_core0_vcodec_clk",
2873 .parent_names = (const char *[]){
2874 "vcodec0_clk_src",
2875 },
2876 .num_parents = 1,
2877 .flags = CLK_SET_RATE_PARENT,
2878 .ops = &clk_branch2_ops,
2879 },
2880 },
2881};
2882
2883static struct clk_branch venus0_core1_vcodec_clk = {
2884 .halt_reg = 0x104c,
2885 .clkr = {
2886 .enable_reg = 0x104c,
2887 .enable_mask = BIT(0),
2888 .hw.init = &(struct clk_init_data){
2889 .name = "venus0_core1_vcodec_clk",
2890 .parent_names = (const char *[]){
2891 "vcodec0_clk_src",
2892 },
2893 .num_parents = 1,
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2896 },
2897 },
2898};
2899
2900static struct clk_branch venus0_ocmemnoc_clk = {
2901 .halt_reg = 0x1038,
2902 .clkr = {
2903 .enable_reg = 0x1038,
2904 .enable_mask = BIT(0),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "venus0_ocmemnoc_clk",
2907 .parent_names = (const char *[]){
2908 "ocmemnoc_clk_src",
2909 },
2910 .num_parents = 1,
2911 .flags = CLK_SET_RATE_PARENT,
2912 .ops = &clk_branch2_ops,
2913 },
2914 },
2915};
2916
2917static struct clk_branch venus0_vcodec0_clk = {
2918 .halt_reg = 0x1028,
2919 .clkr = {
2920 .enable_reg = 0x1028,
2921 .enable_mask = BIT(0),
2922 .hw.init = &(struct clk_init_data){
2923 .name = "venus0_vcodec0_clk",
2924 .parent_names = (const char *[]){
2925 "vcodec0_clk_src",
2926 },
2927 .num_parents = 1,
2928 .flags = CLK_SET_RATE_PARENT,
2929 .ops = &clk_branch2_ops,
2930 },
2931 },
2932};
2933
2934static struct clk_branch vpu_ahb_clk = {
2935 .halt_reg = 0x1430,
2936 .clkr = {
2937 .enable_reg = 0x1430,
2938 .enable_mask = BIT(0),
2939 .hw.init = &(struct clk_init_data){
2940 .name = "vpu_ahb_clk",
2941 .parent_names = (const char *[]){
2942 "mmss_ahb_clk_src",
2943 },
2944 .num_parents = 1,
2945 .flags = CLK_SET_RATE_PARENT,
2946 .ops = &clk_branch2_ops,
2947 },
2948 },
2949};
2950
2951static struct clk_branch vpu_axi_clk = {
2952 .halt_reg = 0x143c,
2953 .clkr = {
2954 .enable_reg = 0x143c,
2955 .enable_mask = BIT(0),
2956 .hw.init = &(struct clk_init_data){
2957 .name = "vpu_axi_clk",
2958 .parent_names = (const char *[]){
2959 "mmss_axi_clk_src",
2960 },
2961 .num_parents = 1,
2962 .flags = CLK_SET_RATE_PARENT,
2963 .ops = &clk_branch2_ops,
2964 },
2965 },
2966};
2967
2968static struct clk_branch vpu_bus_clk = {
2969 .halt_reg = 0x1440,
2970 .clkr = {
2971 .enable_reg = 0x1440,
2972 .enable_mask = BIT(0),
2973 .hw.init = &(struct clk_init_data){
2974 .name = "vpu_bus_clk",
2975 .parent_names = (const char *[]){
2976 "vpu_bus_clk_src",
2977 },
2978 .num_parents = 1,
2979 .flags = CLK_SET_RATE_PARENT,
2980 .ops = &clk_branch2_ops,
2981 },
2982 },
2983};
2984
2985static struct clk_branch vpu_cxo_clk = {
2986 .halt_reg = 0x1434,
2987 .clkr = {
2988 .enable_reg = 0x1434,
2989 .enable_mask = BIT(0),
2990 .hw.init = &(struct clk_init_data){
2991 .name = "vpu_cxo_clk",
2992 .parent_names = (const char *[]){ "xo" },
2993 .num_parents = 1,
2994 .flags = CLK_SET_RATE_PARENT,
2995 .ops = &clk_branch2_ops,
2996 },
2997 },
2998};
2999
3000static struct clk_branch vpu_maple_clk = {
3001 .halt_reg = 0x142c,
3002 .clkr = {
3003 .enable_reg = 0x142c,
3004 .enable_mask = BIT(0),
3005 .hw.init = &(struct clk_init_data){
3006 .name = "vpu_maple_clk",
3007 .parent_names = (const char *[]){
3008 "maple_clk_src",
3009 },
3010 .num_parents = 1,
3011 .flags = CLK_SET_RATE_PARENT,
3012 .ops = &clk_branch2_ops,
3013 },
3014 },
3015};
3016
3017static struct clk_branch vpu_sleep_clk = {
3018 .halt_reg = 0x1438,
3019 .clkr = {
3020 .enable_reg = 0x1438,
3021 .enable_mask = BIT(0),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "vpu_sleep_clk",
3024 .parent_names = (const char *[]){
3025 "sleep_clk_src",
3026 },
3027 .num_parents = 1,
3028 .flags = CLK_SET_RATE_PARENT,
3029 .ops = &clk_branch2_ops,
3030 },
3031 },
3032};
3033
3034static struct clk_branch vpu_vdp_clk = {
3035 .halt_reg = 0x1428,
3036 .clkr = {
3037 .enable_reg = 0x1428,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "vpu_vdp_clk",
3041 .parent_names = (const char *[]){
3042 "vdp_clk_src",
3043 },
3044 .num_parents = 1,
3045 .flags = CLK_SET_RATE_PARENT,
3046 .ops = &clk_branch2_ops,
3047 },
3048 },
3049};
3050
3051static const struct pll_config mmpll1_config = {
3052 .l = 60,
3053 .m = 25,
3054 .n = 32,
3055 .vco_val = 0x0,
3056 .vco_mask = 0x3 << 20,
3057 .pre_div_val = 0x0,
3058 .pre_div_mask = 0x7 << 12,
3059 .post_div_val = 0x0,
3060 .post_div_mask = 0x3 << 8,
3061 .mn_ena_mask = BIT(24),
3062 .main_output_mask = BIT(0),
3063};
3064
3065static const struct pll_config mmpll3_config = {
3066 .l = 48,
3067 .m = 7,
3068 .n = 16,
3069 .vco_val = 0x0,
3070 .vco_mask = 0x3 << 20,
3071 .pre_div_val = 0x0,
3072 .pre_div_mask = 0x7 << 12,
3073 .post_div_val = 0x0,
3074 .post_div_mask = 0x3 << 8,
3075 .mn_ena_mask = BIT(24),
3076 .main_output_mask = BIT(0),
3077 .aux_output_mask = BIT(1),
3078};
3079
3080static struct clk_regmap *mmcc_apq8084_clocks[] = {
3081 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3082 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3083 [MMPLL0] = &mmpll0.clkr,
3084 [MMPLL0_VOTE] = &mmpll0_vote,
3085 [MMPLL1] = &mmpll1.clkr,
3086 [MMPLL1_VOTE] = &mmpll1_vote,
3087 [MMPLL2] = &mmpll2.clkr,
3088 [MMPLL3] = &mmpll3.clkr,
3089 [MMPLL4] = &mmpll4.clkr,
3090 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3091 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3092 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3093 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3094 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3095 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3096 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3097 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3098 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3099 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3100 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3101 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3102 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3103 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3104 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3105 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3106 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3107 [VP_CLK_SRC] = &vp_clk_src.clkr,
3108 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3109 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3110 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3111 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3112 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3113 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3114 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3115 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3116 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3117 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3118 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3119 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3120 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3121 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3122 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3123 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3124 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3125 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3126 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
Georgi Djakov9a6cb702014-10-10 16:57:24 +03003127 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003128 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3129 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3130 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3131 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3132 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3133 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3134 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3135 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3136 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3137 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3138 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3139 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3140 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3141 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3142 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3143 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3144 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3145 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3146 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3147 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3148 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3149 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3150 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3151 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3152 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3153 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3154 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3155 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3156 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3157 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3158 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3159 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3160 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3161 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3162 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3163 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3164 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3165 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3166 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3167 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3168 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3169 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3170 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3171 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3172 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3173 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3174 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3175 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3176 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3177 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3178 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3179 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3180 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3181 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3182 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3183 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3184 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3185 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3186 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3187 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3188 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3189 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3190 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3191 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3192 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3193 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3194 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3195 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3196 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3197 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3198 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3199 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3200 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3201 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3202 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3203 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3204 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3205 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3206 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3207 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3208 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3209 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3210 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3211 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3212 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3213 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3214 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3215 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3216 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3217 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3218 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3219 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3220 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3221 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3222 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3223 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3224 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3225 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3226 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3227 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3228 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3229 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3230 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3231 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3232 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3233 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3234 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3235 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3236 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3237 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3238 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3239 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3240 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3241 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3242 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3243 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3244 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3245 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3246};
3247
3248static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3249 [MMSS_SPDM_RESET] = { 0x0200 },
3250 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3251 [VENUS0_RESET] = { 0x1020 },
3252 [VPU_RESET] = { 0x1400 },
3253 [MDSS_RESET] = { 0x2300 },
3254 [AVSYNC_RESET] = { 0x2400 },
3255 [CAMSS_PHY0_RESET] = { 0x3020 },
3256 [CAMSS_PHY1_RESET] = { 0x3050 },
3257 [CAMSS_PHY2_RESET] = { 0x3080 },
3258 [CAMSS_CSI0_RESET] = { 0x30b0 },
3259 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3260 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3261 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3262 [CAMSS_CSI1_RESET] = { 0x3120 },
3263 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3264 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3265 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3266 [CAMSS_CSI2_RESET] = { 0x3180 },
3267 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3268 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3269 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3270 [CAMSS_CSI3_RESET] = { 0x31e0 },
3271 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3272 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3273 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3274 [CAMSS_ISPIF_RESET] = { 0x3220 },
3275 [CAMSS_CCI_RESET] = { 0x3340 },
3276 [CAMSS_MCLK0_RESET] = { 0x3380 },
3277 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3278 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3279 [CAMSS_MCLK3_RESET] = { 0x3410 },
3280 [CAMSS_GP0_RESET] = { 0x3440 },
3281 [CAMSS_GP1_RESET] = { 0x3470 },
3282 [CAMSS_TOP_RESET] = { 0x3480 },
3283 [CAMSS_AHB_RESET] = { 0x3488 },
3284 [CAMSS_MICRO_RESET] = { 0x3490 },
3285 [CAMSS_JPEG_RESET] = { 0x35a0 },
3286 [CAMSS_VFE_RESET] = { 0x36a0 },
3287 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3288 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3289 [OXILI_RESET] = { 0x4020 },
3290 [OXILICX_RESET] = { 0x4030 },
3291 [OCMEMCX_RESET] = { 0x4050 },
3292 [MMSS_RBCRP_RESET] = { 0x4080 },
3293 [MMSSNOCAHB_RESET] = { 0x5020 },
3294 [MMSSNOCAXI_RESET] = { 0x5060 },
3295};
3296
3297static const struct regmap_config mmcc_apq8084_regmap_config = {
3298 .reg_bits = 32,
3299 .reg_stride = 4,
3300 .val_bits = 32,
3301 .max_register = 0x5104,
3302 .fast_io = true,
3303};
3304
3305static const struct qcom_cc_desc mmcc_apq8084_desc = {
3306 .config = &mmcc_apq8084_regmap_config,
3307 .clks = mmcc_apq8084_clocks,
3308 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3309 .resets = mmcc_apq8084_resets,
3310 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3311};
3312
3313static const struct of_device_id mmcc_apq8084_match_table[] = {
3314 { .compatible = "qcom,mmcc-apq8084" },
3315 { }
3316};
3317MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3318
3319static int mmcc_apq8084_probe(struct platform_device *pdev)
3320{
3321 int ret;
3322 struct regmap *regmap;
3323
3324 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3325 if (ret)
3326 return ret;
3327
3328 regmap = dev_get_regmap(&pdev->dev, NULL);
3329 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3330 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3331
3332 return 0;
3333}
3334
3335static int mmcc_apq8084_remove(struct platform_device *pdev)
3336{
3337 qcom_cc_remove(pdev);
3338 return 0;
3339}
3340
3341static struct platform_driver mmcc_apq8084_driver = {
3342 .probe = mmcc_apq8084_probe,
3343 .remove = mmcc_apq8084_remove,
3344 .driver = {
3345 .name = "mmcc-apq8084",
Georgi Djakov2b46cd22014-06-12 19:41:42 +03003346 .of_match_table = mmcc_apq8084_match_table,
3347 },
3348};
3349module_platform_driver(mmcc_apq8084_driver);
3350
3351MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3352MODULE_LICENSE("GPL v2");
3353MODULE_ALIAS("platform:mmcc-apq8084");