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Eric Miao4f788bb2008-08-06 15:59:06 +08001/*
Eric Miao4f788bb2008-08-06 15:59:06 +08002 * Copyright (C) 2008 Marvell International Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/sched.h>
13#include <linux/init.h>
14#include <linux/cpufreq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Rob Herring23019a72012-03-20 14:33:19 -050016#include <linux/io.h>
Eric Miao4f788bb2008-08-06 15:59:06 +080017
Viresh Kumaradde9042013-04-04 12:54:12 +000018#include <mach/generic.h>
Eric Miao4f788bb2008-08-06 15:59:06 +080019#include <mach/pxa3xx-regs.h>
20
Eric Miao4f788bb2008-08-06 15:59:06 +080021#define HSS_104M (0)
22#define HSS_156M (1)
23#define HSS_208M (2)
24#define HSS_312M (3)
25
26#define SMCFS_78M (0)
27#define SMCFS_104M (2)
28#define SMCFS_208M (5)
29
30#define SFLFS_104M (0)
31#define SFLFS_156M (1)
32#define SFLFS_208M (2)
33#define SFLFS_312M (3)
34
35#define XSPCLK_156M (0)
36#define XSPCLK_NONE (3)
37
38#define DMCFS_26M (0)
39#define DMCFS_260M (3)
40
41struct pxa3xx_freq_info {
42 unsigned int cpufreq_mhz;
43 unsigned int core_xl : 5;
44 unsigned int core_xn : 3;
45 unsigned int hss : 2;
46 unsigned int dmcfs : 2;
47 unsigned int smcfs : 3;
48 unsigned int sflfs : 2;
49 unsigned int df_clkdiv : 3;
50
51 int vcc_core; /* in mV */
52 int vcc_sram; /* in mV */
53};
54
55#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
56{ \
57 .cpufreq_mhz = cpufreq, \
58 .core_xl = _xl, \
59 .core_xn = _xn, \
60 .hss = HSS_##_hss##M, \
61 .dmcfs = DMCFS_##_dmc##M, \
62 .smcfs = SMCFS_##_smc##M, \
63 .sflfs = SFLFS_##_sfl##M, \
64 .df_clkdiv = _dfi, \
65 .vcc_core = vcore, \
66 .vcc_sram = vsram, \
67}
68
69static struct pxa3xx_freq_info pxa300_freqs[] = {
70 /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
71 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
72 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
73 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
74 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
75};
76
77static struct pxa3xx_freq_info pxa320_freqs[] = {
78 /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
79 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
80 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
81 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
82 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
83 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
84};
85
86static unsigned int pxa3xx_freqs_num;
87static struct pxa3xx_freq_info *pxa3xx_freqs;
88static struct cpufreq_frequency_table *pxa3xx_freqs_table;
89
90static int setup_freqs_table(struct cpufreq_policy *policy,
91 struct pxa3xx_freq_info *freqs, int num)
92{
93 struct cpufreq_frequency_table *table;
94 int i;
95
96 table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
97 if (table == NULL)
98 return -ENOMEM;
99
100 for (i = 0; i < num; i++) {
101 table[i].index = i;
102 table[i].frequency = freqs[i].cpufreq_mhz * 1000;
103 }
Daniel Mack68a31de2009-11-20 17:50:34 +0100104 table[num].index = i;
Eric Miao4f788bb2008-08-06 15:59:06 +0800105 table[num].frequency = CPUFREQ_TABLE_END;
106
107 pxa3xx_freqs = freqs;
108 pxa3xx_freqs_num = num;
109 pxa3xx_freqs_table = table;
110
111 return cpufreq_frequency_table_cpuinfo(policy, table);
112}
113
114static void __update_core_freq(struct pxa3xx_freq_info *info)
115{
116 uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
117 uint32_t accr = ACCR;
118 uint32_t xclkcfg;
119
120 accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
121 accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
122
123 /* No clock until core PLL is re-locked */
124 accr |= ACCR_XSPCLK(XSPCLK_NONE);
125
126 xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
127
128 ACCR = accr;
129 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
130
131 while ((ACSR & mask) != (accr & mask))
132 cpu_relax();
133}
134
135static void __update_bus_freq(struct pxa3xx_freq_info *info)
136{
137 uint32_t mask;
138 uint32_t accr = ACCR;
139
140 mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
141 ACCR_DMCFS_MASK;
142
143 accr &= ~mask;
144 accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
145 ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
146
147 ACCR = accr;
148
149 while ((ACSR & mask) != (accr & mask))
150 cpu_relax();
151}
152
153static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
154{
155 return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
156}
157
158static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
159{
Haojian Zhuangecf89b82010-09-19 20:09:10 -0400160 return pxa3xx_get_clk_frequency_khz(0);
Eric Miao4f788bb2008-08-06 15:59:06 +0800161}
162
163static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
164 unsigned int target_freq,
165 unsigned int relation)
166{
167 struct pxa3xx_freq_info *next;
168 struct cpufreq_freqs freqs;
169 unsigned long flags;
170 int idx;
171
172 if (policy->cpu != 0)
173 return -EINVAL;
174
175 /* Lookup the next frequency */
176 if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
177 target_freq, relation, &idx))
178 return -EINVAL;
179
180 next = &pxa3xx_freqs[idx];
181
182 freqs.old = policy->cur;
183 freqs.new = next->cpufreq_mhz * 1000;
Eric Miao4f788bb2008-08-06 15:59:06 +0800184
185 pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
186 freqs.old / 1000, freqs.new / 1000,
187 (freqs.old == freqs.new) ? " (skipped)" : "");
188
189 if (freqs.old == target_freq)
190 return 0;
191
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530192 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
Eric Miao4f788bb2008-08-06 15:59:06 +0800193
194 local_irq_save(flags);
195 __update_core_freq(next);
196 __update_bus_freq(next);
197 local_irq_restore(flags);
198
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530199 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
Eric Miao4f788bb2008-08-06 15:59:06 +0800200
201 return 0;
202}
203
Eric Miao50e77fc2010-08-18 11:51:13 +0800204static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
Eric Miao4f788bb2008-08-06 15:59:06 +0800205{
206 int ret = -EINVAL;
207
208 /* set default policy and cpuinfo */
Eric Miao4f788bb2008-08-06 15:59:06 +0800209 policy->cpuinfo.min_freq = 104000;
210 policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
211 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
Haojian Zhuangecf89b82010-09-19 20:09:10 -0400212 policy->max = pxa3xx_get_clk_frequency_khz(0);
213 policy->cur = policy->min = policy->max;
Eric Miao4f788bb2008-08-06 15:59:06 +0800214
215 if (cpu_is_pxa300() || cpu_is_pxa310())
216 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
217
218 if (cpu_is_pxa320())
219 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
220
221 if (ret) {
222 pr_err("failed to setup frequency table\n");
223 return ret;
224 }
225
226 pr_info("CPUFREQ support for PXA3xx initialized\n");
227 return 0;
228}
229
230static struct cpufreq_driver pxa3xx_cpufreq_driver = {
231 .verify = pxa3xx_cpufreq_verify,
232 .target = pxa3xx_cpufreq_set,
233 .init = pxa3xx_cpufreq_init,
234 .get = pxa3xx_cpufreq_get,
235 .name = "pxa3xx-cpufreq",
236};
237
238static int __init cpufreq_init(void)
239{
240 if (cpu_is_pxa3xx())
241 return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
242
243 return 0;
244}
245module_init(cpufreq_init);
246
247static void __exit cpufreq_exit(void)
248{
249 cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
250}
251module_exit(cpufreq_exit);
252
253MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
254MODULE_LICENSE("GPL");