Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 1 | /* |
| 2 | * TI OMAP4 ISS V4L2 Driver - ISP RESIZER module |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/uaccess.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/mm.h> |
| 20 | #include <linux/sched.h> |
| 21 | |
| 22 | #include "iss.h" |
| 23 | #include "iss_regs.h" |
| 24 | #include "iss_resizer.h" |
| 25 | |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 26 | static const unsigned int resizer_fmts[] = { |
| 27 | V4L2_MBUS_FMT_UYVY8_1X16, |
| 28 | V4L2_MBUS_FMT_YUYV8_1X16, |
| 29 | }; |
| 30 | |
| 31 | /* |
| 32 | * resizer_print_status - Print current RESIZER Module register values. |
| 33 | * @resizer: Pointer to ISS ISP RESIZER device. |
| 34 | * |
| 35 | * Also prints other debug information stored in the RESIZER module. |
| 36 | */ |
| 37 | #define RSZ_PRINT_REGISTER(iss, name)\ |
| 38 | dev_dbg(iss->dev, "###RSZ " #name "=0x%08x\n", \ |
| 39 | readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_##name)) |
| 40 | |
| 41 | #define RZA_PRINT_REGISTER(iss, name)\ |
| 42 | dev_dbg(iss->dev, "###RZA " #name "=0x%08x\n", \ |
| 43 | readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_##name)) |
| 44 | |
| 45 | static void resizer_print_status(struct iss_resizer_device *resizer) |
| 46 | { |
| 47 | struct iss_device *iss = to_iss_device(resizer); |
| 48 | |
| 49 | dev_dbg(iss->dev, "-------------RESIZER Register dump-------------\n"); |
| 50 | |
| 51 | RSZ_PRINT_REGISTER(iss, SYSCONFIG); |
| 52 | RSZ_PRINT_REGISTER(iss, IN_FIFO_CTRL); |
| 53 | RSZ_PRINT_REGISTER(iss, FRACDIV); |
| 54 | RSZ_PRINT_REGISTER(iss, SRC_EN); |
| 55 | RSZ_PRINT_REGISTER(iss, SRC_MODE); |
| 56 | RSZ_PRINT_REGISTER(iss, SRC_FMT0); |
| 57 | RSZ_PRINT_REGISTER(iss, SRC_FMT1); |
| 58 | RSZ_PRINT_REGISTER(iss, SRC_VPS); |
| 59 | RSZ_PRINT_REGISTER(iss, SRC_VSZ); |
| 60 | RSZ_PRINT_REGISTER(iss, SRC_HPS); |
| 61 | RSZ_PRINT_REGISTER(iss, SRC_HSZ); |
| 62 | RSZ_PRINT_REGISTER(iss, DMA_RZA); |
| 63 | RSZ_PRINT_REGISTER(iss, DMA_RZB); |
| 64 | RSZ_PRINT_REGISTER(iss, DMA_STA); |
| 65 | RSZ_PRINT_REGISTER(iss, GCK_MMR); |
| 66 | RSZ_PRINT_REGISTER(iss, GCK_SDR); |
| 67 | RSZ_PRINT_REGISTER(iss, IRQ_RZA); |
| 68 | RSZ_PRINT_REGISTER(iss, IRQ_RZB); |
| 69 | RSZ_PRINT_REGISTER(iss, YUV_Y_MIN); |
| 70 | RSZ_PRINT_REGISTER(iss, YUV_Y_MAX); |
| 71 | RSZ_PRINT_REGISTER(iss, YUV_C_MIN); |
| 72 | RSZ_PRINT_REGISTER(iss, YUV_C_MAX); |
| 73 | RSZ_PRINT_REGISTER(iss, SEQ); |
| 74 | |
| 75 | RZA_PRINT_REGISTER(iss, EN); |
| 76 | RZA_PRINT_REGISTER(iss, MODE); |
| 77 | RZA_PRINT_REGISTER(iss, 420); |
| 78 | RZA_PRINT_REGISTER(iss, I_VPS); |
| 79 | RZA_PRINT_REGISTER(iss, I_HPS); |
| 80 | RZA_PRINT_REGISTER(iss, O_VSZ); |
| 81 | RZA_PRINT_REGISTER(iss, O_HSZ); |
| 82 | RZA_PRINT_REGISTER(iss, V_PHS_Y); |
| 83 | RZA_PRINT_REGISTER(iss, V_PHS_C); |
| 84 | RZA_PRINT_REGISTER(iss, V_DIF); |
| 85 | RZA_PRINT_REGISTER(iss, V_TYP); |
| 86 | RZA_PRINT_REGISTER(iss, V_LPF); |
| 87 | RZA_PRINT_REGISTER(iss, H_PHS); |
| 88 | RZA_PRINT_REGISTER(iss, H_DIF); |
| 89 | RZA_PRINT_REGISTER(iss, H_TYP); |
| 90 | RZA_PRINT_REGISTER(iss, H_LPF); |
| 91 | RZA_PRINT_REGISTER(iss, DWN_EN); |
| 92 | RZA_PRINT_REGISTER(iss, SDR_Y_BAD_H); |
| 93 | RZA_PRINT_REGISTER(iss, SDR_Y_BAD_L); |
| 94 | RZA_PRINT_REGISTER(iss, SDR_Y_SAD_H); |
| 95 | RZA_PRINT_REGISTER(iss, SDR_Y_SAD_L); |
| 96 | RZA_PRINT_REGISTER(iss, SDR_Y_OFT); |
| 97 | RZA_PRINT_REGISTER(iss, SDR_Y_PTR_S); |
| 98 | RZA_PRINT_REGISTER(iss, SDR_Y_PTR_E); |
| 99 | RZA_PRINT_REGISTER(iss, SDR_C_BAD_H); |
| 100 | RZA_PRINT_REGISTER(iss, SDR_C_BAD_L); |
| 101 | RZA_PRINT_REGISTER(iss, SDR_C_SAD_H); |
| 102 | RZA_PRINT_REGISTER(iss, SDR_C_SAD_L); |
| 103 | RZA_PRINT_REGISTER(iss, SDR_C_OFT); |
| 104 | RZA_PRINT_REGISTER(iss, SDR_C_PTR_S); |
| 105 | RZA_PRINT_REGISTER(iss, SDR_C_PTR_E); |
| 106 | |
| 107 | dev_dbg(iss->dev, "-----------------------------------------------\n"); |
| 108 | } |
| 109 | |
| 110 | /* |
| 111 | * resizer_enable - Enable/Disable RESIZER. |
| 112 | * @enable: enable flag |
| 113 | * |
| 114 | */ |
| 115 | static void resizer_enable(struct iss_resizer_device *resizer, u8 enable) |
| 116 | { |
| 117 | struct iss_device *iss = to_iss_device(resizer); |
| 118 | |
| 119 | writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN) & |
| 120 | ~RSZ_SRC_EN_SRC_EN) | |
| 121 | enable ? RSZ_SRC_EN_SRC_EN : 0, |
| 122 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN); |
| 123 | |
| 124 | /* TODO: Enable RSZB */ |
| 125 | writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) & |
| 126 | ~RSZ_EN_EN) | |
| 127 | enable ? RSZ_EN_EN : 0, |
| 128 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN); |
| 129 | } |
| 130 | |
| 131 | /* ----------------------------------------------------------------------------- |
| 132 | * Format- and pipeline-related configuration helpers |
| 133 | */ |
| 134 | |
| 135 | /* |
| 136 | * resizer_set_outaddr - Set memory address to save output image |
| 137 | * @resizer: Pointer to ISP RESIZER device. |
| 138 | * @addr: 32-bit memory address aligned on 32 byte boundary. |
| 139 | * |
| 140 | * Sets the memory address where the output will be saved. |
| 141 | */ |
| 142 | static void resizer_set_outaddr(struct iss_resizer_device *resizer, u32 addr) |
| 143 | { |
| 144 | struct iss_device *iss = to_iss_device(resizer); |
| 145 | struct v4l2_mbus_framefmt *informat, *outformat; |
| 146 | |
| 147 | informat = &resizer->formats[RESIZER_PAD_SINK]; |
| 148 | outformat = &resizer->formats[RESIZER_PAD_SOURCE_MEM]; |
| 149 | |
| 150 | /* Save address splitted in Base Address H & L */ |
| 151 | writel((addr >> 16) & 0xffff, |
| 152 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_BAD_H); |
| 153 | writel(addr & 0xffff, |
| 154 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_BAD_L); |
| 155 | |
| 156 | /* SAD = BAD */ |
| 157 | writel((addr >> 16) & 0xffff, |
| 158 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_SAD_H); |
| 159 | writel(addr & 0xffff, |
| 160 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_SAD_L); |
| 161 | |
| 162 | /* Program UV buffer address... Hardcoded to be contiguous! */ |
| 163 | if ((informat->code == V4L2_MBUS_FMT_UYVY8_1X16) && |
| 164 | (outformat->code == V4L2_MBUS_FMT_YUYV8_1_5X8)) { |
| 165 | u32 c_addr = addr + (resizer->video_out.bpl_value * |
| 166 | (outformat->height - 1)); |
| 167 | |
| 168 | /* Ensure Y_BAD_L[6:0] = C_BAD_L[6:0]*/ |
| 169 | if ((c_addr ^ addr) & 0x7f) { |
| 170 | c_addr &= ~0x7f; |
| 171 | c_addr += 0x80; |
| 172 | c_addr |= addr & 0x7f; |
| 173 | } |
| 174 | |
| 175 | /* Save address splitted in Base Address H & L */ |
| 176 | writel((c_addr >> 16) & 0xffff, |
| 177 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_BAD_H); |
| 178 | writel(c_addr & 0xffff, |
| 179 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_BAD_L); |
| 180 | |
| 181 | /* SAD = BAD */ |
| 182 | writel((c_addr >> 16) & 0xffff, |
| 183 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_SAD_H); |
| 184 | writel(c_addr & 0xffff, |
| 185 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_SAD_L); |
| 186 | } |
| 187 | } |
| 188 | |
| 189 | static void resizer_configure(struct iss_resizer_device *resizer) |
| 190 | { |
| 191 | struct iss_device *iss = to_iss_device(resizer); |
| 192 | struct v4l2_mbus_framefmt *informat, *outformat; |
| 193 | |
| 194 | informat = &resizer->formats[RESIZER_PAD_SINK]; |
| 195 | outformat = &resizer->formats[RESIZER_PAD_SOURCE_MEM]; |
| 196 | |
| 197 | /* Make sure we don't bypass the resizer */ |
| 198 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0) & |
| 199 | ~RSZ_SRC_FMT0_BYPASS, |
| 200 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0); |
| 201 | |
| 202 | /* Select RSZ input */ |
| 203 | writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0) & |
| 204 | ~RSZ_SRC_FMT0_SEL) | |
| 205 | (resizer->input == RESIZER_INPUT_IPIPEIF) ? RSZ_SRC_FMT0_SEL : 0, |
| 206 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0); |
| 207 | |
| 208 | /* RSZ ignores WEN signal from IPIPE/IPIPEIF */ |
| 209 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE) & |
| 210 | ~RSZ_SRC_MODE_WRT, |
| 211 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE); |
| 212 | |
| 213 | /* Set Resizer in free-running mode */ |
| 214 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE) & |
| 215 | ~RSZ_SRC_MODE_OST, |
| 216 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_MODE); |
| 217 | |
| 218 | /* Init Resizer A */ |
| 219 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_MODE) & |
| 220 | ~RZA_MODE_ONE_SHOT, |
| 221 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_MODE); |
| 222 | |
| 223 | /* Set size related things now */ |
| 224 | writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_VPS); |
| 225 | writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_HPS); |
| 226 | writel(informat->height - 2, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_VSZ); |
| 227 | writel(informat->width - 1, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_HSZ); |
| 228 | |
| 229 | writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_I_VPS); |
| 230 | writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_I_HPS); |
| 231 | |
| 232 | writel(outformat->height - 2, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_O_VSZ); |
| 233 | writel(outformat->width - 1, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_O_HSZ); |
| 234 | |
| 235 | writel(0x100, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_V_DIF); |
| 236 | writel(0x100, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_H_DIF); |
| 237 | |
| 238 | /* Buffer output settings */ |
| 239 | writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_PTR_S); |
| 240 | writel(outformat->height - 1, |
| 241 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_PTR_E); |
| 242 | |
| 243 | writel(resizer->video_out.bpl_value, |
| 244 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_Y_OFT); |
| 245 | |
| 246 | /* UYVY -> NV12 conversion */ |
| 247 | if ((informat->code == V4L2_MBUS_FMT_UYVY8_1X16) && |
| 248 | (outformat->code == V4L2_MBUS_FMT_YUYV8_1_5X8)) { |
| 249 | writel(RSZ_420_CEN | RSZ_420_YEN, |
| 250 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_420); |
| 251 | |
| 252 | /* UV Buffer output settings */ |
| 253 | writel(0, iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_PTR_S); |
| 254 | writel(outformat->height - 1, |
| 255 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_PTR_E); |
| 256 | |
| 257 | writel(resizer->video_out.bpl_value, |
| 258 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_SDR_C_OFT); |
| 259 | } else { |
| 260 | writel(0, |
| 261 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_420); |
| 262 | } |
| 263 | |
| 264 | omap4iss_isp_enable_interrupts(iss); |
| 265 | } |
| 266 | |
| 267 | /* ----------------------------------------------------------------------------- |
| 268 | * Interrupt handling |
| 269 | */ |
| 270 | |
| 271 | static void resizer_isr_buffer(struct iss_resizer_device *resizer) |
| 272 | { |
| 273 | struct iss_device *iss = to_iss_device(resizer); |
| 274 | struct iss_buffer *buffer; |
| 275 | |
| 276 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) & |
| 277 | ~RSZ_EN_EN, |
| 278 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN); |
| 279 | |
| 280 | buffer = omap4iss_video_buffer_next(&resizer->video_out); |
| 281 | if (buffer == NULL) |
| 282 | return; |
| 283 | |
| 284 | resizer_set_outaddr(resizer, buffer->iss_addr); |
| 285 | |
| 286 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) | |
| 287 | RSZ_EN_EN, |
| 288 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN); |
| 289 | } |
| 290 | |
| 291 | /* |
| 292 | * resizer_isif0_isr - Handle ISIF0 event |
| 293 | * @resizer: Pointer to ISP RESIZER device. |
| 294 | * |
| 295 | * Executes LSC deferred enablement before next frame starts. |
| 296 | */ |
| 297 | static void resizer_int_dma_isr(struct iss_resizer_device *resizer) |
| 298 | { |
| 299 | struct iss_pipeline *pipe = |
| 300 | to_iss_pipeline(&resizer->subdev.entity); |
| 301 | if (pipe->do_propagation) |
| 302 | atomic_inc(&pipe->frame_number); |
| 303 | |
| 304 | resizer_isr_buffer(resizer); |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * omap4iss_resizer_isr - Configure resizer during interframe time. |
| 309 | * @resizer: Pointer to ISP RESIZER device. |
| 310 | * @events: RESIZER events |
| 311 | */ |
| 312 | void omap4iss_resizer_isr(struct iss_resizer_device *resizer, u32 events) |
| 313 | { |
| 314 | struct iss_device *iss = to_iss_device(resizer); |
| 315 | struct iss_pipeline *pipe = |
| 316 | to_iss_pipeline(&resizer->subdev.entity); |
| 317 | |
Laurent Pinchart | ade1ec3 | 2013-08-28 12:03:50 -0300 | [diff] [blame^] | 318 | if (events & (ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR | |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 319 | ISP5_IRQ_RSZ_FIFO_OVF)) { |
Laurent Pinchart | 499226f | 2013-12-03 21:26:37 -0300 | [diff] [blame] | 320 | dev_dbg(iss->dev, "RSZ Err: FIFO_IN_BLK:%d, FIFO_OVF:%d\n", |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 321 | (events & |
Laurent Pinchart | ade1ec3 | 2013-08-28 12:03:50 -0300 | [diff] [blame^] | 322 | ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR) ? 1 : 0, |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 323 | (events & |
| 324 | ISP5_IRQ_RSZ_FIFO_OVF) ? 1 : 0); |
| 325 | pipe->error = true; |
| 326 | } |
| 327 | |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 328 | if (omap4iss_module_sync_is_stopping(&resizer->wait, |
| 329 | &resizer->stopping)) |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 330 | return; |
| 331 | |
| 332 | if (events & ISP5_IRQ_RSZ_INT_DMA) |
| 333 | resizer_int_dma_isr(resizer); |
| 334 | } |
| 335 | |
| 336 | /* ----------------------------------------------------------------------------- |
| 337 | * ISS video operations |
| 338 | */ |
| 339 | |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 340 | static int resizer_video_queue(struct iss_video *video, |
| 341 | struct iss_buffer *buffer) |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 342 | { |
| 343 | struct iss_resizer_device *resizer = container_of(video, |
| 344 | struct iss_resizer_device, video_out); |
| 345 | |
| 346 | if (!(resizer->output & RESIZER_OUTPUT_MEMORY)) |
| 347 | return -ENODEV; |
| 348 | |
| 349 | resizer_set_outaddr(resizer, buffer->iss_addr); |
| 350 | |
| 351 | /* |
| 352 | * If streaming was enabled before there was a buffer queued |
| 353 | * or underrun happened in the ISR, the hardware was not enabled |
| 354 | * and DMA queue flag ISS_VIDEO_DMAQUEUE_UNDERRUN is still set. |
| 355 | * Enable it now. |
| 356 | */ |
| 357 | if (video->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) { |
| 358 | resizer_enable(resizer, 1); |
| 359 | iss_video_dmaqueue_flags_clr(video); |
| 360 | } |
| 361 | |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | static const struct iss_video_operations resizer_video_ops = { |
| 366 | .queue = resizer_video_queue, |
| 367 | }; |
| 368 | |
| 369 | /* ----------------------------------------------------------------------------- |
| 370 | * V4L2 subdev operations |
| 371 | */ |
| 372 | |
| 373 | /* |
| 374 | * resizer_set_stream - Enable/Disable streaming on the RESIZER module |
| 375 | * @sd: ISP RESIZER V4L2 subdevice |
| 376 | * @enable: Enable/disable stream |
| 377 | */ |
| 378 | static int resizer_set_stream(struct v4l2_subdev *sd, int enable) |
| 379 | { |
| 380 | struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd); |
| 381 | struct iss_device *iss = to_iss_device(resizer); |
| 382 | struct iss_video *video_out = &resizer->video_out; |
| 383 | int ret = 0; |
| 384 | |
| 385 | if (resizer->state == ISS_PIPELINE_STREAM_STOPPED) { |
| 386 | if (enable == ISS_PIPELINE_STREAM_STOPPED) |
| 387 | return 0; |
| 388 | |
| 389 | omap4iss_isp_subclk_enable(iss, OMAP4_ISS_ISP_SUBCLK_RSZ); |
| 390 | |
| 391 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR) | |
| 392 | RSZ_GCK_MMR_MMR, |
| 393 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR); |
| 394 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR) | |
| 395 | RSZ_GCK_SDR_CORE, |
| 396 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR); |
| 397 | |
| 398 | /* FIXME: Enable RSZB also */ |
| 399 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG) | |
| 400 | RSZ_SYSCONFIG_RSZA_CLK_EN, |
| 401 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG); |
| 402 | } |
| 403 | |
| 404 | switch (enable) { |
| 405 | case ISS_PIPELINE_STREAM_CONTINUOUS: |
| 406 | |
| 407 | resizer_configure(resizer); |
| 408 | resizer_print_status(resizer); |
| 409 | |
| 410 | /* |
| 411 | * When outputting to memory with no buffer available, let the |
| 412 | * buffer queue handler start the hardware. A DMA queue flag |
| 413 | * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is |
| 414 | * a buffer available. |
| 415 | */ |
| 416 | if (resizer->output & RESIZER_OUTPUT_MEMORY && |
| 417 | !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED)) |
| 418 | break; |
| 419 | |
| 420 | atomic_set(&resizer->stopping, 0); |
| 421 | resizer_enable(resizer, 1); |
| 422 | iss_video_dmaqueue_flags_clr(video_out); |
| 423 | break; |
| 424 | |
| 425 | case ISS_PIPELINE_STREAM_STOPPED: |
| 426 | if (resizer->state == ISS_PIPELINE_STREAM_STOPPED) |
| 427 | return 0; |
| 428 | if (omap4iss_module_sync_idle(&sd->entity, &resizer->wait, |
| 429 | &resizer->stopping)) |
| 430 | dev_dbg(iss->dev, "%s: module stop timeout.\n", |
| 431 | sd->name); |
| 432 | |
| 433 | resizer_enable(resizer, 0); |
| 434 | omap4iss_isp_disable_interrupts(iss); |
| 435 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG) & |
| 436 | ~RSZ_SYSCONFIG_RSZA_CLK_EN, |
| 437 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SYSCONFIG); |
| 438 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR) & |
| 439 | ~RSZ_GCK_SDR_CORE, |
| 440 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_SDR); |
| 441 | writel(readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR) & |
| 442 | ~RSZ_GCK_MMR_MMR, |
| 443 | iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_GCK_MMR); |
| 444 | omap4iss_isp_subclk_disable(iss, OMAP4_ISS_ISP_SUBCLK_RSZ); |
| 445 | iss_video_dmaqueue_flags_clr(video_out); |
| 446 | break; |
| 447 | } |
| 448 | |
| 449 | resizer->state = enable; |
| 450 | return ret; |
| 451 | } |
| 452 | |
| 453 | static struct v4l2_mbus_framefmt * |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 454 | __resizer_get_format(struct iss_resizer_device *resizer, |
| 455 | struct v4l2_subdev_fh *fh, unsigned int pad, |
| 456 | enum v4l2_subdev_format_whence which) |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 457 | { |
| 458 | if (which == V4L2_SUBDEV_FORMAT_TRY) |
| 459 | return v4l2_subdev_get_try_format(fh, pad); |
| 460 | else |
| 461 | return &resizer->formats[pad]; |
| 462 | } |
| 463 | |
| 464 | /* |
| 465 | * resizer_try_format - Try video format on a pad |
| 466 | * @resizer: ISS RESIZER device |
| 467 | * @fh : V4L2 subdev file handle |
| 468 | * @pad: Pad number |
| 469 | * @fmt: Format |
| 470 | */ |
| 471 | static void |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 472 | resizer_try_format(struct iss_resizer_device *resizer, |
| 473 | struct v4l2_subdev_fh *fh, unsigned int pad, |
| 474 | struct v4l2_mbus_framefmt *fmt, |
| 475 | enum v4l2_subdev_format_whence which) |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 476 | { |
| 477 | enum v4l2_mbus_pixelcode pixelcode; |
| 478 | struct v4l2_mbus_framefmt *format; |
| 479 | unsigned int width = fmt->width; |
| 480 | unsigned int height = fmt->height; |
| 481 | unsigned int i; |
| 482 | |
| 483 | switch (pad) { |
| 484 | case RESIZER_PAD_SINK: |
| 485 | for (i = 0; i < ARRAY_SIZE(resizer_fmts); i++) { |
| 486 | if (fmt->code == resizer_fmts[i]) |
| 487 | break; |
| 488 | } |
| 489 | |
| 490 | /* If not found, use UYVY as default */ |
| 491 | if (i >= ARRAY_SIZE(resizer_fmts)) |
| 492 | fmt->code = V4L2_MBUS_FMT_UYVY8_1X16; |
| 493 | |
| 494 | /* Clamp the input size. */ |
| 495 | fmt->width = clamp_t(u32, width, 1, 8192); |
| 496 | fmt->height = clamp_t(u32, height, 1, 8192); |
| 497 | break; |
| 498 | |
| 499 | case RESIZER_PAD_SOURCE_MEM: |
| 500 | pixelcode = fmt->code; |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 501 | format = __resizer_get_format(resizer, fh, RESIZER_PAD_SINK, |
| 502 | which); |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 503 | memcpy(fmt, format, sizeof(*fmt)); |
| 504 | |
| 505 | if ((pixelcode == V4L2_MBUS_FMT_YUYV8_1_5X8) && |
| 506 | (fmt->code == V4L2_MBUS_FMT_UYVY8_1X16)) |
| 507 | fmt->code = pixelcode; |
| 508 | |
| 509 | /* The data formatter truncates the number of horizontal output |
| 510 | * pixels to a multiple of 16. To avoid clipping data, allow |
| 511 | * callers to request an output size bigger than the input size |
| 512 | * up to the nearest multiple of 16. |
| 513 | */ |
| 514 | fmt->width = clamp_t(u32, width, 32, (fmt->width + 15) & ~15); |
| 515 | fmt->width &= ~15; |
| 516 | fmt->height = clamp_t(u32, height, 32, fmt->height); |
| 517 | break; |
| 518 | |
| 519 | } |
| 520 | |
| 521 | fmt->colorspace = V4L2_COLORSPACE_JPEG; |
| 522 | fmt->field = V4L2_FIELD_NONE; |
| 523 | } |
| 524 | |
| 525 | /* |
| 526 | * resizer_enum_mbus_code - Handle pixel format enumeration |
| 527 | * @sd : pointer to v4l2 subdev structure |
| 528 | * @fh : V4L2 subdev file handle |
| 529 | * @code : pointer to v4l2_subdev_mbus_code_enum structure |
| 530 | * return -EINVAL or zero on success |
| 531 | */ |
| 532 | static int resizer_enum_mbus_code(struct v4l2_subdev *sd, |
| 533 | struct v4l2_subdev_fh *fh, |
| 534 | struct v4l2_subdev_mbus_code_enum *code) |
| 535 | { |
| 536 | struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd); |
| 537 | struct v4l2_mbus_framefmt *format; |
| 538 | |
| 539 | switch (code->pad) { |
| 540 | case RESIZER_PAD_SINK: |
| 541 | if (code->index >= ARRAY_SIZE(resizer_fmts)) |
| 542 | return -EINVAL; |
| 543 | |
| 544 | code->code = resizer_fmts[code->index]; |
| 545 | break; |
| 546 | |
| 547 | case RESIZER_PAD_SOURCE_MEM: |
| 548 | format = __resizer_get_format(resizer, fh, RESIZER_PAD_SINK, |
| 549 | V4L2_SUBDEV_FORMAT_TRY); |
| 550 | |
| 551 | if (code->index == 0) { |
| 552 | code->code = format->code; |
| 553 | break; |
| 554 | } |
| 555 | |
| 556 | switch (format->code) { |
| 557 | case V4L2_MBUS_FMT_UYVY8_1X16: |
| 558 | if (code->index == 1) |
| 559 | code->code = V4L2_MBUS_FMT_YUYV8_1_5X8; |
| 560 | else |
| 561 | return -EINVAL; |
| 562 | break; |
| 563 | default: |
| 564 | if (code->index != 0) |
| 565 | return -EINVAL; |
| 566 | } |
| 567 | |
| 568 | break; |
| 569 | |
| 570 | default: |
| 571 | return -EINVAL; |
| 572 | } |
| 573 | |
| 574 | return 0; |
| 575 | } |
| 576 | |
| 577 | static int resizer_enum_frame_size(struct v4l2_subdev *sd, |
| 578 | struct v4l2_subdev_fh *fh, |
| 579 | struct v4l2_subdev_frame_size_enum *fse) |
| 580 | { |
| 581 | struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd); |
| 582 | struct v4l2_mbus_framefmt format; |
| 583 | |
| 584 | if (fse->index != 0) |
| 585 | return -EINVAL; |
| 586 | |
| 587 | format.code = fse->code; |
| 588 | format.width = 1; |
| 589 | format.height = 1; |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 590 | resizer_try_format(resizer, fh, fse->pad, &format, |
| 591 | V4L2_SUBDEV_FORMAT_TRY); |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 592 | fse->min_width = format.width; |
| 593 | fse->min_height = format.height; |
| 594 | |
| 595 | if (format.code != fse->code) |
| 596 | return -EINVAL; |
| 597 | |
| 598 | format.code = fse->code; |
| 599 | format.width = -1; |
| 600 | format.height = -1; |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 601 | resizer_try_format(resizer, fh, fse->pad, &format, |
| 602 | V4L2_SUBDEV_FORMAT_TRY); |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 603 | fse->max_width = format.width; |
| 604 | fse->max_height = format.height; |
| 605 | |
| 606 | return 0; |
| 607 | } |
| 608 | |
| 609 | /* |
| 610 | * resizer_get_format - Retrieve the video format on a pad |
| 611 | * @sd : ISP RESIZER V4L2 subdevice |
| 612 | * @fh : V4L2 subdev file handle |
| 613 | * @fmt: Format |
| 614 | * |
| 615 | * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond |
| 616 | * to the format type. |
| 617 | */ |
| 618 | static int resizer_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, |
| 619 | struct v4l2_subdev_format *fmt) |
| 620 | { |
| 621 | struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd); |
| 622 | struct v4l2_mbus_framefmt *format; |
| 623 | |
| 624 | format = __resizer_get_format(resizer, fh, fmt->pad, fmt->which); |
| 625 | if (format == NULL) |
| 626 | return -EINVAL; |
| 627 | |
| 628 | fmt->format = *format; |
| 629 | return 0; |
| 630 | } |
| 631 | |
| 632 | /* |
| 633 | * resizer_set_format - Set the video format on a pad |
| 634 | * @sd : ISP RESIZER V4L2 subdevice |
| 635 | * @fh : V4L2 subdev file handle |
| 636 | * @fmt: Format |
| 637 | * |
| 638 | * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond |
| 639 | * to the format type. |
| 640 | */ |
| 641 | static int resizer_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, |
| 642 | struct v4l2_subdev_format *fmt) |
| 643 | { |
| 644 | struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd); |
| 645 | struct v4l2_mbus_framefmt *format; |
| 646 | |
| 647 | format = __resizer_get_format(resizer, fh, fmt->pad, fmt->which); |
| 648 | if (format == NULL) |
| 649 | return -EINVAL; |
| 650 | |
| 651 | resizer_try_format(resizer, fh, fmt->pad, &fmt->format, fmt->which); |
| 652 | *format = fmt->format; |
| 653 | |
| 654 | /* Propagate the format from sink to source */ |
| 655 | if (fmt->pad == RESIZER_PAD_SINK) { |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 656 | format = __resizer_get_format(resizer, fh, |
| 657 | RESIZER_PAD_SOURCE_MEM, |
| 658 | fmt->which); |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 659 | *format = fmt->format; |
| 660 | resizer_try_format(resizer, fh, RESIZER_PAD_SOURCE_MEM, format, |
| 661 | fmt->which); |
| 662 | } |
| 663 | |
| 664 | return 0; |
| 665 | } |
| 666 | |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 667 | static int resizer_link_validate(struct v4l2_subdev *sd, |
| 668 | struct media_link *link, |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 669 | struct v4l2_subdev_format *source_fmt, |
| 670 | struct v4l2_subdev_format *sink_fmt) |
| 671 | { |
| 672 | /* Check if the two ends match */ |
| 673 | if (source_fmt->format.width != sink_fmt->format.width || |
| 674 | source_fmt->format.height != sink_fmt->format.height) |
| 675 | return -EPIPE; |
| 676 | |
| 677 | if (source_fmt->format.code != sink_fmt->format.code) |
| 678 | return -EPIPE; |
| 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | /* |
| 684 | * resizer_init_formats - Initialize formats on all pads |
| 685 | * @sd: ISP RESIZER V4L2 subdevice |
| 686 | * @fh: V4L2 subdev file handle |
| 687 | * |
| 688 | * Initialize all pad formats with default values. If fh is not NULL, try |
| 689 | * formats are initialized on the file handle. Otherwise active formats are |
| 690 | * initialized on the device. |
| 691 | */ |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 692 | static int resizer_init_formats(struct v4l2_subdev *sd, |
| 693 | struct v4l2_subdev_fh *fh) |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 694 | { |
| 695 | struct v4l2_subdev_format format; |
| 696 | |
| 697 | memset(&format, 0, sizeof(format)); |
| 698 | format.pad = RESIZER_PAD_SINK; |
| 699 | format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; |
| 700 | format.format.code = V4L2_MBUS_FMT_UYVY8_1X16; |
| 701 | format.format.width = 4096; |
| 702 | format.format.height = 4096; |
| 703 | resizer_set_format(sd, fh, &format); |
| 704 | |
| 705 | return 0; |
| 706 | } |
| 707 | |
| 708 | /* V4L2 subdev video operations */ |
| 709 | static const struct v4l2_subdev_video_ops resizer_v4l2_video_ops = { |
| 710 | .s_stream = resizer_set_stream, |
| 711 | }; |
| 712 | |
| 713 | /* V4L2 subdev pad operations */ |
| 714 | static const struct v4l2_subdev_pad_ops resizer_v4l2_pad_ops = { |
| 715 | .enum_mbus_code = resizer_enum_mbus_code, |
| 716 | .enum_frame_size = resizer_enum_frame_size, |
| 717 | .get_fmt = resizer_get_format, |
| 718 | .set_fmt = resizer_set_format, |
| 719 | .link_validate = resizer_link_validate, |
| 720 | }; |
| 721 | |
| 722 | /* V4L2 subdev operations */ |
| 723 | static const struct v4l2_subdev_ops resizer_v4l2_ops = { |
| 724 | .video = &resizer_v4l2_video_ops, |
| 725 | .pad = &resizer_v4l2_pad_ops, |
| 726 | }; |
| 727 | |
| 728 | /* V4L2 subdev internal operations */ |
| 729 | static const struct v4l2_subdev_internal_ops resizer_v4l2_internal_ops = { |
| 730 | .open = resizer_init_formats, |
| 731 | }; |
| 732 | |
| 733 | /* ----------------------------------------------------------------------------- |
| 734 | * Media entity operations |
| 735 | */ |
| 736 | |
| 737 | /* |
| 738 | * resizer_link_setup - Setup RESIZER connections |
| 739 | * @entity: RESIZER media entity |
| 740 | * @local: Pad at the local end of the link |
| 741 | * @remote: Pad at the remote end of the link |
| 742 | * @flags: Link flags |
| 743 | * |
| 744 | * return -EINVAL or zero on success |
| 745 | */ |
| 746 | static int resizer_link_setup(struct media_entity *entity, |
| 747 | const struct media_pad *local, |
| 748 | const struct media_pad *remote, u32 flags) |
| 749 | { |
| 750 | struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); |
| 751 | struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd); |
| 752 | struct iss_device *iss = to_iss_device(resizer); |
| 753 | |
| 754 | switch (local->index | media_entity_type(remote->entity)) { |
| 755 | case RESIZER_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV: |
| 756 | /* Read from IPIPE or IPIPEIF. */ |
| 757 | if (!(flags & MEDIA_LNK_FL_ENABLED)) { |
| 758 | resizer->input = RESIZER_INPUT_NONE; |
| 759 | break; |
| 760 | } |
| 761 | |
| 762 | if (resizer->input != RESIZER_INPUT_NONE) |
| 763 | return -EBUSY; |
| 764 | |
| 765 | if (remote->entity == &iss->ipipeif.subdev.entity) |
| 766 | resizer->input = RESIZER_INPUT_IPIPEIF; |
| 767 | else if (remote->entity == &iss->ipipe.subdev.entity) |
| 768 | resizer->input = RESIZER_INPUT_IPIPE; |
| 769 | |
| 770 | |
| 771 | break; |
| 772 | |
| 773 | case RESIZER_PAD_SOURCE_MEM | MEDIA_ENT_T_DEVNODE: |
| 774 | /* Write to memory */ |
| 775 | if (flags & MEDIA_LNK_FL_ENABLED) { |
| 776 | if (resizer->output & ~RESIZER_OUTPUT_MEMORY) |
| 777 | return -EBUSY; |
| 778 | resizer->output |= RESIZER_OUTPUT_MEMORY; |
| 779 | } else { |
| 780 | resizer->output &= ~RESIZER_OUTPUT_MEMORY; |
| 781 | } |
| 782 | break; |
| 783 | |
| 784 | default: |
| 785 | return -EINVAL; |
| 786 | } |
| 787 | |
| 788 | return 0; |
| 789 | } |
| 790 | |
| 791 | /* media operations */ |
| 792 | static const struct media_entity_operations resizer_media_ops = { |
| 793 | .link_setup = resizer_link_setup, |
| 794 | .link_validate = v4l2_subdev_link_validate, |
| 795 | }; |
| 796 | |
| 797 | /* |
| 798 | * resizer_init_entities - Initialize V4L2 subdev and media entity |
| 799 | * @resizer: ISS ISP RESIZER module |
| 800 | * |
| 801 | * Return 0 on success and a negative error code on failure. |
| 802 | */ |
| 803 | static int resizer_init_entities(struct iss_resizer_device *resizer) |
| 804 | { |
| 805 | struct v4l2_subdev *sd = &resizer->subdev; |
| 806 | struct media_pad *pads = resizer->pads; |
| 807 | struct media_entity *me = &sd->entity; |
| 808 | int ret; |
| 809 | |
| 810 | resizer->input = RESIZER_INPUT_NONE; |
| 811 | |
| 812 | v4l2_subdev_init(sd, &resizer_v4l2_ops); |
| 813 | sd->internal_ops = &resizer_v4l2_internal_ops; |
| 814 | strlcpy(sd->name, "OMAP4 ISS ISP resizer", sizeof(sd->name)); |
| 815 | sd->grp_id = 1 << 16; /* group ID for iss subdevs */ |
| 816 | v4l2_set_subdevdata(sd, resizer); |
| 817 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
| 818 | |
| 819 | pads[RESIZER_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
| 820 | pads[RESIZER_PAD_SOURCE_MEM].flags = MEDIA_PAD_FL_SOURCE; |
| 821 | |
| 822 | me->ops = &resizer_media_ops; |
| 823 | ret = media_entity_init(me, RESIZER_PADS_NUM, pads, 0); |
| 824 | if (ret < 0) |
| 825 | return ret; |
| 826 | |
| 827 | resizer_init_formats(sd, NULL); |
| 828 | |
| 829 | resizer->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
| 830 | resizer->video_out.ops = &resizer_video_ops; |
| 831 | resizer->video_out.iss = to_iss_device(resizer); |
| 832 | resizer->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3; |
| 833 | resizer->video_out.bpl_alignment = 32; |
| 834 | resizer->video_out.bpl_zero_padding = 1; |
| 835 | resizer->video_out.bpl_max = 0x1ffe0; |
| 836 | |
| 837 | ret = omap4iss_video_init(&resizer->video_out, "ISP resizer a"); |
| 838 | if (ret < 0) |
| 839 | return ret; |
| 840 | |
| 841 | /* Connect the RESIZER subdev to the video node. */ |
Laurent Pinchart | a0fe029 | 2013-12-03 21:28:37 -0300 | [diff] [blame] | 842 | ret = media_entity_create_link(&resizer->subdev.entity, |
| 843 | RESIZER_PAD_SOURCE_MEM, |
| 844 | &resizer->video_out.video.entity, 0, 0); |
Sergio Aguirre | 69c536b | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 845 | if (ret < 0) |
| 846 | return ret; |
| 847 | |
| 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | void omap4iss_resizer_unregister_entities(struct iss_resizer_device *resizer) |
| 852 | { |
| 853 | media_entity_cleanup(&resizer->subdev.entity); |
| 854 | |
| 855 | v4l2_device_unregister_subdev(&resizer->subdev); |
| 856 | omap4iss_video_unregister(&resizer->video_out); |
| 857 | } |
| 858 | |
| 859 | int omap4iss_resizer_register_entities(struct iss_resizer_device *resizer, |
| 860 | struct v4l2_device *vdev) |
| 861 | { |
| 862 | int ret; |
| 863 | |
| 864 | /* Register the subdev and video node. */ |
| 865 | ret = v4l2_device_register_subdev(vdev, &resizer->subdev); |
| 866 | if (ret < 0) |
| 867 | goto error; |
| 868 | |
| 869 | ret = omap4iss_video_register(&resizer->video_out, vdev); |
| 870 | if (ret < 0) |
| 871 | goto error; |
| 872 | |
| 873 | return 0; |
| 874 | |
| 875 | error: |
| 876 | omap4iss_resizer_unregister_entities(resizer); |
| 877 | return ret; |
| 878 | } |
| 879 | |
| 880 | /* ----------------------------------------------------------------------------- |
| 881 | * ISP RESIZER initialisation and cleanup |
| 882 | */ |
| 883 | |
| 884 | /* |
| 885 | * omap4iss_resizer_init - RESIZER module initialization. |
| 886 | * @iss: Device pointer specific to the OMAP4 ISS. |
| 887 | * |
| 888 | * TODO: Get the initialisation values from platform data. |
| 889 | * |
| 890 | * Return 0 on success or a negative error code otherwise. |
| 891 | */ |
| 892 | int omap4iss_resizer_init(struct iss_device *iss) |
| 893 | { |
| 894 | struct iss_resizer_device *resizer = &iss->resizer; |
| 895 | |
| 896 | resizer->state = ISS_PIPELINE_STREAM_STOPPED; |
| 897 | init_waitqueue_head(&resizer->wait); |
| 898 | |
| 899 | return resizer_init_entities(resizer); |
| 900 | } |
| 901 | |
| 902 | /* |
| 903 | * omap4iss_resizer_cleanup - RESIZER module cleanup. |
| 904 | * @iss: Device pointer specific to the OMAP4 ISS. |
| 905 | */ |
| 906 | void omap4iss_resizer_cleanup(struct iss_device *iss) |
| 907 | { |
| 908 | /* FIXME: are you sure there's nothing to do? */ |
| 909 | } |