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viresh kumar4c18e772010-05-03 09:24:30 +01001/*
viresh kumar4c18e772010-05-03 09:24:30 +01002 * SPEAr platform shared irq layer source file
3 *
Viresh Kumardf1590d2012-11-12 22:56:03 +05304 * Copyright (C) 2009-2012 ST Microelectronics
Viresh Kumar10d89352012-06-20 12:53:02 -07005 * Viresh Kumar <viresh.linux@gmail.com>
viresh kumar4c18e772010-05-03 09:24:30 +01006 *
Viresh Kumardf1590d2012-11-12 22:56:03 +05307 * Copyright (C) 2012 ST Microelectronics
Viresh Kumar9cc23682014-04-18 15:07:16 -07008 * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Viresh Kumardf1590d2012-11-12 22:56:03 +05309 *
viresh kumar4c18e772010-05-03 09:24:30 +010010 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053014#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
viresh kumar4c18e772010-05-03 09:24:30 +010015
16#include <linux/err.h>
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053017#include <linux/export.h>
18#include <linux/interrupt.h>
viresh kumar4c18e772010-05-03 09:24:30 +010019#include <linux/io.h>
20#include <linux/irq.h>
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053021#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
viresh kumar4c18e772010-05-03 09:24:30 +010025#include <linux/spinlock.h>
viresh kumar4c18e772010-05-03 09:24:30 +010026
Rob Herringe9c51552013-01-02 09:37:56 -060027#include "irqchip.h"
28
Thomas Gleixner078bc002014-06-19 21:34:38 +000029/*
Thomas Gleixner078bc002014-06-19 21:34:38 +000030 * struct spear_shirq: shared irq structure
31 *
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000032 * base: Base register address
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000033 * status_reg: Status register offset for chained interrupt handler
34 * mask_reg: Mask register offset for irq chip
Thomas Gleixner4ecc8322014-06-19 21:34:41 +000035 * mask: Mask to apply to the status register
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000036 * virq_base: Base virtual interrupt number
37 * nr_irqs: Number of interrupts handled by this block
38 * offset: Bit offset of the first interrupt
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000039 * irq_chip: Interrupt controller chip used for this instance,
40 * if NULL group is disabled, but accounted
Thomas Gleixner078bc002014-06-19 21:34:38 +000041 */
42struct spear_shirq {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000043 void __iomem *base;
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000044 u32 status_reg;
45 u32 mask_reg;
Thomas Gleixner4ecc8322014-06-19 21:34:41 +000046 u32 mask;
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000047 u32 virq_base;
48 u32 nr_irqs;
49 u32 offset;
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000050 struct irq_chip *irq_chip;
Thomas Gleixner078bc002014-06-19 21:34:38 +000051};
52
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053053/* spear300 shared irq registers offsets and masks */
54#define SPEAR300_INT_ENB_MASK_REG 0x54
55#define SPEAR300_INT_STS_MASK_REG 0x58
56
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000057static DEFINE_RAW_SPINLOCK(shirq_lock);
58
59static void shirq_irq_mask(struct irq_data *d)
60{
61 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
62 u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000063 u32 __iomem *reg = shirq->base + shirq->mask_reg;
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000064
65 raw_spin_lock(&shirq_lock);
66 val = readl(reg) & ~(0x1 << shift);
67 writel(val, reg);
68 raw_spin_unlock(&shirq_lock);
69}
70
71static void shirq_irq_unmask(struct irq_data *d)
72{
73 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
74 u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000075 u32 __iomem *reg = shirq->base + shirq->mask_reg;
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000076
77 raw_spin_lock(&shirq_lock);
78 val = readl(reg) | (0x1 << shift);
79 writel(val, reg);
80 raw_spin_unlock(&shirq_lock);
81}
82
83static struct irq_chip shirq_chip = {
84 .name = "spear-shirq",
85 .irq_mask = shirq_irq_mask,
86 .irq_unmask = shirq_irq_unmask,
87};
88
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053089static struct spear_shirq spear300_shirq_ras1 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000090 .offset = 0,
91 .nr_irqs = 9,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +000092 .mask = ((0x1 << 9) - 1) << 0,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000093 .irq_chip = &shirq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000094 .status_reg = SPEAR300_INT_STS_MASK_REG,
95 .mask_reg = SPEAR300_INT_ENB_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053096};
97
98static struct spear_shirq *spear300_shirq_blocks[] = {
99 &spear300_shirq_ras1,
100};
101
102/* spear310 shared irq registers offsets and masks */
103#define SPEAR310_INT_STS_MASK_REG 0x04
104
105static struct spear_shirq spear310_shirq_ras1 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000106 .offset = 0,
107 .nr_irqs = 8,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000108 .mask = ((0x1 << 8) - 1) << 0,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000109 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000110 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530111};
112
113static struct spear_shirq spear310_shirq_ras2 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000114 .offset = 8,
115 .nr_irqs = 5,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000116 .mask = ((0x1 << 5) - 1) << 8,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000117 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000118 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530119};
120
121static struct spear_shirq spear310_shirq_ras3 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000122 .offset = 13,
123 .nr_irqs = 1,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000124 .mask = ((0x1 << 1) - 1) << 13,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000125 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000126 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530127};
128
129static struct spear_shirq spear310_shirq_intrcomm_ras = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000130 .offset = 14,
131 .nr_irqs = 3,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000132 .mask = ((0x1 << 3) - 1) << 14,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000133 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000134 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530135};
136
137static struct spear_shirq *spear310_shirq_blocks[] = {
138 &spear310_shirq_ras1,
139 &spear310_shirq_ras2,
140 &spear310_shirq_ras3,
141 &spear310_shirq_intrcomm_ras,
142};
143
144/* spear320 shared irq registers offsets and masks */
145#define SPEAR320_INT_STS_MASK_REG 0x04
146#define SPEAR320_INT_CLR_MASK_REG 0x04
147#define SPEAR320_INT_ENB_MASK_REG 0x08
148
Thomas Gleixner03319a12014-06-19 21:34:40 +0000149static struct spear_shirq spear320_shirq_ras3 = {
150 .offset = 0,
151 .nr_irqs = 7,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000152 .mask = ((0x1 << 7) - 1) << 0,
Thomas Gleixner03319a12014-06-19 21:34:40 +0000153};
154
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530155static struct spear_shirq spear320_shirq_ras1 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000156 .offset = 7,
157 .nr_irqs = 3,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000158 .mask = ((0x1 << 3) - 1) << 7,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000159 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000160 .status_reg = SPEAR320_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530161};
162
163static struct spear_shirq spear320_shirq_ras2 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000164 .offset = 10,
165 .nr_irqs = 1,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000166 .mask = ((0x1 << 1) - 1) << 10,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000167 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000168 .status_reg = SPEAR320_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530169};
170
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530171static struct spear_shirq spear320_shirq_intrcomm_ras = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000172 .offset = 11,
173 .nr_irqs = 11,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000174 .mask = ((0x1 << 11) - 1) << 11,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000175 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000176 .status_reg = SPEAR320_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530177};
178
179static struct spear_shirq *spear320_shirq_blocks[] = {
180 &spear320_shirq_ras3,
181 &spear320_shirq_ras1,
182 &spear320_shirq_ras2,
183 &spear320_shirq_intrcomm_ras,
184};
185
viresh kumar4c18e772010-05-03 09:24:30 +0100186static void shirq_handler(unsigned irq, struct irq_desc *desc)
187{
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100188 struct spear_shirq *shirq = irq_get_handler_data(irq);
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000189 u32 pend;
viresh kumar4c18e772010-05-03 09:24:30 +0100190
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000191 pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000192 pend >>= shirq->offset;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530193
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000194 while (pend) {
195 int irq = __ffs(pend);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530196
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000197 pend &= ~(0x1 << irq);
198 generic_handle_irq(shirq->virq_base + irq);
viresh kumar4c18e772010-05-03 09:24:30 +0100199 }
viresh kumar4c18e772010-05-03 09:24:30 +0100200}
201
Thomas Gleixnerf37ecbc2014-06-19 21:34:39 +0000202static void __init spear_shirq_register(struct spear_shirq *shirq,
203 int parent_irq)
viresh kumar4c18e772010-05-03 09:24:30 +0100204{
205 int i;
206
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000207 if (!shirq->irq_chip)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530208 return;
viresh kumar4c18e772010-05-03 09:24:30 +0100209
Russell King2aedd0f2015-06-16 23:07:01 +0100210 irq_set_chained_handler_and_data(parent_irq, shirq_handler, shirq);
Thomas Gleixnerf37ecbc2014-06-19 21:34:39 +0000211
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000212 for (i = 0; i < shirq->nr_irqs; i++) {
213 irq_set_chip_and_handler(shirq->virq_base + i,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000214 shirq->irq_chip, handle_simple_irq);
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000215 set_irq_flags(shirq->virq_base + i, IRQF_VALID);
216 irq_set_chip_data(shirq->virq_base + i, shirq);
viresh kumar4c18e772010-05-03 09:24:30 +0100217 }
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530218}
219
220static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
221 struct device_node *np)
222{
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000223 int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
Thomas Gleixnera26c06f2014-06-19 21:34:37 +0000224 struct irq_domain *shirq_domain;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530225 void __iomem *base;
226
227 base = of_iomap(np, 0);
228 if (!base) {
229 pr_err("%s: failed to map shirq registers\n", __func__);
230 return -ENXIO;
231 }
232
233 for (i = 0; i < block_nr; i++)
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000234 nr_irqs += shirq_blocks[i]->nr_irqs;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530235
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000236 virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
237 if (IS_ERR_VALUE(virq_base)) {
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530238 pr_err("%s: irq desc alloc failed\n", __func__);
239 goto err_unmap;
240 }
241
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000242 shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530243 &irq_domain_simple_ops, NULL);
244 if (WARN_ON(!shirq_domain)) {
245 pr_warn("%s: irq domain init failed\n", __func__);
246 goto err_free_desc;
247 }
248
249 for (i = 0; i < block_nr; i++) {
250 shirq_blocks[i]->base = base;
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000251 shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530252 hwirq);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530253
Thomas Gleixnerf37ecbc2014-06-19 21:34:39 +0000254 parent_irq = irq_of_parse_and_map(np, i);
255 spear_shirq_register(shirq_blocks[i], parent_irq);
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000256 hwirq += shirq_blocks[i]->nr_irqs;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530257 }
258
viresh kumar4c18e772010-05-03 09:24:30 +0100259 return 0;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530260
261err_free_desc:
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000262 irq_free_descs(virq_base, nr_irqs);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530263err_unmap:
264 iounmap(base);
265 return -ENXIO;
266}
267
Thomas Gleixner078bc002014-06-19 21:34:38 +0000268static int __init spear300_shirq_of_init(struct device_node *np,
269 struct device_node *parent)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530270{
271 return shirq_init(spear300_shirq_blocks,
272 ARRAY_SIZE(spear300_shirq_blocks), np);
273}
Rob Herringe9c51552013-01-02 09:37:56 -0600274IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530275
Thomas Gleixner078bc002014-06-19 21:34:38 +0000276static int __init spear310_shirq_of_init(struct device_node *np,
277 struct device_node *parent)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530278{
279 return shirq_init(spear310_shirq_blocks,
280 ARRAY_SIZE(spear310_shirq_blocks), np);
281}
Rob Herringe9c51552013-01-02 09:37:56 -0600282IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530283
Thomas Gleixner078bc002014-06-19 21:34:38 +0000284static int __init spear320_shirq_of_init(struct device_node *np,
285 struct device_node *parent)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530286{
287 return shirq_init(spear320_shirq_blocks,
288 ARRAY_SIZE(spear320_shirq_blocks), np);
viresh kumar4c18e772010-05-03 09:24:30 +0100289}
Rob Herringe9c51552013-01-02 09:37:56 -0600290IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);