Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "drm_crtc.h" |
| 32 | #include "drm_crtc_helper.h" |
| 33 | #include "intel_drv.h" |
| 34 | #include "i915_drm.h" |
| 35 | #include "i915_drv.h" |
| 36 | #include "intel_dp.h" |
| 37 | |
| 38 | #define DP_LINK_STATUS_SIZE 6 |
| 39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 40 | |
| 41 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| 42 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 43 | #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP) |
| 44 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 45 | struct intel_dp_priv { |
| 46 | uint32_t output_reg; |
| 47 | uint32_t DP; |
| 48 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| 49 | uint32_t save_DP; |
| 50 | uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| 51 | bool has_audio; |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 52 | int dpms_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 53 | uint8_t link_bw; |
| 54 | uint8_t lane_count; |
| 55 | uint8_t dpcd[4]; |
| 56 | struct intel_output *intel_output; |
| 57 | struct i2c_adapter adapter; |
| 58 | struct i2c_algo_dp_aux_data algo; |
| 59 | }; |
| 60 | |
| 61 | static void |
| 62 | intel_dp_link_train(struct intel_output *intel_output, uint32_t DP, |
| 63 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]); |
| 64 | |
| 65 | static void |
| 66 | intel_dp_link_down(struct intel_output *intel_output, uint32_t DP); |
| 67 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 68 | void |
| 69 | intel_edp_link_config (struct intel_output *intel_output, |
| 70 | int *lane_num, int *link_bw) |
| 71 | { |
| 72 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 73 | |
| 74 | *lane_num = dp_priv->lane_count; |
| 75 | if (dp_priv->link_bw == DP_LINK_BW_1_62) |
| 76 | *link_bw = 162000; |
| 77 | else if (dp_priv->link_bw == DP_LINK_BW_2_7) |
| 78 | *link_bw = 270000; |
| 79 | } |
| 80 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 81 | static int |
| 82 | intel_dp_max_lane_count(struct intel_output *intel_output) |
| 83 | { |
| 84 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 85 | int max_lane_count = 4; |
| 86 | |
| 87 | if (dp_priv->dpcd[0] >= 0x11) { |
| 88 | max_lane_count = dp_priv->dpcd[2] & 0x1f; |
| 89 | switch (max_lane_count) { |
| 90 | case 1: case 2: case 4: |
| 91 | break; |
| 92 | default: |
| 93 | max_lane_count = 4; |
| 94 | } |
| 95 | } |
| 96 | return max_lane_count; |
| 97 | } |
| 98 | |
| 99 | static int |
| 100 | intel_dp_max_link_bw(struct intel_output *intel_output) |
| 101 | { |
| 102 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 103 | int max_link_bw = dp_priv->dpcd[1]; |
| 104 | |
| 105 | switch (max_link_bw) { |
| 106 | case DP_LINK_BW_1_62: |
| 107 | case DP_LINK_BW_2_7: |
| 108 | break; |
| 109 | default: |
| 110 | max_link_bw = DP_LINK_BW_1_62; |
| 111 | break; |
| 112 | } |
| 113 | return max_link_bw; |
| 114 | } |
| 115 | |
| 116 | static int |
| 117 | intel_dp_link_clock(uint8_t link_bw) |
| 118 | { |
| 119 | if (link_bw == DP_LINK_BW_2_7) |
| 120 | return 270000; |
| 121 | else |
| 122 | return 162000; |
| 123 | } |
| 124 | |
| 125 | /* I think this is a fiction */ |
| 126 | static int |
| 127 | intel_dp_link_required(int pixel_clock) |
| 128 | { |
| 129 | return pixel_clock * 3; |
| 130 | } |
| 131 | |
| 132 | static int |
| 133 | intel_dp_mode_valid(struct drm_connector *connector, |
| 134 | struct drm_display_mode *mode) |
| 135 | { |
| 136 | struct intel_output *intel_output = to_intel_output(connector); |
| 137 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output)); |
| 138 | int max_lanes = intel_dp_max_lane_count(intel_output); |
| 139 | |
| 140 | if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes) |
| 141 | return MODE_CLOCK_HIGH; |
| 142 | |
| 143 | if (mode->clock < 10000) |
| 144 | return MODE_CLOCK_LOW; |
| 145 | |
| 146 | return MODE_OK; |
| 147 | } |
| 148 | |
| 149 | static uint32_t |
| 150 | pack_aux(uint8_t *src, int src_bytes) |
| 151 | { |
| 152 | int i; |
| 153 | uint32_t v = 0; |
| 154 | |
| 155 | if (src_bytes > 4) |
| 156 | src_bytes = 4; |
| 157 | for (i = 0; i < src_bytes; i++) |
| 158 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 159 | return v; |
| 160 | } |
| 161 | |
| 162 | static void |
| 163 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 164 | { |
| 165 | int i; |
| 166 | if (dst_bytes > 4) |
| 167 | dst_bytes = 4; |
| 168 | for (i = 0; i < dst_bytes; i++) |
| 169 | dst[i] = src >> ((3-i) * 8); |
| 170 | } |
| 171 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 172 | /* hrawclock is 1/4 the FSB frequency */ |
| 173 | static int |
| 174 | intel_hrawclk(struct drm_device *dev) |
| 175 | { |
| 176 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 177 | uint32_t clkcfg; |
| 178 | |
| 179 | clkcfg = I915_READ(CLKCFG); |
| 180 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 181 | case CLKCFG_FSB_400: |
| 182 | return 100; |
| 183 | case CLKCFG_FSB_533: |
| 184 | return 133; |
| 185 | case CLKCFG_FSB_667: |
| 186 | return 166; |
| 187 | case CLKCFG_FSB_800: |
| 188 | return 200; |
| 189 | case CLKCFG_FSB_1067: |
| 190 | return 266; |
| 191 | case CLKCFG_FSB_1333: |
| 192 | return 333; |
| 193 | /* these two are just a guess; one of them might be right */ |
| 194 | case CLKCFG_FSB_1600: |
| 195 | case CLKCFG_FSB_1600_ALT: |
| 196 | return 400; |
| 197 | default: |
| 198 | return 133; |
| 199 | } |
| 200 | } |
| 201 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 202 | static int |
| 203 | intel_dp_aux_ch(struct intel_output *intel_output, |
| 204 | uint8_t *send, int send_bytes, |
| 205 | uint8_t *recv, int recv_size) |
| 206 | { |
| 207 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 208 | uint32_t output_reg = dp_priv->output_reg; |
| 209 | struct drm_device *dev = intel_output->base.dev; |
| 210 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 211 | uint32_t ch_ctl = output_reg + 0x10; |
| 212 | uint32_t ch_data = ch_ctl + 4; |
| 213 | int i; |
| 214 | int recv_bytes; |
| 215 | uint32_t ctl; |
| 216 | uint32_t status; |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 217 | uint32_t aux_clock_divider; |
| 218 | int try; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 219 | |
| 220 | /* The clock divider is based off the hrawclk, |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 221 | * and would like to run at 2MHz. So, take the |
| 222 | * hrawclk value and divide by 2 and use that |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 223 | */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 224 | if (IS_eDP(intel_output)) |
| 225 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
| 226 | else if (IS_IGDNG(dev)) |
| 227 | aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 228 | else |
| 229 | aux_clock_divider = intel_hrawclk(dev) / 2; |
| 230 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 231 | /* Must try at least 3 times according to DP spec */ |
| 232 | for (try = 0; try < 5; try++) { |
| 233 | /* Load the send data into the aux channel data registers */ |
| 234 | for (i = 0; i < send_bytes; i += 4) { |
Joe Perches | a419aef | 2009-08-18 11:18:35 -0700 | [diff] [blame] | 235 | uint32_t d = pack_aux(send + i, send_bytes - i); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 236 | |
| 237 | I915_WRITE(ch_data + i, d); |
| 238 | } |
| 239 | |
| 240 | ctl = (DP_AUX_CH_CTL_SEND_BUSY | |
| 241 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 242 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 243 | (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 244 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
| 245 | DP_AUX_CH_CTL_DONE | |
| 246 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 247 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
| 248 | |
| 249 | /* Send the command and wait for it to complete */ |
| 250 | I915_WRITE(ch_ctl, ctl); |
| 251 | (void) I915_READ(ch_ctl); |
| 252 | for (;;) { |
| 253 | udelay(100); |
| 254 | status = I915_READ(ch_ctl); |
| 255 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 256 | break; |
| 257 | } |
| 258 | |
| 259 | /* Clear done status and any errors */ |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 260 | I915_WRITE(ch_ctl, (status | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 261 | DP_AUX_CH_CTL_DONE | |
| 262 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 263 | DP_AUX_CH_CTL_RECEIVE_ERROR)); |
| 264 | (void) I915_READ(ch_ctl); |
| 265 | if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 266 | break; |
| 267 | } |
| 268 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 269 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 270 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 271 | return -EBUSY; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | /* Check for timeout or receive error. |
| 275 | * Timeouts occur when the sink is not connected |
| 276 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 277 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 278 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 279 | return -EIO; |
| 280 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 281 | |
| 282 | /* Timeouts occur when the device isn't connected, so they're |
| 283 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 284 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 285 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 286 | return -ETIMEDOUT; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | /* Unload any bytes sent back from the other side */ |
| 290 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 291 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
| 292 | |
| 293 | if (recv_bytes > recv_size) |
| 294 | recv_bytes = recv_size; |
| 295 | |
| 296 | for (i = 0; i < recv_bytes; i += 4) { |
| 297 | uint32_t d = I915_READ(ch_data + i); |
| 298 | |
| 299 | unpack_aux(d, recv + i, recv_bytes - i); |
| 300 | } |
| 301 | |
| 302 | return recv_bytes; |
| 303 | } |
| 304 | |
| 305 | /* Write data to the aux channel in native mode */ |
| 306 | static int |
| 307 | intel_dp_aux_native_write(struct intel_output *intel_output, |
| 308 | uint16_t address, uint8_t *send, int send_bytes) |
| 309 | { |
| 310 | int ret; |
| 311 | uint8_t msg[20]; |
| 312 | int msg_bytes; |
| 313 | uint8_t ack; |
| 314 | |
| 315 | if (send_bytes > 16) |
| 316 | return -1; |
| 317 | msg[0] = AUX_NATIVE_WRITE << 4; |
| 318 | msg[1] = address >> 8; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 319 | msg[2] = address & 0xff; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 320 | msg[3] = send_bytes - 1; |
| 321 | memcpy(&msg[4], send, send_bytes); |
| 322 | msg_bytes = send_bytes + 4; |
| 323 | for (;;) { |
| 324 | ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1); |
| 325 | if (ret < 0) |
| 326 | return ret; |
| 327 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
| 328 | break; |
| 329 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 330 | udelay(100); |
| 331 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 332 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 333 | } |
| 334 | return send_bytes; |
| 335 | } |
| 336 | |
| 337 | /* Write a single byte to the aux channel in native mode */ |
| 338 | static int |
| 339 | intel_dp_aux_native_write_1(struct intel_output *intel_output, |
| 340 | uint16_t address, uint8_t byte) |
| 341 | { |
| 342 | return intel_dp_aux_native_write(intel_output, address, &byte, 1); |
| 343 | } |
| 344 | |
| 345 | /* read bytes from a native aux channel */ |
| 346 | static int |
| 347 | intel_dp_aux_native_read(struct intel_output *intel_output, |
| 348 | uint16_t address, uint8_t *recv, int recv_bytes) |
| 349 | { |
| 350 | uint8_t msg[4]; |
| 351 | int msg_bytes; |
| 352 | uint8_t reply[20]; |
| 353 | int reply_bytes; |
| 354 | uint8_t ack; |
| 355 | int ret; |
| 356 | |
| 357 | msg[0] = AUX_NATIVE_READ << 4; |
| 358 | msg[1] = address >> 8; |
| 359 | msg[2] = address & 0xff; |
| 360 | msg[3] = recv_bytes - 1; |
| 361 | |
| 362 | msg_bytes = 4; |
| 363 | reply_bytes = recv_bytes + 1; |
| 364 | |
| 365 | for (;;) { |
| 366 | ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, |
| 367 | reply, reply_bytes); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 368 | if (ret == 0) |
| 369 | return -EPROTO; |
| 370 | if (ret < 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 371 | return ret; |
| 372 | ack = reply[0]; |
| 373 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
| 374 | memcpy(recv, reply + 1, ret - 1); |
| 375 | return ret - 1; |
| 376 | } |
| 377 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 378 | udelay(100); |
| 379 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 380 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 381 | } |
| 382 | } |
| 383 | |
| 384 | static int |
| 385 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, |
| 386 | uint8_t *send, int send_bytes, |
| 387 | uint8_t *recv, int recv_bytes) |
| 388 | { |
| 389 | struct intel_dp_priv *dp_priv = container_of(adapter, |
| 390 | struct intel_dp_priv, |
| 391 | adapter); |
| 392 | struct intel_output *intel_output = dp_priv->intel_output; |
| 393 | |
| 394 | return intel_dp_aux_ch(intel_output, |
| 395 | send, send_bytes, recv, recv_bytes); |
| 396 | } |
| 397 | |
| 398 | static int |
| 399 | intel_dp_i2c_init(struct intel_output *intel_output, const char *name) |
| 400 | { |
| 401 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 402 | |
Zhenyu Wang | d54e9d2 | 2009-10-19 15:43:51 +0800 | [diff] [blame] | 403 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 404 | dp_priv->algo.running = false; |
| 405 | dp_priv->algo.address = 0; |
| 406 | dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; |
| 407 | |
| 408 | memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter)); |
| 409 | dp_priv->adapter.owner = THIS_MODULE; |
| 410 | dp_priv->adapter.class = I2C_CLASS_DDC; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 411 | strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); |
| 412 | dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 413 | dp_priv->adapter.algo_data = &dp_priv->algo; |
| 414 | dp_priv->adapter.dev.parent = &intel_output->base.kdev; |
| 415 | |
| 416 | return i2c_dp_aux_add_bus(&dp_priv->adapter); |
| 417 | } |
| 418 | |
| 419 | static bool |
| 420 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 421 | struct drm_display_mode *adjusted_mode) |
| 422 | { |
| 423 | struct intel_output *intel_output = enc_to_intel_output(encoder); |
| 424 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 425 | int lane_count, clock; |
| 426 | int max_lane_count = intel_dp_max_lane_count(intel_output); |
| 427 | int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0; |
| 428 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
| 429 | |
| 430 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
| 431 | for (clock = 0; clock <= max_clock; clock++) { |
| 432 | int link_avail = intel_dp_link_clock(bws[clock]) * lane_count; |
| 433 | |
| 434 | if (intel_dp_link_required(mode->clock) <= link_avail) { |
| 435 | dp_priv->link_bw = bws[clock]; |
| 436 | dp_priv->lane_count = lane_count; |
| 437 | adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 438 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
| 439 | "count %d clock %d\n", |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 440 | dp_priv->link_bw, dp_priv->lane_count, |
| 441 | adjusted_mode->clock); |
| 442 | return true; |
| 443 | } |
| 444 | } |
| 445 | } |
| 446 | return false; |
| 447 | } |
| 448 | |
| 449 | struct intel_dp_m_n { |
| 450 | uint32_t tu; |
| 451 | uint32_t gmch_m; |
| 452 | uint32_t gmch_n; |
| 453 | uint32_t link_m; |
| 454 | uint32_t link_n; |
| 455 | }; |
| 456 | |
| 457 | static void |
| 458 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
| 459 | { |
| 460 | while (*num > 0xffffff || *den > 0xffffff) { |
| 461 | *num >>= 1; |
| 462 | *den >>= 1; |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | static void |
| 467 | intel_dp_compute_m_n(int bytes_per_pixel, |
| 468 | int nlanes, |
| 469 | int pixel_clock, |
| 470 | int link_clock, |
| 471 | struct intel_dp_m_n *m_n) |
| 472 | { |
| 473 | m_n->tu = 64; |
| 474 | m_n->gmch_m = pixel_clock * bytes_per_pixel; |
| 475 | m_n->gmch_n = link_clock * nlanes; |
| 476 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 477 | m_n->link_m = pixel_clock; |
| 478 | m_n->link_n = link_clock; |
| 479 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 480 | } |
| 481 | |
| 482 | void |
| 483 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 484 | struct drm_display_mode *adjusted_mode) |
| 485 | { |
| 486 | struct drm_device *dev = crtc->dev; |
| 487 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 488 | struct drm_connector *connector; |
| 489 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 491 | int lane_count = 4; |
| 492 | struct intel_dp_m_n m_n; |
| 493 | |
| 494 | /* |
| 495 | * Find the lane count in the intel_output private |
| 496 | */ |
| 497 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 498 | struct intel_output *intel_output = to_intel_output(connector); |
| 499 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 500 | |
| 501 | if (!connector->encoder || connector->encoder->crtc != crtc) |
| 502 | continue; |
| 503 | |
| 504 | if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) { |
| 505 | lane_count = dp_priv->lane_count; |
| 506 | break; |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | /* |
| 511 | * Compute the GMCH and Link ratios. The '3' here is |
| 512 | * the number of bytes_per_pixel post-LUT, which we always |
| 513 | * set up for 8-bits of R/G/B, or 3 bytes total. |
| 514 | */ |
| 515 | intel_dp_compute_m_n(3, lane_count, |
| 516 | mode->clock, adjusted_mode->clock, &m_n); |
| 517 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 518 | if (IS_IGDNG(dev)) { |
| 519 | if (intel_crtc->pipe == 0) { |
| 520 | I915_WRITE(TRANSA_DATA_M1, |
| 521 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 522 | m_n.gmch_m); |
| 523 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); |
| 524 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); |
| 525 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); |
| 526 | } else { |
| 527 | I915_WRITE(TRANSB_DATA_M1, |
| 528 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 529 | m_n.gmch_m); |
| 530 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); |
| 531 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); |
| 532 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); |
| 533 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 534 | } else { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 535 | if (intel_crtc->pipe == 0) { |
| 536 | I915_WRITE(PIPEA_GMCH_DATA_M, |
| 537 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 538 | m_n.gmch_m); |
| 539 | I915_WRITE(PIPEA_GMCH_DATA_N, |
| 540 | m_n.gmch_n); |
| 541 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); |
| 542 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); |
| 543 | } else { |
| 544 | I915_WRITE(PIPEB_GMCH_DATA_M, |
| 545 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 546 | m_n.gmch_m); |
| 547 | I915_WRITE(PIPEB_GMCH_DATA_N, |
| 548 | m_n.gmch_n); |
| 549 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); |
| 550 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); |
| 551 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 552 | } |
| 553 | } |
| 554 | |
| 555 | static void |
| 556 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 557 | struct drm_display_mode *adjusted_mode) |
| 558 | { |
| 559 | struct intel_output *intel_output = enc_to_intel_output(encoder); |
| 560 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 561 | struct drm_crtc *crtc = intel_output->enc.crtc; |
| 562 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 563 | |
| 564 | dp_priv->DP = (DP_LINK_TRAIN_OFF | |
| 565 | DP_VOLTAGE_0_4 | |
| 566 | DP_PRE_EMPHASIS_0 | |
| 567 | DP_SYNC_VS_HIGH | |
| 568 | DP_SYNC_HS_HIGH); |
| 569 | |
| 570 | switch (dp_priv->lane_count) { |
| 571 | case 1: |
| 572 | dp_priv->DP |= DP_PORT_WIDTH_1; |
| 573 | break; |
| 574 | case 2: |
| 575 | dp_priv->DP |= DP_PORT_WIDTH_2; |
| 576 | break; |
| 577 | case 4: |
| 578 | dp_priv->DP |= DP_PORT_WIDTH_4; |
| 579 | break; |
| 580 | } |
| 581 | if (dp_priv->has_audio) |
| 582 | dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE; |
| 583 | |
| 584 | memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
| 585 | dp_priv->link_configuration[0] = dp_priv->link_bw; |
| 586 | dp_priv->link_configuration[1] = dp_priv->lane_count; |
| 587 | |
| 588 | /* |
| 589 | * Check for DPCD version > 1.1, |
| 590 | * enable enahanced frame stuff in that case |
| 591 | */ |
| 592 | if (dp_priv->dpcd[0] >= 0x11) { |
| 593 | dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 594 | dp_priv->DP |= DP_ENHANCED_FRAMING; |
| 595 | } |
| 596 | |
| 597 | if (intel_crtc->pipe == 1) |
| 598 | dp_priv->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 599 | |
| 600 | if (IS_eDP(intel_output)) { |
| 601 | /* don't miss out required setting for eDP */ |
| 602 | dp_priv->DP |= DP_PLL_ENABLE; |
| 603 | if (adjusted_mode->clock < 200000) |
| 604 | dp_priv->DP |= DP_PLL_FREQ_160MHZ; |
| 605 | else |
| 606 | dp_priv->DP |= DP_PLL_FREQ_270MHZ; |
| 607 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 608 | } |
| 609 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 610 | static void igdng_edp_backlight_on (struct drm_device *dev) |
| 611 | { |
| 612 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 613 | u32 pp; |
| 614 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 615 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 616 | pp = I915_READ(PCH_PP_CONTROL); |
| 617 | pp |= EDP_BLC_ENABLE; |
| 618 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 619 | } |
| 620 | |
| 621 | static void igdng_edp_backlight_off (struct drm_device *dev) |
| 622 | { |
| 623 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 624 | u32 pp; |
| 625 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 626 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 627 | pp = I915_READ(PCH_PP_CONTROL); |
| 628 | pp &= ~EDP_BLC_ENABLE; |
| 629 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 630 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 631 | |
| 632 | static void |
| 633 | intel_dp_dpms(struct drm_encoder *encoder, int mode) |
| 634 | { |
| 635 | struct intel_output *intel_output = enc_to_intel_output(encoder); |
| 636 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 637 | struct drm_device *dev = intel_output->base.dev; |
| 638 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 639 | uint32_t dp_reg = I915_READ(dp_priv->output_reg); |
| 640 | |
| 641 | if (mode != DRM_MODE_DPMS_ON) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 642 | if (dp_reg & DP_PORT_EN) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 643 | intel_dp_link_down(intel_output, dp_priv->DP); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 644 | if (IS_eDP(intel_output)) |
| 645 | igdng_edp_backlight_off(dev); |
| 646 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 647 | } else { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 648 | if (!(dp_reg & DP_PORT_EN)) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 649 | intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 650 | if (IS_eDP(intel_output)) |
| 651 | igdng_edp_backlight_on(dev); |
| 652 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 653 | } |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 654 | dp_priv->dpms_mode = mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | /* |
| 658 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 659 | * link status information |
| 660 | */ |
| 661 | static bool |
| 662 | intel_dp_get_link_status(struct intel_output *intel_output, |
| 663 | uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 664 | { |
| 665 | int ret; |
| 666 | |
| 667 | ret = intel_dp_aux_native_read(intel_output, |
| 668 | DP_LANE0_1_STATUS, |
| 669 | link_status, DP_LINK_STATUS_SIZE); |
| 670 | if (ret != DP_LINK_STATUS_SIZE) |
| 671 | return false; |
| 672 | return true; |
| 673 | } |
| 674 | |
| 675 | static uint8_t |
| 676 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 677 | int r) |
| 678 | { |
| 679 | return link_status[r - DP_LANE0_1_STATUS]; |
| 680 | } |
| 681 | |
| 682 | static void |
| 683 | intel_dp_save(struct drm_connector *connector) |
| 684 | { |
| 685 | struct intel_output *intel_output = to_intel_output(connector); |
| 686 | struct drm_device *dev = intel_output->base.dev; |
| 687 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 688 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 689 | |
| 690 | dp_priv->save_DP = I915_READ(dp_priv->output_reg); |
| 691 | intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET, |
| 692 | dp_priv->save_link_configuration, |
| 693 | sizeof (dp_priv->save_link_configuration)); |
| 694 | } |
| 695 | |
| 696 | static uint8_t |
| 697 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 698 | int lane) |
| 699 | { |
| 700 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 701 | int s = ((lane & 1) ? |
| 702 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
| 703 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
| 704 | uint8_t l = intel_dp_link_status(link_status, i); |
| 705 | |
| 706 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
| 707 | } |
| 708 | |
| 709 | static uint8_t |
| 710 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 711 | int lane) |
| 712 | { |
| 713 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 714 | int s = ((lane & 1) ? |
| 715 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
| 716 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
| 717 | uint8_t l = intel_dp_link_status(link_status, i); |
| 718 | |
| 719 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
| 720 | } |
| 721 | |
| 722 | |
| 723 | #if 0 |
| 724 | static char *voltage_names[] = { |
| 725 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 726 | }; |
| 727 | static char *pre_emph_names[] = { |
| 728 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 729 | }; |
| 730 | static char *link_train_names[] = { |
| 731 | "pattern 1", "pattern 2", "idle", "off" |
| 732 | }; |
| 733 | #endif |
| 734 | |
| 735 | /* |
| 736 | * These are source-specific values; current Intel hardware supports |
| 737 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 738 | */ |
| 739 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 |
| 740 | |
| 741 | static uint8_t |
| 742 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) |
| 743 | { |
| 744 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 745 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 746 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 747 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 748 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 749 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 750 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 751 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 752 | default: |
| 753 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | static void |
| 758 | intel_get_adjust_train(struct intel_output *intel_output, |
| 759 | uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 760 | int lane_count, |
| 761 | uint8_t train_set[4]) |
| 762 | { |
| 763 | uint8_t v = 0; |
| 764 | uint8_t p = 0; |
| 765 | int lane; |
| 766 | |
| 767 | for (lane = 0; lane < lane_count; lane++) { |
| 768 | uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane); |
| 769 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane); |
| 770 | |
| 771 | if (this_v > v) |
| 772 | v = this_v; |
| 773 | if (this_p > p) |
| 774 | p = this_p; |
| 775 | } |
| 776 | |
| 777 | if (v >= I830_DP_VOLTAGE_MAX) |
| 778 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; |
| 779 | |
| 780 | if (p >= intel_dp_pre_emphasis_max(v)) |
| 781 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 782 | |
| 783 | for (lane = 0; lane < 4; lane++) |
| 784 | train_set[lane] = v | p; |
| 785 | } |
| 786 | |
| 787 | static uint32_t |
| 788 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
| 789 | { |
| 790 | uint32_t signal_levels = 0; |
| 791 | |
| 792 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 793 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 794 | default: |
| 795 | signal_levels |= DP_VOLTAGE_0_4; |
| 796 | break; |
| 797 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 798 | signal_levels |= DP_VOLTAGE_0_6; |
| 799 | break; |
| 800 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 801 | signal_levels |= DP_VOLTAGE_0_8; |
| 802 | break; |
| 803 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 804 | signal_levels |= DP_VOLTAGE_1_2; |
| 805 | break; |
| 806 | } |
| 807 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 808 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 809 | default: |
| 810 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 811 | break; |
| 812 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 813 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 814 | break; |
| 815 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 816 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 817 | break; |
| 818 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 819 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 820 | break; |
| 821 | } |
| 822 | return signal_levels; |
| 823 | } |
| 824 | |
| 825 | static uint8_t |
| 826 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 827 | int lane) |
| 828 | { |
| 829 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
| 830 | int s = (lane & 1) * 4; |
| 831 | uint8_t l = intel_dp_link_status(link_status, i); |
| 832 | |
| 833 | return (l >> s) & 0xf; |
| 834 | } |
| 835 | |
| 836 | /* Check for clock recovery is done on all channels */ |
| 837 | static bool |
| 838 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) |
| 839 | { |
| 840 | int lane; |
| 841 | uint8_t lane_status; |
| 842 | |
| 843 | for (lane = 0; lane < lane_count; lane++) { |
| 844 | lane_status = intel_get_lane_status(link_status, lane); |
| 845 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
| 846 | return false; |
| 847 | } |
| 848 | return true; |
| 849 | } |
| 850 | |
| 851 | /* Check to see if channel eq is done on all channels */ |
| 852 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ |
| 853 | DP_LANE_CHANNEL_EQ_DONE|\ |
| 854 | DP_LANE_SYMBOL_LOCKED) |
| 855 | static bool |
| 856 | intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) |
| 857 | { |
| 858 | uint8_t lane_align; |
| 859 | uint8_t lane_status; |
| 860 | int lane; |
| 861 | |
| 862 | lane_align = intel_dp_link_status(link_status, |
| 863 | DP_LANE_ALIGN_STATUS_UPDATED); |
| 864 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) |
| 865 | return false; |
| 866 | for (lane = 0; lane < lane_count; lane++) { |
| 867 | lane_status = intel_get_lane_status(link_status, lane); |
| 868 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
| 869 | return false; |
| 870 | } |
| 871 | return true; |
| 872 | } |
| 873 | |
| 874 | static bool |
| 875 | intel_dp_set_link_train(struct intel_output *intel_output, |
| 876 | uint32_t dp_reg_value, |
| 877 | uint8_t dp_train_pat, |
| 878 | uint8_t train_set[4], |
| 879 | bool first) |
| 880 | { |
| 881 | struct drm_device *dev = intel_output->base.dev; |
| 882 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 883 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 884 | int ret; |
| 885 | |
| 886 | I915_WRITE(dp_priv->output_reg, dp_reg_value); |
| 887 | POSTING_READ(dp_priv->output_reg); |
| 888 | if (first) |
| 889 | intel_wait_for_vblank(dev); |
| 890 | |
| 891 | intel_dp_aux_native_write_1(intel_output, |
| 892 | DP_TRAINING_PATTERN_SET, |
| 893 | dp_train_pat); |
| 894 | |
| 895 | ret = intel_dp_aux_native_write(intel_output, |
| 896 | DP_TRAINING_LANE0_SET, train_set, 4); |
| 897 | if (ret != 4) |
| 898 | return false; |
| 899 | |
| 900 | return true; |
| 901 | } |
| 902 | |
| 903 | static void |
| 904 | intel_dp_link_train(struct intel_output *intel_output, uint32_t DP, |
| 905 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]) |
| 906 | { |
| 907 | struct drm_device *dev = intel_output->base.dev; |
| 908 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 909 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 910 | uint8_t train_set[4]; |
| 911 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
| 912 | int i; |
| 913 | uint8_t voltage; |
| 914 | bool clock_recovery = false; |
| 915 | bool channel_eq = false; |
| 916 | bool first = true; |
| 917 | int tries; |
| 918 | |
| 919 | /* Write the link configuration data */ |
| 920 | intel_dp_aux_native_write(intel_output, 0x100, |
| 921 | link_configuration, DP_LINK_CONFIGURATION_SIZE); |
| 922 | |
| 923 | DP |= DP_PORT_EN; |
| 924 | DP &= ~DP_LINK_TRAIN_MASK; |
| 925 | memset(train_set, 0, 4); |
| 926 | voltage = 0xff; |
| 927 | tries = 0; |
| 928 | clock_recovery = false; |
| 929 | for (;;) { |
| 930 | /* Use train_set[0] to set the voltage and pre emphasis values */ |
| 931 | uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); |
| 932 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 933 | |
| 934 | if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1, |
| 935 | DP_TRAINING_PATTERN_1, train_set, first)) |
| 936 | break; |
| 937 | first = false; |
| 938 | /* Set training pattern 1 */ |
| 939 | |
| 940 | udelay(100); |
| 941 | if (!intel_dp_get_link_status(intel_output, link_status)) |
| 942 | break; |
| 943 | |
| 944 | if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) { |
| 945 | clock_recovery = true; |
| 946 | break; |
| 947 | } |
| 948 | |
| 949 | /* Check to see if we've tried the max voltage */ |
| 950 | for (i = 0; i < dp_priv->lane_count; i++) |
| 951 | if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 952 | break; |
| 953 | if (i == dp_priv->lane_count) |
| 954 | break; |
| 955 | |
| 956 | /* Check to see if we've tried the same voltage 5 times */ |
| 957 | if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 958 | ++tries; |
| 959 | if (tries == 5) |
| 960 | break; |
| 961 | } else |
| 962 | tries = 0; |
| 963 | voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 964 | |
| 965 | /* Compute new train_set as requested by target */ |
| 966 | intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set); |
| 967 | } |
| 968 | |
| 969 | /* channel equalization */ |
| 970 | tries = 0; |
| 971 | channel_eq = false; |
| 972 | for (;;) { |
| 973 | /* Use train_set[0] to set the voltage and pre emphasis values */ |
| 974 | uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); |
| 975 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 976 | |
| 977 | /* channel eq pattern */ |
| 978 | if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2, |
| 979 | DP_TRAINING_PATTERN_2, train_set, |
| 980 | false)) |
| 981 | break; |
| 982 | |
| 983 | udelay(400); |
| 984 | if (!intel_dp_get_link_status(intel_output, link_status)) |
| 985 | break; |
| 986 | |
| 987 | if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) { |
| 988 | channel_eq = true; |
| 989 | break; |
| 990 | } |
| 991 | |
| 992 | /* Try 5 times */ |
| 993 | if (tries > 5) |
| 994 | break; |
| 995 | |
| 996 | /* Compute new train_set as requested by target */ |
| 997 | intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set); |
| 998 | ++tries; |
| 999 | } |
| 1000 | |
| 1001 | I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF); |
| 1002 | POSTING_READ(dp_priv->output_reg); |
| 1003 | intel_dp_aux_native_write_1(intel_output, |
| 1004 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
| 1005 | } |
| 1006 | |
| 1007 | static void |
| 1008 | intel_dp_link_down(struct intel_output *intel_output, uint32_t DP) |
| 1009 | { |
| 1010 | struct drm_device *dev = intel_output->base.dev; |
| 1011 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1012 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 1013 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1014 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1015 | |
| 1016 | if (IS_eDP(intel_output)) { |
| 1017 | DP &= ~DP_PLL_ENABLE; |
| 1018 | I915_WRITE(dp_priv->output_reg, DP); |
| 1019 | POSTING_READ(dp_priv->output_reg); |
| 1020 | udelay(100); |
| 1021 | } |
| 1022 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1023 | DP &= ~DP_LINK_TRAIN_MASK; |
| 1024 | I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
| 1025 | POSTING_READ(dp_priv->output_reg); |
| 1026 | |
| 1027 | udelay(17000); |
| 1028 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1029 | if (IS_eDP(intel_output)) |
| 1030 | DP |= DP_LINK_TRAIN_OFF; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1031 | I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); |
| 1032 | POSTING_READ(dp_priv->output_reg); |
| 1033 | } |
| 1034 | |
| 1035 | static void |
| 1036 | intel_dp_restore(struct drm_connector *connector) |
| 1037 | { |
| 1038 | struct intel_output *intel_output = to_intel_output(connector); |
| 1039 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 1040 | |
| 1041 | if (dp_priv->save_DP & DP_PORT_EN) |
| 1042 | intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration); |
| 1043 | else |
| 1044 | intel_dp_link_down(intel_output, dp_priv->save_DP); |
| 1045 | } |
| 1046 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1047 | /* |
| 1048 | * According to DP spec |
| 1049 | * 5.1.2: |
| 1050 | * 1. Read DPCD |
| 1051 | * 2. Configure link according to Receiver Capabilities |
| 1052 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 1053 | * 4. Check link status on receipt of hot-plug interrupt |
| 1054 | */ |
| 1055 | |
| 1056 | static void |
| 1057 | intel_dp_check_link_status(struct intel_output *intel_output) |
| 1058 | { |
| 1059 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 1060 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
| 1061 | |
| 1062 | if (!intel_output->enc.crtc) |
| 1063 | return; |
| 1064 | |
| 1065 | if (!intel_dp_get_link_status(intel_output, link_status)) { |
| 1066 | intel_dp_link_down(intel_output, dp_priv->DP); |
| 1067 | return; |
| 1068 | } |
| 1069 | |
| 1070 | if (!intel_channel_eq_ok(link_status, dp_priv->lane_count)) |
| 1071 | intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); |
| 1072 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1073 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1074 | static enum drm_connector_status |
| 1075 | igdng_dp_detect(struct drm_connector *connector) |
| 1076 | { |
| 1077 | struct intel_output *intel_output = to_intel_output(connector); |
| 1078 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 1079 | enum drm_connector_status status; |
| 1080 | |
| 1081 | status = connector_status_disconnected; |
| 1082 | if (intel_dp_aux_native_read(intel_output, |
| 1083 | 0x000, dp_priv->dpcd, |
| 1084 | sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) |
| 1085 | { |
| 1086 | if (dp_priv->dpcd[0] != 0) |
| 1087 | status = connector_status_connected; |
| 1088 | } |
| 1089 | return status; |
| 1090 | } |
| 1091 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1092 | /** |
| 1093 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. |
| 1094 | * |
| 1095 | * \return true if DP port is connected. |
| 1096 | * \return false if DP port is disconnected. |
| 1097 | */ |
| 1098 | static enum drm_connector_status |
| 1099 | intel_dp_detect(struct drm_connector *connector) |
| 1100 | { |
| 1101 | struct intel_output *intel_output = to_intel_output(connector); |
| 1102 | struct drm_device *dev = intel_output->base.dev; |
| 1103 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1104 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 1105 | uint32_t temp, bit; |
| 1106 | enum drm_connector_status status; |
| 1107 | |
| 1108 | dp_priv->has_audio = false; |
| 1109 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1110 | if (IS_IGDNG(dev)) |
| 1111 | return igdng_dp_detect(connector); |
| 1112 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1113 | temp = I915_READ(PORT_HOTPLUG_EN); |
| 1114 | |
| 1115 | I915_WRITE(PORT_HOTPLUG_EN, |
| 1116 | temp | |
| 1117 | DPB_HOTPLUG_INT_EN | |
| 1118 | DPC_HOTPLUG_INT_EN | |
| 1119 | DPD_HOTPLUG_INT_EN); |
| 1120 | |
| 1121 | POSTING_READ(PORT_HOTPLUG_EN); |
| 1122 | |
| 1123 | switch (dp_priv->output_reg) { |
| 1124 | case DP_B: |
| 1125 | bit = DPB_HOTPLUG_INT_STATUS; |
| 1126 | break; |
| 1127 | case DP_C: |
| 1128 | bit = DPC_HOTPLUG_INT_STATUS; |
| 1129 | break; |
| 1130 | case DP_D: |
| 1131 | bit = DPD_HOTPLUG_INT_STATUS; |
| 1132 | break; |
| 1133 | default: |
| 1134 | return connector_status_unknown; |
| 1135 | } |
| 1136 | |
| 1137 | temp = I915_READ(PORT_HOTPLUG_STAT); |
| 1138 | |
| 1139 | if ((temp & bit) == 0) |
| 1140 | return connector_status_disconnected; |
| 1141 | |
| 1142 | status = connector_status_disconnected; |
| 1143 | if (intel_dp_aux_native_read(intel_output, |
| 1144 | 0x000, dp_priv->dpcd, |
| 1145 | sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) |
| 1146 | { |
| 1147 | if (dp_priv->dpcd[0] != 0) |
| 1148 | status = connector_status_connected; |
| 1149 | } |
| 1150 | return status; |
| 1151 | } |
| 1152 | |
| 1153 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 1154 | { |
| 1155 | struct intel_output *intel_output = to_intel_output(connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1156 | struct drm_device *dev = intel_output->base.dev; |
| 1157 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1158 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1159 | |
| 1160 | /* We should parse the EDID data and find out if it has an audio sink |
| 1161 | */ |
| 1162 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1163 | ret = intel_ddc_get_modes(intel_output); |
| 1164 | if (ret) |
| 1165 | return ret; |
| 1166 | |
| 1167 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ |
| 1168 | if (IS_eDP(intel_output)) { |
| 1169 | if (dev_priv->panel_fixed_mode != NULL) { |
| 1170 | struct drm_display_mode *mode; |
| 1171 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
| 1172 | drm_mode_probed_add(connector, mode); |
| 1173 | return 1; |
| 1174 | } |
| 1175 | } |
| 1176 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1177 | } |
| 1178 | |
| 1179 | static void |
| 1180 | intel_dp_destroy (struct drm_connector *connector) |
| 1181 | { |
| 1182 | struct intel_output *intel_output = to_intel_output(connector); |
| 1183 | |
| 1184 | if (intel_output->i2c_bus) |
| 1185 | intel_i2c_destroy(intel_output->i2c_bus); |
| 1186 | drm_sysfs_connector_remove(connector); |
| 1187 | drm_connector_cleanup(connector); |
| 1188 | kfree(intel_output); |
| 1189 | } |
| 1190 | |
| 1191 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
| 1192 | .dpms = intel_dp_dpms, |
| 1193 | .mode_fixup = intel_dp_mode_fixup, |
| 1194 | .prepare = intel_encoder_prepare, |
| 1195 | .mode_set = intel_dp_mode_set, |
| 1196 | .commit = intel_encoder_commit, |
| 1197 | }; |
| 1198 | |
| 1199 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
| 1200 | .dpms = drm_helper_connector_dpms, |
| 1201 | .save = intel_dp_save, |
| 1202 | .restore = intel_dp_restore, |
| 1203 | .detect = intel_dp_detect, |
| 1204 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 1205 | .destroy = intel_dp_destroy, |
| 1206 | }; |
| 1207 | |
| 1208 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 1209 | .get_modes = intel_dp_get_modes, |
| 1210 | .mode_valid = intel_dp_mode_valid, |
| 1211 | .best_encoder = intel_best_encoder, |
| 1212 | }; |
| 1213 | |
| 1214 | static void intel_dp_enc_destroy(struct drm_encoder *encoder) |
| 1215 | { |
| 1216 | drm_encoder_cleanup(encoder); |
| 1217 | } |
| 1218 | |
| 1219 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
| 1220 | .destroy = intel_dp_enc_destroy, |
| 1221 | }; |
| 1222 | |
| 1223 | void |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1224 | intel_dp_hot_plug(struct intel_output *intel_output) |
| 1225 | { |
| 1226 | struct intel_dp_priv *dp_priv = intel_output->dev_priv; |
| 1227 | |
| 1228 | if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) |
| 1229 | intel_dp_check_link_status(intel_output); |
| 1230 | } |
| 1231 | |
| 1232 | void |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1233 | intel_dp_init(struct drm_device *dev, int output_reg) |
| 1234 | { |
| 1235 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1236 | struct drm_connector *connector; |
| 1237 | struct intel_output *intel_output; |
| 1238 | struct intel_dp_priv *dp_priv; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1239 | const char *name = NULL; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1240 | |
| 1241 | intel_output = kcalloc(sizeof(struct intel_output) + |
| 1242 | sizeof(struct intel_dp_priv), 1, GFP_KERNEL); |
| 1243 | if (!intel_output) |
| 1244 | return; |
| 1245 | |
| 1246 | dp_priv = (struct intel_dp_priv *)(intel_output + 1); |
| 1247 | |
| 1248 | connector = &intel_output->base; |
| 1249 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, |
| 1250 | DRM_MODE_CONNECTOR_DisplayPort); |
| 1251 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 1252 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1253 | if (output_reg == DP_A) |
| 1254 | intel_output->type = INTEL_OUTPUT_EDP; |
| 1255 | else |
| 1256 | intel_output->type = INTEL_OUTPUT_DISPLAYPORT; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1257 | |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 1258 | if (output_reg == DP_B) |
| 1259 | intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
| 1260 | else if (output_reg == DP_C) |
| 1261 | intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
| 1262 | else if (output_reg == DP_D) |
| 1263 | intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
| 1264 | |
| 1265 | if (IS_eDP(intel_output)) { |
| 1266 | intel_output->crtc_mask = (1 << 1); |
Zhenyu Wang | 7c8460d | 2009-09-08 14:52:25 +0800 | [diff] [blame] | 1267 | intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 1268 | } else |
| 1269 | intel_output->crtc_mask = (1 << 0) | (1 << 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1270 | connector->interlace_allowed = true; |
| 1271 | connector->doublescan_allowed = 0; |
| 1272 | |
| 1273 | dp_priv->intel_output = intel_output; |
| 1274 | dp_priv->output_reg = output_reg; |
| 1275 | dp_priv->has_audio = false; |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1276 | dp_priv->dpms_mode = DRM_MODE_DPMS_ON; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1277 | intel_output->dev_priv = dp_priv; |
| 1278 | |
| 1279 | drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs, |
| 1280 | DRM_MODE_ENCODER_TMDS); |
| 1281 | drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs); |
| 1282 | |
| 1283 | drm_mode_connector_attach_encoder(&intel_output->base, |
| 1284 | &intel_output->enc); |
| 1285 | drm_sysfs_connector_add(connector); |
| 1286 | |
| 1287 | /* Set up the DDC bus. */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1288 | switch (output_reg) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1289 | case DP_A: |
| 1290 | name = "DPDDC-A"; |
| 1291 | break; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1292 | case DP_B: |
| 1293 | case PCH_DP_B: |
| 1294 | name = "DPDDC-B"; |
| 1295 | break; |
| 1296 | case DP_C: |
| 1297 | case PCH_DP_C: |
| 1298 | name = "DPDDC-C"; |
| 1299 | break; |
| 1300 | case DP_D: |
| 1301 | case PCH_DP_D: |
| 1302 | name = "DPDDC-D"; |
| 1303 | break; |
| 1304 | } |
| 1305 | |
| 1306 | intel_dp_i2c_init(intel_output, name); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1307 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1308 | intel_output->ddc_bus = &dp_priv->adapter; |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1309 | intel_output->hot_plug = intel_dp_hot_plug; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1310 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1311 | if (output_reg == DP_A) { |
| 1312 | /* initialize panel mode from VBT if available for eDP */ |
| 1313 | if (dev_priv->lfp_lvds_vbt_mode) { |
| 1314 | dev_priv->panel_fixed_mode = |
| 1315 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
| 1316 | if (dev_priv->panel_fixed_mode) { |
| 1317 | dev_priv->panel_fixed_mode->type |= |
| 1318 | DRM_MODE_TYPE_PREFERRED; |
| 1319 | } |
| 1320 | } |
| 1321 | } |
| 1322 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1323 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 1324 | * 0xd. Failure to do so will result in spurious interrupts being |
| 1325 | * generated on the port when a cable is not attached. |
| 1326 | */ |
| 1327 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 1328 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 1329 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 1330 | } |
| 1331 | } |