dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 1 | /* |
| 2 | * arch/mips/emma2rh/markeins/irq.c |
| 3 | * This file defines the irq handler for EMMA2RH. |
| 4 | * |
| 5 | * Copyright (C) NEC Electronics Corporation 2004-2006 |
| 6 | * |
| 7 | * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c |
| 8 | * |
| 9 | * Copyright 2001 MontaVista Software Inc. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 24 | */ |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/irq.h> |
| 28 | #include <linux/types.h> |
| 29 | #include <linux/ptrace.h> |
| 30 | #include <linux/delay.h> |
| 31 | |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 32 | #include <asm/irq_cpu.h> |
| 33 | #include <asm/system.h> |
| 34 | #include <asm/mipsregs.h> |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 35 | #include <asm/addrspace.h> |
| 36 | #include <asm/bootinfo.h> |
| 37 | |
Shinya Kuribayashi | d91f2cb | 2008-10-24 01:30:20 +0900 | [diff] [blame] | 38 | #include <asm/emma/emma2rh.h> |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 39 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 40 | static void emma2rh_irq_enable(unsigned int irq) |
| 41 | { |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 42 | u32 reg_value; |
| 43 | u32 reg_bitmask; |
| 44 | u32 reg_index; |
| 45 | |
| 46 | irq -= EMMA2RH_IRQ_BASE; |
| 47 | |
| 48 | reg_index = EMMA2RH_BHIF_INT_EN_0 + |
| 49 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); |
| 50 | reg_value = emma2rh_in32(reg_index); |
| 51 | reg_bitmask = 0x1 << (irq % 32); |
| 52 | emma2rh_out32(reg_index, reg_value | reg_bitmask); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | static void emma2rh_irq_disable(unsigned int irq) |
| 56 | { |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 57 | u32 reg_value; |
| 58 | u32 reg_bitmask; |
| 59 | u32 reg_index; |
| 60 | |
| 61 | irq -= EMMA2RH_IRQ_BASE; |
| 62 | |
| 63 | reg_index = EMMA2RH_BHIF_INT_EN_0 + |
| 64 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); |
| 65 | reg_value = emma2rh_in32(reg_index); |
| 66 | reg_bitmask = 0x1 << (irq % 32); |
| 67 | emma2rh_out32(reg_index, reg_value & ~reg_bitmask); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | struct irq_chip emma2rh_irq_controller = { |
| 71 | .name = "emma2rh_irq", |
| 72 | .ack = emma2rh_irq_disable, |
| 73 | .mask = emma2rh_irq_disable, |
| 74 | .mask_ack = emma2rh_irq_disable, |
| 75 | .unmask = emma2rh_irq_enable, |
| 76 | }; |
| 77 | |
| 78 | void emma2rh_irq_init(void) |
| 79 | { |
| 80 | u32 i; |
| 81 | |
| 82 | for (i = 0; i < NUM_EMMA2RH_IRQ; i++) |
Shinya Kuribayashi | ae3c1d3 | 2009-03-21 22:08:12 +0900 | [diff] [blame^] | 83 | set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, |
| 84 | &emma2rh_irq_controller, |
| 85 | handle_level_irq, "level"); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 86 | } |
| 87 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 88 | static void emma2rh_sw_irq_enable(unsigned int irq) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 89 | { |
| 90 | u32 reg; |
| 91 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 92 | irq -= EMMA2RH_SW_IRQ_BASE; |
| 93 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 94 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
| 95 | reg |= 1 << irq; |
| 96 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); |
| 97 | } |
| 98 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 99 | static void emma2rh_sw_irq_disable(unsigned int irq) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 100 | { |
| 101 | u32 reg; |
| 102 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 103 | irq -= EMMA2RH_SW_IRQ_BASE; |
| 104 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 105 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
| 106 | reg &= ~(1 << irq); |
| 107 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); |
| 108 | } |
| 109 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 110 | struct irq_chip emma2rh_sw_irq_controller = { |
| 111 | .name = "emma2rh_sw_irq", |
| 112 | .ack = emma2rh_sw_irq_disable, |
| 113 | .mask = emma2rh_sw_irq_disable, |
| 114 | .mask_ack = emma2rh_sw_irq_disable, |
| 115 | .unmask = emma2rh_sw_irq_enable, |
| 116 | }; |
| 117 | |
| 118 | void emma2rh_sw_irq_init(void) |
| 119 | { |
| 120 | u32 i; |
| 121 | |
| 122 | for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) |
Shinya Kuribayashi | ae3c1d3 | 2009-03-21 22:08:12 +0900 | [diff] [blame^] | 123 | set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, |
| 124 | &emma2rh_sw_irq_controller, |
| 125 | handle_level_irq, "level"); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 126 | } |
| 127 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 128 | static void emma2rh_gpio_irq_enable(unsigned int irq) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 129 | { |
| 130 | u32 reg; |
| 131 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 132 | irq -= EMMA2RH_GPIO_IRQ_BASE; |
| 133 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 134 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 135 | reg |= 1 << irq; |
| 136 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
| 137 | } |
| 138 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 139 | static void emma2rh_gpio_irq_disable(unsigned int irq) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 140 | { |
| 141 | u32 reg; |
| 142 | |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 143 | irq -= EMMA2RH_GPIO_IRQ_BASE; |
| 144 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 145 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 146 | reg &= ~(1 << irq); |
| 147 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
| 148 | } |
| 149 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 150 | static void emma2rh_gpio_irq_ack(unsigned int irq) |
| 151 | { |
Shinya Kuribayashi | 8da55bb | 2009-03-21 22:06:14 +0900 | [diff] [blame] | 152 | irq -= EMMA2RH_GPIO_IRQ_BASE; |
| 153 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); |
| 154 | } |
| 155 | |
| 156 | static void emma2rh_gpio_irq_mask_ack(unsigned int irq) |
| 157 | { |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 158 | u32 reg; |
| 159 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 160 | irq -= EMMA2RH_GPIO_IRQ_BASE; |
| 161 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 162 | |
| 163 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 164 | reg &= ~(1 << irq); |
| 165 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 166 | } |
| 167 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 168 | struct irq_chip emma2rh_gpio_irq_controller = { |
| 169 | .name = "emma2rh_gpio_irq", |
| 170 | .ack = emma2rh_gpio_irq_ack, |
| 171 | .mask = emma2rh_gpio_irq_disable, |
Shinya Kuribayashi | 8da55bb | 2009-03-21 22:06:14 +0900 | [diff] [blame] | 172 | .mask_ack = emma2rh_gpio_irq_mask_ack, |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 173 | .unmask = emma2rh_gpio_irq_enable, |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 174 | }; |
| 175 | |
| 176 | void emma2rh_gpio_irq_init(void) |
| 177 | { |
| 178 | u32 i; |
| 179 | |
| 180 | for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) |
Shinya Kuribayashi | 8da55bb | 2009-03-21 22:06:14 +0900 | [diff] [blame] | 181 | set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, |
| 182 | &emma2rh_gpio_irq_controller, |
| 183 | handle_edge_irq, "edge"); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 184 | } |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 185 | |
| 186 | static struct irqaction irq_cascade = { |
| 187 | .handler = no_action, |
| 188 | .flags = 0, |
| 189 | .mask = CPU_MASK_NONE, |
| 190 | .name = "cascade", |
| 191 | .dev_id = NULL, |
| 192 | .next = NULL, |
| 193 | }; |
| 194 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 195 | /* |
| 196 | * the first level int-handler will jump here if it is a emma2rh irq |
| 197 | */ |
| 198 | void emma2rh_irq_dispatch(void) |
| 199 | { |
| 200 | u32 intStatus; |
| 201 | u32 bitmask; |
| 202 | u32 i; |
| 203 | |
| 204 | intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) & |
| 205 | emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); |
| 206 | |
| 207 | #ifdef EMMA2RH_SW_CASCADE |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 208 | if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) { |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 209 | u32 swIntStatus; |
| 210 | swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) |
| 211 | & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
| 212 | for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { |
| 213 | if (swIntStatus & bitmask) { |
| 214 | do_IRQ(EMMA2RH_SW_IRQ_BASE + i); |
| 215 | return; |
| 216 | } |
| 217 | } |
| 218 | } |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 219 | /* Skip S/W interrupt */ |
| 220 | intStatus &= ~(1UL << EMMA2RH_SW_CASCADE); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 221 | #endif |
| 222 | |
| 223 | for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { |
| 224 | if (intStatus & bitmask) { |
| 225 | do_IRQ(EMMA2RH_IRQ_BASE + i); |
| 226 | return; |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) & |
| 231 | emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); |
| 232 | |
| 233 | #ifdef EMMA2RH_GPIO_CASCADE |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 234 | if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) { |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 235 | u32 gpioIntStatus; |
| 236 | gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) |
| 237 | & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 238 | for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { |
| 239 | if (gpioIntStatus & bitmask) { |
| 240 | do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i); |
| 241 | return; |
| 242 | } |
| 243 | } |
| 244 | } |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 245 | /* Skip GPIO interrupt */ |
| 246 | intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32)); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 247 | #endif |
| 248 | |
| 249 | for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { |
| 250 | if (intStatus & bitmask) { |
| 251 | do_IRQ(EMMA2RH_IRQ_BASE + i); |
| 252 | return; |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) & |
| 257 | emma2rh_in32(EMMA2RH_BHIF_INT_EN_2); |
| 258 | |
| 259 | for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { |
| 260 | if (intStatus & bitmask) { |
| 261 | do_IRQ(EMMA2RH_IRQ_BASE + i); |
| 262 | return; |
| 263 | } |
| 264 | } |
| 265 | } |
| 266 | |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 267 | void __init arch_init_irq(void) |
| 268 | { |
| 269 | u32 reg; |
| 270 | |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 271 | /* by default, interrupts are disabled. */ |
| 272 | emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0); |
| 273 | emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0); |
| 274 | emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0); |
| 275 | emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0); |
| 276 | emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0); |
| 277 | emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0); |
| 278 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0); |
| 279 | |
| 280 | clear_c0_status(0xff00); |
| 281 | set_c0_status(0x0400); |
| 282 | |
| 283 | #define GPIO_PCI (0xf<<15) |
| 284 | /* setup GPIO interrupt for PCI interface */ |
| 285 | /* direction input */ |
| 286 | reg = emma2rh_in32(EMMA2RH_GPIO_DIR); |
| 287 | emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI); |
| 288 | /* disable interrupt */ |
| 289 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 290 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI); |
| 291 | /* level triggerd */ |
| 292 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE); |
| 293 | emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI); |
| 294 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A); |
| 295 | emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI)); |
| 296 | /* interrupt clear */ |
| 297 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI); |
| 298 | |
| 299 | /* init all controllers */ |
Shinya Kuribayashi | 9b6c04b | 2008-10-24 01:31:16 +0900 | [diff] [blame] | 300 | emma2rh_irq_init(); |
Shinya Kuribayashi | 68ed1ca | 2008-10-24 01:31:43 +0900 | [diff] [blame] | 301 | emma2rh_sw_irq_init(); |
Shinya Kuribayashi | fcb3cfe | 2008-10-24 01:32:11 +0900 | [diff] [blame] | 302 | emma2rh_gpio_irq_init(); |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 303 | mips_cpu_irq_init(); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 304 | |
| 305 | /* setup cascade interrupts */ |
| 306 | setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); |
| 307 | setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); |
| 308 | setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); |
| 309 | } |
| 310 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 311 | asmlinkage void plat_irq_dispatch(void) |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 312 | { |
Thiemo Seufer | 119537c | 2007-03-19 00:13:37 +0000 | [diff] [blame] | 313 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 314 | |
| 315 | if (pending & STATUSF_IP7) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 316 | do_IRQ(CPU_IRQ_BASE + 7); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 317 | else if (pending & STATUSF_IP2) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 318 | emma2rh_irq_dispatch(); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 319 | else if (pending & STATUSF_IP1) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 320 | do_IRQ(CPU_IRQ_BASE + 1); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 321 | else if (pending & STATUSF_IP0) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 322 | do_IRQ(CPU_IRQ_BASE + 0); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 323 | else |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 324 | spurious_interrupt(); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 325 | } |