Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) |
| 7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
| 8 | */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 9 | #include <linux/bitmap.h> |
Andrew Bresticker | fb8f7be1 | 2014-10-20 12:03:55 -0700 | [diff] [blame] | 10 | #include <linux/clocksource.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 11 | #include <linux/init.h> |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 12 | #include <linux/interrupt.h> |
Andrew Bresticker | fb8f7be1 | 2014-10-20 12:03:55 -0700 | [diff] [blame] | 13 | #include <linux/irq.h> |
Andrew Bresticker | 4060bbe | 2014-10-20 12:03:53 -0700 | [diff] [blame] | 14 | #include <linux/irqchip/mips-gic.h> |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 15 | #include <linux/of_address.h> |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 16 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 17 | #include <linux/smp.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 18 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 19 | #include <asm/mips-cm.h> |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 20 | #include <asm/setup.h> |
| 21 | #include <asm/traps.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 22 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 23 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 24 | |
| 25 | #include "irqchip.h" |
| 26 | |
Steven J. Hill | ff86714 | 2013-04-10 16:27:04 -0500 | [diff] [blame] | 27 | unsigned int gic_present; |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 28 | |
Jeffrey Deans | 822350b | 2014-07-17 09:20:53 +0100 | [diff] [blame] | 29 | struct gic_pcpu_mask { |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 30 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
Jeffrey Deans | 822350b | 2014-07-17 09:20:53 +0100 | [diff] [blame] | 31 | }; |
| 32 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 33 | static void __iomem *gic_base; |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 34 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 35 | static DEFINE_SPINLOCK(gic_lock); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 36 | static struct irq_domain *gic_irq_domain; |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 37 | static int gic_shared_intrs; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 38 | static int gic_vpes; |
Andrew Bresticker | 3263d08 | 2014-09-18 14:47:28 -0700 | [diff] [blame] | 39 | static unsigned int gic_cpu_pin; |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 40 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 41 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 42 | static void __gic_irq_dispatch(void); |
| 43 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 44 | static inline unsigned int gic_read(unsigned int reg) |
| 45 | { |
| 46 | return __raw_readl(gic_base + reg); |
| 47 | } |
| 48 | |
| 49 | static inline void gic_write(unsigned int reg, unsigned int val) |
| 50 | { |
| 51 | __raw_writel(val, gic_base + reg); |
| 52 | } |
| 53 | |
| 54 | static inline void gic_update_bits(unsigned int reg, unsigned int mask, |
| 55 | unsigned int val) |
| 56 | { |
| 57 | unsigned int regval; |
| 58 | |
| 59 | regval = gic_read(reg); |
| 60 | regval &= ~mask; |
| 61 | regval |= val; |
| 62 | gic_write(reg, regval); |
| 63 | } |
| 64 | |
| 65 | static inline void gic_reset_mask(unsigned int intr) |
| 66 | { |
| 67 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), |
| 68 | 1 << GIC_INTR_BIT(intr)); |
| 69 | } |
| 70 | |
| 71 | static inline void gic_set_mask(unsigned int intr) |
| 72 | { |
| 73 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), |
| 74 | 1 << GIC_INTR_BIT(intr)); |
| 75 | } |
| 76 | |
| 77 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) |
| 78 | { |
| 79 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + |
| 80 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), |
| 81 | pol << GIC_INTR_BIT(intr)); |
| 82 | } |
| 83 | |
| 84 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) |
| 85 | { |
| 86 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + |
| 87 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), |
| 88 | trig << GIC_INTR_BIT(intr)); |
| 89 | } |
| 90 | |
| 91 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) |
| 92 | { |
| 93 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), |
| 94 | 1 << GIC_INTR_BIT(intr), |
| 95 | dual << GIC_INTR_BIT(intr)); |
| 96 | } |
| 97 | |
| 98 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) |
| 99 | { |
| 100 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + |
| 101 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); |
| 102 | } |
| 103 | |
| 104 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) |
| 105 | { |
| 106 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + |
| 107 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), |
| 108 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); |
| 109 | } |
| 110 | |
Andrew Bresticker | a331ce6 | 2014-10-20 12:03:59 -0700 | [diff] [blame] | 111 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
Steven J. Hill | dfa762e | 2013-04-10 16:28:36 -0500 | [diff] [blame] | 112 | cycle_t gic_read_count(void) |
| 113 | { |
| 114 | unsigned int hi, hi2, lo; |
| 115 | |
| 116 | do { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 117 | hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
| 118 | lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); |
| 119 | hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
Steven J. Hill | dfa762e | 2013-04-10 16:28:36 -0500 | [diff] [blame] | 120 | } while (hi2 != hi); |
| 121 | |
| 122 | return (((cycle_t) hi) << 32) + lo; |
| 123 | } |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 124 | |
Andrew Bresticker | 387904f | 2014-10-20 12:03:49 -0700 | [diff] [blame] | 125 | unsigned int gic_get_count_width(void) |
| 126 | { |
| 127 | unsigned int bits, config; |
| 128 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 129 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
Andrew Bresticker | 387904f | 2014-10-20 12:03:49 -0700 | [diff] [blame] | 130 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
| 131 | GIC_SH_CONFIG_COUNTBITS_SHF); |
| 132 | |
| 133 | return bits; |
| 134 | } |
| 135 | |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 136 | void gic_write_compare(cycle_t cnt) |
| 137 | { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 138 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 139 | (int)(cnt >> 32)); |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 140 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 141 | (int)(cnt & 0xffffffff)); |
| 142 | } |
| 143 | |
Paul Burton | 414408d0 | 2014-03-05 11:35:53 +0000 | [diff] [blame] | 144 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
| 145 | { |
| 146 | unsigned long flags; |
| 147 | |
| 148 | local_irq_save(flags); |
| 149 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 150 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
| 151 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), |
Paul Burton | 414408d0 | 2014-03-05 11:35:53 +0000 | [diff] [blame] | 152 | (int)(cnt >> 32)); |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 153 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
Paul Burton | 414408d0 | 2014-03-05 11:35:53 +0000 | [diff] [blame] | 154 | (int)(cnt & 0xffffffff)); |
| 155 | |
| 156 | local_irq_restore(flags); |
| 157 | } |
| 158 | |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 159 | cycle_t gic_read_compare(void) |
| 160 | { |
| 161 | unsigned int hi, lo; |
| 162 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 163 | hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
| 164 | lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 165 | |
| 166 | return (((cycle_t) hi) << 32) + lo; |
| 167 | } |
Steven J. Hill | dfa762e | 2013-04-10 16:28:36 -0500 | [diff] [blame] | 168 | #endif |
| 169 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 170 | static bool gic_local_irq_is_routable(int intr) |
| 171 | { |
| 172 | u32 vpe_ctl; |
| 173 | |
| 174 | /* All local interrupts are routable in EIC mode. */ |
| 175 | if (cpu_has_veic) |
| 176 | return true; |
| 177 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 178 | vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 179 | switch (intr) { |
| 180 | case GIC_LOCAL_INT_TIMER: |
| 181 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; |
| 182 | case GIC_LOCAL_INT_PERFCTR: |
| 183 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; |
| 184 | case GIC_LOCAL_INT_FDC: |
| 185 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; |
| 186 | case GIC_LOCAL_INT_SWINT0: |
| 187 | case GIC_LOCAL_INT_SWINT1: |
| 188 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; |
| 189 | default: |
| 190 | return true; |
| 191 | } |
| 192 | } |
| 193 | |
Andrew Bresticker | 3263d08 | 2014-09-18 14:47:28 -0700 | [diff] [blame] | 194 | static void gic_bind_eic_interrupt(int irq, int set) |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 195 | { |
| 196 | /* Convert irq vector # to hw int # */ |
| 197 | irq -= GIC_PIN_TO_VEC_OFFSET; |
| 198 | |
| 199 | /* Set irq to use shadow set */ |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 200 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
| 201 | GIC_VPE_EIC_SS(irq), set); |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 202 | } |
| 203 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 204 | void gic_send_ipi(unsigned int intr) |
| 205 | { |
Andrew Bresticker | 53a7bc8 | 2014-10-20 12:03:57 -0700 | [diff] [blame] | 206 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 207 | } |
| 208 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 209 | int gic_get_c0_compare_int(void) |
| 210 | { |
| 211 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) |
| 212 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
| 213 | return irq_create_mapping(gic_irq_domain, |
| 214 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); |
| 215 | } |
| 216 | |
| 217 | int gic_get_c0_perfcount_int(void) |
| 218 | { |
| 219 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { |
| 220 | /* Is the erformance counter shared with the timer? */ |
| 221 | if (cp0_perfcount_irq < 0) |
| 222 | return -1; |
| 223 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
| 224 | } |
| 225 | return irq_create_mapping(gic_irq_domain, |
| 226 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); |
| 227 | } |
| 228 | |
Andrew Bresticker | 3263d08 | 2014-09-18 14:47:28 -0700 | [diff] [blame] | 229 | static unsigned int gic_get_int(void) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 230 | { |
| 231 | unsigned int i; |
Andrew Bresticker | 8f5ee79 | 2014-10-20 12:03:56 -0700 | [diff] [blame] | 232 | unsigned long *pcpu_mask; |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 233 | unsigned long pending_reg, intrmask_reg; |
Andrew Bresticker | 8f5ee79 | 2014-10-20 12:03:56 -0700 | [diff] [blame] | 234 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
| 235 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 236 | |
| 237 | /* Get per-cpu bitmaps */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 238 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
| 239 | |
Andrew Bresticker | 824f3f7 | 2014-10-20 12:03:54 -0700 | [diff] [blame] | 240 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
| 241 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 242 | |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 243 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 244 | pending[i] = gic_read(pending_reg); |
| 245 | intrmask[i] = gic_read(intrmask_reg); |
| 246 | pending_reg += 0x4; |
| 247 | intrmask_reg += 0x4; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 248 | } |
| 249 | |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 250 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
| 251 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 252 | |
Andrew Bresticker | 3263d08 | 2014-09-18 14:47:28 -0700 | [diff] [blame] | 253 | return find_first_bit(pending, gic_shared_intrs); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 254 | } |
| 255 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 256 | static void gic_mask_irq(struct irq_data *d) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 257 | { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 258 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 259 | } |
| 260 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 261 | static void gic_unmask_irq(struct irq_data *d) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 262 | { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 263 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 264 | } |
| 265 | |
Andrew Bresticker | 5561c9e | 2014-09-18 14:47:20 -0700 | [diff] [blame] | 266 | static void gic_ack_irq(struct irq_data *d) |
| 267 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 268 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 269 | |
Andrew Bresticker | 53a7bc8 | 2014-10-20 12:03:57 -0700 | [diff] [blame] | 270 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
Andrew Bresticker | 5561c9e | 2014-09-18 14:47:20 -0700 | [diff] [blame] | 271 | } |
| 272 | |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 273 | static int gic_set_type(struct irq_data *d, unsigned int type) |
| 274 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 275 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 276 | unsigned long flags; |
| 277 | bool is_edge; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 278 | |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 279 | spin_lock_irqsave(&gic_lock, flags); |
| 280 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 281 | case IRQ_TYPE_EDGE_FALLING: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 282 | gic_set_polarity(irq, GIC_POL_NEG); |
| 283 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
| 284 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 285 | is_edge = true; |
| 286 | break; |
| 287 | case IRQ_TYPE_EDGE_RISING: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 288 | gic_set_polarity(irq, GIC_POL_POS); |
| 289 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
| 290 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 291 | is_edge = true; |
| 292 | break; |
| 293 | case IRQ_TYPE_EDGE_BOTH: |
| 294 | /* polarity is irrelevant in this case */ |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 295 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
| 296 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 297 | is_edge = true; |
| 298 | break; |
| 299 | case IRQ_TYPE_LEVEL_LOW: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 300 | gic_set_polarity(irq, GIC_POL_NEG); |
| 301 | gic_set_trigger(irq, GIC_TRIG_LEVEL); |
| 302 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 303 | is_edge = false; |
| 304 | break; |
| 305 | case IRQ_TYPE_LEVEL_HIGH: |
| 306 | default: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 307 | gic_set_polarity(irq, GIC_POL_POS); |
| 308 | gic_set_trigger(irq, GIC_TRIG_LEVEL); |
| 309 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 310 | is_edge = false; |
| 311 | break; |
| 312 | } |
| 313 | |
| 314 | if (is_edge) { |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 315 | __irq_set_chip_handler_name_locked(d->irq, |
| 316 | &gic_edge_irq_controller, |
| 317 | handle_edge_irq, NULL); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 318 | } else { |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 319 | __irq_set_chip_handler_name_locked(d->irq, |
| 320 | &gic_level_irq_controller, |
| 321 | handle_level_irq, NULL); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 322 | } |
| 323 | spin_unlock_irqrestore(&gic_lock, flags); |
| 324 | |
| 325 | return 0; |
| 326 | } |
| 327 | |
| 328 | #ifdef CONFIG_SMP |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 329 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
| 330 | bool force) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 331 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 332 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 333 | cpumask_t tmp = CPU_MASK_NONE; |
| 334 | unsigned long flags; |
| 335 | int i; |
| 336 | |
Rusty Russell | 0de2652 | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 337 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 338 | if (cpus_empty(tmp)) |
Andrew Bresticker | 14d160a | 2014-09-18 14:47:22 -0700 | [diff] [blame] | 339 | return -EINVAL; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 340 | |
| 341 | /* Assumption : cpumask refers to a single CPU */ |
| 342 | spin_lock_irqsave(&gic_lock, flags); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 343 | |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 344 | /* Re-route this IRQ */ |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 345 | gic_map_to_vpe(irq, first_cpu(tmp)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 346 | |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 347 | /* Update the pcpu_masks */ |
| 348 | for (i = 0; i < NR_CPUS; i++) |
| 349 | clear_bit(irq, pcpu_masks[i].pcpu_mask); |
| 350 | set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); |
| 351 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 352 | cpumask_copy(d->affinity, cpumask); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 353 | spin_unlock_irqrestore(&gic_lock, flags); |
| 354 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 355 | return IRQ_SET_MASK_OK_NOCOPY; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 356 | } |
| 357 | #endif |
| 358 | |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 359 | static struct irq_chip gic_level_irq_controller = { |
| 360 | .name = "MIPS GIC", |
| 361 | .irq_mask = gic_mask_irq, |
| 362 | .irq_unmask = gic_unmask_irq, |
| 363 | .irq_set_type = gic_set_type, |
| 364 | #ifdef CONFIG_SMP |
| 365 | .irq_set_affinity = gic_set_affinity, |
| 366 | #endif |
| 367 | }; |
| 368 | |
| 369 | static struct irq_chip gic_edge_irq_controller = { |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 370 | .name = "MIPS GIC", |
Andrew Bresticker | 5561c9e | 2014-09-18 14:47:20 -0700 | [diff] [blame] | 371 | .irq_ack = gic_ack_irq, |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 372 | .irq_mask = gic_mask_irq, |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 373 | .irq_unmask = gic_unmask_irq, |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 374 | .irq_set_type = gic_set_type, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 375 | #ifdef CONFIG_SMP |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 376 | .irq_set_affinity = gic_set_affinity, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 377 | #endif |
| 378 | }; |
| 379 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 380 | static unsigned int gic_get_local_int(void) |
| 381 | { |
| 382 | unsigned long pending, masked; |
| 383 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 384 | pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
| 385 | masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 386 | |
| 387 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); |
| 388 | |
| 389 | return find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
| 390 | } |
| 391 | |
| 392 | static void gic_mask_local_irq(struct irq_data *d) |
| 393 | { |
| 394 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 395 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 396 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | static void gic_unmask_local_irq(struct irq_data *d) |
| 400 | { |
| 401 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 402 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 403 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | static struct irq_chip gic_local_irq_controller = { |
| 407 | .name = "MIPS GIC Local", |
| 408 | .irq_mask = gic_mask_local_irq, |
| 409 | .irq_unmask = gic_unmask_local_irq, |
| 410 | }; |
| 411 | |
| 412 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) |
| 413 | { |
| 414 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 415 | int i; |
| 416 | unsigned long flags; |
| 417 | |
| 418 | spin_lock_irqsave(&gic_lock, flags); |
| 419 | for (i = 0; i < gic_vpes; i++) { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 420 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
| 421 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 422 | } |
| 423 | spin_unlock_irqrestore(&gic_lock, flags); |
| 424 | } |
| 425 | |
| 426 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) |
| 427 | { |
| 428 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 429 | int i; |
| 430 | unsigned long flags; |
| 431 | |
| 432 | spin_lock_irqsave(&gic_lock, flags); |
| 433 | for (i = 0; i < gic_vpes; i++) { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 434 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
| 435 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 436 | } |
| 437 | spin_unlock_irqrestore(&gic_lock, flags); |
| 438 | } |
| 439 | |
| 440 | static struct irq_chip gic_all_vpes_local_irq_controller = { |
| 441 | .name = "MIPS GIC Local", |
| 442 | .irq_mask = gic_mask_local_irq_all_vpes, |
| 443 | .irq_unmask = gic_unmask_local_irq_all_vpes, |
| 444 | }; |
| 445 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 446 | static void __gic_irq_dispatch(void) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 447 | { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 448 | unsigned int intr, virq; |
| 449 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 450 | while ((intr = gic_get_local_int()) != GIC_NUM_LOCAL_INTRS) { |
| 451 | virq = irq_linear_revmap(gic_irq_domain, |
| 452 | GIC_LOCAL_TO_HWIRQ(intr)); |
| 453 | do_IRQ(virq); |
| 454 | } |
| 455 | |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 456 | while ((intr = gic_get_int()) != gic_shared_intrs) { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 457 | virq = irq_linear_revmap(gic_irq_domain, |
| 458 | GIC_SHARED_TO_HWIRQ(intr)); |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 459 | do_IRQ(virq); |
| 460 | } |
| 461 | } |
| 462 | |
| 463 | static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc) |
| 464 | { |
| 465 | __gic_irq_dispatch(); |
| 466 | } |
| 467 | |
| 468 | #ifdef CONFIG_MIPS_GIC_IPI |
| 469 | static int gic_resched_int_base; |
| 470 | static int gic_call_int_base; |
| 471 | |
| 472 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) |
| 473 | { |
| 474 | return gic_resched_int_base + cpu; |
| 475 | } |
| 476 | |
| 477 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
| 478 | { |
| 479 | return gic_call_int_base + cpu; |
| 480 | } |
| 481 | |
| 482 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
| 483 | { |
| 484 | scheduler_ipi(); |
| 485 | |
| 486 | return IRQ_HANDLED; |
| 487 | } |
| 488 | |
| 489 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) |
| 490 | { |
| 491 | smp_call_function_interrupt(); |
| 492 | |
| 493 | return IRQ_HANDLED; |
| 494 | } |
| 495 | |
| 496 | static struct irqaction irq_resched = { |
| 497 | .handler = ipi_resched_interrupt, |
| 498 | .flags = IRQF_PERCPU, |
| 499 | .name = "IPI resched" |
| 500 | }; |
| 501 | |
| 502 | static struct irqaction irq_call = { |
| 503 | .handler = ipi_call_interrupt, |
| 504 | .flags = IRQF_PERCPU, |
| 505 | .name = "IPI call" |
| 506 | }; |
| 507 | |
| 508 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, |
| 509 | struct irqaction *action) |
| 510 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 511 | int virq = irq_create_mapping(gic_irq_domain, |
| 512 | GIC_SHARED_TO_HWIRQ(intr)); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 513 | int i; |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 514 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 515 | gic_map_to_vpe(intr, cpu); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 516 | for (i = 0; i < NR_CPUS; i++) |
| 517 | clear_bit(intr, pcpu_masks[i].pcpu_mask); |
Jeffrey Deans | b0a88ae | 2014-07-17 09:20:55 +0100 | [diff] [blame] | 518 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
| 519 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 520 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
| 521 | |
| 522 | irq_set_handler(virq, handle_percpu_irq); |
| 523 | setup_irq(virq, action); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 524 | } |
| 525 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 526 | static __init void gic_ipi_init(void) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 527 | { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 528 | int i; |
| 529 | |
| 530 | /* Use last 2 * NR_CPUS interrupts as IPIs */ |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 531 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 532 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
| 533 | |
| 534 | for (i = 0; i < nr_cpu_ids; i++) { |
| 535 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); |
| 536 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); |
| 537 | } |
| 538 | } |
| 539 | #else |
| 540 | static inline void gic_ipi_init(void) |
| 541 | { |
| 542 | } |
| 543 | #endif |
| 544 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 545 | static void __init gic_basic_init(void) |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 546 | { |
| 547 | unsigned int i; |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 548 | |
| 549 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 550 | |
| 551 | /* Setup defaults */ |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 552 | for (i = 0; i < gic_shared_intrs; i++) { |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 553 | gic_set_polarity(i, GIC_POL_POS); |
| 554 | gic_set_trigger(i, GIC_TRIG_LEVEL); |
| 555 | gic_reset_mask(i); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 556 | } |
| 557 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 558 | for (i = 0; i < gic_vpes; i++) { |
| 559 | unsigned int j; |
| 560 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 561 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 562 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
| 563 | if (!gic_local_irq_is_routable(j)) |
| 564 | continue; |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 565 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 566 | } |
| 567 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 568 | } |
| 569 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 570 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
| 571 | irq_hw_number_t hw) |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 572 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 573 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
| 574 | int ret = 0; |
| 575 | int i; |
| 576 | unsigned long flags; |
| 577 | |
| 578 | if (!gic_local_irq_is_routable(intr)) |
| 579 | return -EPERM; |
| 580 | |
| 581 | /* |
| 582 | * HACK: These are all really percpu interrupts, but the rest |
| 583 | * of the MIPS kernel code does not use the percpu IRQ API for |
| 584 | * the CP0 timer and performance counter interrupts. |
| 585 | */ |
| 586 | if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) { |
| 587 | irq_set_chip_and_handler(virq, |
| 588 | &gic_local_irq_controller, |
| 589 | handle_percpu_devid_irq); |
| 590 | irq_set_percpu_devid(virq); |
| 591 | } else { |
| 592 | irq_set_chip_and_handler(virq, |
| 593 | &gic_all_vpes_local_irq_controller, |
| 594 | handle_percpu_irq); |
| 595 | } |
| 596 | |
| 597 | spin_lock_irqsave(&gic_lock, flags); |
| 598 | for (i = 0; i < gic_vpes; i++) { |
| 599 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; |
| 600 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 601 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 602 | |
| 603 | switch (intr) { |
| 604 | case GIC_LOCAL_INT_WD: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 605 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 606 | break; |
| 607 | case GIC_LOCAL_INT_COMPARE: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 608 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 609 | break; |
| 610 | case GIC_LOCAL_INT_TIMER: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 611 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 612 | break; |
| 613 | case GIC_LOCAL_INT_PERFCTR: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 614 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 615 | break; |
| 616 | case GIC_LOCAL_INT_SWINT0: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 617 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 618 | break; |
| 619 | case GIC_LOCAL_INT_SWINT1: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 620 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 621 | break; |
| 622 | case GIC_LOCAL_INT_FDC: |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 623 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 624 | break; |
| 625 | default: |
| 626 | pr_err("Invalid local IRQ %d\n", intr); |
| 627 | ret = -EINVAL; |
| 628 | break; |
| 629 | } |
| 630 | } |
| 631 | spin_unlock_irqrestore(&gic_lock, flags); |
| 632 | |
| 633 | return ret; |
| 634 | } |
| 635 | |
| 636 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, |
| 637 | irq_hw_number_t hw) |
| 638 | { |
| 639 | int intr = GIC_HWIRQ_TO_SHARED(hw); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 640 | unsigned long flags; |
| 641 | |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 642 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
| 643 | handle_level_irq); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 644 | |
| 645 | spin_lock_irqsave(&gic_lock, flags); |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 646 | gic_map_to_pin(intr, gic_cpu_pin); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 647 | /* Map to VPE 0 by default */ |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 648 | gic_map_to_vpe(intr, 0); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 649 | set_bit(intr, pcpu_masks[0].pcpu_mask); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 650 | spin_unlock_irqrestore(&gic_lock, flags); |
| 651 | |
| 652 | return 0; |
| 653 | } |
| 654 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 655 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
| 656 | irq_hw_number_t hw) |
| 657 | { |
| 658 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) |
| 659 | return gic_local_irq_domain_map(d, virq, hw); |
| 660 | return gic_shared_irq_domain_map(d, virq, hw); |
| 661 | } |
| 662 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 663 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
| 664 | const u32 *intspec, unsigned int intsize, |
| 665 | irq_hw_number_t *out_hwirq, |
| 666 | unsigned int *out_type) |
| 667 | { |
| 668 | if (intsize != 3) |
| 669 | return -EINVAL; |
| 670 | |
| 671 | if (intspec[0] == GIC_SHARED) |
| 672 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); |
| 673 | else if (intspec[0] == GIC_LOCAL) |
| 674 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); |
| 675 | else |
| 676 | return -EINVAL; |
| 677 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
| 678 | |
| 679 | return 0; |
| 680 | } |
| 681 | |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 682 | static struct irq_domain_ops gic_irq_domain_ops = { |
| 683 | .map = gic_irq_domain_map, |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 684 | .xlate = gic_irq_domain_xlate, |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 685 | }; |
| 686 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 687 | static void __init __gic_init(unsigned long gic_base_addr, |
| 688 | unsigned long gic_addrspace_size, |
| 689 | unsigned int cpu_vec, unsigned int irqbase, |
| 690 | struct device_node *node) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 691 | { |
| 692 | unsigned int gicconfig; |
| 693 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 694 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 695 | |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 696 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 697 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 698 | GIC_SH_CONFIG_NUMINTRS_SHF; |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 699 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 700 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 701 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 702 | GIC_SH_CONFIG_NUMVPES_SHF; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 703 | gic_vpes = gic_vpes + 1; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 704 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 705 | if (cpu_has_veic) { |
| 706 | /* Always use vector 1 in EIC mode */ |
| 707 | gic_cpu_pin = 0; |
| 708 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
| 709 | __gic_irq_dispatch); |
| 710 | } else { |
| 711 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; |
| 712 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, |
| 713 | gic_irq_dispatch); |
| 714 | } |
| 715 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 716 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 717 | gic_shared_intrs, irqbase, |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 718 | &gic_irq_domain_ops, NULL); |
| 719 | if (!gic_irq_domain) |
| 720 | panic("Failed to add GIC IRQ domain"); |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 721 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 722 | gic_basic_init(); |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 723 | |
| 724 | gic_ipi_init(); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 725 | } |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 726 | |
| 727 | void __init gic_init(unsigned long gic_base_addr, |
| 728 | unsigned long gic_addrspace_size, |
| 729 | unsigned int cpu_vec, unsigned int irqbase) |
| 730 | { |
| 731 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); |
| 732 | } |
| 733 | |
| 734 | static int __init gic_of_init(struct device_node *node, |
| 735 | struct device_node *parent) |
| 736 | { |
| 737 | struct resource res; |
| 738 | unsigned int cpu_vec, i = 0, reserved = 0; |
| 739 | phys_addr_t gic_base; |
| 740 | size_t gic_len; |
| 741 | |
| 742 | /* Find the first available CPU vector. */ |
| 743 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", |
| 744 | i++, &cpu_vec)) |
| 745 | reserved |= BIT(cpu_vec); |
| 746 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { |
| 747 | if (!(reserved & BIT(cpu_vec))) |
| 748 | break; |
| 749 | } |
| 750 | if (cpu_vec == 8) { |
| 751 | pr_err("No CPU vectors available for GIC\n"); |
| 752 | return -ENODEV; |
| 753 | } |
| 754 | |
| 755 | if (of_address_to_resource(node, 0, &res)) { |
| 756 | /* |
| 757 | * Probe the CM for the GIC base address if not specified |
| 758 | * in the device-tree. |
| 759 | */ |
| 760 | if (mips_cm_present()) { |
| 761 | gic_base = read_gcr_gic_base() & |
| 762 | ~CM_GCR_GIC_BASE_GICEN_MSK; |
| 763 | gic_len = 0x20000; |
| 764 | } else { |
| 765 | pr_err("Failed to get GIC memory range\n"); |
| 766 | return -ENODEV; |
| 767 | } |
| 768 | } else { |
| 769 | gic_base = res.start; |
| 770 | gic_len = resource_size(&res); |
| 771 | } |
| 772 | |
| 773 | if (mips_cm_present()) |
| 774 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); |
| 775 | gic_present = true; |
| 776 | |
| 777 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |