Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * pinmux driver for CSR SiRFprimaII |
| 3 | * |
| 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
| 5 | * |
| 6 | * Licensed under GPLv2 or later. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/platform_device.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/pinctrl/pinctrl.h> |
| 16 | #include <linux/pinctrl/pinmux.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_address.h> |
| 19 | #include <linux/of_device.h> |
| 20 | #include <linux/of_platform.h> |
| 21 | #include <linux/bitops.h> |
| 22 | |
| 23 | #define DRIVER_NAME "pinmux-sirf" |
| 24 | |
| 25 | #define SIRFSOC_NUM_PADS 622 |
| 26 | #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) |
| 27 | #define SIRFSOC_RSC_PIN_MUX 0x4 |
| 28 | |
| 29 | /* |
| 30 | * pad list for the pinmux subsystem |
| 31 | * refer to CS-131858-DC-6A.xls |
| 32 | */ |
Stephen Warren | 25aec32 | 2011-10-19 16:19:26 -0600 | [diff] [blame] | 33 | static const struct pinctrl_pin_desc sirfsoc_pads[] = { |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 34 | PINCTRL_PIN(4, "pwm0"), |
| 35 | PINCTRL_PIN(5, "pwm1"), |
| 36 | PINCTRL_PIN(6, "pwm2"), |
| 37 | PINCTRL_PIN(7, "pwm3"), |
| 38 | PINCTRL_PIN(8, "warm_rst_b"), |
| 39 | PINCTRL_PIN(9, "odo_0"), |
| 40 | PINCTRL_PIN(10, "odo_1"), |
| 41 | PINCTRL_PIN(11, "dr_dir"), |
| 42 | PINCTRL_PIN(13, "scl_1"), |
| 43 | PINCTRL_PIN(15, "sda_1"), |
| 44 | PINCTRL_PIN(16, "x_ldd[16]"), |
| 45 | PINCTRL_PIN(17, "x_ldd[17]"), |
| 46 | PINCTRL_PIN(18, "x_ldd[18]"), |
| 47 | PINCTRL_PIN(19, "x_ldd[19]"), |
| 48 | PINCTRL_PIN(20, "x_ldd[20]"), |
| 49 | PINCTRL_PIN(21, "x_ldd[21]"), |
| 50 | PINCTRL_PIN(22, "x_ldd[22]"), |
| 51 | PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"), |
| 52 | PINCTRL_PIN(24, "gps_sgn"), |
| 53 | PINCTRL_PIN(25, "gps_mag"), |
| 54 | PINCTRL_PIN(26, "gps_clk"), |
| 55 | PINCTRL_PIN(27, "sd_cd_b_1"), |
| 56 | PINCTRL_PIN(28, "sd_vcc_on_1"), |
| 57 | PINCTRL_PIN(29, "sd_wp_b_1"), |
| 58 | PINCTRL_PIN(30, "sd_clk_3"), |
| 59 | PINCTRL_PIN(31, "sd_cmd_3"), |
| 60 | |
| 61 | PINCTRL_PIN(32, "x_sd_dat_3[0]"), |
| 62 | PINCTRL_PIN(33, "x_sd_dat_3[1]"), |
| 63 | PINCTRL_PIN(34, "x_sd_dat_3[2]"), |
| 64 | PINCTRL_PIN(35, "x_sd_dat_3[3]"), |
| 65 | PINCTRL_PIN(36, "x_sd_clk_4"), |
| 66 | PINCTRL_PIN(37, "x_sd_cmd_4"), |
| 67 | PINCTRL_PIN(38, "x_sd_dat_4[0]"), |
| 68 | PINCTRL_PIN(39, "x_sd_dat_4[1]"), |
| 69 | PINCTRL_PIN(40, "x_sd_dat_4[2]"), |
| 70 | PINCTRL_PIN(41, "x_sd_dat_4[3]"), |
| 71 | PINCTRL_PIN(42, "x_cko_1"), |
| 72 | PINCTRL_PIN(43, "x_ac97_bit_clk"), |
| 73 | PINCTRL_PIN(44, "x_ac97_dout"), |
| 74 | PINCTRL_PIN(45, "x_ac97_din"), |
| 75 | PINCTRL_PIN(46, "x_ac97_sync"), |
| 76 | PINCTRL_PIN(47, "x_txd_1"), |
| 77 | PINCTRL_PIN(48, "x_txd_2"), |
| 78 | PINCTRL_PIN(49, "x_rxd_1"), |
| 79 | PINCTRL_PIN(50, "x_rxd_2"), |
| 80 | PINCTRL_PIN(51, "x_usclk_0"), |
| 81 | PINCTRL_PIN(52, "x_utxd_0"), |
| 82 | PINCTRL_PIN(53, "x_urxd_0"), |
| 83 | PINCTRL_PIN(54, "x_utfs_0"), |
| 84 | PINCTRL_PIN(55, "x_urfs_0"), |
| 85 | PINCTRL_PIN(56, "x_usclk_1"), |
| 86 | PINCTRL_PIN(57, "x_utxd_1"), |
| 87 | PINCTRL_PIN(58, "x_urxd_1"), |
| 88 | PINCTRL_PIN(59, "x_utfs_1"), |
| 89 | PINCTRL_PIN(60, "x_urfs_1"), |
| 90 | PINCTRL_PIN(61, "x_usclk_2"), |
| 91 | PINCTRL_PIN(62, "x_utxd_2"), |
| 92 | PINCTRL_PIN(63, "x_urxd_2"), |
| 93 | |
| 94 | PINCTRL_PIN(64, "x_utfs_2"), |
| 95 | PINCTRL_PIN(65, "x_urfs_2"), |
| 96 | PINCTRL_PIN(66, "x_df_we_b"), |
| 97 | PINCTRL_PIN(67, "x_df_re_b"), |
| 98 | PINCTRL_PIN(68, "x_txd_0"), |
| 99 | PINCTRL_PIN(69, "x_rxd_0"), |
| 100 | PINCTRL_PIN(78, "x_cko_0"), |
| 101 | PINCTRL_PIN(79, "x_vip_pxd[7]"), |
| 102 | PINCTRL_PIN(80, "x_vip_pxd[6]"), |
| 103 | PINCTRL_PIN(81, "x_vip_pxd[5]"), |
| 104 | PINCTRL_PIN(82, "x_vip_pxd[4]"), |
| 105 | PINCTRL_PIN(83, "x_vip_pxd[3]"), |
| 106 | PINCTRL_PIN(84, "x_vip_pxd[2]"), |
| 107 | PINCTRL_PIN(85, "x_vip_pxd[1]"), |
| 108 | PINCTRL_PIN(86, "x_vip_pxd[0]"), |
| 109 | PINCTRL_PIN(87, "x_vip_vsync"), |
| 110 | PINCTRL_PIN(88, "x_vip_hsync"), |
| 111 | PINCTRL_PIN(89, "x_vip_pxclk"), |
| 112 | PINCTRL_PIN(90, "x_sda_0"), |
| 113 | PINCTRL_PIN(91, "x_scl_0"), |
| 114 | PINCTRL_PIN(92, "x_df_ry_by"), |
| 115 | PINCTRL_PIN(93, "x_df_cs_b[1]"), |
| 116 | PINCTRL_PIN(94, "x_df_cs_b[0]"), |
| 117 | PINCTRL_PIN(95, "x_l_pclk"), |
| 118 | |
| 119 | PINCTRL_PIN(96, "x_l_lck"), |
| 120 | PINCTRL_PIN(97, "x_l_fck"), |
| 121 | PINCTRL_PIN(98, "x_l_de"), |
| 122 | PINCTRL_PIN(99, "x_ldd[0]"), |
| 123 | PINCTRL_PIN(100, "x_ldd[1]"), |
| 124 | PINCTRL_PIN(101, "x_ldd[2]"), |
| 125 | PINCTRL_PIN(102, "x_ldd[3]"), |
| 126 | PINCTRL_PIN(103, "x_ldd[4]"), |
| 127 | PINCTRL_PIN(104, "x_ldd[5]"), |
| 128 | PINCTRL_PIN(105, "x_ldd[6]"), |
| 129 | PINCTRL_PIN(106, "x_ldd[7]"), |
| 130 | PINCTRL_PIN(107, "x_ldd[8]"), |
| 131 | PINCTRL_PIN(108, "x_ldd[9]"), |
| 132 | PINCTRL_PIN(109, "x_ldd[10]"), |
| 133 | PINCTRL_PIN(110, "x_ldd[11]"), |
| 134 | PINCTRL_PIN(111, "x_ldd[12]"), |
| 135 | PINCTRL_PIN(112, "x_ldd[13]"), |
| 136 | PINCTRL_PIN(113, "x_ldd[14]"), |
| 137 | PINCTRL_PIN(114, "x_ldd[15]"), |
| 138 | }; |
| 139 | |
| 140 | /** |
| 141 | * @dev: a pointer back to containing device |
| 142 | * @virtbase: the offset to the controller in virtual memory |
| 143 | */ |
| 144 | struct sirfsoc_pmx { |
| 145 | struct device *dev; |
| 146 | struct pinctrl_dev *pmx; |
| 147 | void __iomem *gpio_virtbase; |
| 148 | void __iomem *rsc_virtbase; |
| 149 | }; |
| 150 | |
| 151 | /* SIRFSOC_GPIO_PAD_EN set */ |
| 152 | struct sirfsoc_muxmask { |
| 153 | unsigned long group; |
| 154 | unsigned long mask; |
| 155 | }; |
| 156 | |
| 157 | struct sirfsoc_padmux { |
| 158 | unsigned long muxmask_counts; |
| 159 | const struct sirfsoc_muxmask *muxmask; |
| 160 | /* RSC_PIN_MUX set */ |
| 161 | unsigned long funcmask; |
| 162 | unsigned long funcval; |
| 163 | }; |
| 164 | |
| 165 | /** |
| 166 | * struct sirfsoc_pin_group - describes a SiRFprimaII pin group |
| 167 | * @name: the name of this specific pin group |
| 168 | * @pins: an array of discrete physical pins used in this group, taken |
| 169 | * from the driver-local pin enumeration space |
| 170 | * @num_pins: the number of pins in this group array, i.e. the number of |
| 171 | * elements in .pins so we can iterate over that array |
| 172 | */ |
| 173 | struct sirfsoc_pin_group { |
| 174 | const char *name; |
| 175 | const unsigned int *pins; |
| 176 | const unsigned num_pins; |
| 177 | }; |
| 178 | |
| 179 | static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { |
| 180 | { |
| 181 | .group = 3, |
| 182 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | |
| 183 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | |
| 184 | BIT(17) | BIT(18), |
| 185 | }, { |
| 186 | .group = 2, |
| 187 | .mask = BIT(31), |
| 188 | }, |
| 189 | }; |
| 190 | |
| 191 | static const struct sirfsoc_padmux lcd_16bits_padmux = { |
| 192 | .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), |
| 193 | .muxmask = lcd_16bits_sirfsoc_muxmask, |
| 194 | .funcmask = BIT(4), |
| 195 | .funcval = 0, |
| 196 | }; |
| 197 | |
| 198 | static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, |
| 199 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; |
| 200 | |
| 201 | static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { |
| 202 | { |
| 203 | .group = 3, |
| 204 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | |
| 205 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | |
| 206 | BIT(17) | BIT(18), |
| 207 | }, { |
| 208 | .group = 2, |
| 209 | .mask = BIT(31), |
| 210 | }, { |
| 211 | .group = 0, |
| 212 | .mask = BIT(16) | BIT(17), |
| 213 | }, |
| 214 | }; |
| 215 | |
| 216 | static const struct sirfsoc_padmux lcd_18bits_padmux = { |
| 217 | .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), |
| 218 | .muxmask = lcd_18bits_muxmask, |
| 219 | .funcmask = BIT(4), |
| 220 | .funcval = 0, |
| 221 | }; |
| 222 | |
| 223 | static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, |
| 224 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; |
| 225 | |
| 226 | static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { |
| 227 | { |
| 228 | .group = 3, |
| 229 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | |
| 230 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | |
| 231 | BIT(17) | BIT(18), |
| 232 | }, { |
| 233 | .group = 2, |
| 234 | .mask = BIT(31), |
| 235 | }, { |
| 236 | .group = 0, |
| 237 | .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | static const struct sirfsoc_padmux lcd_24bits_padmux = { |
| 242 | .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), |
| 243 | .muxmask = lcd_24bits_muxmask, |
| 244 | .funcmask = BIT(4), |
| 245 | .funcval = 0, |
| 246 | }; |
| 247 | |
| 248 | static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, |
| 249 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; |
| 250 | |
| 251 | static const struct sirfsoc_muxmask lcdrom_muxmask[] = { |
| 252 | { |
| 253 | .group = 3, |
| 254 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | |
| 255 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | |
| 256 | BIT(17) | BIT(18), |
| 257 | }, { |
| 258 | .group = 2, |
| 259 | .mask = BIT(31), |
| 260 | }, { |
| 261 | .group = 0, |
| 262 | .mask = BIT(23), |
| 263 | }, |
| 264 | }; |
| 265 | |
| 266 | static const struct sirfsoc_padmux lcdrom_padmux = { |
| 267 | .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), |
| 268 | .muxmask = lcdrom_muxmask, |
| 269 | .funcmask = BIT(4), |
| 270 | .funcval = BIT(4), |
| 271 | }; |
| 272 | |
| 273 | static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, |
| 274 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; |
| 275 | |
| 276 | static const struct sirfsoc_muxmask uart0_muxmask[] = { |
| 277 | { |
| 278 | .group = 2, |
| 279 | .mask = BIT(4) | BIT(5), |
| 280 | }, { |
| 281 | .group = 1, |
| 282 | .mask = BIT(23) | BIT(28), |
| 283 | }, |
| 284 | }; |
| 285 | |
| 286 | static const struct sirfsoc_padmux uart0_padmux = { |
| 287 | .muxmask_counts = ARRAY_SIZE(uart0_muxmask), |
| 288 | .muxmask = uart0_muxmask, |
| 289 | .funcmask = BIT(9), |
| 290 | .funcval = BIT(9), |
| 291 | }; |
| 292 | |
| 293 | static const unsigned uart0_pins[] = { 55, 60, 68, 69 }; |
| 294 | |
| 295 | static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { |
| 296 | { |
| 297 | .group = 2, |
| 298 | .mask = BIT(4) | BIT(5), |
| 299 | }, |
| 300 | }; |
| 301 | |
| 302 | static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { |
| 303 | .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), |
| 304 | .muxmask = uart0_nostreamctrl_muxmask, |
| 305 | }; |
| 306 | |
| 307 | static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; |
| 308 | |
| 309 | static const struct sirfsoc_muxmask uart1_muxmask[] = { |
| 310 | { |
| 311 | .group = 1, |
| 312 | .mask = BIT(15) | BIT(17), |
| 313 | }, |
| 314 | }; |
| 315 | |
| 316 | static const struct sirfsoc_padmux uart1_padmux = { |
| 317 | .muxmask_counts = ARRAY_SIZE(uart1_muxmask), |
| 318 | .muxmask = uart1_muxmask, |
| 319 | }; |
| 320 | |
| 321 | static const unsigned uart1_pins[] = { 47, 49 }; |
| 322 | |
| 323 | static const struct sirfsoc_muxmask uart2_muxmask[] = { |
| 324 | { |
| 325 | .group = 1, |
| 326 | .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), |
| 327 | }, |
| 328 | }; |
| 329 | |
| 330 | static const struct sirfsoc_padmux uart2_padmux = { |
| 331 | .muxmask_counts = ARRAY_SIZE(uart2_muxmask), |
| 332 | .muxmask = uart2_muxmask, |
| 333 | .funcmask = BIT(10), |
| 334 | .funcval = BIT(10), |
| 335 | }; |
| 336 | |
| 337 | static const unsigned uart2_pins[] = { 48, 50, 56, 59 }; |
| 338 | |
| 339 | static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { |
| 340 | { |
| 341 | .group = 1, |
| 342 | .mask = BIT(16) | BIT(18), |
| 343 | }, |
| 344 | }; |
| 345 | |
| 346 | static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { |
| 347 | .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), |
| 348 | .muxmask = uart2_nostreamctrl_muxmask, |
| 349 | }; |
| 350 | |
| 351 | static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; |
| 352 | |
| 353 | static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { |
| 354 | { |
| 355 | .group = 0, |
| 356 | .mask = BIT(30) | BIT(31), |
| 357 | }, { |
| 358 | .group = 1, |
| 359 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), |
| 360 | }, |
| 361 | }; |
| 362 | |
| 363 | static const struct sirfsoc_padmux sdmmc3_padmux = { |
| 364 | .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), |
| 365 | .muxmask = sdmmc3_muxmask, |
| 366 | .funcmask = BIT(7), |
| 367 | .funcval = 0, |
| 368 | }; |
| 369 | |
| 370 | static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; |
| 371 | |
| 372 | static const struct sirfsoc_muxmask spi0_muxmask[] = { |
| 373 | { |
| 374 | .group = 1, |
| 375 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), |
| 376 | }, |
| 377 | }; |
| 378 | |
| 379 | static const struct sirfsoc_padmux spi0_padmux = { |
| 380 | .muxmask_counts = ARRAY_SIZE(spi0_muxmask), |
| 381 | .muxmask = spi0_muxmask, |
| 382 | .funcmask = BIT(7), |
| 383 | .funcval = BIT(7), |
| 384 | }; |
| 385 | |
| 386 | static const unsigned spi0_pins[] = { 32, 33, 34, 35 }; |
| 387 | |
| 388 | static const struct sirfsoc_muxmask sdmmc4_muxmask[] = { |
| 389 | { |
| 390 | .group = 1, |
| 391 | .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), |
| 392 | }, |
| 393 | }; |
| 394 | |
| 395 | static const struct sirfsoc_padmux sdmmc4_padmux = { |
| 396 | .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask), |
| 397 | .muxmask = sdmmc4_muxmask, |
| 398 | }; |
| 399 | |
| 400 | static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 }; |
| 401 | |
| 402 | static const struct sirfsoc_muxmask cko1_muxmask[] = { |
| 403 | { |
| 404 | .group = 1, |
| 405 | .mask = BIT(10), |
| 406 | }, |
| 407 | }; |
| 408 | |
| 409 | static const struct sirfsoc_padmux cko1_padmux = { |
| 410 | .muxmask_counts = ARRAY_SIZE(cko1_muxmask), |
| 411 | .muxmask = cko1_muxmask, |
| 412 | .funcmask = BIT(3), |
| 413 | .funcval = 0, |
| 414 | }; |
| 415 | |
| 416 | static const unsigned cko1_pins[] = { 42 }; |
| 417 | |
| 418 | static const struct sirfsoc_muxmask i2s_muxmask[] = { |
| 419 | { |
| 420 | .group = 1, |
| 421 | .mask = |
| 422 | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19) |
| 423 | | BIT(23) | BIT(28), |
| 424 | }, |
| 425 | }; |
| 426 | |
| 427 | static const struct sirfsoc_padmux i2s_padmux = { |
| 428 | .muxmask_counts = ARRAY_SIZE(i2s_muxmask), |
| 429 | .muxmask = i2s_muxmask, |
| 430 | .funcmask = BIT(3) | BIT(9), |
| 431 | .funcval = BIT(3), |
| 432 | }; |
| 433 | |
| 434 | static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; |
| 435 | |
| 436 | static const struct sirfsoc_muxmask ac97_muxmask[] = { |
| 437 | { |
| 438 | .group = 1, |
| 439 | .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), |
| 440 | }, |
| 441 | }; |
| 442 | |
| 443 | static const struct sirfsoc_padmux ac97_padmux = { |
| 444 | .muxmask_counts = ARRAY_SIZE(ac97_muxmask), |
| 445 | .muxmask = ac97_muxmask, |
| 446 | .funcmask = BIT(8), |
| 447 | .funcval = 0, |
| 448 | }; |
| 449 | |
| 450 | static const unsigned ac97_pins[] = { 33, 34, 35, 36 }; |
| 451 | |
| 452 | static const struct sirfsoc_muxmask spi1_muxmask[] = { |
| 453 | { |
| 454 | .group = 1, |
| 455 | .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), |
| 456 | }, |
| 457 | }; |
| 458 | |
| 459 | static const struct sirfsoc_padmux spi1_padmux = { |
| 460 | .muxmask_counts = ARRAY_SIZE(spi1_muxmask), |
| 461 | .muxmask = spi1_muxmask, |
| 462 | .funcmask = BIT(8), |
| 463 | .funcval = BIT(8), |
| 464 | }; |
| 465 | |
Barry Song | f59d28d | 2011-12-02 10:32:15 +0800 | [diff] [blame] | 466 | static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 467 | |
| 468 | static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { |
| 469 | { |
| 470 | .group = 0, |
| 471 | .mask = BIT(27) | BIT(28) | BIT(29), |
| 472 | }, |
| 473 | }; |
| 474 | |
| 475 | static const struct sirfsoc_padmux sdmmc1_padmux = { |
| 476 | .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), |
| 477 | .muxmask = sdmmc1_muxmask, |
| 478 | }; |
| 479 | |
| 480 | static const unsigned sdmmc1_pins[] = { 27, 28, 29 }; |
| 481 | |
| 482 | static const struct sirfsoc_muxmask gps_muxmask[] = { |
| 483 | { |
| 484 | .group = 0, |
| 485 | .mask = BIT(24) | BIT(25) | BIT(26), |
| 486 | }, |
| 487 | }; |
| 488 | |
| 489 | static const struct sirfsoc_padmux gps_padmux = { |
| 490 | .muxmask_counts = ARRAY_SIZE(gps_muxmask), |
| 491 | .muxmask = gps_muxmask, |
| 492 | .funcmask = BIT(12) | BIT(13) | BIT(14), |
| 493 | .funcval = BIT(12), |
| 494 | }; |
| 495 | |
| 496 | static const unsigned gps_pins[] = { 24, 25, 26 }; |
| 497 | |
| 498 | static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { |
| 499 | { |
| 500 | .group = 0, |
| 501 | .mask = BIT(24) | BIT(25) | BIT(26), |
| 502 | }, { |
| 503 | .group = 1, |
| 504 | .mask = BIT(29), |
| 505 | }, { |
| 506 | .group = 2, |
| 507 | .mask = BIT(0) | BIT(1), |
| 508 | }, |
| 509 | }; |
| 510 | |
| 511 | static const struct sirfsoc_padmux sdmmc5_padmux = { |
| 512 | .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), |
| 513 | .muxmask = sdmmc5_muxmask, |
| 514 | .funcmask = BIT(13) | BIT(14), |
| 515 | .funcval = BIT(13) | BIT(14), |
| 516 | }; |
| 517 | |
| 518 | static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 }; |
| 519 | |
| 520 | static const struct sirfsoc_muxmask usp0_muxmask[] = { |
| 521 | { |
| 522 | .group = 1, |
| 523 | .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), |
| 524 | }, |
| 525 | }; |
| 526 | |
| 527 | static const struct sirfsoc_padmux usp0_padmux = { |
| 528 | .muxmask_counts = ARRAY_SIZE(usp0_muxmask), |
| 529 | .muxmask = usp0_muxmask, |
| 530 | .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), |
| 531 | .funcval = 0, |
| 532 | }; |
| 533 | |
| 534 | static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; |
| 535 | |
| 536 | static const struct sirfsoc_muxmask usp1_muxmask[] = { |
| 537 | { |
| 538 | .group = 1, |
| 539 | .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), |
| 540 | }, |
| 541 | }; |
| 542 | |
| 543 | static const struct sirfsoc_padmux usp1_padmux = { |
| 544 | .muxmask_counts = ARRAY_SIZE(usp1_muxmask), |
| 545 | .muxmask = usp1_muxmask, |
| 546 | .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), |
| 547 | .funcval = 0, |
| 548 | }; |
| 549 | |
| 550 | static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; |
| 551 | |
| 552 | static const struct sirfsoc_muxmask usp2_muxmask[] = { |
| 553 | { |
| 554 | .group = 1, |
| 555 | .mask = BIT(29) | BIT(30) | BIT(31), |
| 556 | }, { |
| 557 | .group = 2, |
| 558 | .mask = BIT(0) | BIT(1), |
| 559 | }, |
| 560 | }; |
| 561 | |
| 562 | static const struct sirfsoc_padmux usp2_padmux = { |
| 563 | .muxmask_counts = ARRAY_SIZE(usp2_muxmask), |
| 564 | .muxmask = usp2_muxmask, |
| 565 | .funcmask = BIT(13) | BIT(14), |
| 566 | .funcval = 0, |
| 567 | }; |
| 568 | |
| 569 | static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; |
| 570 | |
| 571 | static const struct sirfsoc_muxmask nand_muxmask[] = { |
| 572 | { |
| 573 | .group = 2, |
| 574 | .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), |
| 575 | }, |
| 576 | }; |
| 577 | |
| 578 | static const struct sirfsoc_padmux nand_padmux = { |
| 579 | .muxmask_counts = ARRAY_SIZE(nand_muxmask), |
| 580 | .muxmask = nand_muxmask, |
| 581 | .funcmask = BIT(5), |
| 582 | .funcval = 0, |
| 583 | }; |
| 584 | |
| 585 | static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; |
| 586 | |
| 587 | static const struct sirfsoc_padmux sdmmc0_padmux = { |
| 588 | .muxmask_counts = 0, |
| 589 | .funcmask = BIT(5), |
| 590 | .funcval = 0, |
| 591 | }; |
| 592 | |
| 593 | static const unsigned sdmmc0_pins[] = { }; |
| 594 | |
| 595 | static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { |
| 596 | { |
| 597 | .group = 2, |
| 598 | .mask = BIT(2) | BIT(3), |
| 599 | }, |
| 600 | }; |
| 601 | |
| 602 | static const struct sirfsoc_padmux sdmmc2_padmux = { |
| 603 | .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), |
| 604 | .muxmask = sdmmc2_muxmask, |
| 605 | .funcmask = BIT(5), |
| 606 | .funcval = BIT(5), |
| 607 | }; |
| 608 | |
| 609 | static const unsigned sdmmc2_pins[] = { 66, 67 }; |
| 610 | |
| 611 | static const struct sirfsoc_muxmask cko0_muxmask[] = { |
| 612 | { |
| 613 | .group = 2, |
| 614 | .mask = BIT(14), |
| 615 | }, |
| 616 | }; |
| 617 | |
| 618 | static const struct sirfsoc_padmux cko0_padmux = { |
| 619 | .muxmask_counts = ARRAY_SIZE(cko0_muxmask), |
| 620 | .muxmask = cko0_muxmask, |
| 621 | }; |
| 622 | |
| 623 | static const unsigned cko0_pins[] = { 78 }; |
| 624 | |
| 625 | static const struct sirfsoc_muxmask vip_muxmask[] = { |
| 626 | { |
| 627 | .group = 2, |
| 628 | .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
| 629 | | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | |
| 630 | BIT(25), |
| 631 | }, |
| 632 | }; |
| 633 | |
| 634 | static const struct sirfsoc_padmux vip_padmux = { |
| 635 | .muxmask_counts = ARRAY_SIZE(vip_muxmask), |
| 636 | .muxmask = vip_muxmask, |
| 637 | .funcmask = BIT(0), |
| 638 | .funcval = 0, |
| 639 | }; |
| 640 | |
| 641 | static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; |
| 642 | |
| 643 | static const struct sirfsoc_muxmask i2c0_muxmask[] = { |
| 644 | { |
| 645 | .group = 2, |
| 646 | .mask = BIT(26) | BIT(27), |
| 647 | }, |
| 648 | }; |
| 649 | |
| 650 | static const struct sirfsoc_padmux i2c0_padmux = { |
| 651 | .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), |
| 652 | .muxmask = i2c0_muxmask, |
| 653 | }; |
| 654 | |
| 655 | static const unsigned i2c0_pins[] = { 90, 91 }; |
| 656 | |
| 657 | static const struct sirfsoc_muxmask i2c1_muxmask[] = { |
| 658 | { |
| 659 | .group = 0, |
| 660 | .mask = BIT(13) | BIT(15), |
| 661 | }, |
| 662 | }; |
| 663 | |
| 664 | static const struct sirfsoc_padmux i2c1_padmux = { |
| 665 | .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), |
| 666 | .muxmask = i2c1_muxmask, |
| 667 | }; |
| 668 | |
| 669 | static const unsigned i2c1_pins[] = { 13, 15 }; |
| 670 | |
| 671 | static const struct sirfsoc_muxmask viprom_muxmask[] = { |
| 672 | { |
| 673 | .group = 2, |
| 674 | .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
| 675 | | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | |
| 676 | BIT(25), |
| 677 | }, { |
| 678 | .group = 0, |
| 679 | .mask = BIT(12), |
| 680 | }, |
| 681 | }; |
| 682 | |
| 683 | static const struct sirfsoc_padmux viprom_padmux = { |
| 684 | .muxmask_counts = ARRAY_SIZE(viprom_muxmask), |
| 685 | .muxmask = viprom_muxmask, |
| 686 | .funcmask = BIT(0), |
| 687 | .funcval = BIT(0), |
| 688 | }; |
| 689 | |
| 690 | static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; |
| 691 | |
| 692 | static const struct sirfsoc_muxmask pwm0_muxmask[] = { |
| 693 | { |
| 694 | .group = 0, |
| 695 | .mask = BIT(4), |
| 696 | }, |
| 697 | }; |
| 698 | |
| 699 | static const struct sirfsoc_padmux pwm0_padmux = { |
| 700 | .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), |
| 701 | .muxmask = pwm0_muxmask, |
| 702 | .funcmask = BIT(12), |
| 703 | .funcval = 0, |
| 704 | }; |
| 705 | |
| 706 | static const unsigned pwm0_pins[] = { 4 }; |
| 707 | |
| 708 | static const struct sirfsoc_muxmask pwm1_muxmask[] = { |
| 709 | { |
| 710 | .group = 0, |
| 711 | .mask = BIT(5), |
| 712 | }, |
| 713 | }; |
| 714 | |
| 715 | static const struct sirfsoc_padmux pwm1_padmux = { |
| 716 | .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), |
| 717 | .muxmask = pwm1_muxmask, |
| 718 | }; |
| 719 | |
| 720 | static const unsigned pwm1_pins[] = { 5 }; |
| 721 | |
| 722 | static const struct sirfsoc_muxmask pwm2_muxmask[] = { |
| 723 | { |
| 724 | .group = 0, |
| 725 | .mask = BIT(6), |
| 726 | }, |
| 727 | }; |
| 728 | |
| 729 | static const struct sirfsoc_padmux pwm2_padmux = { |
| 730 | .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), |
| 731 | .muxmask = pwm2_muxmask, |
| 732 | }; |
| 733 | |
| 734 | static const unsigned pwm2_pins[] = { 6 }; |
| 735 | |
| 736 | static const struct sirfsoc_muxmask pwm3_muxmask[] = { |
| 737 | { |
| 738 | .group = 0, |
| 739 | .mask = BIT(7), |
| 740 | }, |
| 741 | }; |
| 742 | |
| 743 | static const struct sirfsoc_padmux pwm3_padmux = { |
| 744 | .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), |
| 745 | .muxmask = pwm3_muxmask, |
| 746 | }; |
| 747 | |
| 748 | static const unsigned pwm3_pins[] = { 7 }; |
| 749 | |
| 750 | static const struct sirfsoc_muxmask warm_rst_muxmask[] = { |
| 751 | { |
| 752 | .group = 0, |
| 753 | .mask = BIT(8), |
| 754 | }, |
| 755 | }; |
| 756 | |
| 757 | static const struct sirfsoc_padmux warm_rst_padmux = { |
| 758 | .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), |
| 759 | .muxmask = warm_rst_muxmask, |
| 760 | }; |
| 761 | |
| 762 | static const unsigned warm_rst_pins[] = { 8 }; |
| 763 | |
| 764 | static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { |
| 765 | { |
| 766 | .group = 1, |
| 767 | .mask = BIT(22), |
| 768 | }, |
| 769 | }; |
| 770 | static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { |
| 771 | .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), |
| 772 | .muxmask = usb0_utmi_drvbus_muxmask, |
| 773 | .funcmask = BIT(6), |
| 774 | .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ |
| 775 | }; |
| 776 | |
| 777 | static const unsigned usb0_utmi_drvbus_pins[] = { 54 }; |
| 778 | |
| 779 | static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { |
| 780 | { |
| 781 | .group = 1, |
| 782 | .mask = BIT(27), |
| 783 | }, |
| 784 | }; |
| 785 | |
| 786 | static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { |
| 787 | .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), |
| 788 | .muxmask = usb1_utmi_drvbus_muxmask, |
| 789 | .funcmask = BIT(11), |
| 790 | .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ |
| 791 | }; |
| 792 | |
| 793 | static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; |
| 794 | |
| 795 | static const struct sirfsoc_muxmask pulse_count_muxmask[] = { |
| 796 | { |
| 797 | .group = 0, |
| 798 | .mask = BIT(9) | BIT(10) | BIT(11), |
| 799 | }, |
| 800 | }; |
| 801 | |
| 802 | static const struct sirfsoc_padmux pulse_count_padmux = { |
| 803 | .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), |
| 804 | .muxmask = pulse_count_muxmask, |
| 805 | }; |
| 806 | |
| 807 | static const unsigned pulse_count_pins[] = { 9, 10, 11 }; |
| 808 | |
| 809 | #define SIRFSOC_PIN_GROUP(n, p) \ |
| 810 | { \ |
| 811 | .name = n, \ |
| 812 | .pins = p, \ |
| 813 | .num_pins = ARRAY_SIZE(p), \ |
| 814 | } |
| 815 | |
| 816 | static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { |
| 817 | SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), |
| 818 | SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), |
| 819 | SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), |
| 820 | SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), |
| 821 | SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), |
| 822 | SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), |
| 823 | SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), |
| 824 | SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), |
| 825 | SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), |
| 826 | SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), |
| 827 | SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), |
| 828 | SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), |
| 829 | SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), |
| 830 | SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), |
| 831 | SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), |
| 832 | SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), |
| 833 | SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), |
| 834 | SIRFSOC_PIN_GROUP("vipgrp", vip_pins), |
| 835 | SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), |
| 836 | SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), |
| 837 | SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), |
| 838 | SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), |
| 839 | SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), |
| 840 | SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), |
| 841 | SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), |
| 842 | SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), |
| 843 | SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins), |
| 844 | SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), |
| 845 | SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), |
| 846 | SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), |
| 847 | SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), |
| 848 | SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), |
| 849 | SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), |
| 850 | SIRFSOC_PIN_GROUP("nandgrp", nand_pins), |
| 851 | SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), |
| 852 | SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), |
| 853 | SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), |
| 854 | }; |
| 855 | |
| 856 | static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector) |
| 857 | { |
| 858 | if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) |
| 859 | return -EINVAL; |
| 860 | return 0; |
| 861 | } |
| 862 | |
| 863 | static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, |
| 864 | unsigned selector) |
| 865 | { |
| 866 | if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) |
| 867 | return NULL; |
| 868 | return sirfsoc_pin_groups[selector].name; |
| 869 | } |
| 870 | |
| 871 | static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, |
Stephen Warren | a5818a8 | 2011-10-19 16:19:25 -0600 | [diff] [blame] | 872 | const unsigned **pins, |
Jean-Christophe PLAGNIOL-VILLARD | ad7761a | 2011-10-25 00:11:56 +0800 | [diff] [blame] | 873 | unsigned *num_pins) |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 874 | { |
| 875 | if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) |
| 876 | return -EINVAL; |
Stephen Warren | a5818a8 | 2011-10-19 16:19:25 -0600 | [diff] [blame] | 877 | *pins = sirfsoc_pin_groups[selector].pins; |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 878 | *num_pins = sirfsoc_pin_groups[selector].num_pins; |
| 879 | return 0; |
| 880 | } |
| 881 | |
| 882 | static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
| 883 | unsigned offset) |
| 884 | { |
| 885 | seq_printf(s, " " DRIVER_NAME); |
| 886 | } |
| 887 | |
| 888 | static struct pinctrl_ops sirfsoc_pctrl_ops = { |
| 889 | .list_groups = sirfsoc_list_groups, |
| 890 | .get_group_name = sirfsoc_get_group_name, |
| 891 | .get_group_pins = sirfsoc_get_group_pins, |
| 892 | .pin_dbg_show = sirfsoc_pin_dbg_show, |
| 893 | }; |
| 894 | |
| 895 | struct sirfsoc_pmx_func { |
| 896 | const char *name; |
| 897 | const char * const *groups; |
| 898 | const unsigned num_groups; |
| 899 | const struct sirfsoc_padmux *padmux; |
| 900 | }; |
| 901 | |
| 902 | static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; |
| 903 | static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; |
| 904 | static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; |
| 905 | static const char * const lcdromgrp[] = { "lcdromgrp" }; |
| 906 | static const char * const uart0grp[] = { "uart0grp" }; |
| 907 | static const char * const uart1grp[] = { "uart1grp" }; |
| 908 | static const char * const uart2grp[] = { "uart2grp" }; |
| 909 | static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; |
| 910 | static const char * const usp0grp[] = { "usp0grp" }; |
| 911 | static const char * const usp1grp[] = { "usp1grp" }; |
| 912 | static const char * const usp2grp[] = { "usp2grp" }; |
| 913 | static const char * const i2c0grp[] = { "i2c0grp" }; |
| 914 | static const char * const i2c1grp[] = { "i2c1grp" }; |
| 915 | static const char * const pwm0grp[] = { "pwm0grp" }; |
| 916 | static const char * const pwm1grp[] = { "pwm1grp" }; |
| 917 | static const char * const pwm2grp[] = { "pwm2grp" }; |
| 918 | static const char * const pwm3grp[] = { "pwm3grp" }; |
| 919 | static const char * const vipgrp[] = { "vipgrp" }; |
| 920 | static const char * const vipromgrp[] = { "vipromgrp" }; |
| 921 | static const char * const warm_rstgrp[] = { "warm_rstgrp" }; |
| 922 | static const char * const cko0grp[] = { "cko0grp" }; |
| 923 | static const char * const cko1grp[] = { "cko1grp" }; |
| 924 | static const char * const sdmmc0grp[] = { "sdmmc0grp" }; |
| 925 | static const char * const sdmmc1grp[] = { "sdmmc1grp" }; |
| 926 | static const char * const sdmmc2grp[] = { "sdmmc2grp" }; |
| 927 | static const char * const sdmmc3grp[] = { "sdmmc3grp" }; |
| 928 | static const char * const sdmmc4grp[] = { "sdmmc4grp" }; |
| 929 | static const char * const sdmmc5grp[] = { "sdmmc5grp" }; |
| 930 | static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; |
| 931 | static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; |
| 932 | static const char * const pulse_countgrp[] = { "pulse_countgrp" }; |
| 933 | static const char * const i2sgrp[] = { "i2sgrp" }; |
| 934 | static const char * const ac97grp[] = { "ac97grp" }; |
| 935 | static const char * const nandgrp[] = { "nandgrp" }; |
| 936 | static const char * const spi0grp[] = { "spi0grp" }; |
| 937 | static const char * const spi1grp[] = { "spi1grp" }; |
| 938 | static const char * const gpsgrp[] = { "gpsgrp" }; |
| 939 | |
| 940 | #define SIRFSOC_PMX_FUNCTION(n, g, m) \ |
| 941 | { \ |
| 942 | .name = n, \ |
| 943 | .groups = g, \ |
| 944 | .num_groups = ARRAY_SIZE(g), \ |
| 945 | .padmux = &m, \ |
| 946 | } |
| 947 | |
| 948 | static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { |
| 949 | SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), |
| 950 | SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), |
| 951 | SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), |
| 952 | SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), |
| 953 | SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), |
| 954 | SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), |
| 955 | SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), |
| 956 | SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), |
| 957 | SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), |
| 958 | SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), |
| 959 | SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), |
| 960 | SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), |
| 961 | SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), |
| 962 | SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), |
| 963 | SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), |
| 964 | SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), |
| 965 | SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), |
| 966 | SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), |
| 967 | SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux), |
| 968 | SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), |
| 969 | SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), |
| 970 | SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), |
| 971 | SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), |
| 972 | SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), |
| 973 | SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), |
| 974 | SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), |
| 975 | SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), |
| 976 | SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), |
| 977 | SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), |
| 978 | SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), |
| 979 | SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), |
| 980 | SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), |
| 981 | SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), |
| 982 | SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), |
| 983 | SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), |
| 984 | SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), |
| 985 | SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), |
| 986 | }; |
| 987 | |
| 988 | static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, |
| 989 | bool enable) |
| 990 | { |
| 991 | int i; |
| 992 | const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; |
| 993 | const struct sirfsoc_muxmask *mask = mux->muxmask; |
| 994 | |
| 995 | for (i = 0; i < mux->muxmask_counts; i++) { |
| 996 | u32 muxval; |
| 997 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); |
| 998 | if (enable) |
| 999 | muxval = muxval & ~mask[i].mask; |
| 1000 | else |
| 1001 | muxval = muxval | mask[i].mask; |
| 1002 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); |
| 1003 | } |
| 1004 | |
| 1005 | if (mux->funcmask && enable) { |
| 1006 | u32 func_en_val; |
| 1007 | func_en_val = |
| 1008 | readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); |
| 1009 | func_en_val = |
| 1010 | (func_en_val & ~mux->funcmask) | (mux-> |
| 1011 | funcval); |
| 1012 | writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, |
| 1017 | unsigned group) |
| 1018 | { |
| 1019 | struct sirfsoc_pmx *spmx; |
| 1020 | |
| 1021 | spmx = pinctrl_dev_get_drvdata(pmxdev); |
| 1022 | sirfsoc_pinmux_endisable(spmx, selector, true); |
| 1023 | |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
| 1027 | static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, |
| 1028 | unsigned group) |
| 1029 | { |
| 1030 | struct sirfsoc_pmx *spmx; |
| 1031 | |
| 1032 | spmx = pinctrl_dev_get_drvdata(pmxdev); |
| 1033 | sirfsoc_pinmux_endisable(spmx, selector, false); |
| 1034 | } |
| 1035 | |
| 1036 | static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector) |
| 1037 | { |
| 1038 | if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions)) |
| 1039 | return -EINVAL; |
| 1040 | return 0; |
| 1041 | } |
| 1042 | |
| 1043 | static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, |
| 1044 | unsigned selector) |
| 1045 | { |
| 1046 | return sirfsoc_pmx_functions[selector].name; |
| 1047 | } |
| 1048 | |
| 1049 | static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, |
| 1050 | const char * const **groups, |
| 1051 | unsigned * const num_groups) |
| 1052 | { |
| 1053 | *groups = sirfsoc_pmx_functions[selector].groups; |
| 1054 | *num_groups = sirfsoc_pmx_functions[selector].num_groups; |
| 1055 | return 0; |
| 1056 | } |
| 1057 | |
| 1058 | static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, |
| 1059 | struct pinctrl_gpio_range *range, unsigned offset) |
| 1060 | { |
| 1061 | struct sirfsoc_pmx *spmx; |
| 1062 | |
| 1063 | int group = range->id; |
| 1064 | |
| 1065 | u32 muxval; |
| 1066 | |
| 1067 | spmx = pinctrl_dev_get_drvdata(pmxdev); |
| 1068 | |
| 1069 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); |
Chanho Park | 3c739ad | 2011-11-11 18:47:58 +0900 | [diff] [blame] | 1070 | muxval = muxval | (1 << (offset - range->pin_base)); |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 1071 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); |
| 1072 | |
| 1073 | return 0; |
| 1074 | } |
| 1075 | |
| 1076 | static struct pinmux_ops sirfsoc_pinmux_ops = { |
| 1077 | .list_functions = sirfsoc_pinmux_list_funcs, |
| 1078 | .enable = sirfsoc_pinmux_enable, |
| 1079 | .disable = sirfsoc_pinmux_disable, |
| 1080 | .get_function_name = sirfsoc_pinmux_get_func_name, |
| 1081 | .get_function_groups = sirfsoc_pinmux_get_groups, |
| 1082 | .gpio_request_enable = sirfsoc_pinmux_request_gpio, |
| 1083 | }; |
| 1084 | |
| 1085 | static struct pinctrl_desc sirfsoc_pinmux_desc = { |
| 1086 | .name = DRIVER_NAME, |
| 1087 | .pins = sirfsoc_pads, |
| 1088 | .npins = ARRAY_SIZE(sirfsoc_pads), |
| 1089 | .maxpin = SIRFSOC_NUM_PADS - 1, |
| 1090 | .pctlops = &sirfsoc_pctrl_ops, |
| 1091 | .pmxops = &sirfsoc_pinmux_ops, |
| 1092 | .owner = THIS_MODULE, |
| 1093 | }; |
| 1094 | |
| 1095 | /* |
| 1096 | * Todo: bind irq_chip to every pinctrl_gpio_range |
| 1097 | */ |
| 1098 | static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { |
| 1099 | { |
| 1100 | .name = "sirfsoc-gpio*", |
| 1101 | .id = 0, |
| 1102 | .base = 0, |
Chanho Park | 3c739ad | 2011-11-11 18:47:58 +0900 | [diff] [blame] | 1103 | .pin_base = 0, |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 1104 | .npins = 32, |
| 1105 | }, { |
| 1106 | .name = "sirfsoc-gpio*", |
| 1107 | .id = 1, |
| 1108 | .base = 32, |
Chanho Park | 3c739ad | 2011-11-11 18:47:58 +0900 | [diff] [blame] | 1109 | .pin_base = 32, |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 1110 | .npins = 32, |
| 1111 | }, { |
| 1112 | .name = "sirfsoc-gpio*", |
| 1113 | .id = 2, |
| 1114 | .base = 64, |
Chanho Park | 3c739ad | 2011-11-11 18:47:58 +0900 | [diff] [blame] | 1115 | .pin_base = 64, |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 1116 | .npins = 32, |
| 1117 | }, { |
| 1118 | .name = "sirfsoc-gpio*", |
| 1119 | .id = 3, |
| 1120 | .base = 96, |
Chanho Park | 3c739ad | 2011-11-11 18:47:58 +0900 | [diff] [blame] | 1121 | .pin_base = 96, |
Rongjun Ying | 393daa8 | 2011-10-09 03:11:13 -0700 | [diff] [blame] | 1122 | .npins = 19, |
| 1123 | }, |
| 1124 | }; |
| 1125 | |
| 1126 | static void __iomem *sirfsoc_rsc_of_iomap(void) |
| 1127 | { |
| 1128 | const struct of_device_id rsc_ids[] = { |
| 1129 | { .compatible = "sirf,prima2-rsc" }, |
| 1130 | {} |
| 1131 | }; |
| 1132 | struct device_node *np; |
| 1133 | |
| 1134 | np = of_find_matching_node(NULL, rsc_ids); |
| 1135 | if (!np) |
| 1136 | panic("unable to find compatible rsc node in dtb\n"); |
| 1137 | |
| 1138 | return of_iomap(np, 0); |
| 1139 | } |
| 1140 | |
| 1141 | static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev) |
| 1142 | { |
| 1143 | int ret; |
| 1144 | struct sirfsoc_pmx *spmx; |
| 1145 | struct device_node *np = pdev->dev.of_node; |
| 1146 | int i; |
| 1147 | |
| 1148 | /* Create state holders etc for this driver */ |
| 1149 | spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); |
| 1150 | if (!spmx) |
| 1151 | return -ENOMEM; |
| 1152 | |
| 1153 | spmx->dev = &pdev->dev; |
| 1154 | |
| 1155 | platform_set_drvdata(pdev, spmx); |
| 1156 | |
| 1157 | spmx->gpio_virtbase = of_iomap(np, 0); |
| 1158 | if (!spmx->gpio_virtbase) { |
| 1159 | ret = -ENOMEM; |
| 1160 | dev_err(&pdev->dev, "can't map gpio registers\n"); |
| 1161 | goto out_no_gpio_remap; |
| 1162 | } |
| 1163 | |
| 1164 | spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); |
| 1165 | if (!spmx->rsc_virtbase) { |
| 1166 | ret = -ENOMEM; |
| 1167 | dev_err(&pdev->dev, "can't map rsc registers\n"); |
| 1168 | goto out_no_rsc_remap; |
| 1169 | } |
| 1170 | |
| 1171 | /* Now register the pin controller and all pins it handles */ |
| 1172 | spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); |
| 1173 | if (!spmx->pmx) { |
| 1174 | dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); |
| 1175 | ret = -EINVAL; |
| 1176 | goto out_no_pmx; |
| 1177 | } |
| 1178 | |
| 1179 | for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) |
| 1180 | pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); |
| 1181 | |
| 1182 | dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); |
| 1183 | |
| 1184 | return 0; |
| 1185 | |
| 1186 | out_no_pmx: |
| 1187 | iounmap(spmx->rsc_virtbase); |
| 1188 | out_no_rsc_remap: |
| 1189 | iounmap(spmx->gpio_virtbase); |
| 1190 | out_no_gpio_remap: |
| 1191 | platform_set_drvdata(pdev, NULL); |
| 1192 | devm_kfree(&pdev->dev, spmx); |
| 1193 | return ret; |
| 1194 | } |
| 1195 | |
| 1196 | static const struct of_device_id pinmux_ids[] = { |
| 1197 | { .compatible = "sirf,prima2-gpio-pinmux" }, |
| 1198 | {} |
| 1199 | }; |
| 1200 | |
| 1201 | static struct platform_driver sirfsoc_pinmux_driver = { |
| 1202 | .driver = { |
| 1203 | .name = DRIVER_NAME, |
| 1204 | .owner = THIS_MODULE, |
| 1205 | .of_match_table = pinmux_ids, |
| 1206 | }, |
| 1207 | .probe = sirfsoc_pinmux_probe, |
| 1208 | }; |
| 1209 | |
| 1210 | static int __init sirfsoc_pinmux_init(void) |
| 1211 | { |
| 1212 | return platform_driver_register(&sirfsoc_pinmux_driver); |
| 1213 | } |
| 1214 | arch_initcall(sirfsoc_pinmux_init); |
| 1215 | |
| 1216 | MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " |
| 1217 | "Barry Song <baohua.song@csr.com>"); |
| 1218 | MODULE_DESCRIPTION("SIRFSOC pin control driver"); |
| 1219 | MODULE_LICENSE("GPL"); |