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Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +00001 STMicroelectronics 10/100/1000 Synopsys Ethernet driver
2
Giuseppe CAVALLARO49cfbf62013-04-08 02:09:59 +00003Copyright (C) 2007-2013 STMicroelectronics Ltd
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +00004Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5
6This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
Giuseppe CAVALLARO5b993262011-12-21 03:58:20 +00007(Synopsys IP blocks).
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +00008
9Currently this network device driver is for all STM embedded MAC/GMAC
Giuseppe CAVALLARO5b993262011-12-21 03:58:20 +000010(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
11FF1152AMT0221 D1215994A VIRTEX FPGA board.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000012
Giuseppe CAVALLARO49cfbf62013-04-08 02:09:59 +000013DWC Ether MAC 10/100/1000 Universal version 3.70a (and older) and DWC Ether
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +000014MAC 10/100 Universal version 4.0 have been used for developing this driver.
Giuseppe CAVALLARO5b993262011-12-21 03:58:20 +000015
16This driver supports both the platform bus and PCI.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000017
18Please, for more information also visit: www.stlinux.com
19
201) Kernel Configuration
21The kernel configuration option is STMMAC_ETH:
22 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
23 STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH)
24
252) Driver parameters list:
26 debug: message level (0: no output, 16: all);
27 phyaddr: to manually provide the physical address to the PHY device;
28 dma_rxsize: DMA rx ring size;
29 dma_txsize: DMA tx ring size;
30 buf_sz: DMA buffer size;
31 tc: control the HW FIFO threshold;
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000032 watchdog: transmit timeout (in milliseconds);
33 flow_ctrl: Flow control ability [on/off];
34 pause: Flow Control Pause Time;
Giuseppe CAVALLARO49cfbf62013-04-08 02:09:59 +000035 eee_timer: tx EEE timer;
36 chain_mode: select chain mode instead of ring.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000037
383) Command line options
39Driver parameters can be also passed in command line by using:
40 stmmaceth=dma_rxsize:128,dma_txsize:512
41
424) Driver information and notes
43
444.1) Transmit process
45The xmit method is invoked when the kernel needs to transmit a packet; it sets
46the descriptors in the ring and informs the DMA engine that there is a packet
47ready to be transmitted.
48Once the controller has finished transmitting the packet, an interrupt is
49triggered; So the driver will be able to release the socket buffers.
50By default, the driver sets the NETIF_F_SG bit in the features field of the
51net_device structure enabling the scatter/gather feature.
52
534.2) Receive process
54When one or more packets are received, an interrupt happens. The interrupts
55are not queued so the driver has to scan all the descriptors in the ring during
56the receive process.
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +000057This is based on NAPI so the interrupt handler signals only if there is work
58to be done, and it exits.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000059Then the poll method will be scheduled at some future point.
60The incoming packets are stored, by the DMA, in a list of pre-allocated socket
61buffers in order to avoid the memcpy (Zero-copy).
62
Giuseppe CAVALLAROf9e01b52012-11-25 23:10:45 +0000634.3) Interrupt Mitigation
64The driver is able to mitigate the number of its DMA interrupts
65using NAPI for the reception on chips older than the 3.50.
66New chips have an HW RX-Watchdog used for this mitigation.
67
68On Tx-side, the mitigation schema is based on a SW timer that calls the
69tx function (stmmac_tx) to reclaim the resource after transmitting the
70frames.
71Also there is another parameter (like a threshold) used to program
72the descriptors avoiding to set the interrupt on completion bit in
73when the frame is sent (xmit).
74
75Mitigation parameters can be tuned by ethtool.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000076
774.4) WOL
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +000078Wake up on Lan feature through Magic and Unicast frames are supported for the
79GMAC core.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000080
814.5) DMA descriptors
82Driver handles both normal and enhanced descriptors. The latter has been only
Giuseppe CAVALLARO51e31372011-10-18 00:01:20 +000083tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later.
84
85STMMAC supports DMA descriptor to operate both in dual buffer (RING)
86and linked-list(CHAINED) mode. In RING each descriptor points to two
87data buffer pointers whereas in CHAINED mode they point to only one data
88buffer pointer. RING mode is the default.
89
90In CHAINED mode each descriptor will have pointer to next descriptor in
91the list, hence creating the explicit chaining in the descriptor itself,
92whereas such explicit chaining is not possible in RING mode.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +000093
944.6) Ethtool support
95Ethtool is supported. Driver statistics and internal errors can be taken using:
96ethtool -S ethX command. It is possible to dump registers etc.
97
984.7) Jumbo and Segmentation Offloading
99Jumbo frames are supported and tested for the GMAC.
100The GSO has been also added but it's performed in software.
101LRO is not supported.
102
1034.8) Physical
104The driver is compatible with PAL to work with PHY and GPHY devices.
105
1064.9) Platform information
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000107Several driver's information can be passed through the platform
108These are included in the include/linux/stmmac.h header file
109and detailed below as well:
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +0000110
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +0000111struct plat_stmmacenet_data {
112 char *phy_bus_name;
Giuseppe Cavallarof5539b52010-11-12 12:43:34 -0800113 int bus_id;
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000114 int phy_addr;
115 int interface;
116 struct stmmac_mdio_bus_data *mdio_bus_data;
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000117 struct stmmac_dma_cfg *dma_cfg;
Giuseppe Cavallarof5539b52010-11-12 12:43:34 -0800118 int clk_csr;
119 int has_gmac;
120 int enh_desc;
121 int tx_coe;
Deepak SIKRI55f9a4d2012-04-04 04:33:20 +0000122 int rx_coe;
Giuseppe Cavallarof5539b52010-11-12 12:43:34 -0800123 int bugged_jumbo;
124 int pmt;
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000125 int force_sf_dma_mode;
Sonic Zhange2a240c2013-08-28 18:55:39 +0800126 int force_thresh_dma_mode;
Giuseppe CAVALLAROf9e01b52012-11-25 23:10:45 +0000127 int riwt_off;
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000128 void (*fix_mac_speed)(void *priv, unsigned int speed);
129 void (*bus_setup)(void __iomem *ioaddr);
130 int (*init)(struct platform_device *pdev);
131 void (*exit)(struct platform_device *pdev);
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +0000132 void *custom_cfg;
133 void *custom_data;
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000134 void *bsp_priv;
135 };
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +0000136
137Where:
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +0000138 o phy_bus_name: phy bus name to attach to the stmmac.
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000139 o bus_id: bus identifier.
140 o phy_addr: the physical address can be passed from the platform.
141 If it is set to -1 the driver will automatically
142 detect it at run-time by probing all the 32 addresses.
143 o interface: PHY device's interface.
144 o mdio_bus_data: specific platform fields for the MDIO bus.
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +0000145 o dma_cfg: internal DMA parameters
146 o pbl: the Programmable Burst Length is maximum number of beats to
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000147 be transferred in one DMA transaction.
148 GMAC also enables the 4xPBL by default.
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +0000149 o fixed_burst/mixed_burst/burst_len
Giuseppe CAVALLAROcd7201f2012-04-04 04:33:27 +0000150 o clk_csr: fixed CSR Clock range selection.
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000151 o has_gmac: uses the GMAC core.
152 o enh_desc: if sets the MAC will use the enhanced descriptor structure.
153 o tx_coe: core is able to perform the tx csum in HW.
Deepak SIKRI55f9a4d2012-04-04 04:33:20 +0000154 o rx_coe: the supports three check sum offloading engine types:
155 type_1, type_2 (full csum) and no RX coe.
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000156 o bugged_jumbo: some HWs are not able to perform the csum in HW for
157 over-sized frames due to limited buffer sizes.
158 Setting this flag the csum will be done in SW on
159 JUMBO frames.
160 o pmt: core has the embedded power module (optional).
161 o force_sf_dma_mode: force DMA to use the Store and Forward mode
162 instead of the Threshold.
Masanari Iidac17cb8b2013-10-30 16:46:15 +0900163 o force_thresh_dma_mode: force DMA to use the Threshold mode other than
Sonic Zhange2a240c2013-08-28 18:55:39 +0800164 the Store and Forward mode.
Giuseppe CAVALLAROf9e01b52012-11-25 23:10:45 +0000165 o riwt_off: force to disable the RX watchdog feature and switch to NAPI mode.
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000166 o fix_mac_speed: this callback is used for modifying some syscfg registers
167 (on ST SoCs) according to the link speed negotiated by the
168 physical layer .
169 o bus_setup: perform HW setup of the bus. For example, on some ST platforms
170 this field is used to configure the AMBA bridge to generate more
171 efficient STBus traffic.
Giuseppe CAVALLARO49cfbf62013-04-08 02:09:59 +0000172 o init/exit: callbacks used for calling a custom initialization;
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000173 this is sometime necessary on some platforms (e.g. ST boxes)
174 where the HW needs to have set some PIO lines or system cfg
175 registers.
Giuseppe CAVALLARO3d237712012-06-04 19:22:56 +0000176 o custom_cfg/custom_data: this is a custom configuration that can be passed
Giuseppe CAVALLARO49cfbf62013-04-08 02:09:59 +0000177 while initializing the resources.
Masanari Iidac17cb8b2013-10-30 16:46:15 +0900178 o bsp_priv: another private pointer.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +0000179
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000180For MDIO bus The we have:
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000181
182 struct stmmac_mdio_bus_data {
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000183 int (*phy_reset)(void *priv);
184 unsigned int phy_mask;
185 int *irqs;
186 int probed_phy_irq;
187 };
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +0000188
189Where:
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000190 o phy_reset: hook to reset the phy device attached to the bus.
191 o phy_mask: phy mask passed when register the MDIO bus within the driver.
192 o irqs: list of IRQs, one per PHY.
193 o probed_phy_irq: if irqs is NULL, use this for probed PHY.
Giuseppe CAVALLAROa1d6f3f2010-03-31 21:44:04 +0000194
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000195For DMA engine we have the following internal fields that should be
196tuned according to the HW capabilities.
197
198struct stmmac_dma_cfg {
199 int pbl;
200 int fixed_burst;
201 int burst_len_supported;
202};
203
204Where:
205 o pbl: Programmable Burst Length
206 o fixed_burst: program the DMA to use the fixed burst mode
207 o burst_len: this is the value we put in the register
208 supported values are provided as macros in
209 linux/stmmac.h header file.
210
211---
212
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000213Below an example how the structures above are using on ST platforms.
Giuseppe Cavallarof5539b52010-11-12 12:43:34 -0800214
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000215 static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = {
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000216 .has_gmac = 0,
217 .enh_desc = 0,
218 .fix_mac_speed = stxYYY_ethernet_fix_mac_speed,
219 |
220 |-> to write an internal syscfg
221 | on this platform when the
222 | link speed changes from 10 to
223 | 100 and viceversa
224 .init = &stmmac_claim_resource,
225 |
226 |-> On ST SoC this calls own "PAD"
227 | manager framework to claim
228 | all the resources necessary
229 | (GPIO ...). The .custom_cfg field
230 | is used to pass a custom config.
231};
232
233Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact,
234there are two MAC cores: one MAC is for MDIO Bus/PHY emulation
235with fixed_link support.
236
237static struct stmmac_mdio_bus_data stmmac1_mdio_bus = {
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000238 .phy_reset = phy_reset;
239 |
240 |-> function to provide the phy_reset on this board
241 .phy_mask = 0,
242};
243
244static struct fixed_phy_status stmmac0_fixed_phy_status = {
245 .link = 1,
246 .speed = 100,
247 .duplex = 1,
248};
249
250During the board's device_init we can configure the first
251MAC for fixed_link by calling:
252 fixed_phy_add(PHY_POLL, 1, &stmmac0_fixed_phy_status));)
253and the second one, with a real PHY device attached to the bus,
254by using the stmmac_mdio_bus_data structure (to provide the id, the
255reset procedure etc).
256
2574.10) List of source files:
258 o Kconfig
259 o Makefile
260 o stmmac_main.c: main network device driver;
261 o stmmac_mdio.c: mdio functions;
Giuseppe CAVALLARO0ec2ccd2012-06-27 21:14:36 +0000262 o stmmac_pci: PCI driver;
263 o stmmac_platform.c: platform driver
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000264 o stmmac_ethtool.c: ethtool support;
265 o stmmac_timer.[ch]: timer code used for mitigating the driver dma interrupts
Giuseppe CAVALLARO0ec2ccd2012-06-27 21:14:36 +0000266 (only tested on ST40 platforms based);
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000267 o stmmac.h: private driver structure;
268 o common.h: common definitions and VFTs;
269 o descs.h: descriptor structure definitions;
270 o dwmac1000_core.c: GMAC core functions;
271 o dwmac1000_dma.c: dma functions for the GMAC chip;
272 o dwmac1000.h: specific header file for the GMAC;
273 o dwmac100_core: MAC 100 core and dma code;
Masanari Iidac17cb8b2013-10-30 16:46:15 +0900274 o dwmac100_dma.c: dma functions for the MAC chip;
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000275 o dwmac1000.h: specific header file for the MAC;
Giuseppe CAVALLARO0ec2ccd2012-06-27 21:14:36 +0000276 o dwmac_lib.c: generic DMA functions shared among chips;
277 o enh_desc.c: functions for handling enhanced descriptors;
278 o norm_desc.c: functions for handling normal descriptors;
279 o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes;
280 o mmc_core.c/mmc.h: Management MAC Counters;
Giuseppe CAVALLARO49cfbf62013-04-08 02:09:59 +0000281 o stmmac_hwtstamp.c: HW timestamp support for PTP
282 o stmmac_ptp.c: PTP 1588 clock
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000283
Giuseppe CAVALLARO4f2f25f2011-09-01 21:51:42 +00002845) Debug Information
285
286The driver exports many information i.e. internal statistics,
287debug information, MAC and DMA registers etc.
288
289These can be read in several ways depending on the
290type of the information actually needed.
291
292For example a user can be use the ethtool support
293to get statistics: e.g. using: ethtool -S ethX
294(that shows the Management counters (MMC) if supported)
295or sees the MAC/DMA registers: e.g. using: ethtool -d ethX
296
297Compiling the Kernel with CONFIG_DEBUG_FS and enabling the
298STMMAC_DEBUG_FS option the driver will export the following
299debugfs entries:
300
301/sys/kernel/debug/stmmaceth/descriptors_status
302 To show the DMA TX/RX descriptor rings
303
304Developer can also use the "debug" module parameter to get
305further debug information.
306
307In the end, there are other macros (that cannot be enabled
308via menuconfig) to turn-on the RX/TX DMA debugging,
309specific MAC core debug printk etc. Others to enable the
310debug in the TX and RX processes.
311All these are only useful during the developing stage
312and should never enabled inside the code for general usage.
313In fact, these can generate an huge amount of debug messages.
314
Giuseppe CAVALLARO0ec2ccd2012-06-27 21:14:36 +00003156) Energy Efficient Ethernet
316
317Energy Efficient Ethernet(EEE) enables IEEE 802.3 MAC sublayer along
318with a family of Physical layer to operate in the Low power Idle(LPI)
319mode. The EEE mode supports the IEEE 802.3 MAC operation at 100Mbps,
3201000Mbps & 10Gbps.
321
322The LPI mode allows power saving by switching off parts of the
323communication device functionality when there is no data to be
324transmitted & received. The system on both the side of the link can
325disable some functionalities & save power during the period of low-link
326utilization. The MAC controls whether the system should enter or exit
327the LPI mode & communicate this to PHY.
328
329As soon as the interface is opened, the driver verifies if the EEE can
330be supported. This is done by looking at both the DMA HW capability
331register and the PHY devices MCD registers.
332To enter in Tx LPI mode the driver needs to have a software timer
333that enable and disable the LPI mode when there is nothing to be
334transmitted.
335
Giuseppe CAVALLARO94fbbbf2013-03-26 04:43:12 +00003367) Extended descriptors
337The extended descriptors give us information about the receive Ethernet payload
338when it is carrying PTP packets or TCP/UDP/ICMP over IP.
339These are not available on GMAC Synopsys chips older than the 3.50.
340At probe time the driver will decide if these can be actually used.
341This support also is mandatory for PTPv2 because the extra descriptors 6 and 7
342are used for saving the hardware timestamps.
343
3448) Precision Time Protocol (PTP)
345The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP),
346which enables precise synchronization of clocks in measurement and
347control systems implemented with technologies such as network
348communication.
349
350In addition to the basic timestamp features mentioned in IEEE 1588-2002
351Timestamps, new GMAC cores support the advanced timestamp features.
352IEEE 1588-2008 that can be enabled when configure the Kernel.
353
3549) SGMII/RGMII supports
355New GMAC devices provide own way to manage RGMII/SGMII.
356This information is available at run-time by looking at the
357HW capability register. This means that the stmmac can manage
358auto-negotiation and link status w/o using the PHYLIB stuff
359In fact, the HW provides a subset of extended registers to
360restart the ANE, verify Full/Half duplex mode and Speed.
361Also thanks to these registers it is possible to look at the
362Auto-negotiated Link Parter Ability.
363
36410) TODO:
Giuseppe CAVALLARO557e2a32011-07-20 00:05:24 +0000365 o XGMAC is not supported.
Giuseppe CAVALLARO94fbbbf2013-03-26 04:43:12 +0000366 o Complete the TBI & RTBI support.
Masanari Iidac17cb8b2013-10-30 16:46:15 +0900367 o extend VLAN support for 3.70a SYNP GMAC.