Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 1 | /* |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 2 | * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 3 | * |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 4 | * Copyright (C) 2014 Samsung Electrnoics |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 5 | * Chanwoo Choi <cw00.choi@samsung.com> |
| 6 | * Krzysztof Kozlowski <k.kozlowski@samsung.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __MAX14577_PRIVATE_H__ |
| 20 | #define __MAX14577_PRIVATE_H__ |
| 21 | |
| 22 | #include <linux/i2c.h> |
| 23 | #include <linux/regmap.h> |
| 24 | |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 25 | #define I2C_ADDR_PMIC (0x46 >> 1) |
| 26 | #define I2C_ADDR_MUIC (0x4A >> 1) |
| 27 | #define I2C_ADDR_FG (0x6C >> 1) |
| 28 | |
Krzysztof Kozlowski | eccb80c | 2014-04-14 11:17:14 +0200 | [diff] [blame] | 29 | enum maxim_device_type { |
| 30 | MAXIM_DEVICE_TYPE_UNKNOWN = 0, |
| 31 | MAXIM_DEVICE_TYPE_MAX14577, |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 32 | MAXIM_DEVICE_TYPE_MAX77836, |
Krzysztof Kozlowski | eccb80c | 2014-04-14 11:17:14 +0200 | [diff] [blame] | 33 | |
| 34 | MAXIM_DEVICE_TYPE_NUM, |
| 35 | }; |
| 36 | |
Krzysztof Kozlowski | 575343d | 2014-04-14 11:17:13 +0200 | [diff] [blame] | 37 | /* Slave addr = 0x4A: MUIC and Charger */ |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 38 | enum max14577_reg { |
| 39 | MAX14577_REG_DEVICEID = 0x00, |
| 40 | MAX14577_REG_INT1 = 0x01, |
| 41 | MAX14577_REG_INT2 = 0x02, |
| 42 | MAX14577_REG_INT3 = 0x03, |
| 43 | MAX14577_REG_STATUS1 = 0x04, |
| 44 | MAX14577_REG_STATUS2 = 0x05, |
| 45 | MAX14577_REG_STATUS3 = 0x06, |
| 46 | MAX14577_REG_INTMASK1 = 0x07, |
| 47 | MAX14577_REG_INTMASK2 = 0x08, |
| 48 | MAX14577_REG_INTMASK3 = 0x09, |
| 49 | MAX14577_REG_CDETCTRL1 = 0x0A, |
| 50 | MAX14577_REG_RFU = 0x0B, |
| 51 | MAX14577_REG_CONTROL1 = 0x0C, |
| 52 | MAX14577_REG_CONTROL2 = 0x0D, |
| 53 | MAX14577_REG_CONTROL3 = 0x0E, |
| 54 | MAX14577_REG_CHGCTRL1 = 0x0F, |
| 55 | MAX14577_REG_CHGCTRL2 = 0x10, |
| 56 | MAX14577_REG_CHGCTRL3 = 0x11, |
| 57 | MAX14577_REG_CHGCTRL4 = 0x12, |
| 58 | MAX14577_REG_CHGCTRL5 = 0x13, |
| 59 | MAX14577_REG_CHGCTRL6 = 0x14, |
| 60 | MAX14577_REG_CHGCTRL7 = 0x15, |
| 61 | |
| 62 | MAX14577_REG_END, |
| 63 | }; |
| 64 | |
| 65 | /* Slave addr = 0x4A: MUIC */ |
| 66 | enum max14577_muic_reg { |
| 67 | MAX14577_MUIC_REG_STATUS1 = 0x04, |
| 68 | MAX14577_MUIC_REG_STATUS2 = 0x05, |
| 69 | MAX14577_MUIC_REG_CONTROL1 = 0x0C, |
| 70 | MAX14577_MUIC_REG_CONTROL3 = 0x0E, |
| 71 | |
| 72 | MAX14577_MUIC_REG_END, |
| 73 | }; |
| 74 | |
| 75 | enum max14577_muic_charger_type { |
| 76 | MAX14577_CHARGER_TYPE_NONE = 0, |
| 77 | MAX14577_CHARGER_TYPE_USB, |
| 78 | MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT, |
| 79 | MAX14577_CHARGER_TYPE_DEDICATED_CHG, |
| 80 | MAX14577_CHARGER_TYPE_SPECIAL_500MA, |
| 81 | MAX14577_CHARGER_TYPE_SPECIAL_1A, |
| 82 | MAX14577_CHARGER_TYPE_RESERVED, |
| 83 | MAX14577_CHARGER_TYPE_DEAD_BATTERY = 7, |
| 84 | }; |
| 85 | |
| 86 | /* MAX14577 interrupts */ |
Krzysztof Kozlowski | c784685 | 2014-04-14 11:17:17 +0200 | [diff] [blame] | 87 | #define MAX14577_INT1_ADC_MASK BIT(0) |
| 88 | #define MAX14577_INT1_ADCLOW_MASK BIT(1) |
| 89 | #define MAX14577_INT1_ADCERR_MASK BIT(2) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 90 | |
Krzysztof Kozlowski | c784685 | 2014-04-14 11:17:17 +0200 | [diff] [blame] | 91 | #define MAX14577_INT2_CHGTYP_MASK BIT(0) |
| 92 | #define MAX14577_INT2_CHGDETRUN_MASK BIT(1) |
| 93 | #define MAX14577_INT2_DCDTMR_MASK BIT(2) |
| 94 | #define MAX14577_INT2_DBCHG_MASK BIT(3) |
| 95 | #define MAX14577_INT2_VBVOLT_MASK BIT(4) |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 96 | #define MAX77836_INT2_VIDRM_MASK BIT(5) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 97 | |
Krzysztof Kozlowski | c784685 | 2014-04-14 11:17:17 +0200 | [diff] [blame] | 98 | #define MAX14577_INT3_EOC_MASK BIT(0) |
| 99 | #define MAX14577_INT3_CGMBC_MASK BIT(1) |
| 100 | #define MAX14577_INT3_OVP_MASK BIT(2) |
| 101 | #define MAX14577_INT3_MBCCHGERR_MASK BIT(3) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 102 | |
| 103 | /* MAX14577 DEVICE ID register */ |
| 104 | #define DEVID_VENDORID_SHIFT 0 |
| 105 | #define DEVID_DEVICEID_SHIFT 3 |
| 106 | #define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT) |
| 107 | #define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT) |
| 108 | |
| 109 | /* MAX14577 STATUS1 register */ |
| 110 | #define STATUS1_ADC_SHIFT 0 |
| 111 | #define STATUS1_ADCLOW_SHIFT 5 |
| 112 | #define STATUS1_ADCERR_SHIFT 6 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 113 | #define MAX77836_STATUS1_ADC1K_SHIFT 7 |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 114 | #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 115 | #define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT) |
| 116 | #define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT) |
| 117 | #define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 118 | |
| 119 | /* MAX14577 STATUS2 register */ |
| 120 | #define STATUS2_CHGTYP_SHIFT 0 |
| 121 | #define STATUS2_CHGDETRUN_SHIFT 3 |
| 122 | #define STATUS2_DCDTMR_SHIFT 4 |
| 123 | #define STATUS2_DBCHG_SHIFT 5 |
| 124 | #define STATUS2_VBVOLT_SHIFT 6 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 125 | #define MAX77836_STATUS2_VIDRM_SHIFT 7 |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 126 | #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 127 | #define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT) |
| 128 | #define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT) |
| 129 | #define STATUS2_DBCHG_MASK BIT(STATUS2_DBCHG_SHIFT) |
| 130 | #define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT) |
| 131 | #define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 132 | |
| 133 | /* MAX14577 CONTROL1 register */ |
| 134 | #define COMN1SW_SHIFT 0 |
| 135 | #define COMP2SW_SHIFT 3 |
| 136 | #define MICEN_SHIFT 6 |
| 137 | #define IDBEN_SHIFT 7 |
| 138 | #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) |
| 139 | #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 140 | #define MICEN_MASK BIT(MICEN_SHIFT) |
| 141 | #define IDBEN_MASK BIT(IDBEN_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 142 | #define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK) |
| 143 | #define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \ |
| 144 | | (1 << COMN1SW_SHIFT)) |
| 145 | #define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ |
| 146 | | (2 << COMN1SW_SHIFT)) |
| 147 | #define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \ |
| 148 | | (3 << COMN1SW_SHIFT)) |
| 149 | #define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ |
| 150 | | (0 << COMN1SW_SHIFT)) |
| 151 | |
| 152 | /* MAX14577 CONTROL2 register */ |
| 153 | #define CTRL2_LOWPWR_SHIFT (0) |
| 154 | #define CTRL2_ADCEN_SHIFT (1) |
| 155 | #define CTRL2_CPEN_SHIFT (2) |
| 156 | #define CTRL2_SFOUTASRT_SHIFT (3) |
| 157 | #define CTRL2_SFOUTORD_SHIFT (4) |
| 158 | #define CTRL2_ACCDET_SHIFT (5) |
| 159 | #define CTRL2_USBCPINT_SHIFT (6) |
| 160 | #define CTRL2_RCPS_SHIFT (7) |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 161 | #define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT) |
| 162 | #define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT) |
| 163 | #define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT) |
| 164 | #define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT) |
| 165 | #define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT) |
| 166 | #define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT) |
| 167 | #define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT) |
| 168 | #define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 169 | |
| 170 | #define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \ |
| 171 | (0 << CTRL2_LOWPWR_SHIFT)) |
| 172 | #define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \ |
| 173 | (1 << CTRL2_LOWPWR_SHIFT)) |
| 174 | |
| 175 | /* MAX14577 CONTROL3 register */ |
| 176 | #define CTRL3_JIGSET_SHIFT 0 |
| 177 | #define CTRL3_BOOTSET_SHIFT 2 |
| 178 | #define CTRL3_ADCDBSET_SHIFT 4 |
| 179 | #define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT) |
| 180 | #define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT) |
| 181 | #define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT) |
| 182 | |
| 183 | /* Slave addr = 0x4A: Charger */ |
| 184 | enum max14577_charger_reg { |
| 185 | MAX14577_CHG_REG_STATUS3 = 0x06, |
| 186 | MAX14577_CHG_REG_CHG_CTRL1 = 0x0F, |
| 187 | MAX14577_CHG_REG_CHG_CTRL2 = 0x10, |
| 188 | MAX14577_CHG_REG_CHG_CTRL3 = 0x11, |
| 189 | MAX14577_CHG_REG_CHG_CTRL4 = 0x12, |
| 190 | MAX14577_CHG_REG_CHG_CTRL5 = 0x13, |
| 191 | MAX14577_CHG_REG_CHG_CTRL6 = 0x14, |
| 192 | MAX14577_CHG_REG_CHG_CTRL7 = 0x15, |
| 193 | |
| 194 | MAX14577_CHG_REG_END, |
| 195 | }; |
| 196 | |
| 197 | /* MAX14577 STATUS3 register */ |
| 198 | #define STATUS3_EOC_SHIFT 0 |
| 199 | #define STATUS3_CGMBC_SHIFT 1 |
| 200 | #define STATUS3_OVP_SHIFT 2 |
| 201 | #define STATUS3_MBCCHGERR_SHIFT 3 |
| 202 | #define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT) |
| 203 | #define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT) |
| 204 | #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT) |
| 205 | #define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT) |
| 206 | |
| 207 | /* MAX14577 CDETCTRL1 register */ |
| 208 | #define CDETCTRL1_CHGDETEN_SHIFT 0 |
| 209 | #define CDETCTRL1_CHGTYPMAN_SHIFT 1 |
| 210 | #define CDETCTRL1_DCDEN_SHIFT 2 |
| 211 | #define CDETCTRL1_DCD2SCT_SHIFT 3 |
| 212 | #define CDETCTRL1_DCHKTM_SHIFT 4 |
| 213 | #define CDETCTRL1_DBEXIT_SHIFT 5 |
| 214 | #define CDETCTRL1_DBIDLE_SHIFT 6 |
| 215 | #define CDETCTRL1_CDPDET_SHIFT 7 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 216 | #define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT) |
| 217 | #define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT) |
| 218 | #define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT) |
| 219 | #define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT) |
| 220 | #define CDETCTRL1_DCHKTM_MASK BIT(CDETCTRL1_DCHKTM_SHIFT) |
| 221 | #define CDETCTRL1_DBEXIT_MASK BIT(CDETCTRL1_DBEXIT_SHIFT) |
| 222 | #define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT) |
| 223 | #define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 224 | |
| 225 | /* MAX14577 CHGCTRL1 register */ |
| 226 | #define CHGCTRL1_TCHW_SHIFT 4 |
| 227 | #define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT) |
| 228 | |
| 229 | /* MAX14577 CHGCTRL2 register */ |
| 230 | #define CHGCTRL2_MBCHOSTEN_SHIFT 6 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 231 | #define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 232 | #define CHGCTRL2_VCHGR_RC_SHIFT 7 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 233 | #define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 234 | |
| 235 | /* MAX14577 CHGCTRL3 register */ |
| 236 | #define CHGCTRL3_MBCCVWRC_SHIFT 0 |
| 237 | #define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT) |
| 238 | |
| 239 | /* MAX14577 CHGCTRL4 register */ |
| 240 | #define CHGCTRL4_MBCICHWRCH_SHIFT 0 |
| 241 | #define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT) |
| 242 | #define CHGCTRL4_MBCICHWRCL_SHIFT 4 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 243 | #define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 244 | |
| 245 | /* MAX14577 CHGCTRL5 register */ |
| 246 | #define CHGCTRL5_EOCS_SHIFT 0 |
| 247 | #define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT) |
| 248 | |
| 249 | /* MAX14577 CHGCTRL6 register */ |
| 250 | #define CHGCTRL6_AUTOSTOP_SHIFT 5 |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 251 | #define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT) |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 252 | |
| 253 | /* MAX14577 CHGCTRL7 register */ |
| 254 | #define CHGCTRL7_OTPCGHCVS_SHIFT 0 |
| 255 | #define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT) |
| 256 | |
| 257 | /* MAX14577 regulator current limits (as in CHGCTRL4 register), uA */ |
| 258 | #define MAX14577_REGULATOR_CURRENT_LIMIT_MIN 90000 |
| 259 | #define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_START 200000 |
| 260 | #define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000 |
| 261 | #define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000 |
| 262 | |
| 263 | /* MAX14577 regulator SFOUT LDO voltage, fixed, uV */ |
| 264 | #define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000 |
| 265 | |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 266 | /* Slave addr = 0x46: PMIC */ |
| 267 | enum max77836_pmic_reg { |
| 268 | MAX77836_PMIC_REG_PMIC_ID = 0x20, |
| 269 | MAX77836_PMIC_REG_PMIC_REV = 0x21, |
| 270 | MAX77836_PMIC_REG_INTSRC = 0x22, |
| 271 | MAX77836_PMIC_REG_INTSRC_MASK = 0x23, |
| 272 | MAX77836_PMIC_REG_TOPSYS_INT = 0x24, |
| 273 | MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26, |
| 274 | MAX77836_PMIC_REG_TOPSYS_STAT = 0x28, |
| 275 | MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A, |
| 276 | MAX77836_PMIC_REG_LSCNFG = 0x2B, |
| 277 | |
| 278 | MAX77836_LDO_REG_CNFG1_LDO1 = 0x51, |
| 279 | MAX77836_LDO_REG_CNFG2_LDO1 = 0x52, |
| 280 | MAX77836_LDO_REG_CNFG1_LDO2 = 0x53, |
| 281 | MAX77836_LDO_REG_CNFG2_LDO2 = 0x54, |
| 282 | MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55, |
| 283 | |
| 284 | MAX77836_COMP_REG_COMP1 = 0x60, |
| 285 | |
| 286 | MAX77836_PMIC_REG_END, |
| 287 | }; |
| 288 | |
| 289 | #define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1 |
| 290 | #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3 |
| 291 | #define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT) |
| 292 | #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT) |
| 293 | |
| 294 | /* MAX77836 PMIC interrupts */ |
| 295 | #define MAX77836_TOPSYS_INT_T120C_SHIFT 0 |
| 296 | #define MAX77836_TOPSYS_INT_T140C_SHIFT 1 |
| 297 | #define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT) |
| 298 | #define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT) |
| 299 | |
| 300 | /* Slave addr = 0x6C: Fuel-Gauge/Battery */ |
| 301 | enum max77836_fg_reg { |
| 302 | MAX77836_FG_REG_VCELL_MSB = 0x02, |
| 303 | MAX77836_FG_REG_VCELL_LSB = 0x03, |
| 304 | MAX77836_FG_REG_SOC_MSB = 0x04, |
| 305 | MAX77836_FG_REG_SOC_LSB = 0x05, |
| 306 | MAX77836_FG_REG_MODE_H = 0x06, |
| 307 | MAX77836_FG_REG_MODE_L = 0x07, |
| 308 | MAX77836_FG_REG_VERSION_MSB = 0x08, |
| 309 | MAX77836_FG_REG_VERSION_LSB = 0x09, |
| 310 | MAX77836_FG_REG_HIBRT_H = 0x0A, |
| 311 | MAX77836_FG_REG_HIBRT_L = 0x0B, |
| 312 | MAX77836_FG_REG_CONFIG_H = 0x0C, |
| 313 | MAX77836_FG_REG_CONFIG_L = 0x0D, |
| 314 | MAX77836_FG_REG_VALRT_MIN = 0x14, |
| 315 | MAX77836_FG_REG_VALRT_MAX = 0x15, |
| 316 | MAX77836_FG_REG_CRATE_MSB = 0x16, |
| 317 | MAX77836_FG_REG_CRATE_LSB = 0x17, |
| 318 | MAX77836_FG_REG_VRESET = 0x18, |
| 319 | MAX77836_FG_REG_FGID = 0x19, |
| 320 | MAX77836_FG_REG_STATUS_H = 0x1A, |
| 321 | MAX77836_FG_REG_STATUS_L = 0x1B, |
| 322 | /* |
| 323 | * TODO: TABLE registers |
| 324 | * TODO: CMD register |
| 325 | */ |
| 326 | |
| 327 | MAX77836_FG_REG_END, |
| 328 | }; |
| 329 | |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 330 | enum max14577_irq { |
| 331 | /* INT1 */ |
| 332 | MAX14577_IRQ_INT1_ADC, |
| 333 | MAX14577_IRQ_INT1_ADCLOW, |
| 334 | MAX14577_IRQ_INT1_ADCERR, |
| 335 | |
| 336 | /* INT2 */ |
| 337 | MAX14577_IRQ_INT2_CHGTYP, |
| 338 | MAX14577_IRQ_INT2_CHGDETRUN, |
| 339 | MAX14577_IRQ_INT2_DCDTMR, |
| 340 | MAX14577_IRQ_INT2_DBCHG, |
| 341 | MAX14577_IRQ_INT2_VBVOLT, |
| 342 | |
| 343 | /* INT3 */ |
| 344 | MAX14577_IRQ_INT3_EOC, |
| 345 | MAX14577_IRQ_INT3_CGMBC, |
| 346 | MAX14577_IRQ_INT3_OVP, |
| 347 | MAX14577_IRQ_INT3_MBCCHGERR, |
| 348 | |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 349 | /* TOPSYS_INT, only MAX77836 */ |
| 350 | MAX77836_IRQ_TOPSYS_T140C, |
| 351 | MAX77836_IRQ_TOPSYS_T120C, |
| 352 | |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 353 | MAX14577_IRQ_NUM, |
| 354 | }; |
| 355 | |
| 356 | struct max14577 { |
| 357 | struct device *dev; |
| 358 | struct i2c_client *i2c; /* Slave addr = 0x4A */ |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 359 | struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */ |
Krzysztof Kozlowski | eccb80c | 2014-04-14 11:17:14 +0200 | [diff] [blame] | 360 | enum maxim_device_type dev_type; |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 361 | |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 362 | struct regmap *regmap; /* For MUIC and Charger */ |
| 363 | struct regmap *regmap_pmic; |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 364 | |
Krzysztof Kozlowski | aee2a57 | 2014-04-14 11:17:18 +0200 | [diff] [blame^] | 365 | struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */ |
| 366 | struct regmap_irq_chip_data *irq_data_pmic; |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 367 | int irq; |
Chanwoo Choi | 3008ddb | 2013-11-22 16:51:05 +0100 | [diff] [blame] | 368 | }; |
| 369 | |
| 370 | /* MAX14577 shared regmap API function */ |
| 371 | static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest) |
| 372 | { |
| 373 | unsigned int val; |
| 374 | int ret; |
| 375 | |
| 376 | ret = regmap_read(map, reg, &val); |
| 377 | *dest = val; |
| 378 | |
| 379 | return ret; |
| 380 | } |
| 381 | |
| 382 | static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf, |
| 383 | int count) |
| 384 | { |
| 385 | return regmap_bulk_read(map, reg, buf, count); |
| 386 | } |
| 387 | |
| 388 | static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value) |
| 389 | { |
| 390 | return regmap_write(map, reg, value); |
| 391 | } |
| 392 | |
| 393 | static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf, |
| 394 | int count) |
| 395 | { |
| 396 | return regmap_bulk_write(map, reg, buf, count); |
| 397 | } |
| 398 | |
| 399 | static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask, |
| 400 | u8 val) |
| 401 | { |
| 402 | return regmap_update_bits(map, reg, mask, val); |
| 403 | } |
| 404 | |
| 405 | #endif /* __MAX14577_PRIVATE_H__ */ |