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Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Padmavathi Vennaa80258f2013-02-14 09:10:06 +053028#include <linux/of_dma.h>
Sachin Kamatbcc7fa92013-03-04 14:36:27 +053029#include <linux/err.h>
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +010030#include <linux/pm_runtime.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070031
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000032#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090033#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +020037enum pl330_cachectrl {
38 CCTRL0, /* Noncacheable and nonbufferable */
39 CCTRL1, /* Bufferable only */
40 CCTRL2, /* Cacheable, but do not allocate */
41 CCTRL3, /* Cacheable and bufferable, but do not allocate */
42 INVALID1, /* AWCACHE = 0x1000 */
43 INVALID2,
44 CCTRL6, /* Cacheable write-through, allocate on writes only */
45 CCTRL7, /* Cacheable write-back, allocate on writes only */
Boojin Kimb7d861d2011-12-26 18:49:52 +090046};
47
48enum pl330_byteswap {
49 SWAP_NO,
50 SWAP_2,
51 SWAP_4,
52 SWAP_8,
53 SWAP_16,
54};
55
Boojin Kimb7d861d2011-12-26 18:49:52 +090056/* Register and Bit field Definitions */
57#define DS 0x0
58#define DS_ST_STOP 0x0
59#define DS_ST_EXEC 0x1
60#define DS_ST_CMISS 0x2
61#define DS_ST_UPDTPC 0x3
62#define DS_ST_WFE 0x4
63#define DS_ST_ATBRR 0x5
64#define DS_ST_QBUSY 0x6
65#define DS_ST_WFP 0x7
66#define DS_ST_KILL 0x8
67#define DS_ST_CMPLT 0x9
68#define DS_ST_FLTCMP 0xe
69#define DS_ST_FAULT 0xf
70
71#define DPC 0x4
72#define INTEN 0x20
73#define ES 0x24
74#define INTSTATUS 0x28
75#define INTCLR 0x2c
76#define FSM 0x30
77#define FSC 0x34
78#define FTM 0x38
79
80#define _FTC 0x40
81#define FTC(n) (_FTC + (n)*0x4)
82
83#define _CS 0x100
84#define CS(n) (_CS + (n)*0x8)
85#define CS_CNS (1 << 21)
86
87#define _CPC 0x104
88#define CPC(n) (_CPC + (n)*0x8)
89
90#define _SA 0x400
91#define SA(n) (_SA + (n)*0x20)
92
93#define _DA 0x404
94#define DA(n) (_DA + (n)*0x20)
95
96#define _CC 0x408
97#define CC(n) (_CC + (n)*0x20)
98
99#define CC_SRCINC (1 << 0)
100#define CC_DSTINC (1 << 14)
101#define CC_SRCPRI (1 << 8)
102#define CC_DSTPRI (1 << 22)
103#define CC_SRCNS (1 << 9)
104#define CC_DSTNS (1 << 23)
105#define CC_SRCIA (1 << 10)
106#define CC_DSTIA (1 << 24)
107#define CC_SRCBRSTLEN_SHFT 4
108#define CC_DSTBRSTLEN_SHFT 18
109#define CC_SRCBRSTSIZE_SHFT 1
110#define CC_DSTBRSTSIZE_SHFT 15
111#define CC_SRCCCTRL_SHFT 11
112#define CC_SRCCCTRL_MASK 0x7
113#define CC_DSTCCTRL_SHFT 25
114#define CC_DRCCCTRL_MASK 0x7
115#define CC_SWAP_SHFT 28
116
117#define _LC0 0x40c
118#define LC0(n) (_LC0 + (n)*0x20)
119
120#define _LC1 0x410
121#define LC1(n) (_LC1 + (n)*0x20)
122
123#define DBGSTATUS 0xd00
124#define DBG_BUSY (1 << 0)
125
126#define DBGCMD 0xd04
127#define DBGINST0 0xd08
128#define DBGINST1 0xd0c
129
130#define CR0 0xe00
131#define CR1 0xe04
132#define CR2 0xe08
133#define CR3 0xe0c
134#define CR4 0xe10
135#define CRD 0xe14
136
137#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900138#define PERIPH_REV_SHIFT 20
139#define PERIPH_REV_MASK 0xf
140#define PERIPH_REV_R0P0 0
141#define PERIPH_REV_R1P0 1
142#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900143
144#define CR0_PERIPH_REQ_SET (1 << 0)
145#define CR0_BOOT_EN_SET (1 << 1)
146#define CR0_BOOT_MAN_NS (1 << 2)
147#define CR0_NUM_CHANS_SHIFT 4
148#define CR0_NUM_CHANS_MASK 0x7
149#define CR0_NUM_PERIPH_SHIFT 12
150#define CR0_NUM_PERIPH_MASK 0x1f
151#define CR0_NUM_EVENTS_SHIFT 17
152#define CR0_NUM_EVENTS_MASK 0x1f
153
154#define CR1_ICACHE_LEN_SHIFT 0
155#define CR1_ICACHE_LEN_MASK 0x7
156#define CR1_NUM_ICACHELINES_SHIFT 4
157#define CR1_NUM_ICACHELINES_MASK 0xf
158
159#define CRD_DATA_WIDTH_SHIFT 0
160#define CRD_DATA_WIDTH_MASK 0x7
161#define CRD_WR_CAP_SHIFT 4
162#define CRD_WR_CAP_MASK 0x7
163#define CRD_WR_Q_DEP_SHIFT 8
164#define CRD_WR_Q_DEP_MASK 0xf
165#define CRD_RD_CAP_SHIFT 12
166#define CRD_RD_CAP_MASK 0x7
167#define CRD_RD_Q_DEP_SHIFT 16
168#define CRD_RD_Q_DEP_MASK 0xf
169#define CRD_DATA_BUFF_SHIFT 20
170#define CRD_DATA_BUFF_MASK 0x3ff
171
172#define PART 0x330
173#define DESIGNER 0x41
174#define REVISION 0x0
175#define INTEG_CFG 0x0
176#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177
Boojin Kimb7d861d2011-12-26 18:49:52 +0900178#define PL330_STATE_STOPPED (1 << 0)
179#define PL330_STATE_EXECUTING (1 << 1)
180#define PL330_STATE_WFE (1 << 2)
181#define PL330_STATE_FAULTING (1 << 3)
182#define PL330_STATE_COMPLETING (1 << 4)
183#define PL330_STATE_WFP (1 << 5)
184#define PL330_STATE_KILLING (1 << 6)
185#define PL330_STATE_FAULT_COMPLETING (1 << 7)
186#define PL330_STATE_CACHEMISS (1 << 8)
187#define PL330_STATE_UPDTPC (1 << 9)
188#define PL330_STATE_ATBARRIER (1 << 10)
189#define PL330_STATE_QUEUEBUSY (1 << 11)
190#define PL330_STATE_INVALID (1 << 15)
191
192#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
193 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194
195#define CMD_DMAADDH 0x54
196#define CMD_DMAEND 0x00
197#define CMD_DMAFLUSHP 0x35
198#define CMD_DMAGO 0xa0
199#define CMD_DMALD 0x04
200#define CMD_DMALDP 0x25
201#define CMD_DMALP 0x20
202#define CMD_DMALPEND 0x28
203#define CMD_DMAKILL 0x01
204#define CMD_DMAMOV 0xbc
205#define CMD_DMANOP 0x18
206#define CMD_DMARMB 0x12
207#define CMD_DMASEV 0x34
208#define CMD_DMAST 0x08
209#define CMD_DMASTP 0x29
210#define CMD_DMASTZ 0x0c
211#define CMD_DMAWFE 0x36
212#define CMD_DMAWFP 0x30
213#define CMD_DMAWMB 0x13
214
215#define SZ_DMAADDH 3
216#define SZ_DMAEND 1
217#define SZ_DMAFLUSHP 2
218#define SZ_DMALD 1
219#define SZ_DMALDP 2
220#define SZ_DMALP 2
221#define SZ_DMALPEND 2
222#define SZ_DMAKILL 1
223#define SZ_DMAMOV 6
224#define SZ_DMANOP 1
225#define SZ_DMARMB 1
226#define SZ_DMASEV 2
227#define SZ_DMAST 1
228#define SZ_DMASTP 2
229#define SZ_DMASTZ 1
230#define SZ_DMAWFE 2
231#define SZ_DMAWFP 2
232#define SZ_DMAWMB 1
233#define SZ_DMAGO 6
234
235#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
236#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237
238#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
239#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
240
241/*
242 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
243 * at 1byte/burst for P<->M and M<->M respectively.
244 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
245 * should be enough for P<->M and M<->M respectively.
246 */
247#define MCODE_BUFF_PER_REQ 256
248
Boojin Kimb7d861d2011-12-26 18:49:52 +0900249/* Use this _only_ to wait on transient states */
250#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
251
252#ifdef PL330_DEBUG_MCGEN
253static unsigned cmd_line;
254#define PL330_DBGCMD_DUMP(off, x...) do { \
255 printk("%x:", cmd_line); \
256 printk(x); \
257 cmd_line += off; \
258 } while (0)
259#define PL330_DBGMC_START(addr) (cmd_line = addr)
260#else
261#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
262#define PL330_DBGMC_START(addr) do {} while (0)
263#endif
264
265/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000266
Jassi Brarb3040e42010-05-23 20:28:19 -0700267#define NR_DEFAULT_DESC 16
268
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +0100269/* Delay for runtime PM autosuspend, ms */
270#define PL330_AUTOSUSPEND_DELAY 20
271
Boojin Kimb7d861d2011-12-26 18:49:52 +0900272/* Populated by the PL330 core driver for DMA API driver's info */
273struct pl330_config {
274 u32 periph_id;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900275#define DMAC_MODE_NS (1 << 0)
276 unsigned int mode;
277 unsigned int data_bus_width:10; /* In number of bits */
Liviu Dudau1f0a5cb2014-11-06 17:20:12 +0000278 unsigned int data_buf_dep:11;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900279 unsigned int num_chan:4;
280 unsigned int num_peri:6;
281 u32 peri_ns;
282 unsigned int num_events:6;
283 u32 irq_ns;
284};
285
Boojin Kimb7d861d2011-12-26 18:49:52 +0900286/**
287 * Request Configuration.
288 * The PL330 core does not modify this and uses the last
289 * working configuration if the request doesn't provide any.
290 *
291 * The Client may want to provide this info only for the
292 * first request and a request with new settings.
293 */
294struct pl330_reqcfg {
295 /* Address Incrementing */
296 unsigned dst_inc:1;
297 unsigned src_inc:1;
298
299 /*
300 * For now, the SRC & DST protection levels
301 * and burst size/length are assumed same.
302 */
303 bool nonsecure;
304 bool privileged;
305 bool insnaccess;
306 unsigned brst_len:5;
307 unsigned brst_size:3; /* in power of 2 */
308
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +0200309 enum pl330_cachectrl dcctl;
310 enum pl330_cachectrl scctl;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900311 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900312 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900313};
314
315/*
316 * One cycle of DMAC operation.
317 * There may be more than one xfer in a request.
318 */
319struct pl330_xfer {
320 u32 src_addr;
321 u32 dst_addr;
322 /* Size to xfer */
323 u32 bytes;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900324};
325
326/* The xfer callbacks are made with one of these arguments. */
327enum pl330_op_err {
328 /* The all xfers in the request were success. */
329 PL330_ERR_NONE,
330 /* If req aborted due to global error. */
331 PL330_ERR_ABORT,
332 /* If req failed due to problem with Channel. */
333 PL330_ERR_FAIL,
334};
335
Boojin Kimb7d861d2011-12-26 18:49:52 +0900336enum dmamov_dst {
337 SAR = 0,
338 CCR,
339 DAR,
340};
341
342enum pl330_dst {
343 SRC = 0,
344 DST,
345};
346
347enum pl330_cond {
348 SINGLE,
349 BURST,
350 ALWAYS,
351};
352
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200353struct dma_pl330_desc;
354
Boojin Kimb7d861d2011-12-26 18:49:52 +0900355struct _pl330_req {
356 u32 mc_bus;
357 void *mc_cpu;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200358 struct dma_pl330_desc *desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900359};
360
361/* ToBeDone for tasklet */
362struct _pl330_tbd {
363 bool reset_dmac;
364 bool reset_mngr;
365 u8 reset_chan;
366};
367
368/* A DMAC Thread */
369struct pl330_thread {
370 u8 id;
371 int ev;
372 /* If the channel is not yet acquired by any client */
373 bool free;
374 /* Parent DMAC */
375 struct pl330_dmac *dmac;
376 /* Only two at a time */
377 struct _pl330_req req[2];
378 /* Index of the last enqueued request */
379 unsigned lstenq;
380 /* Index of the last submitted request or -1 if the DMA is stopped */
381 int req_running;
382};
383
384enum pl330_dmac_state {
385 UNINIT,
386 INIT,
387 DYING,
388};
389
Jassi Brarb3040e42010-05-23 20:28:19 -0700390enum desc_status {
391 /* In the DMAC pool */
392 FREE,
393 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900394 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700395 * Also may be sitting on the work_list.
396 */
397 PREP,
398 /*
399 * Sitting on the work_list and already submitted
400 * to the PL330 core. Not more than two descriptors
401 * of a channel can be BUSY at any time.
402 */
403 BUSY,
404 /*
405 * Sitting on the channel work_list but xfer done
406 * by PL330 core
407 */
408 DONE,
409};
410
411struct dma_pl330_chan {
412 /* Schedule desc completion */
413 struct tasklet_struct task;
414
415 /* DMA-Engine Channel */
416 struct dma_chan chan;
417
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +0100418 /* List of submitted descriptors */
419 struct list_head submitted_list;
420 /* List of issued descriptors */
Jassi Brarb3040e42010-05-23 20:28:19 -0700421 struct list_head work_list;
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +0200422 /* List of completed descriptors */
423 struct list_head completed_list;
Jassi Brarb3040e42010-05-23 20:28:19 -0700424
425 /* Pointer to the DMAC that manages this channel,
426 * NULL if the channel is available to be acquired.
427 * As the parent, this DMAC also provides descriptors
428 * to the channel.
429 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200430 struct pl330_dmac *dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -0700431
432 /* To protect channel manipulation */
433 spinlock_t lock;
434
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +0200435 /*
436 * Hardware channel thread of PL330 DMAC. NULL if the channel is
437 * available.
Jassi Brarb3040e42010-05-23 20:28:19 -0700438 */
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +0200439 struct pl330_thread *thread;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900440
441 /* For D-to-M and M-to-D channels */
442 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900443 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900444 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900445
446 /* for cyclic capability */
447 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700448};
449
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200450struct pl330_dmac {
Jassi Brarb3040e42010-05-23 20:28:19 -0700451 /* DMA-Engine Device */
452 struct dma_device ddma;
453
Lars-Peter Clausenb714b842013-11-25 16:07:46 +0100454 /* Holds info about sg limitations */
455 struct device_dma_parameters dma_parms;
456
Jassi Brarb3040e42010-05-23 20:28:19 -0700457 /* Pool of descriptors available for the DMAC's channels */
458 struct list_head desc_pool;
459 /* To protect desc_pool manipulation */
460 spinlock_t pool_lock;
461
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200462 /* Size of MicroCode buffers for each channel. */
463 unsigned mcbufsz;
464 /* ioremap'ed address of PL330 registers. */
465 void __iomem *base;
466 /* Populated by the PL330 core driver during pl330_add */
467 struct pl330_config pcfg;
468
469 spinlock_t lock;
470 /* Maximum possible events/irqs */
471 int events[32];
472 /* BUS address of MicroCode buffer */
473 dma_addr_t mcode_bus;
474 /* CPU address of MicroCode buffer */
475 void *mcode_cpu;
476 /* List of all Channel threads */
477 struct pl330_thread *channels;
478 /* Pointer to the MANAGER thread */
479 struct pl330_thread *manager;
480 /* To handle bad news in interrupt */
481 struct tasklet_struct tasks;
482 struct _pl330_tbd dmac_tbd;
483 /* State of DMAC operation */
484 enum pl330_dmac_state state;
485 /* Holds list of reqs with due callbacks */
486 struct list_head req_done;
487
Jassi Brarb3040e42010-05-23 20:28:19 -0700488 /* Peripheral channels connected to this DMAC */
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +0100489 unsigned int num_peripherals;
Rob Herring4e0e6102011-07-25 16:05:04 -0500490 struct dma_pl330_chan *peripherals; /* keep at end */
Jassi Brarb3040e42010-05-23 20:28:19 -0700491};
492
493struct dma_pl330_desc {
494 /* To attach to a queue as child */
495 struct list_head node;
496
497 /* Descriptor for the DMA Engine API */
498 struct dma_async_tx_descriptor txd;
499
500 /* Xfer for PL330 core */
501 struct pl330_xfer px;
502
503 struct pl330_reqcfg rqcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -0700504
505 enum desc_status status;
506
Robert Baldygaaee4d1f2015-02-11 13:23:17 +0100507 int bytes_requested;
508 bool last;
509
Jassi Brarb3040e42010-05-23 20:28:19 -0700510 /* The channel which currently holds this desc */
511 struct dma_pl330_chan *pchan;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200512
513 enum dma_transfer_direction rqtype;
514 /* Index of peripheral for the xfer. */
515 unsigned peri:5;
516 /* Hook to attach to DMAC's list of reqs with due callback */
517 struct list_head rqd;
518};
519
520struct _xfer_spec {
521 u32 ccr;
522 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -0700523};
524
Boojin Kimb7d861d2011-12-26 18:49:52 +0900525static inline bool _queue_empty(struct pl330_thread *thrd)
526{
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +0200527 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900528}
529
530static inline bool _queue_full(struct pl330_thread *thrd)
531{
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +0200532 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900533}
534
535static inline bool is_manager(struct pl330_thread *thrd)
536{
Lars-Peter Clausenfbbcd9b2014-07-06 20:32:28 +0200537 return thrd->dmac->manager == thrd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900538}
539
540/* If manager of the thread is in Non-Secure mode */
541static inline bool _manager_ns(struct pl330_thread *thrd)
542{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200543 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900544}
545
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900546static inline u32 get_revision(u32 periph_id)
547{
548 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
549}
550
Boojin Kimb7d861d2011-12-26 18:49:52 +0900551static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
552 enum pl330_dst da, u16 val)
553{
554 if (dry_run)
555 return SZ_DMAADDH;
556
557 buf[0] = CMD_DMAADDH;
558 buf[0] |= (da << 1);
559 *((u16 *)&buf[1]) = val;
560
561 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
562 da == 1 ? "DA" : "SA", val);
563
564 return SZ_DMAADDH;
565}
566
567static inline u32 _emit_END(unsigned dry_run, u8 buf[])
568{
569 if (dry_run)
570 return SZ_DMAEND;
571
572 buf[0] = CMD_DMAEND;
573
574 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
575
576 return SZ_DMAEND;
577}
578
579static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
580{
581 if (dry_run)
582 return SZ_DMAFLUSHP;
583
584 buf[0] = CMD_DMAFLUSHP;
585
586 peri &= 0x1f;
587 peri <<= 3;
588 buf[1] = peri;
589
590 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
591
592 return SZ_DMAFLUSHP;
593}
594
595static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
596{
597 if (dry_run)
598 return SZ_DMALD;
599
600 buf[0] = CMD_DMALD;
601
602 if (cond == SINGLE)
603 buf[0] |= (0 << 1) | (1 << 0);
604 else if (cond == BURST)
605 buf[0] |= (1 << 1) | (1 << 0);
606
607 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
608 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
609
610 return SZ_DMALD;
611}
612
613static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
614 enum pl330_cond cond, u8 peri)
615{
616 if (dry_run)
617 return SZ_DMALDP;
618
619 buf[0] = CMD_DMALDP;
620
621 if (cond == BURST)
622 buf[0] |= (1 << 1);
623
624 peri &= 0x1f;
625 peri <<= 3;
626 buf[1] = peri;
627
628 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
629 cond == SINGLE ? 'S' : 'B', peri >> 3);
630
631 return SZ_DMALDP;
632}
633
634static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
635 unsigned loop, u8 cnt)
636{
637 if (dry_run)
638 return SZ_DMALP;
639
640 buf[0] = CMD_DMALP;
641
642 if (loop)
643 buf[0] |= (1 << 1);
644
645 cnt--; /* DMAC increments by 1 internally */
646 buf[1] = cnt;
647
648 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
649
650 return SZ_DMALP;
651}
652
653struct _arg_LPEND {
654 enum pl330_cond cond;
655 bool forever;
656 unsigned loop;
657 u8 bjump;
658};
659
660static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
661 const struct _arg_LPEND *arg)
662{
663 enum pl330_cond cond = arg->cond;
664 bool forever = arg->forever;
665 unsigned loop = arg->loop;
666 u8 bjump = arg->bjump;
667
668 if (dry_run)
669 return SZ_DMALPEND;
670
671 buf[0] = CMD_DMALPEND;
672
673 if (loop)
674 buf[0] |= (1 << 2);
675
676 if (!forever)
677 buf[0] |= (1 << 4);
678
679 if (cond == SINGLE)
680 buf[0] |= (0 << 1) | (1 << 0);
681 else if (cond == BURST)
682 buf[0] |= (1 << 1) | (1 << 0);
683
684 buf[1] = bjump;
685
686 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
687 forever ? "FE" : "END",
688 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
689 loop ? '1' : '0',
690 bjump);
691
692 return SZ_DMALPEND;
693}
694
695static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
696{
697 if (dry_run)
698 return SZ_DMAKILL;
699
700 buf[0] = CMD_DMAKILL;
701
702 return SZ_DMAKILL;
703}
704
705static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
706 enum dmamov_dst dst, u32 val)
707{
708 if (dry_run)
709 return SZ_DMAMOV;
710
711 buf[0] = CMD_DMAMOV;
712 buf[1] = dst;
713 *((u32 *)&buf[2]) = val;
714
715 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
716 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
717
718 return SZ_DMAMOV;
719}
720
721static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
722{
723 if (dry_run)
724 return SZ_DMANOP;
725
726 buf[0] = CMD_DMANOP;
727
728 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
729
730 return SZ_DMANOP;
731}
732
733static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
734{
735 if (dry_run)
736 return SZ_DMARMB;
737
738 buf[0] = CMD_DMARMB;
739
740 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
741
742 return SZ_DMARMB;
743}
744
745static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
746{
747 if (dry_run)
748 return SZ_DMASEV;
749
750 buf[0] = CMD_DMASEV;
751
752 ev &= 0x1f;
753 ev <<= 3;
754 buf[1] = ev;
755
756 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
757
758 return SZ_DMASEV;
759}
760
761static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
762{
763 if (dry_run)
764 return SZ_DMAST;
765
766 buf[0] = CMD_DMAST;
767
768 if (cond == SINGLE)
769 buf[0] |= (0 << 1) | (1 << 0);
770 else if (cond == BURST)
771 buf[0] |= (1 << 1) | (1 << 0);
772
773 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
774 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
775
776 return SZ_DMAST;
777}
778
779static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
780 enum pl330_cond cond, u8 peri)
781{
782 if (dry_run)
783 return SZ_DMASTP;
784
785 buf[0] = CMD_DMASTP;
786
787 if (cond == BURST)
788 buf[0] |= (1 << 1);
789
790 peri &= 0x1f;
791 peri <<= 3;
792 buf[1] = peri;
793
794 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
795 cond == SINGLE ? 'S' : 'B', peri >> 3);
796
797 return SZ_DMASTP;
798}
799
800static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
801{
802 if (dry_run)
803 return SZ_DMASTZ;
804
805 buf[0] = CMD_DMASTZ;
806
807 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
808
809 return SZ_DMASTZ;
810}
811
812static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
813 unsigned invalidate)
814{
815 if (dry_run)
816 return SZ_DMAWFE;
817
818 buf[0] = CMD_DMAWFE;
819
820 ev &= 0x1f;
821 ev <<= 3;
822 buf[1] = ev;
823
824 if (invalidate)
825 buf[1] |= (1 << 1);
826
827 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
828 ev >> 3, invalidate ? ", I" : "");
829
830 return SZ_DMAWFE;
831}
832
833static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
834 enum pl330_cond cond, u8 peri)
835{
836 if (dry_run)
837 return SZ_DMAWFP;
838
839 buf[0] = CMD_DMAWFP;
840
841 if (cond == SINGLE)
842 buf[0] |= (0 << 1) | (0 << 0);
843 else if (cond == BURST)
844 buf[0] |= (1 << 1) | (0 << 0);
845 else
846 buf[0] |= (0 << 1) | (1 << 0);
847
848 peri &= 0x1f;
849 peri <<= 3;
850 buf[1] = peri;
851
852 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
853 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
854
855 return SZ_DMAWFP;
856}
857
858static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
859{
860 if (dry_run)
861 return SZ_DMAWMB;
862
863 buf[0] = CMD_DMAWMB;
864
865 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
866
867 return SZ_DMAWMB;
868}
869
870struct _arg_GO {
871 u8 chan;
872 u32 addr;
873 unsigned ns;
874};
875
876static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
877 const struct _arg_GO *arg)
878{
879 u8 chan = arg->chan;
880 u32 addr = arg->addr;
881 unsigned ns = arg->ns;
882
883 if (dry_run)
884 return SZ_DMAGO;
885
886 buf[0] = CMD_DMAGO;
887 buf[0] |= (ns << 1);
888
889 buf[1] = chan & 0x7;
890
891 *((u32 *)&buf[2]) = addr;
892
893 return SZ_DMAGO;
894}
895
896#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
897
898/* Returns Time-Out */
899static bool _until_dmac_idle(struct pl330_thread *thrd)
900{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200901 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900902 unsigned long loops = msecs_to_loops(5);
903
904 do {
905 /* Until Manager is Idle */
906 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
907 break;
908
909 cpu_relax();
910 } while (--loops);
911
912 if (!loops)
913 return true;
914
915 return false;
916}
917
918static inline void _execute_DBGINSN(struct pl330_thread *thrd,
919 u8 insn[], bool as_manager)
920{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200921 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900922 u32 val;
923
924 val = (insn[0] << 16) | (insn[1] << 24);
925 if (!as_manager) {
926 val |= (1 << 0);
927 val |= (thrd->id << 8); /* Channel Number */
928 }
929 writel(val, regs + DBGINST0);
930
931 val = *((u32 *)&insn[2]);
932 writel(val, regs + DBGINST1);
933
934 /* If timed out due to halted state-machine */
935 if (_until_dmac_idle(thrd)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200936 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
Boojin Kimb7d861d2011-12-26 18:49:52 +0900937 return;
938 }
939
940 /* Get going */
941 writel(0, regs + DBGCMD);
942}
943
Boojin Kimb7d861d2011-12-26 18:49:52 +0900944static inline u32 _state(struct pl330_thread *thrd)
945{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200946 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900947 u32 val;
948
949 if (is_manager(thrd))
950 val = readl(regs + DS) & 0xf;
951 else
952 val = readl(regs + CS(thrd->id)) & 0xf;
953
954 switch (val) {
955 case DS_ST_STOP:
956 return PL330_STATE_STOPPED;
957 case DS_ST_EXEC:
958 return PL330_STATE_EXECUTING;
959 case DS_ST_CMISS:
960 return PL330_STATE_CACHEMISS;
961 case DS_ST_UPDTPC:
962 return PL330_STATE_UPDTPC;
963 case DS_ST_WFE:
964 return PL330_STATE_WFE;
965 case DS_ST_FAULT:
966 return PL330_STATE_FAULTING;
967 case DS_ST_ATBRR:
968 if (is_manager(thrd))
969 return PL330_STATE_INVALID;
970 else
971 return PL330_STATE_ATBARRIER;
972 case DS_ST_QBUSY:
973 if (is_manager(thrd))
974 return PL330_STATE_INVALID;
975 else
976 return PL330_STATE_QUEUEBUSY;
977 case DS_ST_WFP:
978 if (is_manager(thrd))
979 return PL330_STATE_INVALID;
980 else
981 return PL330_STATE_WFP;
982 case DS_ST_KILL:
983 if (is_manager(thrd))
984 return PL330_STATE_INVALID;
985 else
986 return PL330_STATE_KILLING;
987 case DS_ST_CMPLT:
988 if (is_manager(thrd))
989 return PL330_STATE_INVALID;
990 else
991 return PL330_STATE_COMPLETING;
992 case DS_ST_FLTCMP:
993 if (is_manager(thrd))
994 return PL330_STATE_INVALID;
995 else
996 return PL330_STATE_FAULT_COMPLETING;
997 default:
998 return PL330_STATE_INVALID;
999 }
1000}
1001
1002static void _stop(struct pl330_thread *thrd)
1003{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001004 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001005 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1006
1007 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1008 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1009
1010 /* Return if nothing needs to be done */
1011 if (_state(thrd) == PL330_STATE_COMPLETING
1012 || _state(thrd) == PL330_STATE_KILLING
1013 || _state(thrd) == PL330_STATE_STOPPED)
1014 return;
1015
1016 _emit_KILL(0, insn);
1017
1018 /* Stop generating interrupts for SEV */
1019 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1020
1021 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1022}
1023
1024/* Start doing req 'idx' of thread 'thrd' */
1025static bool _trigger(struct pl330_thread *thrd)
1026{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001027 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001028 struct _pl330_req *req;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001029 struct dma_pl330_desc *desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001030 struct _arg_GO go;
1031 unsigned ns;
1032 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1033 int idx;
1034
1035 /* Return if already ACTIVE */
1036 if (_state(thrd) != PL330_STATE_STOPPED)
1037 return true;
1038
1039 idx = 1 - thrd->lstenq;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001040 if (thrd->req[idx].desc != NULL) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001041 req = &thrd->req[idx];
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001042 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001043 idx = thrd->lstenq;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001044 if (thrd->req[idx].desc != NULL)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001045 req = &thrd->req[idx];
1046 else
1047 req = NULL;
1048 }
1049
1050 /* Return if no request */
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001051 if (!req)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001052 return true;
1053
Addy Ke0091b9d2014-12-08 19:28:20 +08001054 /* Return if req is running */
1055 if (idx == thrd->req_running)
1056 return true;
1057
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001058 desc = req->desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001059
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001060 ns = desc->rqcfg.nonsecure ? 1 : 0;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001061
1062 /* See 'Abort Sources' point-4 at Page 2-25 */
1063 if (_manager_ns(thrd) && !ns)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001064 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001065 __func__, __LINE__);
1066
1067 go.chan = thrd->id;
1068 go.addr = req->mc_bus;
1069 go.ns = ns;
1070 _emit_GO(0, insn, &go);
1071
1072 /* Set to generate interrupts for SEV */
1073 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1074
1075 /* Only manager can execute GO */
1076 _execute_DBGINSN(thrd, insn, true);
1077
1078 thrd->req_running = idx;
1079
1080 return true;
1081}
1082
1083static bool _start(struct pl330_thread *thrd)
1084{
1085 switch (_state(thrd)) {
1086 case PL330_STATE_FAULT_COMPLETING:
1087 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1088
1089 if (_state(thrd) == PL330_STATE_KILLING)
1090 UNTIL(thrd, PL330_STATE_STOPPED)
1091
1092 case PL330_STATE_FAULTING:
1093 _stop(thrd);
1094
1095 case PL330_STATE_KILLING:
1096 case PL330_STATE_COMPLETING:
1097 UNTIL(thrd, PL330_STATE_STOPPED)
1098
1099 case PL330_STATE_STOPPED:
1100 return _trigger(thrd);
1101
1102 case PL330_STATE_WFP:
1103 case PL330_STATE_QUEUEBUSY:
1104 case PL330_STATE_ATBARRIER:
1105 case PL330_STATE_UPDTPC:
1106 case PL330_STATE_CACHEMISS:
1107 case PL330_STATE_EXECUTING:
1108 return true;
1109
1110 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1111 default:
1112 return false;
1113 }
1114}
1115
1116static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1117 const struct _xfer_spec *pxs, int cyc)
1118{
1119 int off = 0;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001120 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001121
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001122 /* check lock-up free version */
1123 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1124 while (cyc--) {
1125 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1126 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1127 }
1128 } else {
1129 while (cyc--) {
1130 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1131 off += _emit_RMB(dry_run, &buf[off]);
1132 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1133 off += _emit_WMB(dry_run, &buf[off]);
1134 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001135 }
1136
1137 return off;
1138}
1139
1140static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1141 const struct _xfer_spec *pxs, int cyc)
1142{
1143 int off = 0;
1144
1145 while (cyc--) {
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001146 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1147 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001148 off += _emit_ST(dry_run, &buf[off], ALWAYS);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001149 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001150 }
1151
1152 return off;
1153}
1154
1155static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1156 const struct _xfer_spec *pxs, int cyc)
1157{
1158 int off = 0;
1159
1160 while (cyc--) {
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001161 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001162 off += _emit_LD(dry_run, &buf[off], ALWAYS);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001163 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1164 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001165 }
1166
1167 return off;
1168}
1169
1170static int _bursts(unsigned dry_run, u8 buf[],
1171 const struct _xfer_spec *pxs, int cyc)
1172{
1173 int off = 0;
1174
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001175 switch (pxs->desc->rqtype) {
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001176 case DMA_MEM_TO_DEV:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001177 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1178 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001179 case DMA_DEV_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001180 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1181 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001182 case DMA_MEM_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001183 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1184 break;
1185 default:
1186 off += 0x40000000; /* Scare off the Client */
1187 break;
1188 }
1189
1190 return off;
1191}
1192
1193/* Returns bytes consumed and updates bursts */
1194static inline int _loop(unsigned dry_run, u8 buf[],
1195 unsigned long *bursts, const struct _xfer_spec *pxs)
1196{
1197 int cyc, cycmax, szlp, szlpend, szbrst, off;
1198 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1199 struct _arg_LPEND lpend;
1200
1201 /* Max iterations possible in DMALP is 256 */
1202 if (*bursts >= 256*256) {
1203 lcnt1 = 256;
1204 lcnt0 = 256;
1205 cyc = *bursts / lcnt1 / lcnt0;
1206 } else if (*bursts > 256) {
1207 lcnt1 = 256;
1208 lcnt0 = *bursts / lcnt1;
1209 cyc = 1;
1210 } else {
1211 lcnt1 = *bursts;
1212 lcnt0 = 0;
1213 cyc = 1;
1214 }
1215
1216 szlp = _emit_LP(1, buf, 0, 0);
1217 szbrst = _bursts(1, buf, pxs, 1);
1218
1219 lpend.cond = ALWAYS;
1220 lpend.forever = false;
1221 lpend.loop = 0;
1222 lpend.bjump = 0;
1223 szlpend = _emit_LPEND(1, buf, &lpend);
1224
1225 if (lcnt0) {
1226 szlp *= 2;
1227 szlpend *= 2;
1228 }
1229
1230 /*
1231 * Max bursts that we can unroll due to limit on the
1232 * size of backward jump that can be encoded in DMALPEND
1233 * which is 8-bits and hence 255
1234 */
1235 cycmax = (255 - (szlp + szlpend)) / szbrst;
1236
1237 cyc = (cycmax < cyc) ? cycmax : cyc;
1238
1239 off = 0;
1240
1241 if (lcnt0) {
1242 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1243 ljmp0 = off;
1244 }
1245
1246 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1247 ljmp1 = off;
1248
1249 off += _bursts(dry_run, &buf[off], pxs, cyc);
1250
1251 lpend.cond = ALWAYS;
1252 lpend.forever = false;
1253 lpend.loop = 1;
1254 lpend.bjump = off - ljmp1;
1255 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1256
1257 if (lcnt0) {
1258 lpend.cond = ALWAYS;
1259 lpend.forever = false;
1260 lpend.loop = 0;
1261 lpend.bjump = off - ljmp0;
1262 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1263 }
1264
1265 *bursts = lcnt1 * cyc;
1266 if (lcnt0)
1267 *bursts *= lcnt0;
1268
1269 return off;
1270}
1271
1272static inline int _setup_loops(unsigned dry_run, u8 buf[],
1273 const struct _xfer_spec *pxs)
1274{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001275 struct pl330_xfer *x = &pxs->desc->px;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001276 u32 ccr = pxs->ccr;
1277 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1278 int off = 0;
1279
1280 while (bursts) {
1281 c = bursts;
1282 off += _loop(dry_run, &buf[off], &c, pxs);
1283 bursts -= c;
1284 }
1285
1286 return off;
1287}
1288
1289static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1290 const struct _xfer_spec *pxs)
1291{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001292 struct pl330_xfer *x = &pxs->desc->px;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001293 int off = 0;
1294
1295 /* DMAMOV SAR, x->src_addr */
1296 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1297 /* DMAMOV DAR, x->dst_addr */
1298 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1299
1300 /* Setup Loop(s) */
1301 off += _setup_loops(dry_run, &buf[off], pxs);
1302
1303 return off;
1304}
1305
1306/*
1307 * A req is a sequence of one or more xfer units.
1308 * Returns the number of bytes taken to setup the MC for the req.
1309 */
1310static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1311 unsigned index, struct _xfer_spec *pxs)
1312{
1313 struct _pl330_req *req = &thrd->req[index];
1314 struct pl330_xfer *x;
1315 u8 *buf = req->mc_cpu;
1316 int off = 0;
1317
1318 PL330_DBGMC_START(req->mc_bus);
1319
1320 /* DMAMOV CCR, ccr */
1321 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1322
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001323 x = &pxs->desc->px;
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001324 /* Error if xfer length is not aligned at burst size */
1325 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1326 return -EINVAL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001327
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001328 off += _setup_xfer(dry_run, &buf[off], pxs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001329
1330 /* DMASEV peripheral/event */
1331 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1332 /* DMAEND */
1333 off += _emit_END(dry_run, &buf[off]);
1334
1335 return off;
1336}
1337
1338static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1339{
1340 u32 ccr = 0;
1341
1342 if (rqc->src_inc)
1343 ccr |= CC_SRCINC;
1344
1345 if (rqc->dst_inc)
1346 ccr |= CC_DSTINC;
1347
1348 /* We set same protection levels for Src and DST for now */
1349 if (rqc->privileged)
1350 ccr |= CC_SRCPRI | CC_DSTPRI;
1351 if (rqc->nonsecure)
1352 ccr |= CC_SRCNS | CC_DSTNS;
1353 if (rqc->insnaccess)
1354 ccr |= CC_SRCIA | CC_DSTIA;
1355
1356 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1357 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1358
1359 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1360 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1361
1362 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1363 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1364
1365 ccr |= (rqc->swap << CC_SWAP_SHFT);
1366
1367 return ccr;
1368}
1369
Boojin Kimb7d861d2011-12-26 18:49:52 +09001370/*
1371 * Submit a list of xfers after which the client wants notification.
1372 * Client is not notified after each xfer unit, just once after all
1373 * xfer units are done or some error occurs.
1374 */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001375static int pl330_submit_req(struct pl330_thread *thrd,
1376 struct dma_pl330_desc *desc)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001377{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001378 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001379 struct _xfer_spec xs;
1380 unsigned long flags;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001381 unsigned idx;
1382 u32 ccr;
1383 int ret = 0;
1384
Boojin Kimb7d861d2011-12-26 18:49:52 +09001385 if (pl330->state == DYING
1386 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001387 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001388 __func__, __LINE__);
1389 return -EAGAIN;
1390 }
1391
1392 /* If request for non-existing peripheral */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001393 if (desc->rqtype != DMA_MEM_TO_MEM &&
1394 desc->peri >= pl330->pcfg.num_peri) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001395 dev_info(thrd->dmac->ddma.dev,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001396 "%s:%d Invalid peripheral(%u)!\n",
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001397 __func__, __LINE__, desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001398 return -EINVAL;
1399 }
1400
1401 spin_lock_irqsave(&pl330->lock, flags);
1402
1403 if (_queue_full(thrd)) {
1404 ret = -EAGAIN;
1405 goto xfer_exit;
1406 }
1407
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001408 /* Prefer Secure Channel */
1409 if (!_manager_ns(thrd))
1410 desc->rqcfg.nonsecure = 0;
1411 else
1412 desc->rqcfg.nonsecure = 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001413
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001414 ccr = _prepare_ccr(&desc->rqcfg);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001415
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001416 idx = thrd->req[0].desc == NULL ? 0 : 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001417
1418 xs.ccr = ccr;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001419 xs.desc = desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001420
1421 /* First dry run to check if req is acceptable */
1422 ret = _setup_req(1, thrd, idx, &xs);
1423 if (ret < 0)
1424 goto xfer_exit;
1425
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001426 if (ret > pl330->mcbufsz / 2) {
1427 dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001428 __func__, __LINE__);
1429 ret = -ENOMEM;
1430 goto xfer_exit;
1431 }
1432
1433 /* Hook the request */
1434 thrd->lstenq = idx;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001435 thrd->req[idx].desc = desc;
Lars-Peter Clausenbe025322014-07-06 20:32:24 +02001436 _setup_req(0, thrd, idx, &xs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001437
1438 ret = 0;
1439
1440xfer_exit:
1441 spin_unlock_irqrestore(&pl330->lock, flags);
1442
1443 return ret;
1444}
1445
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001446static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001447{
Javier Martinez Canillasb1e51d72014-07-19 03:21:47 +02001448 struct dma_pl330_chan *pch;
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001449 unsigned long flags;
1450
Javier Martinez Canillasb1e51d72014-07-19 03:21:47 +02001451 if (!desc)
1452 return;
1453
1454 pch = desc->pchan;
1455
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001456 /* If desc aborted */
1457 if (!pch)
1458 return;
1459
1460 spin_lock_irqsave(&pch->lock, flags);
1461
1462 desc->status = DONE;
1463
1464 spin_unlock_irqrestore(&pch->lock, flags);
1465
1466 tasklet_schedule(&pch->task);
1467}
1468
Boojin Kimb7d861d2011-12-26 18:49:52 +09001469static void pl330_dotask(unsigned long data)
1470{
1471 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001472 unsigned long flags;
1473 int i;
1474
1475 spin_lock_irqsave(&pl330->lock, flags);
1476
1477 /* The DMAC itself gone nuts */
1478 if (pl330->dmac_tbd.reset_dmac) {
1479 pl330->state = DYING;
1480 /* Reset the manager too */
1481 pl330->dmac_tbd.reset_mngr = true;
1482 /* Clear the reset flag */
1483 pl330->dmac_tbd.reset_dmac = false;
1484 }
1485
1486 if (pl330->dmac_tbd.reset_mngr) {
1487 _stop(pl330->manager);
1488 /* Reset all channels */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001489 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001490 /* Clear the reset flag */
1491 pl330->dmac_tbd.reset_mngr = false;
1492 }
1493
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001494 for (i = 0; i < pl330->pcfg.num_chan; i++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001495
1496 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1497 struct pl330_thread *thrd = &pl330->channels[i];
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001498 void __iomem *regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001499 enum pl330_op_err err;
1500
1501 _stop(thrd);
1502
1503 if (readl(regs + FSC) & (1 << thrd->id))
1504 err = PL330_ERR_FAIL;
1505 else
1506 err = PL330_ERR_ABORT;
1507
1508 spin_unlock_irqrestore(&pl330->lock, flags);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001509 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1510 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001511 spin_lock_irqsave(&pl330->lock, flags);
1512
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001513 thrd->req[0].desc = NULL;
1514 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001515 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001516
1517 /* Clear the reset flag */
1518 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1519 }
1520 }
1521
1522 spin_unlock_irqrestore(&pl330->lock, flags);
1523
1524 return;
1525}
1526
1527/* Returns 1 if state was updated, 0 otherwise */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001528static int pl330_update(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001529{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001530 struct dma_pl330_desc *descdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001531 unsigned long flags;
1532 void __iomem *regs;
1533 u32 val;
1534 int id, ev, ret = 0;
1535
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001536 regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001537
1538 spin_lock_irqsave(&pl330->lock, flags);
1539
1540 val = readl(regs + FSM) & 0x1;
1541 if (val)
1542 pl330->dmac_tbd.reset_mngr = true;
1543 else
1544 pl330->dmac_tbd.reset_mngr = false;
1545
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001546 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001547 pl330->dmac_tbd.reset_chan |= val;
1548 if (val) {
1549 int i = 0;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001550 while (i < pl330->pcfg.num_chan) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001551 if (val & (1 << i)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001552 dev_info(pl330->ddma.dev,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001553 "Reset Channel-%d\t CS-%x FTC-%x\n",
1554 i, readl(regs + CS(i)),
1555 readl(regs + FTC(i)));
1556 _stop(&pl330->channels[i]);
1557 }
1558 i++;
1559 }
1560 }
1561
1562 /* Check which event happened i.e, thread notified */
1563 val = readl(regs + ES);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001564 if (pl330->pcfg.num_events < 32
1565 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001566 pl330->dmac_tbd.reset_dmac = true;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001567 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1568 __LINE__);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001569 ret = 1;
1570 goto updt_exit;
1571 }
1572
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001573 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001574 if (val & (1 << ev)) { /* Event occurred */
1575 struct pl330_thread *thrd;
1576 u32 inten = readl(regs + INTEN);
1577 int active;
1578
1579 /* Clear the event */
1580 if (inten & (1 << ev))
1581 writel(1 << ev, regs + INTCLR);
1582
1583 ret = 1;
1584
1585 id = pl330->events[ev];
1586
1587 thrd = &pl330->channels[id];
1588
1589 active = thrd->req_running;
1590 if (active == -1) /* Aborted */
1591 continue;
1592
Javi Merinofdec53d2012-06-13 15:07:00 +01001593 /* Detach the req */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001594 descdone = thrd->req[active].desc;
1595 thrd->req[active].desc = NULL;
Javi Merinofdec53d2012-06-13 15:07:00 +01001596
Addy Ke0091b9d2014-12-08 19:28:20 +08001597 thrd->req_running = -1;
1598
Boojin Kimb7d861d2011-12-26 18:49:52 +09001599 /* Get going again ASAP */
1600 _start(thrd);
1601
1602 /* For now, just make a list of callbacks to be done */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001603 list_add_tail(&descdone->rqd, &pl330->req_done);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001604 }
1605 }
1606
1607 /* Now that we are in no hurry, do the callbacks */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001608 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1609 list_del(&descdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001610 spin_unlock_irqrestore(&pl330->lock, flags);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001611 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001612 spin_lock_irqsave(&pl330->lock, flags);
1613 }
1614
1615updt_exit:
1616 spin_unlock_irqrestore(&pl330->lock, flags);
1617
1618 if (pl330->dmac_tbd.reset_dmac
1619 || pl330->dmac_tbd.reset_mngr
1620 || pl330->dmac_tbd.reset_chan) {
1621 ret = 1;
1622 tasklet_schedule(&pl330->tasks);
1623 }
1624
1625 return ret;
1626}
1627
Boojin Kimb7d861d2011-12-26 18:49:52 +09001628/* Reserve an event */
1629static inline int _alloc_event(struct pl330_thread *thrd)
1630{
1631 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001632 int ev;
1633
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001634 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001635 if (pl330->events[ev] == -1) {
1636 pl330->events[ev] = thrd->id;
1637 return ev;
1638 }
1639
1640 return -1;
1641}
1642
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001643static bool _chan_ns(const struct pl330_dmac *pl330, int i)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001644{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001645 return pl330->pcfg.irq_ns & (1 << i);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001646}
1647
1648/* Upon success, returns IdentityToken for the
1649 * allocated channel, NULL otherwise.
1650 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001651static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001652{
1653 struct pl330_thread *thrd = NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001654 unsigned long flags;
1655 int chans, i;
1656
Boojin Kimb7d861d2011-12-26 18:49:52 +09001657 if (pl330->state == DYING)
1658 return NULL;
1659
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001660 chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001661
1662 spin_lock_irqsave(&pl330->lock, flags);
1663
1664 for (i = 0; i < chans; i++) {
1665 thrd = &pl330->channels[i];
1666 if ((thrd->free) && (!_manager_ns(thrd) ||
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001667 _chan_ns(pl330, i))) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001668 thrd->ev = _alloc_event(thrd);
1669 if (thrd->ev >= 0) {
1670 thrd->free = false;
1671 thrd->lstenq = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001672 thrd->req[0].desc = NULL;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001673 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001674 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001675 break;
1676 }
1677 }
1678 thrd = NULL;
1679 }
1680
1681 spin_unlock_irqrestore(&pl330->lock, flags);
1682
1683 return thrd;
1684}
1685
1686/* Release an event */
1687static inline void _free_event(struct pl330_thread *thrd, int ev)
1688{
1689 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001690
1691 /* If the event is valid and was held by the thread */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001692 if (ev >= 0 && ev < pl330->pcfg.num_events
Boojin Kimb7d861d2011-12-26 18:49:52 +09001693 && pl330->events[ev] == thrd->id)
1694 pl330->events[ev] = -1;
1695}
1696
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02001697static void pl330_release_channel(struct pl330_thread *thrd)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001698{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001699 struct pl330_dmac *pl330;
1700 unsigned long flags;
1701
1702 if (!thrd || thrd->free)
1703 return;
1704
1705 _stop(thrd);
1706
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001707 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1708 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001709
1710 pl330 = thrd->dmac;
1711
1712 spin_lock_irqsave(&pl330->lock, flags);
1713 _free_event(thrd, thrd->ev);
1714 thrd->free = true;
1715 spin_unlock_irqrestore(&pl330->lock, flags);
1716}
1717
1718/* Initialize the structure for PL330 configuration, that can be used
1719 * by the client driver the make best use of the DMAC
1720 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001721static void read_dmac_config(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001722{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001723 void __iomem *regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001724 u32 val;
1725
1726 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1727 val &= CRD_DATA_WIDTH_MASK;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001728 pl330->pcfg.data_bus_width = 8 * (1 << val);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001729
1730 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1731 val &= CRD_DATA_BUFF_MASK;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001732 pl330->pcfg.data_buf_dep = val + 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001733
1734 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1735 val &= CR0_NUM_CHANS_MASK;
1736 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001737 pl330->pcfg.num_chan = val;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001738
1739 val = readl(regs + CR0);
1740 if (val & CR0_PERIPH_REQ_SET) {
1741 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1742 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001743 pl330->pcfg.num_peri = val;
1744 pl330->pcfg.peri_ns = readl(regs + CR4);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001745 } else {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001746 pl330->pcfg.num_peri = 0;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001747 }
1748
1749 val = readl(regs + CR0);
1750 if (val & CR0_BOOT_MAN_NS)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001751 pl330->pcfg.mode |= DMAC_MODE_NS;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001752 else
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001753 pl330->pcfg.mode &= ~DMAC_MODE_NS;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001754
1755 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1756 val &= CR0_NUM_EVENTS_MASK;
1757 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001758 pl330->pcfg.num_events = val;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001759
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001760 pl330->pcfg.irq_ns = readl(regs + CR3);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001761}
1762
1763static inline void _reset_thread(struct pl330_thread *thrd)
1764{
1765 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001766
1767 thrd->req[0].mc_cpu = pl330->mcode_cpu
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001768 + (thrd->id * pl330->mcbufsz);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001769 thrd->req[0].mc_bus = pl330->mcode_bus
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001770 + (thrd->id * pl330->mcbufsz);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001771 thrd->req[0].desc = NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001772
1773 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001774 + pl330->mcbufsz / 2;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001775 thrd->req[1].mc_bus = thrd->req[0].mc_bus
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001776 + pl330->mcbufsz / 2;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001777 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001778
1779 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001780}
1781
1782static int dmac_alloc_threads(struct pl330_dmac *pl330)
1783{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001784 int chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001785 struct pl330_thread *thrd;
1786 int i;
1787
1788 /* Allocate 1 Manager and 'chans' Channel threads */
1789 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1790 GFP_KERNEL);
1791 if (!pl330->channels)
1792 return -ENOMEM;
1793
1794 /* Init Channel threads */
1795 for (i = 0; i < chans; i++) {
1796 thrd = &pl330->channels[i];
1797 thrd->id = i;
1798 thrd->dmac = pl330;
1799 _reset_thread(thrd);
1800 thrd->free = true;
1801 }
1802
1803 /* MANAGER is indexed at the end */
1804 thrd = &pl330->channels[chans];
1805 thrd->id = chans;
1806 thrd->dmac = pl330;
1807 thrd->free = false;
1808 pl330->manager = thrd;
1809
1810 return 0;
1811}
1812
1813static int dmac_alloc_resources(struct pl330_dmac *pl330)
1814{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001815 int chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001816 int ret;
1817
1818 /*
1819 * Alloc MicroCode buffer for 'chans' Channel threads.
1820 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1821 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001822 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1823 chans * pl330->mcbufsz,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001824 &pl330->mcode_bus, GFP_KERNEL);
1825 if (!pl330->mcode_cpu) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001826 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001827 __func__, __LINE__);
1828 return -ENOMEM;
1829 }
1830
1831 ret = dmac_alloc_threads(pl330);
1832 if (ret) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001833 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001834 __func__, __LINE__);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001835 dma_free_coherent(pl330->ddma.dev,
1836 chans * pl330->mcbufsz,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001837 pl330->mcode_cpu, pl330->mcode_bus);
1838 return ret;
1839 }
1840
1841 return 0;
1842}
1843
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001844static int pl330_add(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001845{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001846 void __iomem *regs;
1847 int i, ret;
1848
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001849 regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001850
1851 /* Check if we can handle this DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001852 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1853 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1854 pl330->pcfg.periph_id);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001855 return -EINVAL;
1856 }
1857
1858 /* Read the configuration of the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001859 read_dmac_config(pl330);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001860
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001861 if (pl330->pcfg.num_events == 0) {
1862 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001863 __func__, __LINE__);
1864 return -EINVAL;
1865 }
1866
Boojin Kimb7d861d2011-12-26 18:49:52 +09001867 spin_lock_init(&pl330->lock);
1868
1869 INIT_LIST_HEAD(&pl330->req_done);
1870
1871 /* Use default MC buffer size if not provided */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001872 if (!pl330->mcbufsz)
1873 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001874
1875 /* Mark all events as free */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001876 for (i = 0; i < pl330->pcfg.num_events; i++)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001877 pl330->events[i] = -1;
1878
1879 /* Allocate resources needed by the DMAC */
1880 ret = dmac_alloc_resources(pl330);
1881 if (ret) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001882 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
Boojin Kimb7d861d2011-12-26 18:49:52 +09001883 return ret;
1884 }
1885
1886 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1887
1888 pl330->state = INIT;
1889
1890 return 0;
1891}
1892
1893static int dmac_free_threads(struct pl330_dmac *pl330)
1894{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001895 struct pl330_thread *thrd;
1896 int i;
1897
1898 /* Release Channel threads */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001899 for (i = 0; i < pl330->pcfg.num_chan; i++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001900 thrd = &pl330->channels[i];
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02001901 pl330_release_channel(thrd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001902 }
1903
1904 /* Free memory */
1905 kfree(pl330->channels);
1906
1907 return 0;
1908}
1909
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001910static void pl330_del(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001911{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001912 pl330->state = UNINIT;
1913
1914 tasklet_kill(&pl330->tasks);
1915
1916 /* Free DMAC resources */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001917 dmac_free_threads(pl330);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001918
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001919 dma_free_coherent(pl330->ddma.dev,
1920 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1921 pl330->mcode_bus);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001922}
1923
Thomas Abraham3e2ec132011-10-24 11:43:02 +02001924/* forward declaration */
1925static struct amba_driver pl330_driver;
1926
Jassi Brarb3040e42010-05-23 20:28:19 -07001927static inline struct dma_pl330_chan *
1928to_pchan(struct dma_chan *ch)
1929{
1930 if (!ch)
1931 return NULL;
1932
1933 return container_of(ch, struct dma_pl330_chan, chan);
1934}
1935
1936static inline struct dma_pl330_desc *
1937to_desc(struct dma_async_tx_descriptor *tx)
1938{
1939 return container_of(tx, struct dma_pl330_desc, txd);
1940}
1941
Jassi Brarb3040e42010-05-23 20:28:19 -07001942static inline void fill_queue(struct dma_pl330_chan *pch)
1943{
1944 struct dma_pl330_desc *desc;
1945 int ret;
1946
1947 list_for_each_entry(desc, &pch->work_list, node) {
1948
1949 /* If already submitted */
1950 if (desc->status == BUSY)
Jassi Brar30fb9802013-02-13 16:13:14 +05301951 continue;
Jassi Brarb3040e42010-05-23 20:28:19 -07001952
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001953 ret = pl330_submit_req(pch->thread, desc);
Jassi Brarb3040e42010-05-23 20:28:19 -07001954 if (!ret) {
1955 desc->status = BUSY;
Jassi Brarb3040e42010-05-23 20:28:19 -07001956 } else if (ret == -EAGAIN) {
1957 /* QFull or DMAC Dying */
1958 break;
1959 } else {
1960 /* Unacceptable request */
1961 desc->status = DONE;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001962 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
Jassi Brarb3040e42010-05-23 20:28:19 -07001963 __func__, __LINE__, desc->txd.cookie);
1964 tasklet_schedule(&pch->task);
1965 }
1966 }
1967}
1968
1969static void pl330_tasklet(unsigned long data)
1970{
1971 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
1972 struct dma_pl330_desc *desc, *_dt;
1973 unsigned long flags;
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01001974 bool power_down = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07001975
1976 spin_lock_irqsave(&pch->lock, flags);
1977
1978 /* Pick up ripe tomatoes */
1979 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
1980 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05301981 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05301982 dma_cookie_complete(&desc->txd);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02001983 list_move_tail(&desc->node, &pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07001984 }
1985
1986 /* Try to submit a req imm. next to the last completed cookie */
1987 fill_queue(pch);
1988
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01001989 if (list_empty(&pch->work_list)) {
1990 spin_lock(&pch->thread->dmac->lock);
1991 _stop(pch->thread);
1992 spin_unlock(&pch->thread->dmac->lock);
1993 power_down = true;
1994 } else {
1995 /* Make sure the PL330 Channel thread is active */
1996 spin_lock(&pch->thread->dmac->lock);
1997 _start(pch->thread);
1998 spin_unlock(&pch->thread->dmac->lock);
1999 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002000
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002001 while (!list_empty(&pch->completed_list)) {
2002 dma_async_tx_callback callback;
2003 void *callback_param;
Jassi Brarb3040e42010-05-23 20:28:19 -07002004
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002005 desc = list_first_entry(&pch->completed_list,
2006 struct dma_pl330_desc, node);
2007
2008 callback = desc->txd.callback;
2009 callback_param = desc->txd.callback_param;
2010
2011 if (pch->cyclic) {
2012 desc->status = PREP;
2013 list_move_tail(&desc->node, &pch->work_list);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002014 if (power_down) {
2015 spin_lock(&pch->thread->dmac->lock);
2016 _start(pch->thread);
2017 spin_unlock(&pch->thread->dmac->lock);
2018 power_down = false;
2019 }
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002020 } else {
2021 desc->status = FREE;
2022 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2023 }
2024
Dan Williamsd38a8c62013-10-18 19:35:23 +02002025 dma_descriptor_unmap(&desc->txd);
2026
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002027 if (callback) {
2028 spin_unlock_irqrestore(&pch->lock, flags);
2029 callback(callback_param);
2030 spin_lock_irqsave(&pch->lock, flags);
2031 }
2032 }
2033 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002034
2035 /* If work list empty, power down */
2036 if (power_down) {
2037 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2038 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2039 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002040}
2041
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002042bool pl330_filter(struct dma_chan *chan, void *param)
2043{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002044 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002045
2046 if (chan->device->dev->driver != &pl330_driver.drv)
2047 return false;
2048
Thomas Abrahamcd072512011-10-24 11:43:11 +02002049 peri_id = chan->private;
Dan Carpenter2f986ec2013-11-08 12:51:16 +03002050 return *peri_id == (unsigned long)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002051}
2052EXPORT_SYMBOL(pl330_filter);
2053
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302054static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2055 struct of_dma *ofdma)
2056{
2057 int count = dma_spec->args_count;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002058 struct pl330_dmac *pl330 = ofdma->of_dma_data;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002059 unsigned int chan_id;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302060
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002061 if (!pl330)
2062 return NULL;
2063
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302064 if (count != 1)
2065 return NULL;
2066
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002067 chan_id = dma_spec->args[0];
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002068 if (chan_id >= pl330->num_peripherals)
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002069 return NULL;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302070
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002071 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302072}
2073
Jassi Brarb3040e42010-05-23 20:28:19 -07002074static int pl330_alloc_chan_resources(struct dma_chan *chan)
2075{
2076 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002077 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002078 unsigned long flags;
2079
2080 spin_lock_irqsave(&pch->lock, flags);
2081
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002082 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002083 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002084
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002085 pch->thread = pl330_request_channel(pl330);
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002086 if (!pch->thread) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002087 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302088 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002089 }
2090
2091 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2092
2093 spin_unlock_irqrestore(&pch->lock, flags);
2094
2095 return 1;
2096}
2097
Maxime Ripard740aa952014-11-17 14:42:29 +01002098static int pl330_config(struct dma_chan *chan,
2099 struct dma_slave_config *slave_config)
2100{
2101 struct dma_pl330_chan *pch = to_pchan(chan);
2102
2103 if (slave_config->direction == DMA_MEM_TO_DEV) {
2104 if (slave_config->dst_addr)
2105 pch->fifo_addr = slave_config->dst_addr;
2106 if (slave_config->dst_addr_width)
2107 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2108 if (slave_config->dst_maxburst)
2109 pch->burst_len = slave_config->dst_maxburst;
2110 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2111 if (slave_config->src_addr)
2112 pch->fifo_addr = slave_config->src_addr;
2113 if (slave_config->src_addr_width)
2114 pch->burst_sz = __ffs(slave_config->src_addr_width);
2115 if (slave_config->src_maxburst)
2116 pch->burst_len = slave_config->src_maxburst;
2117 }
2118
2119 return 0;
2120}
2121
2122static int pl330_terminate_all(struct dma_chan *chan)
Jassi Brarb3040e42010-05-23 20:28:19 -07002123{
2124 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002125 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -07002126 unsigned long flags;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002127 struct pl330_dmac *pl330 = pch->dmac;
Boojin Kimae43b882011-09-02 09:44:32 +09002128 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002129
Maxime Ripard740aa952014-11-17 14:42:29 +01002130 spin_lock_irqsave(&pch->lock, flags);
2131 spin_lock(&pl330->lock);
2132 _stop(pch->thread);
2133 spin_unlock(&pl330->lock);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002134
Maxime Ripard740aa952014-11-17 14:42:29 +01002135 pch->thread->req[0].desc = NULL;
2136 pch->thread->req[1].desc = NULL;
2137 pch->thread->req_running = -1;
Lars-Peter Clausenc26939e2014-07-06 20:32:32 +02002138
Maxime Ripard740aa952014-11-17 14:42:29 +01002139 /* Mark all desc done */
2140 list_for_each_entry(desc, &pch->submitted_list, node) {
2141 desc->status = FREE;
2142 dma_cookie_complete(&desc->txd);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002143 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002144
Maxime Ripard740aa952014-11-17 14:42:29 +01002145 list_for_each_entry(desc, &pch->work_list , node) {
2146 desc->status = FREE;
2147 dma_cookie_complete(&desc->txd);
2148 }
2149
2150 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2151 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2152 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2153 spin_unlock_irqrestore(&pch->lock, flags);
2154
Jassi Brarb3040e42010-05-23 20:28:19 -07002155 return 0;
2156}
2157
2158static void pl330_free_chan_resources(struct dma_chan *chan)
2159{
2160 struct dma_pl330_chan *pch = to_pchan(chan);
2161 unsigned long flags;
2162
Jassi Brarb3040e42010-05-23 20:28:19 -07002163 tasklet_kill(&pch->task);
2164
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002165 pm_runtime_get_sync(pch->dmac->ddma.dev);
Bartlomiej Zolnierkiewiczda331ba2013-07-03 15:00:43 -07002166 spin_lock_irqsave(&pch->lock, flags);
2167
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002168 pl330_release_channel(pch->thread);
2169 pch->thread = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002170
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002171 if (pch->cyclic)
2172 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2173
Jassi Brarb3040e42010-05-23 20:28:19 -07002174 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002175 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2176 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002177}
2178
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002179int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2180 struct dma_pl330_desc *desc)
2181{
2182 struct pl330_thread *thrd = pch->thread;
2183 struct pl330_dmac *pl330 = pch->dmac;
2184 void __iomem *regs = thrd->dmac->base;
2185 u32 val, addr;
2186
2187 pm_runtime_get_sync(pl330->ddma.dev);
2188 val = addr = 0;
2189 if (desc->rqcfg.src_inc) {
2190 val = readl(regs + SA(thrd->id));
2191 addr = desc->px.src_addr;
2192 } else {
2193 val = readl(regs + DA(thrd->id));
2194 addr = desc->px.dst_addr;
2195 }
2196 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2197 pm_runtime_put_autosuspend(pl330->ddma.dev);
2198 return val - addr;
2199}
2200
Jassi Brarb3040e42010-05-23 20:28:19 -07002201static enum dma_status
2202pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2203 struct dma_tx_state *txstate)
2204{
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002205 enum dma_status ret;
2206 unsigned long flags;
2207 struct dma_pl330_desc *desc, *running = NULL;
2208 struct dma_pl330_chan *pch = to_pchan(chan);
2209 unsigned int transferred, residual = 0;
2210
2211 ret = dma_cookie_status(chan, cookie, txstate);
2212
2213 if (!txstate)
2214 return ret;
2215
2216 if (ret == DMA_COMPLETE)
2217 goto out;
2218
2219 spin_lock_irqsave(&pch->lock, flags);
2220
2221 if (pch->thread->req_running != -1)
2222 running = pch->thread->req[pch->thread->req_running].desc;
2223
2224 /* Check in pending list */
2225 list_for_each_entry(desc, &pch->work_list, node) {
2226 if (desc->status == DONE)
2227 transferred = desc->bytes_requested;
2228 else if (running && desc == running)
2229 transferred =
2230 pl330_get_current_xferred_count(pch, desc);
2231 else
2232 transferred = 0;
2233 residual += desc->bytes_requested - transferred;
2234 if (desc->txd.cookie == cookie) {
2235 ret = desc->status;
2236 break;
2237 }
2238 if (desc->last)
2239 residual = 0;
2240 }
2241 spin_unlock_irqrestore(&pch->lock, flags);
2242
2243out:
2244 dma_set_residue(txstate, residual);
2245
2246 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002247}
2248
2249static void pl330_issue_pending(struct dma_chan *chan)
2250{
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002251 struct dma_pl330_chan *pch = to_pchan(chan);
2252 unsigned long flags;
2253
2254 spin_lock_irqsave(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002255 if (list_empty(&pch->work_list)) {
2256 /*
2257 * Warn on nothing pending. Empty submitted_list may
2258 * break our pm_runtime usage counter as it is
2259 * updated on work_list emptiness status.
2260 */
2261 WARN_ON(list_empty(&pch->submitted_list));
2262 pm_runtime_get_sync(pch->dmac->ddma.dev);
2263 }
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002264 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2265 spin_unlock_irqrestore(&pch->lock, flags);
2266
2267 pl330_tasklet((unsigned long)pch);
Jassi Brarb3040e42010-05-23 20:28:19 -07002268}
2269
2270/*
2271 * We returned the last one of the circular list of descriptor(s)
2272 * from prep_xxx, so the argument to submit corresponds to the last
2273 * descriptor of the list.
2274 */
2275static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2276{
2277 struct dma_pl330_desc *desc, *last = to_desc(tx);
2278 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2279 dma_cookie_t cookie;
2280 unsigned long flags;
2281
2282 spin_lock_irqsave(&pch->lock, flags);
2283
2284 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002285 while (!list_empty(&last->node)) {
2286 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002287 if (pch->cyclic) {
2288 desc->txd.callback = last->txd.callback;
2289 desc->txd.callback_param = last->txd.callback_param;
2290 }
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002291 last->last = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002292
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002293 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002294
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002295 list_move_tail(&desc->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002296 }
2297
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002298 last->last = true;
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002299 cookie = dma_cookie_assign(&last->txd);
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002300 list_add_tail(&last->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002301 spin_unlock_irqrestore(&pch->lock, flags);
2302
2303 return cookie;
2304}
2305
2306static inline void _init_desc(struct dma_pl330_desc *desc)
2307{
Jassi Brarb3040e42010-05-23 20:28:19 -07002308 desc->rqcfg.swap = SWAP_NO;
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +02002309 desc->rqcfg.scctl = CCTRL0;
2310 desc->rqcfg.dcctl = CCTRL0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002311 desc->txd.tx_submit = pl330_tx_submit;
2312
2313 INIT_LIST_HEAD(&desc->node);
2314}
2315
2316/* Returns the number of descriptors added to the DMAC pool */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002317static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002318{
2319 struct dma_pl330_desc *desc;
2320 unsigned long flags;
2321 int i;
2322
Will Deacon0baf8f62013-12-02 18:01:30 +00002323 desc = kcalloc(count, sizeof(*desc), flg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002324 if (!desc)
2325 return 0;
2326
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002327 spin_lock_irqsave(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002328
2329 for (i = 0; i < count; i++) {
2330 _init_desc(&desc[i]);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002331 list_add_tail(&desc[i].node, &pl330->desc_pool);
Jassi Brarb3040e42010-05-23 20:28:19 -07002332 }
2333
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002334 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002335
2336 return count;
2337}
2338
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002339static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
Jassi Brarb3040e42010-05-23 20:28:19 -07002340{
2341 struct dma_pl330_desc *desc = NULL;
2342 unsigned long flags;
2343
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002344 spin_lock_irqsave(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002345
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002346 if (!list_empty(&pl330->desc_pool)) {
2347 desc = list_entry(pl330->desc_pool.next,
Jassi Brarb3040e42010-05-23 20:28:19 -07002348 struct dma_pl330_desc, node);
2349
2350 list_del_init(&desc->node);
2351
2352 desc->status = PREP;
2353 desc->txd.callback = NULL;
2354 }
2355
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002356 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002357
2358 return desc;
2359}
2360
2361static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2362{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002363 struct pl330_dmac *pl330 = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002364 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002365 struct dma_pl330_desc *desc;
2366
2367 /* Pluck one desc from the pool of DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002368 desc = pluck_desc(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002369
2370 /* If the DMAC pool is empty, alloc new */
2371 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002372 if (!add_desc(pl330, GFP_ATOMIC, 1))
Jassi Brarb3040e42010-05-23 20:28:19 -07002373 return NULL;
2374
2375 /* Try again */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002376 desc = pluck_desc(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002377 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002378 dev_err(pch->dmac->ddma.dev,
Jassi Brarb3040e42010-05-23 20:28:19 -07002379 "%s:%d ALERT!\n", __func__, __LINE__);
2380 return NULL;
2381 }
2382 }
2383
2384 /* Initialize the descriptor */
2385 desc->pchan = pch;
2386 desc->txd.cookie = 0;
2387 async_tx_ack(&desc->txd);
2388
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002389 desc->peri = peri_id ? pch->chan.chan_id : 0;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002390 desc->rqcfg.pcfg = &pch->dmac->pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002391
2392 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2393
2394 return desc;
2395}
2396
2397static inline void fill_px(struct pl330_xfer *px,
2398 dma_addr_t dst, dma_addr_t src, size_t len)
2399{
Jassi Brarb3040e42010-05-23 20:28:19 -07002400 px->bytes = len;
2401 px->dst_addr = dst;
2402 px->src_addr = src;
2403}
2404
2405static struct dma_pl330_desc *
2406__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2407 dma_addr_t src, size_t len)
2408{
2409 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2410
2411 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002412 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
Jassi Brarb3040e42010-05-23 20:28:19 -07002413 __func__, __LINE__);
2414 return NULL;
2415 }
2416
2417 /*
2418 * Ideally we should lookout for reqs bigger than
2419 * those that can be programmed with 256 bytes of
2420 * MC buffer, but considering a req size is seldom
2421 * going to be word-unaligned and more than 200MB,
2422 * we take it easy.
2423 * Also, should the limit is reached we'd rather
2424 * have the platform increase MC buffer size than
2425 * complicating this API driver.
2426 */
2427 fill_px(&desc->px, dst, src, len);
2428
2429 return desc;
2430}
2431
2432/* Call after fixing burst size */
2433static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2434{
2435 struct dma_pl330_chan *pch = desc->pchan;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002436 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002437 int burst_len;
2438
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002439 burst_len = pl330->pcfg.data_bus_width / 8;
Jon Medhurstc27f9552014-11-07 18:05:18 +00002440 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002441 burst_len >>= desc->rqcfg.brst_size;
2442
2443 /* src/dst_burst_len can't be more than 16 */
2444 if (burst_len > 16)
2445 burst_len = 16;
2446
2447 while (burst_len > 1) {
2448 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2449 break;
2450 burst_len--;
2451 }
2452
2453 return burst_len;
2454}
2455
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002456static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2457 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002458 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02002459 unsigned long flags)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002460{
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002461 struct dma_pl330_desc *desc = NULL, *first = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002462 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002463 struct pl330_dmac *pl330 = pch->dmac;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002464 unsigned int i;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002465 dma_addr_t dst;
2466 dma_addr_t src;
2467
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002468 if (len % period_len != 0)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002469 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002470
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002471 if (!is_slave_direction(direction)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002472 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002473 __func__, __LINE__);
2474 return NULL;
2475 }
2476
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002477 for (i = 0; i < len / period_len; i++) {
2478 desc = pl330_get_desc(pch);
2479 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002480 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002481 __func__, __LINE__);
2482
2483 if (!first)
2484 return NULL;
2485
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002486 spin_lock_irqsave(&pl330->pool_lock, flags);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002487
2488 while (!list_empty(&first->node)) {
2489 desc = list_entry(first->node.next,
2490 struct dma_pl330_desc, node);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002491 list_move_tail(&desc->node, &pl330->desc_pool);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002492 }
2493
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002494 list_move_tail(&first->node, &pl330->desc_pool);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002495
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002496 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002497
2498 return NULL;
2499 }
2500
2501 switch (direction) {
2502 case DMA_MEM_TO_DEV:
2503 desc->rqcfg.src_inc = 1;
2504 desc->rqcfg.dst_inc = 0;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002505 src = dma_addr;
2506 dst = pch->fifo_addr;
2507 break;
2508 case DMA_DEV_TO_MEM:
2509 desc->rqcfg.src_inc = 0;
2510 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002511 src = pch->fifo_addr;
2512 dst = dma_addr;
2513 break;
2514 default:
2515 break;
2516 }
2517
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002518 desc->rqtype = direction;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002519 desc->rqcfg.brst_size = pch->burst_sz;
2520 desc->rqcfg.brst_len = 1;
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002521 desc->bytes_requested = period_len;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002522 fill_px(&desc->px, dst, src, period_len);
2523
2524 if (!first)
2525 first = desc;
2526 else
2527 list_add_tail(&desc->node, &first->node);
2528
2529 dma_addr += period_len;
2530 }
2531
2532 if (!desc)
2533 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002534
2535 pch->cyclic = true;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002536 desc->txd.flags = flags;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002537
2538 return &desc->txd;
2539}
2540
Jassi Brarb3040e42010-05-23 20:28:19 -07002541static struct dma_async_tx_descriptor *
2542pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2543 dma_addr_t src, size_t len, unsigned long flags)
2544{
2545 struct dma_pl330_desc *desc;
2546 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002547 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002548 int burst;
2549
Rob Herring4e0e6102011-07-25 16:05:04 -05002550 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002551 return NULL;
2552
Jassi Brarb3040e42010-05-23 20:28:19 -07002553 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2554 if (!desc)
2555 return NULL;
2556
2557 desc->rqcfg.src_inc = 1;
2558 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002559 desc->rqtype = DMA_MEM_TO_MEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002560
2561 /* Select max possible burst size */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002562 burst = pl330->pcfg.data_bus_width / 8;
Jassi Brarb3040e42010-05-23 20:28:19 -07002563
Jon Medhurst137bd112014-11-07 18:05:17 +00002564 /*
2565 * Make sure we use a burst size that aligns with all the memcpy
2566 * parameters because our DMA programming algorithm doesn't cope with
2567 * transfers which straddle an entry in the DMA device's MFIFO.
2568 */
2569 while ((src | dst | len) & (burst - 1))
Jassi Brarb3040e42010-05-23 20:28:19 -07002570 burst /= 2;
Jassi Brarb3040e42010-05-23 20:28:19 -07002571
2572 desc->rqcfg.brst_size = 0;
2573 while (burst != (1 << desc->rqcfg.brst_size))
2574 desc->rqcfg.brst_size++;
2575
Jon Medhurst137bd112014-11-07 18:05:17 +00002576 /*
2577 * If burst size is smaller than bus width then make sure we only
2578 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2579 */
2580 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2581 desc->rqcfg.brst_len = 1;
2582
Jassi Brarb3040e42010-05-23 20:28:19 -07002583 desc->rqcfg.brst_len = get_burst_len(desc, len);
2584
2585 desc->txd.flags = flags;
2586
2587 return &desc->txd;
2588}
2589
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002590static void __pl330_giveback_desc(struct pl330_dmac *pl330,
Chanho Park52a9d172013-08-09 20:11:33 +09002591 struct dma_pl330_desc *first)
2592{
2593 unsigned long flags;
2594 struct dma_pl330_desc *desc;
2595
2596 if (!first)
2597 return;
2598
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002599 spin_lock_irqsave(&pl330->pool_lock, flags);
Chanho Park52a9d172013-08-09 20:11:33 +09002600
2601 while (!list_empty(&first->node)) {
2602 desc = list_entry(first->node.next,
2603 struct dma_pl330_desc, node);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002604 list_move_tail(&desc->node, &pl330->desc_pool);
Chanho Park52a9d172013-08-09 20:11:33 +09002605 }
2606
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002607 list_move_tail(&first->node, &pl330->desc_pool);
Chanho Park52a9d172013-08-09 20:11:33 +09002608
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002609 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Chanho Park52a9d172013-08-09 20:11:33 +09002610}
2611
Jassi Brarb3040e42010-05-23 20:28:19 -07002612static struct dma_async_tx_descriptor *
2613pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302614 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002615 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002616{
2617 struct dma_pl330_desc *first, *desc = NULL;
2618 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002619 struct scatterlist *sg;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002620 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002621 dma_addr_t addr;
2622
Thomas Abrahamcd072512011-10-24 11:43:11 +02002623 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002624 return NULL;
2625
Boojin Kim1b9bb712011-09-02 09:44:30 +09002626 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002627
2628 first = NULL;
2629
2630 for_each_sg(sgl, sg, sg_len, i) {
2631
2632 desc = pl330_get_desc(pch);
2633 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002634 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002635
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002636 dev_err(pch->dmac->ddma.dev,
Jassi Brarb3040e42010-05-23 20:28:19 -07002637 "%s:%d Unable to fetch desc\n",
2638 __func__, __LINE__);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002639 __pl330_giveback_desc(pl330, first);
Jassi Brarb3040e42010-05-23 20:28:19 -07002640
2641 return NULL;
2642 }
2643
2644 if (!first)
2645 first = desc;
2646 else
2647 list_add_tail(&desc->node, &first->node);
2648
Vinod Kouldb8196d2011-10-13 22:34:23 +05302649 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002650 desc->rqcfg.src_inc = 1;
2651 desc->rqcfg.dst_inc = 0;
2652 fill_px(&desc->px,
2653 addr, sg_dma_address(sg), sg_dma_len(sg));
2654 } else {
2655 desc->rqcfg.src_inc = 0;
2656 desc->rqcfg.dst_inc = 1;
2657 fill_px(&desc->px,
2658 sg_dma_address(sg), addr, sg_dma_len(sg));
2659 }
2660
Boojin Kim1b9bb712011-09-02 09:44:30 +09002661 desc->rqcfg.brst_size = pch->burst_sz;
Jassi Brarb3040e42010-05-23 20:28:19 -07002662 desc->rqcfg.brst_len = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002663 desc->rqtype = direction;
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002664 desc->bytes_requested = sg_dma_len(sg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002665 }
2666
2667 /* Return the last desc in the chain */
2668 desc->txd.flags = flg;
2669 return &desc->txd;
2670}
2671
2672static irqreturn_t pl330_irq_handler(int irq, void *data)
2673{
2674 if (pl330_update(data))
2675 return IRQ_HANDLED;
2676 else
2677 return IRQ_NONE;
2678}
2679
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002680#define PL330_DMA_BUSWIDTHS \
2681 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2682 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2683 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2684 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2685 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2686
Krzysztof Kozlowskib816ccc2014-11-18 12:17:56 +01002687/*
2688 * Runtime PM callbacks are provided by amba/bus.c driver.
2689 *
2690 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2691 * bus driver will only disable/enable the clock in runtime PM callbacks.
2692 */
2693static int __maybe_unused pl330_suspend(struct device *dev)
2694{
2695 struct amba_device *pcdev = to_amba_device(dev);
2696
2697 pm_runtime_disable(dev);
2698
2699 if (!pm_runtime_status_suspended(dev)) {
2700 /* amba did not disable the clock */
2701 amba_pclk_disable(pcdev);
2702 }
2703 amba_pclk_unprepare(pcdev);
2704
2705 return 0;
2706}
2707
2708static int __maybe_unused pl330_resume(struct device *dev)
2709{
2710 struct amba_device *pcdev = to_amba_device(dev);
2711 int ret;
2712
2713 ret = amba_pclk_prepare(pcdev);
2714 if (ret)
2715 return ret;
2716
2717 if (!pm_runtime_status_suspended(dev))
2718 ret = amba_pclk_enable(pcdev);
2719
2720 pm_runtime_enable(dev);
2721
2722 return ret;
2723}
2724
2725static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2726
Bill Pemberton463a1f82012-11-19 13:22:55 -05002727static int
Russell Kingaa25afa2011-02-19 15:55:00 +00002728pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002729{
2730 struct dma_pl330_platdata *pdat;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002731 struct pl330_config *pcfg;
2732 struct pl330_dmac *pl330;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302733 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002734 struct dma_device *pd;
2735 struct resource *res;
2736 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002737 int num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002738
Jingoo Hand4adcc02013-07-30 17:09:11 +09002739 pdat = dev_get_platdata(&adev->dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002740
Russell King64113012013-06-27 10:29:32 +01002741 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2742 if (ret)
2743 return ret;
2744
Jassi Brarb3040e42010-05-23 20:28:19 -07002745 /* Allocate a new DMAC and its Channels */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002746 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2747 if (!pl330) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002748 dev_err(&adev->dev, "unable to allocate mem\n");
2749 return -ENOMEM;
2750 }
2751
Andrew Jacksoncee42392014-11-06 11:39:47 +00002752 pd = &pl330->ddma;
2753 pd->dev = &adev->dev;
2754
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002755 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002756
2757 res = &adev->res;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002758 pl330->base = devm_ioremap_resource(&adev->dev, res);
2759 if (IS_ERR(pl330->base))
2760 return PTR_ERR(pl330->base);
Jassi Brarb3040e42010-05-23 20:28:19 -07002761
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002762 amba_set_drvdata(adev, pl330);
Boojin Kima2f52032011-09-02 09:44:29 +09002763
Dan Carpenter02808b42013-11-08 12:50:24 +03002764 for (i = 0; i < AMBA_NR_IRQS; i++) {
Michal Simeke98b3ca2013-09-30 08:50:48 +02002765 irq = adev->irq[i];
2766 if (irq) {
2767 ret = devm_request_irq(&adev->dev, irq,
2768 pl330_irq_handler, 0,
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002769 dev_name(&adev->dev), pl330);
Michal Simeke98b3ca2013-09-30 08:50:48 +02002770 if (ret)
2771 return ret;
2772 } else {
2773 break;
2774 }
2775 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002776
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002777 pcfg = &pl330->pcfg;
2778
2779 pcfg->periph_id = adev->periphid;
2780 ret = pl330_add(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002781 if (ret)
Michal Simek173e8382013-09-04 16:40:17 +02002782 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002783
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002784 INIT_LIST_HEAD(&pl330->desc_pool);
2785 spin_lock_init(&pl330->pool_lock);
Jassi Brarb3040e42010-05-23 20:28:19 -07002786
2787 /* Create a descriptor pool of default size */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002788 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
Jassi Brarb3040e42010-05-23 20:28:19 -07002789 dev_warn(&adev->dev, "unable to allocate desc\n");
2790
Jassi Brarb3040e42010-05-23 20:28:19 -07002791 INIT_LIST_HEAD(&pd->channels);
2792
2793 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002794 if (pdat)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002795 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
Olof Johanssonc8473822012-04-08 16:26:19 -07002796 else
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002797 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
Olof Johanssonc8473822012-04-08 16:26:19 -07002798
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002799 pl330->num_peripherals = num_chan;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002800
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002801 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2802 if (!pl330->peripherals) {
Sachin Kamat61c6e752012-09-17 15:20:23 +05302803 ret = -ENOMEM;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002804 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
Sachin Kamate4d43c12012-11-15 06:27:50 +00002805 goto probe_err2;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302806 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002807
Rob Herring4e0e6102011-07-25 16:05:04 -05002808 for (i = 0; i < num_chan; i++) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002809 pch = &pl330->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002810 if (!adev->dev.of_node)
2811 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2812 else
2813 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002814
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002815 INIT_LIST_HEAD(&pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002816 INIT_LIST_HEAD(&pch->work_list);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002817 INIT_LIST_HEAD(&pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002818 spin_lock_init(&pch->lock);
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002819 pch->thread = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002820 pch->chan.device = pd;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002821 pch->dmac = pl330;
Jassi Brarb3040e42010-05-23 20:28:19 -07002822
2823 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002824 list_add_tail(&pch->chan.device_node, &pd->channels);
2825 }
2826
Thomas Abraham93ed5542011-10-24 11:43:31 +02002827 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002828 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002829 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002830 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002831 if (pcfg->num_peri) {
Thomas Abraham93ed5542011-10-24 11:43:31 +02002832 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2833 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302834 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002835 }
2836 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002837
2838 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2839 pd->device_free_chan_resources = pl330_free_chan_resources;
2840 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002841 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07002842 pd->device_tx_status = pl330_tx_status;
2843 pd->device_prep_slave_sg = pl330_prep_slave_sg;
Maxime Ripard740aa952014-11-17 14:42:29 +01002844 pd->device_config = pl330_config;
2845 pd->device_terminate_all = pl330_terminate_all;
Jassi Brarb3040e42010-05-23 20:28:19 -07002846 pd->device_issue_pending = pl330_issue_pending;
Maxime Riparddcabe4562014-11-17 14:42:50 +01002847 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2848 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2849 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002850 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
Jassi Brarb3040e42010-05-23 20:28:19 -07002851
2852 ret = dma_async_device_register(pd);
2853 if (ret) {
2854 dev_err(&adev->dev, "unable to register DMAC\n");
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302855 goto probe_err3;
2856 }
2857
2858 if (adev->dev.of_node) {
2859 ret = of_dma_controller_register(adev->dev.of_node,
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002860 of_dma_pl330_xlate, pl330);
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302861 if (ret) {
2862 dev_err(&adev->dev,
2863 "unable to register DMA to the generic DT DMA helpers\n");
2864 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002865 }
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002866
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002867 adev->dev.dma_parms = &pl330->dma_parms;
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002868
Vinod Kouldbaf6d82013-09-02 21:54:48 +05302869 /*
2870 * This is the limit for transfers with a buswidth of 1, larger
2871 * buswidths will have larger limits.
2872 */
2873 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2874 if (ret)
2875 dev_err(&adev->dev, "unable to set the seg size\n");
2876
Jassi Brarb3040e42010-05-23 20:28:19 -07002877
Jassi Brarb3040e42010-05-23 20:28:19 -07002878 dev_info(&adev->dev,
Liviu Dudau1f0a5cb2014-11-06 17:20:12 +00002879 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
Jassi Brarb3040e42010-05-23 20:28:19 -07002880 dev_info(&adev->dev,
2881 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002882 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2883 pcfg->num_peri, pcfg->num_events);
Jassi Brarb3040e42010-05-23 20:28:19 -07002884
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002885 pm_runtime_irq_safe(&adev->dev);
2886 pm_runtime_use_autosuspend(&adev->dev);
2887 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2888 pm_runtime_mark_last_busy(&adev->dev);
2889 pm_runtime_put_autosuspend(&adev->dev);
2890
Jassi Brarb3040e42010-05-23 20:28:19 -07002891 return 0;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302892probe_err3:
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302893 /* Idle the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002894 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302895 chan.device_node) {
2896
2897 /* Remove the channel */
2898 list_del(&pch->chan.device_node);
2899
2900 /* Flush the channel */
Krzysztof Kozlowski0f5ebab2014-09-29 14:42:20 +02002901 if (pch->thread) {
Maxime Ripard740aa952014-11-17 14:42:29 +01002902 pl330_terminate_all(&pch->chan);
Krzysztof Kozlowski0f5ebab2014-09-29 14:42:20 +02002903 pl330_free_chan_resources(&pch->chan);
2904 }
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302905 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002906probe_err2:
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002907 pl330_del(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002908
2909 return ret;
2910}
2911
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08002912static int pl330_remove(struct amba_device *adev)
Jassi Brarb3040e42010-05-23 20:28:19 -07002913{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002914 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002915 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002916
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002917 pm_runtime_get_noresume(pl330->ddma.dev);
2918
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302919 if (adev->dev.of_node)
2920 of_dma_controller_free(adev->dev.of_node);
Padmavathi Venna421da892013-02-14 09:10:07 +05302921
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002922 dma_async_device_unregister(&pl330->ddma);
Jassi Brarb3040e42010-05-23 20:28:19 -07002923
2924 /* Idle the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002925 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
Jassi Brarb3040e42010-05-23 20:28:19 -07002926 chan.device_node) {
2927
2928 /* Remove the channel */
2929 list_del(&pch->chan.device_node);
2930
2931 /* Flush the channel */
Krzysztof Kozlowski6e4a2a82014-09-29 14:42:21 +02002932 if (pch->thread) {
Maxime Ripard740aa952014-11-17 14:42:29 +01002933 pl330_terminate_all(&pch->chan);
Krzysztof Kozlowski6e4a2a82014-09-29 14:42:21 +02002934 pl330_free_chan_resources(&pch->chan);
2935 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002936 }
2937
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002938 pl330_del(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002939
Jassi Brarb3040e42010-05-23 20:28:19 -07002940 return 0;
2941}
2942
2943static struct amba_id pl330_ids[] = {
2944 {
2945 .id = 0x00041330,
2946 .mask = 0x000fffff,
2947 },
2948 { 0, 0 },
2949};
2950
Dave Martine8fa5162011-10-05 15:15:20 +01002951MODULE_DEVICE_TABLE(amba, pl330_ids);
2952
Jassi Brarb3040e42010-05-23 20:28:19 -07002953static struct amba_driver pl330_driver = {
2954 .drv = {
2955 .owner = THIS_MODULE,
2956 .name = "dma-pl330",
Krzysztof Kozlowskib816ccc2014-11-18 12:17:56 +01002957 .pm = &pl330_pm,
Jassi Brarb3040e42010-05-23 20:28:19 -07002958 },
2959 .id_table = pl330_ids,
2960 .probe = pl330_probe,
2961 .remove = pl330_remove,
2962};
2963
viresh kumar9e5ed092012-03-15 10:40:38 +01002964module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07002965
Jassi Brar046209f2014-12-05 19:07:49 +05302966MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
Jassi Brarb3040e42010-05-23 20:28:19 -07002967MODULE_DESCRIPTION("API Driver for PL330 DMAC");
2968MODULE_LICENSE("GPL");