blob: 45daba726b665fd753a1338244536595a00099f6 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
Jeff Garzik03a8c662006-06-27 07:57:22 -040028 [link no longer provides useful info -jgarzik]
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30*/
31
32#define DRV_NAME "via-rhine"
Roger Luethie84df482007-03-06 19:57:37 +010033#define DRV_VERSION "1.4.3"
34#define DRV_RELDATE "2007-03-06"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36
37/* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41static int max_interrupt_work = 20;
42
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
Dustin Marquessb47157f2007-08-10 14:05:15 -070045#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46 || defined(CONFIG_SPARC) || defined(__ia64__) \
47 || defined(__sh__) || defined(__mips__)
48static int rx_copybreak = 1518;
49#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070050static int rx_copybreak;
Dustin Marquessb47157f2007-08-10 14:05:15 -070051#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Roger Luethib933b4d2006-08-14 23:00:21 -070053/* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
55static int avoid_D3;
56
Linus Torvalds1da177e2005-04-16 15:20:36 -070057/*
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
60 */
61
62/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64static const int multicast_filter_limit = 32;
65
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74#define TX_RING_SIZE 16
75#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
Roger Luethi633949a2006-08-14 23:00:17 -070076#define RX_RING_SIZE 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
78/* Operational parameters that usually are not changed. */
79
80/* Time in jiffies before concluding the transmitter is hung. */
81#define TX_TIMEOUT (2*HZ)
82
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#include <linux/module.h>
86#include <linux/moduleparam.h>
87#include <linux/kernel.h>
88#include <linux/string.h>
89#include <linux/timer.h>
90#include <linux/errno.h>
91#include <linux/ioport.h>
92#include <linux/slab.h>
93#include <linux/interrupt.h>
94#include <linux/pci.h>
Domen Puncer1e7f0bd2005-06-26 18:22:14 -040095#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#include <linux/netdevice.h>
97#include <linux/etherdevice.h>
98#include <linux/skbuff.h>
99#include <linux/init.h>
100#include <linux/delay.h>
101#include <linux/mii.h>
102#include <linux/ethtool.h>
103#include <linux/crc32.h>
104#include <linux/bitops.h>
105#include <asm/processor.h> /* Processor type for cache alignment. */
106#include <asm/io.h>
107#include <asm/irq.h>
108#include <asm/uaccess.h>
Roger Luethie84df482007-03-06 19:57:37 +0100109#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111/* These identify the driver base version and may not be removed. */
Stephen Hemmingerc8de1fc2009-02-26 10:19:31 +0000112static const char version[] __devinitconst =
113 KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE
114 " Written by Donald Becker\n";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115
116/* This driver was written to use PCI memory space. Some early versions
117 of the Rhine may only work correctly with I/O space accesses. */
118#ifdef CONFIG_VIA_RHINE_MMIO
119#define USE_MMIO
120#else
121#endif
122
123MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
124MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
125MODULE_LICENSE("GPL");
126
127module_param(max_interrupt_work, int, 0);
128module_param(debug, int, 0);
129module_param(rx_copybreak, int, 0);
Roger Luethib933b4d2006-08-14 23:00:21 -0700130module_param(avoid_D3, bool, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
132MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
133MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
Roger Luethib933b4d2006-08-14 23:00:21 -0700134MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
136/*
137 Theory of Operation
138
139I. Board Compatibility
140
141This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
142controller.
143
144II. Board-specific settings
145
146Boards with this chip are functional only in a bus-master PCI slot.
147
148Many operational settings are loaded from the EEPROM to the Config word at
149offset 0x78. For most of these settings, this driver assumes that they are
150correct.
151If this driver is compiled to use PCI memory space operations the EEPROM
152must be configured to enable memory ops.
153
154III. Driver operation
155
156IIIa. Ring buffers
157
158This driver uses two statically allocated fixed-size descriptor lists
159formed into rings by a branch from the final descriptor to the beginning of
160the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
161
162IIIb/c. Transmit/Receive Structure
163
164This driver attempts to use a zero-copy receive and transmit scheme.
165
166Alas, all data buffers are required to start on a 32 bit boundary, so
167the driver must often copy transmit packets into bounce buffers.
168
169The driver allocates full frame size skbuffs for the Rx ring buffers at
170open() time and passes the skb->data field to the chip as receive data
171buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
172a fresh skbuff is allocated and the frame is copied to the new skbuff.
173When the incoming frame is larger, the skbuff is passed directly up the
174protocol stack. Buffers consumed this way are replaced by newly allocated
175skbuffs in the last phase of rhine_rx().
176
177The RX_COPYBREAK value is chosen to trade-off the memory wasted by
178using a full-sized skbuff for small frames vs. the copying costs of larger
179frames. New boards are typically used in generously configured machines
180and the underfilled buffers have negligible impact compared to the benefit of
181a single allocation size, so the default value of zero results in never
182copying packets. When copying is done, the cost is usually mitigated by using
183a combined copy/checksum routine. Copying also preloads the cache, which is
184most useful with small frames.
185
186Since the VIA chips are only able to transfer data to buffers on 32 bit
187boundaries, the IP header at offset 14 in an ethernet frame isn't
188longword aligned for further processing. Copying these unaligned buffers
189has the beneficial effect of 16-byte aligning the IP header.
190
191IIId. Synchronization
192
193The driver runs as two independent, single-threaded flows of control. One
194is the send-packet routine, which enforces single-threaded use by the
Wang Chenb74ca3a2008-12-08 01:14:16 -0800195netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
196which is single threaded by the hardware and interrupt handling software.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197
198The send packet thread has partial control over the Tx ring. It locks the
Wang Chenb74ca3a2008-12-08 01:14:16 -0800199netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
200the ring is not available it stops the transmit queue by
201calling netif_stop_queue.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202
203The interrupt handler has exclusive control over the Rx ring and records stats
204from the Tx ring. After reaping the stats, it marks the Tx queue entry as
205empty by incrementing the dirty_tx mark. If at least half of the entries in
206the Rx ring are available the transmit queue is woken up if it was stopped.
207
208IV. Notes
209
210IVb. References
211
212Preliminary VT86C100A manual from http://www.via.com.tw/
213http://www.scyld.com/expert/100mbps.html
214http://www.scyld.com/expert/NWay.html
215ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
216ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
217
218
219IVc. Errata
220
221The VT86C100A manual is not reliable information.
222The 3043 chip does not handle unaligned transmit or receive buffers, resulting
223in significant performance degradation for bounce buffer copies on transmit
224and unaligned IP headers on receive.
225The chip does not pad to minimum transmit length.
226
227*/
228
229
230/* This table drives the PCI probe routines. It's mostly boilerplate in all
231 of the drivers, and will likely be provided by some future kernel.
232 Note the matching code -- the first table entry matchs all 56** cards but
233 second only the 1234 card.
234*/
235
236enum rhine_revs {
237 VT86C100A = 0x00,
238 VTunknown0 = 0x20,
239 VT6102 = 0x40,
240 VT8231 = 0x50, /* Integrated MAC */
241 VT8233 = 0x60, /* Integrated MAC */
242 VT8235 = 0x74, /* Integrated MAC */
243 VT8237 = 0x78, /* Integrated MAC */
244 VTunknown1 = 0x7C,
245 VT6105 = 0x80,
246 VT6105_B0 = 0x83,
247 VT6105L = 0x8A,
248 VT6107 = 0x8C,
249 VTunknown2 = 0x8E,
250 VT6105M = 0x90, /* Management adapter */
251};
252
253enum rhine_quirks {
254 rqWOL = 0x0001, /* Wake-On-LAN support */
255 rqForceReset = 0x0002,
256 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
257 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
258 rqRhineI = 0x0100, /* See comment below */
259};
260/*
261 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
262 * MMIO as well as for the collision counter and the Tx FIFO underflow
263 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
264 */
265
266/* Beware of PCI posted writes */
267#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
268
Jeff Garzik46009c82006-06-27 09:12:38 -0400269static const struct pci_device_id rhine_pci_tbl[] = {
270 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
271 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
272 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
273 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 { } /* terminate list */
275};
276MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
277
278
279/* Offsets to the device registers. */
280enum register_offsets {
281 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
282 ChipCmd1=0x09,
283 IntrStatus=0x0C, IntrEnable=0x0E,
284 MulticastFilter0=0x10, MulticastFilter1=0x14,
285 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
286 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
287 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
288 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
289 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
290 StickyHW=0x83, IntrStatus2=0x84,
291 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
292 WOLcrClr1=0xA6, WOLcgClr=0xA7,
293 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
294};
295
296/* Bits in ConfigD */
297enum backoff_bits {
298 BackOptional=0x01, BackModify=0x02,
299 BackCaptureEffect=0x04, BackRandom=0x08
300};
301
302#ifdef USE_MMIO
303/* Registers we check that mmio and reg are the same. */
304static const int mmio_verify_registers[] = {
305 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
306 0
307};
308#endif
309
310/* Bits in the interrupt status/mask registers. */
311enum intr_status_bits {
312 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
313 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
314 IntrPCIErr=0x0040,
315 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
316 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
317 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
318 IntrRxWakeUp=0x8000,
319 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
320 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
321 IntrTxErrSummary=0x082218,
322};
323
324/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
325enum wol_bits {
326 WOLucast = 0x10,
327 WOLmagic = 0x20,
328 WOLbmcast = 0x30,
329 WOLlnkon = 0x40,
330 WOLlnkoff = 0x80,
331};
332
333/* The Rx and Tx buffer descriptors. */
334struct rx_desc {
Al Viro53c03f52007-08-23 02:33:30 -0400335 __le32 rx_status;
336 __le32 desc_length; /* Chain flag, Buffer/frame length */
337 __le32 addr;
338 __le32 next_desc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339};
340struct tx_desc {
Al Viro53c03f52007-08-23 02:33:30 -0400341 __le32 tx_status;
342 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
343 __le32 addr;
344 __le32 next_desc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345};
346
347/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
348#define TXDESC 0x00e08000
349
350enum rx_status_bits {
351 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
352};
353
354/* Bits in *_desc.*_status */
355enum desc_status_bits {
356 DescOwn=0x80000000
357};
358
359/* Bits in ChipCmd. */
360enum chip_cmd_bits {
361 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
362 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
363 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
364 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
365};
366
367struct rhine_private {
368 /* Descriptor rings */
369 struct rx_desc *rx_ring;
370 struct tx_desc *tx_ring;
371 dma_addr_t rx_ring_dma;
372 dma_addr_t tx_ring_dma;
373
374 /* The addresses of receive-in-place skbuffs. */
375 struct sk_buff *rx_skbuff[RX_RING_SIZE];
376 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
377
378 /* The saved address of a sent-in-place packet/buffer, for later free(). */
379 struct sk_buff *tx_skbuff[TX_RING_SIZE];
380 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
381
Roger Luethi4be5de22006-04-04 20:49:16 +0200382 /* Tx bounce buffers (Rhine-I only) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383 unsigned char *tx_buf[TX_RING_SIZE];
384 unsigned char *tx_bufs;
385 dma_addr_t tx_bufs_dma;
386
387 struct pci_dev *pdev;
388 long pioaddr;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700389 struct net_device *dev;
390 struct napi_struct napi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 struct net_device_stats stats;
392 spinlock_t lock;
393
394 /* Frequently used values: keep some adjacent for cache effect. */
395 u32 quirks;
396 struct rx_desc *rx_head_desc;
397 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
398 unsigned int cur_tx, dirty_tx;
399 unsigned int rx_buf_sz; /* Based on MTU+slack. */
400 u8 wolopts;
401
402 u8 tx_thresh, rx_thresh;
403
404 struct mii_if_info mii_if;
405 void __iomem *base;
406};
407
408static int mdio_read(struct net_device *dev, int phy_id, int location);
409static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
410static int rhine_open(struct net_device *dev);
411static void rhine_tx_timeout(struct net_device *dev);
412static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100413static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414static void rhine_tx(struct net_device *dev);
Roger Luethi633949a2006-08-14 23:00:17 -0700415static int rhine_rx(struct net_device *dev, int limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416static void rhine_error(struct net_device *dev, int intr_status);
417static void rhine_set_rx_mode(struct net_device *dev);
418static struct net_device_stats *rhine_get_stats(struct net_device *dev);
419static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
Jeff Garzik7282d492006-09-13 14:30:00 -0400420static const struct ethtool_ops netdev_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421static int rhine_close(struct net_device *dev);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -0700422static void rhine_shutdown (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423
424#define RHINE_WAIT_FOR(condition) do { \
425 int i=1024; \
426 while (!(condition) && --i) \
427 ; \
428 if (debug > 1 && i < 512) \
429 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
430 DRV_NAME, 1024-i, __func__, __LINE__); \
431} while(0)
432
433static inline u32 get_intr_status(struct net_device *dev)
434{
435 struct rhine_private *rp = netdev_priv(dev);
436 void __iomem *ioaddr = rp->base;
437 u32 intr_status;
438
439 intr_status = ioread16(ioaddr + IntrStatus);
440 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
441 if (rp->quirks & rqStatusWBRace)
442 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
443 return intr_status;
444}
445
446/*
447 * Get power related registers into sane state.
448 * Notify user about past WOL event.
449 */
450static void rhine_power_init(struct net_device *dev)
451{
452 struct rhine_private *rp = netdev_priv(dev);
453 void __iomem *ioaddr = rp->base;
454 u16 wolstat;
455
456 if (rp->quirks & rqWOL) {
457 /* Make sure chip is in power state D0 */
458 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
459
460 /* Disable "force PME-enable" */
461 iowrite8(0x80, ioaddr + WOLcgClr);
462
463 /* Clear power-event config bits (WOL) */
464 iowrite8(0xFF, ioaddr + WOLcrClr);
465 /* More recent cards can manage two additional patterns */
466 if (rp->quirks & rq6patterns)
467 iowrite8(0x03, ioaddr + WOLcrClr1);
468
469 /* Save power-event status bits */
470 wolstat = ioread8(ioaddr + PwrcsrSet);
471 if (rp->quirks & rq6patterns)
472 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
473
474 /* Clear power-event status bits */
475 iowrite8(0xFF, ioaddr + PwrcsrClr);
476 if (rp->quirks & rq6patterns)
477 iowrite8(0x03, ioaddr + PwrcsrClr1);
478
479 if (wolstat) {
480 char *reason;
481 switch (wolstat) {
482 case WOLmagic:
483 reason = "Magic packet";
484 break;
485 case WOLlnkon:
486 reason = "Link went up";
487 break;
488 case WOLlnkoff:
489 reason = "Link went down";
490 break;
491 case WOLucast:
492 reason = "Unicast packet";
493 break;
494 case WOLbmcast:
495 reason = "Multicast/broadcast packet";
496 break;
497 default:
498 reason = "Unknown";
499 }
500 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
501 DRV_NAME, reason);
502 }
503 }
504}
505
506static void rhine_chip_reset(struct net_device *dev)
507{
508 struct rhine_private *rp = netdev_priv(dev);
509 void __iomem *ioaddr = rp->base;
510
511 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
512 IOSYNC;
513
514 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
515 printk(KERN_INFO "%s: Reset not complete yet. "
516 "Trying harder.\n", DRV_NAME);
517
518 /* Force reset */
519 if (rp->quirks & rqForceReset)
520 iowrite8(0x40, ioaddr + MiscCmd);
521
522 /* Reset can take somewhat longer (rare) */
523 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
524 }
525
526 if (debug > 1)
527 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
528 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
529 "failed" : "succeeded");
530}
531
532#ifdef USE_MMIO
533static void enable_mmio(long pioaddr, u32 quirks)
534{
535 int n;
536 if (quirks & rqRhineI) {
537 /* More recent docs say that this bit is reserved ... */
538 n = inb(pioaddr + ConfigA) | 0x20;
539 outb(n, pioaddr + ConfigA);
540 } else {
541 n = inb(pioaddr + ConfigD) | 0x80;
542 outb(n, pioaddr + ConfigD);
543 }
544}
545#endif
546
547/*
548 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
549 * (plus 0x6C for Rhine-I/II)
550 */
551static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
552{
553 struct rhine_private *rp = netdev_priv(dev);
554 void __iomem *ioaddr = rp->base;
555
556 outb(0x20, pioaddr + MACRegEEcsr);
557 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
558
559#ifdef USE_MMIO
560 /*
561 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
562 * MMIO. If reloading EEPROM was done first this could be avoided, but
563 * it is not known if that still works with the "win98-reboot" problem.
564 */
565 enable_mmio(pioaddr, rp->quirks);
566#endif
567
568 /* Turn off EEPROM-controlled wake-up (magic packet) */
569 if (rp->quirks & rqWOL)
570 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
571
572}
573
574#ifdef CONFIG_NET_POLL_CONTROLLER
575static void rhine_poll(struct net_device *dev)
576{
577 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +0100578 rhine_interrupt(dev->irq, (void *)dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579 enable_irq(dev->irq);
580}
581#endif
582
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700583static int rhine_napipoll(struct napi_struct *napi, int budget)
Roger Luethi633949a2006-08-14 23:00:17 -0700584{
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700585 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
586 struct net_device *dev = rp->dev;
Roger Luethi633949a2006-08-14 23:00:17 -0700587 void __iomem *ioaddr = rp->base;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700588 int work_done;
Roger Luethi633949a2006-08-14 23:00:17 -0700589
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700590 work_done = rhine_rx(dev, budget);
Roger Luethi633949a2006-08-14 23:00:17 -0700591
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700592 if (work_done < budget) {
Ben Hutchings288379f2009-01-19 16:43:59 -0800593 napi_complete(napi);
Roger Luethi633949a2006-08-14 23:00:17 -0700594
595 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
596 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
597 IntrTxDone | IntrTxError | IntrTxUnderrun |
598 IntrPCIErr | IntrStatsMax | IntrLinkChange,
599 ioaddr + IntrEnable);
Roger Luethi633949a2006-08-14 23:00:17 -0700600 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700601 return work_done;
Roger Luethi633949a2006-08-14 23:00:17 -0700602}
Roger Luethi633949a2006-08-14 23:00:17 -0700603
Adrian Bunkde4e7c82008-01-30 22:02:05 +0200604static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605{
606 struct rhine_private *rp = netdev_priv(dev);
607
608 /* Reset the chip to erase previous misconfiguration. */
609 rhine_chip_reset(dev);
610
611 /* Rhine-I needs extra time to recuperate before EEPROM reload */
612 if (rp->quirks & rqRhineI)
613 msleep(5);
614
615 /* Reload EEPROM controlled bytes cleared by soft reset */
616 rhine_reload_eeprom(pioaddr, dev);
617}
618
Stephen Hemminger5d1d07d2008-11-21 17:30:11 -0800619static const struct net_device_ops rhine_netdev_ops = {
620 .ndo_open = rhine_open,
621 .ndo_stop = rhine_close,
622 .ndo_start_xmit = rhine_start_tx,
623 .ndo_get_stats = rhine_get_stats,
624 .ndo_set_multicast_list = rhine_set_rx_mode,
625 .ndo_validate_addr = eth_validate_addr,
Stephen Hemmingerfe96aaa2009-01-09 11:13:14 +0000626 .ndo_set_mac_address = eth_mac_addr,
Stephen Hemminger5d1d07d2008-11-21 17:30:11 -0800627 .ndo_do_ioctl = netdev_ioctl,
628 .ndo_tx_timeout = rhine_tx_timeout,
629#ifdef CONFIG_NET_POLL_CONTROLLER
630 .ndo_poll_controller = rhine_poll,
631#endif
632};
633
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634static int __devinit rhine_init_one(struct pci_dev *pdev,
635 const struct pci_device_id *ent)
636{
637 struct net_device *dev;
638 struct rhine_private *rp;
639 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640 u32 quirks;
641 long pioaddr;
642 long memaddr;
643 void __iomem *ioaddr;
644 int io_size, phy_id;
645 const char *name;
646#ifdef USE_MMIO
647 int bar = 1;
648#else
649 int bar = 0;
650#endif
651
652/* when built into the kernel, we only print version if device is found */
653#ifndef MODULE
654 static int printed_version;
655 if (!printed_version++)
656 printk(version);
657#endif
658
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 io_size = 256;
660 phy_id = 0;
661 quirks = 0;
662 name = "Rhine";
Auke Kok44c10132007-06-08 15:46:36 -0700663 if (pdev->revision < VTunknown0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 quirks = rqRhineI;
665 io_size = 128;
666 }
Auke Kok44c10132007-06-08 15:46:36 -0700667 else if (pdev->revision >= VT6102) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 quirks = rqWOL | rqForceReset;
Auke Kok44c10132007-06-08 15:46:36 -0700669 if (pdev->revision < VT6105) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 name = "Rhine II";
671 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
672 }
673 else {
674 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
Auke Kok44c10132007-06-08 15:46:36 -0700675 if (pdev->revision >= VT6105_B0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 quirks |= rq6patterns;
Auke Kok44c10132007-06-08 15:46:36 -0700677 if (pdev->revision < VT6105M)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 name = "Rhine III";
679 else
680 name = "Rhine III (Management Adapter)";
681 }
682 }
683
684 rc = pci_enable_device(pdev);
685 if (rc)
686 goto err_out;
687
688 /* this should always be supported */
Yang Hongyang284901a2009-04-06 19:01:15 -0700689 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690 if (rc) {
691 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
692 "the card!?\n");
693 goto err_out;
694 }
695
696 /* sanity check */
697 if ((pci_resource_len(pdev, 0) < io_size) ||
698 (pci_resource_len(pdev, 1) < io_size)) {
699 rc = -EIO;
700 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
701 goto err_out;
702 }
703
704 pioaddr = pci_resource_start(pdev, 0);
705 memaddr = pci_resource_start(pdev, 1);
706
707 pci_set_master(pdev);
708
709 dev = alloc_etherdev(sizeof(struct rhine_private));
710 if (!dev) {
711 rc = -ENOMEM;
712 printk(KERN_ERR "alloc_etherdev failed\n");
713 goto err_out;
714 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 SET_NETDEV_DEV(dev, &pdev->dev);
716
717 rp = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700718 rp->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 rp->quirks = quirks;
720 rp->pioaddr = pioaddr;
721 rp->pdev = pdev;
722
723 rc = pci_request_regions(pdev, DRV_NAME);
724 if (rc)
725 goto err_out_free_netdev;
726
727 ioaddr = pci_iomap(pdev, bar, io_size);
728 if (!ioaddr) {
729 rc = -EIO;
730 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
731 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
732 goto err_out_free_res;
733 }
734
735#ifdef USE_MMIO
736 enable_mmio(pioaddr, quirks);
737
738 /* Check that selected MMIO registers match the PIO ones */
739 i = 0;
740 while (mmio_verify_registers[i]) {
741 int reg = mmio_verify_registers[i++];
742 unsigned char a = inb(pioaddr+reg);
743 unsigned char b = readb(ioaddr+reg);
744 if (a != b) {
745 rc = -EIO;
746 printk(KERN_ERR "MMIO do not match PIO [%02x] "
747 "(%02x != %02x)\n", reg, a, b);
748 goto err_out_unmap;
749 }
750 }
751#endif /* USE_MMIO */
752
753 dev->base_addr = (unsigned long)ioaddr;
754 rp->base = ioaddr;
755
756 /* Get chip registers into a sane state */
757 rhine_power_init(dev);
758 rhine_hw_init(dev, pioaddr);
759
760 for (i = 0; i < 6; i++)
761 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400762 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400764 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 rc = -EIO;
766 printk(KERN_ERR "Invalid MAC address\n");
767 goto err_out_unmap;
768 }
769
770 /* For Rhine-I/II, phy_id is loaded from EEPROM */
771 if (!phy_id)
772 phy_id = ioread8(ioaddr + 0x6C);
773
774 dev->irq = pdev->irq;
775
776 spin_lock_init(&rp->lock);
777 rp->mii_if.dev = dev;
778 rp->mii_if.mdio_read = mdio_read;
779 rp->mii_if.mdio_write = mdio_write;
780 rp->mii_if.phy_id_mask = 0x1f;
781 rp->mii_if.reg_num_mask = 0x1f;
782
783 /* The chip-specific entries in the device structure. */
Stephen Hemminger5d1d07d2008-11-21 17:30:11 -0800784 dev->netdev_ops = &rhine_netdev_ops;
785 dev->ethtool_ops = &netdev_ethtool_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 dev->watchdog_timeo = TX_TIMEOUT;
Stephen Hemminger5d1d07d2008-11-21 17:30:11 -0800787
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700788 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
Francois Romieu32b0f532008-07-11 00:30:14 +0200789
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 if (rp->quirks & rqRhineI)
791 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
792
793 /* dev->name not defined before register_netdev()! */
794 rc = register_netdev(dev);
795 if (rc)
796 goto err_out_unmap;
797
Johannes Berge1749612008-10-27 15:59:26 -0700798 printk(KERN_INFO "%s: VIA %s at 0x%lx, %pM, IRQ %d.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 dev->name, name,
800#ifdef USE_MMIO
Joe Perches0795af52007-10-03 17:59:30 -0700801 memaddr,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802#else
Joe Perches0795af52007-10-03 17:59:30 -0700803 (long)ioaddr,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804#endif
Johannes Berge1749612008-10-27 15:59:26 -0700805 dev->dev_addr, pdev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806
807 pci_set_drvdata(pdev, dev);
808
809 {
810 u16 mii_cmd;
811 int mii_status = mdio_read(dev, phy_id, 1);
812 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
813 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
814 if (mii_status != 0xffff && mii_status != 0x0000) {
815 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
816 printk(KERN_INFO "%s: MII PHY found at address "
817 "%d, status 0x%4.4x advertising %4.4x "
818 "Link %4.4x.\n", dev->name, phy_id,
819 mii_status, rp->mii_if.advertising,
820 mdio_read(dev, phy_id, 5));
821
822 /* set IFF_RUNNING */
823 if (mii_status & BMSR_LSTATUS)
824 netif_carrier_on(dev);
825 else
826 netif_carrier_off(dev);
827
828 }
829 }
830 rp->mii_if.phy_id = phy_id;
Roger Luethib933b4d2006-08-14 23:00:21 -0700831 if (debug > 1 && avoid_D3)
832 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
833 dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834
835 return 0;
836
837err_out_unmap:
838 pci_iounmap(pdev, ioaddr);
839err_out_free_res:
840 pci_release_regions(pdev);
841err_out_free_netdev:
842 free_netdev(dev);
843err_out:
844 return rc;
845}
846
847static int alloc_ring(struct net_device* dev)
848{
849 struct rhine_private *rp = netdev_priv(dev);
850 void *ring;
851 dma_addr_t ring_dma;
852
853 ring = pci_alloc_consistent(rp->pdev,
854 RX_RING_SIZE * sizeof(struct rx_desc) +
855 TX_RING_SIZE * sizeof(struct tx_desc),
856 &ring_dma);
857 if (!ring) {
858 printk(KERN_ERR "Could not allocate DMA memory.\n");
859 return -ENOMEM;
860 }
861 if (rp->quirks & rqRhineI) {
862 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
863 PKT_BUF_SZ * TX_RING_SIZE,
864 &rp->tx_bufs_dma);
865 if (rp->tx_bufs == NULL) {
866 pci_free_consistent(rp->pdev,
867 RX_RING_SIZE * sizeof(struct rx_desc) +
868 TX_RING_SIZE * sizeof(struct tx_desc),
869 ring, ring_dma);
870 return -ENOMEM;
871 }
872 }
873
874 rp->rx_ring = ring;
875 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
876 rp->rx_ring_dma = ring_dma;
877 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
878
879 return 0;
880}
881
882static void free_ring(struct net_device* dev)
883{
884 struct rhine_private *rp = netdev_priv(dev);
885
886 pci_free_consistent(rp->pdev,
887 RX_RING_SIZE * sizeof(struct rx_desc) +
888 TX_RING_SIZE * sizeof(struct tx_desc),
889 rp->rx_ring, rp->rx_ring_dma);
890 rp->tx_ring = NULL;
891
892 if (rp->tx_bufs)
893 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
894 rp->tx_bufs, rp->tx_bufs_dma);
895
896 rp->tx_bufs = NULL;
897
898}
899
900static void alloc_rbufs(struct net_device *dev)
901{
902 struct rhine_private *rp = netdev_priv(dev);
903 dma_addr_t next;
904 int i;
905
906 rp->dirty_rx = rp->cur_rx = 0;
907
908 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
909 rp->rx_head_desc = &rp->rx_ring[0];
910 next = rp->rx_ring_dma;
911
912 /* Init the ring entries */
913 for (i = 0; i < RX_RING_SIZE; i++) {
914 rp->rx_ring[i].rx_status = 0;
915 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
916 next += sizeof(struct rx_desc);
917 rp->rx_ring[i].next_desc = cpu_to_le32(next);
918 rp->rx_skbuff[i] = NULL;
919 }
920 /* Mark the last entry as wrapping the ring. */
921 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
922
923 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
924 for (i = 0; i < RX_RING_SIZE; i++) {
Kevin Lob26b5552008-08-27 11:35:09 +0800925 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926 rp->rx_skbuff[i] = skb;
927 if (skb == NULL)
928 break;
929 skb->dev = dev; /* Mark as being used by this device. */
930
931 rp->rx_skbuff_dma[i] =
David S. Miller689be432005-06-28 15:25:31 -0700932 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 PCI_DMA_FROMDEVICE);
934
935 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
936 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
937 }
938 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
939}
940
941static void free_rbufs(struct net_device* dev)
942{
943 struct rhine_private *rp = netdev_priv(dev);
944 int i;
945
946 /* Free all the skbuffs in the Rx queue. */
947 for (i = 0; i < RX_RING_SIZE; i++) {
948 rp->rx_ring[i].rx_status = 0;
949 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
950 if (rp->rx_skbuff[i]) {
951 pci_unmap_single(rp->pdev,
952 rp->rx_skbuff_dma[i],
953 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
954 dev_kfree_skb(rp->rx_skbuff[i]);
955 }
956 rp->rx_skbuff[i] = NULL;
957 }
958}
959
960static void alloc_tbufs(struct net_device* dev)
961{
962 struct rhine_private *rp = netdev_priv(dev);
963 dma_addr_t next;
964 int i;
965
966 rp->dirty_tx = rp->cur_tx = 0;
967 next = rp->tx_ring_dma;
968 for (i = 0; i < TX_RING_SIZE; i++) {
969 rp->tx_skbuff[i] = NULL;
970 rp->tx_ring[i].tx_status = 0;
971 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
972 next += sizeof(struct tx_desc);
973 rp->tx_ring[i].next_desc = cpu_to_le32(next);
Roger Luethi4be5de22006-04-04 20:49:16 +0200974 if (rp->quirks & rqRhineI)
975 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 }
977 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
978
979}
980
981static void free_tbufs(struct net_device* dev)
982{
983 struct rhine_private *rp = netdev_priv(dev);
984 int i;
985
986 for (i = 0; i < TX_RING_SIZE; i++) {
987 rp->tx_ring[i].tx_status = 0;
988 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
989 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
990 if (rp->tx_skbuff[i]) {
991 if (rp->tx_skbuff_dma[i]) {
992 pci_unmap_single(rp->pdev,
993 rp->tx_skbuff_dma[i],
994 rp->tx_skbuff[i]->len,
995 PCI_DMA_TODEVICE);
996 }
997 dev_kfree_skb(rp->tx_skbuff[i]);
998 }
999 rp->tx_skbuff[i] = NULL;
1000 rp->tx_buf[i] = NULL;
1001 }
1002}
1003
1004static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1005{
1006 struct rhine_private *rp = netdev_priv(dev);
1007 void __iomem *ioaddr = rp->base;
1008
1009 mii_check_media(&rp->mii_if, debug, init_media);
1010
1011 if (rp->mii_if.full_duplex)
1012 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1013 ioaddr + ChipCmd1);
1014 else
1015 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1016 ioaddr + ChipCmd1);
Roger Luethi00b428c2006-03-28 20:53:56 +02001017 if (debug > 1)
1018 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1019 rp->mii_if.force_media, netif_carrier_ok(dev));
1020}
1021
1022/* Called after status of force_media possibly changed */
Adrian Bunk0761be42006-04-10 23:22:21 -07001023static void rhine_set_carrier(struct mii_if_info *mii)
Roger Luethi00b428c2006-03-28 20:53:56 +02001024{
1025 if (mii->force_media) {
1026 /* autoneg is off: Link is always assumed to be up */
1027 if (!netif_carrier_ok(mii->dev))
1028 netif_carrier_on(mii->dev);
1029 }
1030 else /* Let MMI library update carrier status */
1031 rhine_check_media(mii->dev, 0);
1032 if (debug > 1)
1033 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1034 mii->dev->name, mii->force_media,
1035 netif_carrier_ok(mii->dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036}
1037
1038static void init_registers(struct net_device *dev)
1039{
1040 struct rhine_private *rp = netdev_priv(dev);
1041 void __iomem *ioaddr = rp->base;
1042 int i;
1043
1044 for (i = 0; i < 6; i++)
1045 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1046
1047 /* Initialize other registers. */
1048 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1049 /* Configure initial FIFO thresholds. */
1050 iowrite8(0x20, ioaddr + TxConfig);
1051 rp->tx_thresh = 0x20;
1052 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1053
1054 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1055 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1056
1057 rhine_set_rx_mode(dev);
1058
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001059 napi_enable(&rp->napi);
Stephen Hemmingerab197662006-08-14 23:00:18 -07001060
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 /* Enable interrupts by setting the interrupt mask. */
1062 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1063 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1064 IntrTxDone | IntrTxError | IntrTxUnderrun |
1065 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1066 ioaddr + IntrEnable);
1067
1068 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1069 ioaddr + ChipCmd);
1070 rhine_check_media(dev, 1);
1071}
1072
1073/* Enable MII link status auto-polling (required for IntrLinkChange) */
1074static void rhine_enable_linkmon(void __iomem *ioaddr)
1075{
1076 iowrite8(0, ioaddr + MIICmd);
1077 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1078 iowrite8(0x80, ioaddr + MIICmd);
1079
1080 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1081
1082 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1083}
1084
1085/* Disable MII link status auto-polling (required for MDIO access) */
1086static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1087{
1088 iowrite8(0, ioaddr + MIICmd);
1089
1090 if (quirks & rqRhineI) {
1091 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1092
John W. Linville38bb6b22006-05-19 10:51:21 -04001093 /* Can be called from ISR. Evil. */
1094 mdelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095
1096 /* 0x80 must be set immediately before turning it off */
1097 iowrite8(0x80, ioaddr + MIICmd);
1098
1099 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1100
1101 /* Heh. Now clear 0x80 again. */
1102 iowrite8(0, ioaddr + MIICmd);
1103 }
1104 else
1105 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1106}
1107
1108/* Read and write over the MII Management Data I/O (MDIO) interface. */
1109
1110static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1111{
1112 struct rhine_private *rp = netdev_priv(dev);
1113 void __iomem *ioaddr = rp->base;
1114 int result;
1115
1116 rhine_disable_linkmon(ioaddr, rp->quirks);
1117
1118 /* rhine_disable_linkmon already cleared MIICmd */
1119 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1120 iowrite8(regnum, ioaddr + MIIRegAddr);
1121 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1122 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1123 result = ioread16(ioaddr + MIIData);
1124
1125 rhine_enable_linkmon(ioaddr);
1126 return result;
1127}
1128
1129static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1130{
1131 struct rhine_private *rp = netdev_priv(dev);
1132 void __iomem *ioaddr = rp->base;
1133
1134 rhine_disable_linkmon(ioaddr, rp->quirks);
1135
1136 /* rhine_disable_linkmon already cleared MIICmd */
1137 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1138 iowrite8(regnum, ioaddr + MIIRegAddr);
1139 iowrite16(value, ioaddr + MIIData);
1140 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1141 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1142
1143 rhine_enable_linkmon(ioaddr);
1144}
1145
1146static int rhine_open(struct net_device *dev)
1147{
1148 struct rhine_private *rp = netdev_priv(dev);
1149 void __iomem *ioaddr = rp->base;
1150 int rc;
1151
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001152 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153 dev);
1154 if (rc)
1155 return rc;
1156
1157 if (debug > 1)
1158 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1159 dev->name, rp->pdev->irq);
1160
1161 rc = alloc_ring(dev);
1162 if (rc) {
1163 free_irq(rp->pdev->irq, dev);
1164 return rc;
1165 }
1166 alloc_rbufs(dev);
1167 alloc_tbufs(dev);
1168 rhine_chip_reset(dev);
1169 init_registers(dev);
1170 if (debug > 2)
1171 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1172 "MII status: %4.4x.\n",
1173 dev->name, ioread16(ioaddr + ChipCmd),
1174 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1175
1176 netif_start_queue(dev);
1177
1178 return 0;
1179}
1180
1181static void rhine_tx_timeout(struct net_device *dev)
1182{
1183 struct rhine_private *rp = netdev_priv(dev);
1184 void __iomem *ioaddr = rp->base;
1185
1186 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1187 "%4.4x, resetting...\n",
1188 dev->name, ioread16(ioaddr + IntrStatus),
1189 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1190
1191 /* protect against concurrent rx interrupts */
1192 disable_irq(rp->pdev->irq);
1193
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001194 napi_disable(&rp->napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001195
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 spin_lock(&rp->lock);
1197
1198 /* clear all descriptors */
1199 free_tbufs(dev);
1200 free_rbufs(dev);
1201 alloc_tbufs(dev);
1202 alloc_rbufs(dev);
1203
1204 /* Reinitialize the hardware. */
1205 rhine_chip_reset(dev);
1206 init_registers(dev);
1207
1208 spin_unlock(&rp->lock);
1209 enable_irq(rp->pdev->irq);
1210
1211 dev->trans_start = jiffies;
1212 rp->stats.tx_errors++;
1213 netif_wake_queue(dev);
1214}
1215
1216static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1217{
1218 struct rhine_private *rp = netdev_priv(dev);
1219 void __iomem *ioaddr = rp->base;
1220 unsigned entry;
1221
1222 /* Caution: the write order is important here, set the field
1223 with the "ownership" bits last. */
1224
1225 /* Calculate the next Tx descriptor entry. */
1226 entry = rp->cur_tx % TX_RING_SIZE;
1227
Herbert Xu5b057c62006-06-23 02:06:41 -07001228 if (skb_padto(skb, ETH_ZLEN))
1229 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230
1231 rp->tx_skbuff[entry] = skb;
1232
1233 if ((rp->quirks & rqRhineI) &&
Patrick McHardy84fa7932006-08-29 16:44:56 -07001234 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 /* Must use alignment buffer. */
1236 if (skb->len > PKT_BUF_SZ) {
1237 /* packet too long, drop it */
1238 dev_kfree_skb(skb);
1239 rp->tx_skbuff[entry] = NULL;
1240 rp->stats.tx_dropped++;
1241 return 0;
1242 }
Craig Brind3e0d1672006-04-27 02:30:46 -07001243
1244 /* Padding is not copied and so must be redone. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
Craig Brind3e0d1672006-04-27 02:30:46 -07001246 if (skb->len < ETH_ZLEN)
1247 memset(rp->tx_buf[entry] + skb->len, 0,
1248 ETH_ZLEN - skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 rp->tx_skbuff_dma[entry] = 0;
1250 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1251 (rp->tx_buf[entry] -
1252 rp->tx_bufs));
1253 } else {
1254 rp->tx_skbuff_dma[entry] =
1255 pci_map_single(rp->pdev, skb->data, skb->len,
1256 PCI_DMA_TODEVICE);
1257 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1258 }
1259
1260 rp->tx_ring[entry].desc_length =
1261 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1262
1263 /* lock eth irq */
1264 spin_lock_irq(&rp->lock);
1265 wmb();
1266 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1267 wmb();
1268
1269 rp->cur_tx++;
1270
1271 /* Non-x86 Todo: explicitly flush cache lines here. */
1272
1273 /* Wake the potentially-idle transmit channel */
1274 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1275 ioaddr + ChipCmd1);
1276 IOSYNC;
1277
1278 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1279 netif_stop_queue(dev);
1280
1281 dev->trans_start = jiffies;
1282
1283 spin_unlock_irq(&rp->lock);
1284
1285 if (debug > 4) {
1286 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1287 dev->name, rp->cur_tx-1, entry);
1288 }
1289 return 0;
1290}
1291
1292/* The interrupt handler does all of the Rx thread work and cleans up
1293 after the Tx thread. */
David Howells7d12e782006-10-05 14:55:46 +01001294static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295{
1296 struct net_device *dev = dev_instance;
1297 struct rhine_private *rp = netdev_priv(dev);
1298 void __iomem *ioaddr = rp->base;
1299 u32 intr_status;
1300 int boguscnt = max_interrupt_work;
1301 int handled = 0;
1302
1303 while ((intr_status = get_intr_status(dev))) {
1304 handled = 1;
1305
1306 /* Acknowledge all of the current interrupt sources ASAP. */
1307 if (intr_status & IntrTxDescRace)
1308 iowrite8(0x08, ioaddr + IntrStatus2);
1309 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1310 IOSYNC;
1311
1312 if (debug > 4)
1313 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1314 dev->name, intr_status);
1315
1316 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
Roger Luethi633949a2006-08-14 23:00:17 -07001317 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
Roger Luethi633949a2006-08-14 23:00:17 -07001318 iowrite16(IntrTxAborted |
1319 IntrTxDone | IntrTxError | IntrTxUnderrun |
1320 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1321 ioaddr + IntrEnable);
1322
Ben Hutchings288379f2009-01-19 16:43:59 -08001323 napi_schedule(&rp->napi);
Roger Luethi633949a2006-08-14 23:00:17 -07001324 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325
1326 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1327 if (intr_status & IntrTxErrSummary) {
1328 /* Avoid scavenging before Tx engine turned off */
1329 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1330 if (debug > 2 &&
1331 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1332 printk(KERN_WARNING "%s: "
Joe Perches24500222007-11-19 17:48:28 -08001333 "rhine_interrupt() Tx engine "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334 "still on.\n", dev->name);
1335 }
1336 rhine_tx(dev);
1337 }
1338
1339 /* Abnormal error summary/uncommon events handlers. */
1340 if (intr_status & (IntrPCIErr | IntrLinkChange |
1341 IntrStatsMax | IntrTxError | IntrTxAborted |
1342 IntrTxUnderrun | IntrTxDescRace))
1343 rhine_error(dev, intr_status);
1344
1345 if (--boguscnt < 0) {
1346 printk(KERN_WARNING "%s: Too much work at interrupt, "
1347 "status=%#8.8x.\n",
1348 dev->name, intr_status);
1349 break;
1350 }
1351 }
1352
1353 if (debug > 3)
1354 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1355 dev->name, ioread16(ioaddr + IntrStatus));
1356 return IRQ_RETVAL(handled);
1357}
1358
1359/* This routine is logically part of the interrupt handler, but isolated
1360 for clarity. */
1361static void rhine_tx(struct net_device *dev)
1362{
1363 struct rhine_private *rp = netdev_priv(dev);
1364 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1365
1366 spin_lock(&rp->lock);
1367
1368 /* find and cleanup dirty tx descriptors */
1369 while (rp->dirty_tx != rp->cur_tx) {
1370 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1371 if (debug > 6)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001372 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373 entry, txstatus);
1374 if (txstatus & DescOwn)
1375 break;
1376 if (txstatus & 0x8000) {
1377 if (debug > 1)
1378 printk(KERN_DEBUG "%s: Transmit error, "
1379 "Tx status %8.8x.\n",
1380 dev->name, txstatus);
1381 rp->stats.tx_errors++;
1382 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1383 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1384 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1385 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1386 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1387 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1388 rp->stats.tx_fifo_errors++;
1389 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1390 break; /* Keep the skb - we try again */
1391 }
1392 /* Transmitter restarted in 'abnormal' handler. */
1393 } else {
1394 if (rp->quirks & rqRhineI)
1395 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1396 else
1397 rp->stats.collisions += txstatus & 0x0F;
1398 if (debug > 6)
1399 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1400 (txstatus >> 3) & 0xF,
1401 txstatus & 0xF);
1402 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1403 rp->stats.tx_packets++;
1404 }
1405 /* Free the original skb. */
1406 if (rp->tx_skbuff_dma[entry]) {
1407 pci_unmap_single(rp->pdev,
1408 rp->tx_skbuff_dma[entry],
1409 rp->tx_skbuff[entry]->len,
1410 PCI_DMA_TODEVICE);
1411 }
1412 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1413 rp->tx_skbuff[entry] = NULL;
1414 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1415 }
1416 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1417 netif_wake_queue(dev);
1418
1419 spin_unlock(&rp->lock);
1420}
1421
Roger Luethi633949a2006-08-14 23:00:17 -07001422/* Process up to limit frames from receive ring */
1423static int rhine_rx(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424{
1425 struct rhine_private *rp = netdev_priv(dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001426 int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427 int entry = rp->cur_rx % RX_RING_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428
1429 if (debug > 4) {
1430 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1431 dev->name, entry,
1432 le32_to_cpu(rp->rx_head_desc->rx_status));
1433 }
1434
1435 /* If EOP is set on the next entry, it's a new packet. Send it up. */
Roger Luethi633949a2006-08-14 23:00:17 -07001436 for (count = 0; count < limit; ++count) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437 struct rx_desc *desc = rp->rx_head_desc;
1438 u32 desc_status = le32_to_cpu(desc->rx_status);
1439 int data_size = desc_status >> 16;
1440
Roger Luethi633949a2006-08-14 23:00:17 -07001441 if (desc_status & DescOwn)
1442 break;
1443
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 if (debug > 4)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001445 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446 desc_status);
Roger Luethi633949a2006-08-14 23:00:17 -07001447
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1449 if ((desc_status & RxWholePkt) != RxWholePkt) {
1450 printk(KERN_WARNING "%s: Oversized Ethernet "
1451 "frame spanned multiple buffers, entry "
1452 "%#x length %d status %8.8x!\n",
1453 dev->name, entry, data_size,
1454 desc_status);
1455 printk(KERN_WARNING "%s: Oversized Ethernet "
1456 "frame %p vs %p.\n", dev->name,
1457 rp->rx_head_desc, &rp->rx_ring[entry]);
1458 rp->stats.rx_length_errors++;
1459 } else if (desc_status & RxErr) {
1460 /* There was a error. */
1461 if (debug > 2)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001462 printk(KERN_DEBUG "rhine_rx() Rx "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463 "error was %8.8x.\n",
1464 desc_status);
1465 rp->stats.rx_errors++;
1466 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1467 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1468 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1469 if (desc_status & 0x0002) {
1470 /* this can also be updated outside the interrupt handler */
1471 spin_lock(&rp->lock);
1472 rp->stats.rx_crc_errors++;
1473 spin_unlock(&rp->lock);
1474 }
1475 }
1476 } else {
1477 struct sk_buff *skb;
1478 /* Length should omit the CRC */
1479 int pkt_len = data_size - 4;
1480
1481 /* Check if the packet is long enough to accept without
1482 copying to a minimally-sized skbuff. */
1483 if (pkt_len < rx_copybreak &&
Kevin Lob26b5552008-08-27 11:35:09 +08001484 (skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN)) != NULL) {
1485 skb_reserve(skb, NET_IP_ALIGN); /* 16 byte align the IP header */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486 pci_dma_sync_single_for_cpu(rp->pdev,
1487 rp->rx_skbuff_dma[entry],
1488 rp->rx_buf_sz,
1489 PCI_DMA_FROMDEVICE);
1490
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001491 skb_copy_to_linear_data(skb,
David S. Miller689be432005-06-28 15:25:31 -07001492 rp->rx_skbuff[entry]->data,
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001493 pkt_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 skb_put(skb, pkt_len);
1495 pci_dma_sync_single_for_device(rp->pdev,
1496 rp->rx_skbuff_dma[entry],
1497 rp->rx_buf_sz,
1498 PCI_DMA_FROMDEVICE);
1499 } else {
1500 skb = rp->rx_skbuff[entry];
1501 if (skb == NULL) {
1502 printk(KERN_ERR "%s: Inconsistent Rx "
1503 "descriptor chain.\n",
1504 dev->name);
1505 break;
1506 }
1507 rp->rx_skbuff[entry] = NULL;
1508 skb_put(skb, pkt_len);
1509 pci_unmap_single(rp->pdev,
1510 rp->rx_skbuff_dma[entry],
1511 rp->rx_buf_sz,
1512 PCI_DMA_FROMDEVICE);
1513 }
1514 skb->protocol = eth_type_trans(skb, dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001515 netif_receive_skb(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516 rp->stats.rx_bytes += pkt_len;
1517 rp->stats.rx_packets++;
1518 }
1519 entry = (++rp->cur_rx) % RX_RING_SIZE;
1520 rp->rx_head_desc = &rp->rx_ring[entry];
1521 }
1522
1523 /* Refill the Rx ring buffers. */
1524 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1525 struct sk_buff *skb;
1526 entry = rp->dirty_rx % RX_RING_SIZE;
1527 if (rp->rx_skbuff[entry] == NULL) {
Kevin Lob26b5552008-08-27 11:35:09 +08001528 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001529 rp->rx_skbuff[entry] = skb;
1530 if (skb == NULL)
1531 break; /* Better luck next round. */
1532 skb->dev = dev; /* Mark as being used by this device. */
1533 rp->rx_skbuff_dma[entry] =
David S. Miller689be432005-06-28 15:25:31 -07001534 pci_map_single(rp->pdev, skb->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535 rp->rx_buf_sz,
1536 PCI_DMA_FROMDEVICE);
1537 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1538 }
1539 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1540 }
Roger Luethi633949a2006-08-14 23:00:17 -07001541
1542 return count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543}
1544
1545/*
1546 * Clears the "tally counters" for CRC errors and missed frames(?).
1547 * It has been reported that some chips need a write of 0 to clear
1548 * these, for others the counters are set to 1 when written to and
1549 * instead cleared when read. So we clear them both ways ...
1550 */
1551static inline void clear_tally_counters(void __iomem *ioaddr)
1552{
1553 iowrite32(0, ioaddr + RxMissed);
1554 ioread16(ioaddr + RxCRCErrs);
1555 ioread16(ioaddr + RxMissed);
1556}
1557
1558static void rhine_restart_tx(struct net_device *dev) {
1559 struct rhine_private *rp = netdev_priv(dev);
1560 void __iomem *ioaddr = rp->base;
1561 int entry = rp->dirty_tx % TX_RING_SIZE;
1562 u32 intr_status;
1563
1564 /*
1565 * If new errors occured, we need to sort them out before doing Tx.
1566 * In that case the ISR will be back here RSN anyway.
1567 */
1568 intr_status = get_intr_status(dev);
1569
1570 if ((intr_status & IntrTxErrSummary) == 0) {
1571
1572 /* We know better than the chip where it should continue. */
1573 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1574 ioaddr + TxRingPtr);
1575
1576 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1577 ioaddr + ChipCmd);
1578 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1579 ioaddr + ChipCmd1);
1580 IOSYNC;
1581 }
1582 else {
1583 /* This should never happen */
1584 if (debug > 1)
1585 printk(KERN_WARNING "%s: rhine_restart_tx() "
1586 "Another error occured %8.8x.\n",
1587 dev->name, intr_status);
1588 }
1589
1590}
1591
1592static void rhine_error(struct net_device *dev, int intr_status)
1593{
1594 struct rhine_private *rp = netdev_priv(dev);
1595 void __iomem *ioaddr = rp->base;
1596
1597 spin_lock(&rp->lock);
1598
1599 if (intr_status & IntrLinkChange)
John W. Linville38bb6b22006-05-19 10:51:21 -04001600 rhine_check_media(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601 if (intr_status & IntrStatsMax) {
1602 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1603 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1604 clear_tally_counters(ioaddr);
1605 }
1606 if (intr_status & IntrTxAborted) {
1607 if (debug > 1)
1608 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1609 dev->name, intr_status);
1610 }
1611 if (intr_status & IntrTxUnderrun) {
1612 if (rp->tx_thresh < 0xE0)
1613 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1614 if (debug > 1)
1615 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1616 "threshold now %2.2x.\n",
1617 dev->name, rp->tx_thresh);
1618 }
1619 if (intr_status & IntrTxDescRace) {
1620 if (debug > 2)
1621 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1622 dev->name);
1623 }
1624 if ((intr_status & IntrTxError) &&
1625 (intr_status & (IntrTxAborted |
1626 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1627 if (rp->tx_thresh < 0xE0) {
1628 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1629 }
1630 if (debug > 1)
1631 printk(KERN_INFO "%s: Unspecified error. Tx "
1632 "threshold now %2.2x.\n",
1633 dev->name, rp->tx_thresh);
1634 }
1635 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1636 IntrTxError))
1637 rhine_restart_tx(dev);
1638
1639 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1640 IntrTxError | IntrTxAborted | IntrNormalSummary |
1641 IntrTxDescRace)) {
1642 if (debug > 1)
1643 printk(KERN_ERR "%s: Something Wicked happened! "
1644 "%8.8x.\n", dev->name, intr_status);
1645 }
1646
1647 spin_unlock(&rp->lock);
1648}
1649
1650static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1651{
1652 struct rhine_private *rp = netdev_priv(dev);
1653 void __iomem *ioaddr = rp->base;
1654 unsigned long flags;
1655
1656 spin_lock_irqsave(&rp->lock, flags);
1657 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1658 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1659 clear_tally_counters(ioaddr);
1660 spin_unlock_irqrestore(&rp->lock, flags);
1661
1662 return &rp->stats;
1663}
1664
1665static void rhine_set_rx_mode(struct net_device *dev)
1666{
1667 struct rhine_private *rp = netdev_priv(dev);
1668 void __iomem *ioaddr = rp->base;
1669 u32 mc_filter[2]; /* Multicast hash filter */
1670 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1671
1672 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673 rx_mode = 0x1C;
1674 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1675 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1676 } else if ((dev->mc_count > multicast_filter_limit)
1677 || (dev->flags & IFF_ALLMULTI)) {
1678 /* Too many to match, or accept all multicasts. */
1679 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1680 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1681 rx_mode = 0x0C;
1682 } else {
1683 struct dev_mc_list *mclist;
1684 int i;
1685 memset(mc_filter, 0, sizeof(mc_filter));
1686 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1687 i++, mclist = mclist->next) {
1688 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1689
1690 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1691 }
1692 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1693 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1694 rx_mode = 0x0C;
1695 }
1696 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1697}
1698
1699static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1700{
1701 struct rhine_private *rp = netdev_priv(dev);
1702
1703 strcpy(info->driver, DRV_NAME);
1704 strcpy(info->version, DRV_VERSION);
1705 strcpy(info->bus_info, pci_name(rp->pdev));
1706}
1707
1708static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1709{
1710 struct rhine_private *rp = netdev_priv(dev);
1711 int rc;
1712
1713 spin_lock_irq(&rp->lock);
1714 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1715 spin_unlock_irq(&rp->lock);
1716
1717 return rc;
1718}
1719
1720static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1721{
1722 struct rhine_private *rp = netdev_priv(dev);
1723 int rc;
1724
1725 spin_lock_irq(&rp->lock);
1726 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1727 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001728 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729
1730 return rc;
1731}
1732
1733static int netdev_nway_reset(struct net_device *dev)
1734{
1735 struct rhine_private *rp = netdev_priv(dev);
1736
1737 return mii_nway_restart(&rp->mii_if);
1738}
1739
1740static u32 netdev_get_link(struct net_device *dev)
1741{
1742 struct rhine_private *rp = netdev_priv(dev);
1743
1744 return mii_link_ok(&rp->mii_if);
1745}
1746
1747static u32 netdev_get_msglevel(struct net_device *dev)
1748{
1749 return debug;
1750}
1751
1752static void netdev_set_msglevel(struct net_device *dev, u32 value)
1753{
1754 debug = value;
1755}
1756
1757static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1758{
1759 struct rhine_private *rp = netdev_priv(dev);
1760
1761 if (!(rp->quirks & rqWOL))
1762 return;
1763
1764 spin_lock_irq(&rp->lock);
1765 wol->supported = WAKE_PHY | WAKE_MAGIC |
1766 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1767 wol->wolopts = rp->wolopts;
1768 spin_unlock_irq(&rp->lock);
1769}
1770
1771static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1772{
1773 struct rhine_private *rp = netdev_priv(dev);
1774 u32 support = WAKE_PHY | WAKE_MAGIC |
1775 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1776
1777 if (!(rp->quirks & rqWOL))
1778 return -EINVAL;
1779
1780 if (wol->wolopts & ~support)
1781 return -EINVAL;
1782
1783 spin_lock_irq(&rp->lock);
1784 rp->wolopts = wol->wolopts;
1785 spin_unlock_irq(&rp->lock);
1786
1787 return 0;
1788}
1789
Jeff Garzik7282d492006-09-13 14:30:00 -04001790static const struct ethtool_ops netdev_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791 .get_drvinfo = netdev_get_drvinfo,
1792 .get_settings = netdev_get_settings,
1793 .set_settings = netdev_set_settings,
1794 .nway_reset = netdev_nway_reset,
1795 .get_link = netdev_get_link,
1796 .get_msglevel = netdev_get_msglevel,
1797 .set_msglevel = netdev_set_msglevel,
1798 .get_wol = rhine_get_wol,
1799 .set_wol = rhine_set_wol,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800};
1801
1802static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1803{
1804 struct rhine_private *rp = netdev_priv(dev);
1805 int rc;
1806
1807 if (!netif_running(dev))
1808 return -EINVAL;
1809
1810 spin_lock_irq(&rp->lock);
1811 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1812 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001813 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
1815 return rc;
1816}
1817
1818static int rhine_close(struct net_device *dev)
1819{
1820 struct rhine_private *rp = netdev_priv(dev);
1821 void __iomem *ioaddr = rp->base;
1822
1823 spin_lock_irq(&rp->lock);
1824
1825 netif_stop_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001826 napi_disable(&rp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001827
1828 if (debug > 1)
1829 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1830 "status was %4.4x.\n",
1831 dev->name, ioread16(ioaddr + ChipCmd));
1832
1833 /* Switch to loopback mode to avoid hardware races. */
1834 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1835
1836 /* Disable interrupts by clearing the interrupt mask. */
1837 iowrite16(0x0000, ioaddr + IntrEnable);
1838
1839 /* Stop the chip's Tx and Rx processes. */
1840 iowrite16(CmdStop, ioaddr + ChipCmd);
1841
1842 spin_unlock_irq(&rp->lock);
1843
1844 free_irq(rp->pdev->irq, dev);
1845 free_rbufs(dev);
1846 free_tbufs(dev);
1847 free_ring(dev);
1848
1849 return 0;
1850}
1851
1852
1853static void __devexit rhine_remove_one(struct pci_dev *pdev)
1854{
1855 struct net_device *dev = pci_get_drvdata(pdev);
1856 struct rhine_private *rp = netdev_priv(dev);
1857
1858 unregister_netdev(dev);
1859
1860 pci_iounmap(pdev, rp->base);
1861 pci_release_regions(pdev);
1862
1863 free_netdev(dev);
1864 pci_disable_device(pdev);
1865 pci_set_drvdata(pdev, NULL);
1866}
1867
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001868static void rhine_shutdown (struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001869{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870 struct net_device *dev = pci_get_drvdata(pdev);
1871 struct rhine_private *rp = netdev_priv(dev);
1872 void __iomem *ioaddr = rp->base;
1873
1874 if (!(rp->quirks & rqWOL))
1875 return; /* Nothing to do for non-WOL adapters */
1876
1877 rhine_power_init(dev);
1878
1879 /* Make sure we use pattern 0, 1 and not 4, 5 */
1880 if (rp->quirks & rq6patterns)
Laura Garciaf11cf252008-02-23 18:56:35 +01001881 iowrite8(0x04, ioaddr + WOLcgClr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
1883 if (rp->wolopts & WAKE_MAGIC) {
1884 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1885 /*
1886 * Turn EEPROM-controlled wake-up back on -- some hardware may
1887 * not cooperate otherwise.
1888 */
1889 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1890 }
1891
1892 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1893 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1894
1895 if (rp->wolopts & WAKE_PHY)
1896 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1897
1898 if (rp->wolopts & WAKE_UCAST)
1899 iowrite8(WOLucast, ioaddr + WOLcrSet);
1900
1901 if (rp->wolopts) {
1902 /* Enable legacy WOL (for old motherboards) */
1903 iowrite8(0x01, ioaddr + PwcfgSet);
1904 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1905 }
1906
1907 /* Hit power state D3 (sleep) */
Roger Luethib933b4d2006-08-14 23:00:21 -07001908 if (!avoid_D3)
1909 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910
1911 /* TODO: Check use of pci_enable_wake() */
1912
1913}
1914
1915#ifdef CONFIG_PM
1916static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1917{
1918 struct net_device *dev = pci_get_drvdata(pdev);
1919 struct rhine_private *rp = netdev_priv(dev);
1920 unsigned long flags;
1921
1922 if (!netif_running(dev))
1923 return 0;
1924
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001925 napi_disable(&rp->napi);
Francois Romieu32b0f532008-07-11 00:30:14 +02001926
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 netif_device_detach(dev);
1928 pci_save_state(pdev);
1929
1930 spin_lock_irqsave(&rp->lock, flags);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001931 rhine_shutdown(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932 spin_unlock_irqrestore(&rp->lock, flags);
1933
1934 free_irq(dev->irq, dev);
1935 return 0;
1936}
1937
1938static int rhine_resume(struct pci_dev *pdev)
1939{
1940 struct net_device *dev = pci_get_drvdata(pdev);
1941 struct rhine_private *rp = netdev_priv(dev);
1942 unsigned long flags;
1943 int ret;
1944
1945 if (!netif_running(dev))
1946 return 0;
1947
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001948 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001949 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1950
1951 ret = pci_set_power_state(pdev, PCI_D0);
1952 if (debug > 1)
1953 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1954 dev->name, ret ? "failed" : "succeeded", ret);
1955
1956 pci_restore_state(pdev);
1957
1958 spin_lock_irqsave(&rp->lock, flags);
1959#ifdef USE_MMIO
1960 enable_mmio(rp->pioaddr, rp->quirks);
1961#endif
1962 rhine_power_init(dev);
1963 free_tbufs(dev);
1964 free_rbufs(dev);
1965 alloc_tbufs(dev);
1966 alloc_rbufs(dev);
1967 init_registers(dev);
1968 spin_unlock_irqrestore(&rp->lock, flags);
1969
1970 netif_device_attach(dev);
1971
1972 return 0;
1973}
1974#endif /* CONFIG_PM */
1975
1976static struct pci_driver rhine_driver = {
1977 .name = DRV_NAME,
1978 .id_table = rhine_pci_tbl,
1979 .probe = rhine_init_one,
1980 .remove = __devexit_p(rhine_remove_one),
1981#ifdef CONFIG_PM
1982 .suspend = rhine_suspend,
1983 .resume = rhine_resume,
1984#endif /* CONFIG_PM */
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001985 .shutdown = rhine_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001986};
1987
Roger Luethie84df482007-03-06 19:57:37 +01001988static struct dmi_system_id __initdata rhine_dmi_table[] = {
1989 {
1990 .ident = "EPIA-M",
1991 .matches = {
1992 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
1993 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
1994 },
1995 },
1996 {
1997 .ident = "KV7",
1998 .matches = {
1999 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2000 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2001 },
2002 },
2003 { NULL }
2004};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002005
2006static int __init rhine_init(void)
2007{
2008/* when a module, this is printed whether or not devices are found in probe */
2009#ifdef MODULE
2010 printk(version);
2011#endif
Roger Luethie84df482007-03-06 19:57:37 +01002012 if (dmi_check_system(rhine_dmi_table)) {
2013 /* these BIOSes fail at PXE boot if chip is in D3 */
2014 avoid_D3 = 1;
2015 printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2016 "enabled.\n",
2017 DRV_NAME);
2018 }
2019 else if (avoid_D3)
2020 printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2021
Jeff Garzik29917622006-08-19 17:48:59 -04002022 return pci_register_driver(&rhine_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023}
2024
2025
2026static void __exit rhine_cleanup(void)
2027{
2028 pci_unregister_driver(&rhine_driver);
2029}
2030
2031
2032module_init(rhine_init);
2033module_exit(rhine_cleanup);