blob: 8181ed1313865015a169b1e19e44de5ad3df8eb5 [file] [log] [blame]
Matt Porterc2dde5f2012-08-22 21:09:34 -04001/*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
Lad, Prabhakarb7a4fd52015-02-04 13:03:27 +000018#include <linux/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040019#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/list.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
Peter Ujfalusied646102014-07-31 13:12:38 +030027#include <linux/of.h>
Peter Ujfalusidc9b60552015-10-14 14:42:47 +030028#include <linux/of_dma.h>
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +030029#include <linux/of_irq.h>
30#include <linux/of_address.h>
31#include <linux/of_device.h>
32#include <linux/pm_runtime.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040033
Matt Porter3ad7a422013-03-06 11:15:31 -050034#include <linux/platform_data/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040035
36#include "dmaengine.h"
37#include "virt-dma.h"
38
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +030039/* Offsets matching "struct edmacc_param" */
40#define PARM_OPT 0x00
41#define PARM_SRC 0x04
42#define PARM_A_B_CNT 0x08
43#define PARM_DST 0x0c
44#define PARM_SRC_DST_BIDX 0x10
45#define PARM_LINK_BCNTRLD 0x14
46#define PARM_SRC_DST_CIDX 0x18
47#define PARM_CCNT 0x1c
48
49#define PARM_SIZE 0x20
50
51/* Offsets for EDMA CC global channel registers and their shadows */
52#define SH_ER 0x00 /* 64 bits */
53#define SH_ECR 0x08 /* 64 bits */
54#define SH_ESR 0x10 /* 64 bits */
55#define SH_CER 0x18 /* 64 bits */
56#define SH_EER 0x20 /* 64 bits */
57#define SH_EECR 0x28 /* 64 bits */
58#define SH_EESR 0x30 /* 64 bits */
59#define SH_SER 0x38 /* 64 bits */
60#define SH_SECR 0x40 /* 64 bits */
61#define SH_IER 0x50 /* 64 bits */
62#define SH_IECR 0x58 /* 64 bits */
63#define SH_IESR 0x60 /* 64 bits */
64#define SH_IPR 0x68 /* 64 bits */
65#define SH_ICR 0x70 /* 64 bits */
66#define SH_IEVAL 0x78
67#define SH_QER 0x80
68#define SH_QEER 0x84
69#define SH_QEECR 0x88
70#define SH_QEESR 0x8c
71#define SH_QSER 0x90
72#define SH_QSECR 0x94
73#define SH_SIZE 0x200
74
75/* Offsets for EDMA CC global registers */
76#define EDMA_REV 0x0000
77#define EDMA_CCCFG 0x0004
78#define EDMA_QCHMAP 0x0200 /* 8 registers */
79#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80#define EDMA_QDMAQNUM 0x0260
81#define EDMA_QUETCMAP 0x0280
82#define EDMA_QUEPRI 0x0284
83#define EDMA_EMR 0x0300 /* 64 bits */
84#define EDMA_EMCR 0x0308 /* 64 bits */
85#define EDMA_QEMR 0x0310
86#define EDMA_QEMCR 0x0314
87#define EDMA_CCERR 0x0318
88#define EDMA_CCERRCLR 0x031c
89#define EDMA_EEVAL 0x0320
90#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91#define EDMA_QRAE 0x0380 /* 4 registers */
92#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93#define EDMA_QSTAT 0x0600 /* 2 registers */
94#define EDMA_QWMTHRA 0x0620
95#define EDMA_QWMTHRB 0x0624
96#define EDMA_CCSTAT 0x0640
97
98#define EDMA_M 0x1000 /* global channel registers */
99#define EDMA_ECR 0x1008
100#define EDMA_ECRH 0x100C
101#define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102#define EDMA_PARM 0x4000 /* PaRAM entries */
103
104#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
105
106#define EDMA_DCHMAP 0x0100 /* 64 registers */
107
108/* CCCFG register */
109#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
Dan Carpenterf5ea7ad2015-11-04 16:38:31 +0300110#define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300111#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
112#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
113#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114#define CHMAP_EXIST BIT(24)
115
John Ogness4ac31d12016-01-28 11:29:08 +0100116/* CCSTAT register */
117#define EDMA_CCSTAT_ACTV BIT(4)
118
Matt Porterc2dde5f2012-08-22 21:09:34 -0400119/*
Joel Fernandes2abd5f12013-09-23 18:05:15 -0500120 * Max of 20 segments per channel to conserve PaRAM slots
121 * Also note that MAX_NR_SG should be atleast the no.of periods
122 * that are required for ASoC, otherwise DMA prep calls will
123 * fail. Today davinci-pcm is the only user of this driver and
124 * requires atleast 17 slots, so we setup the default to 20.
125 */
126#define MAX_NR_SG 20
Matt Porterc2dde5f2012-08-22 21:09:34 -0400127#define EDMA_MAX_SLOTS MAX_NR_SG
128#define EDMA_DESCRIPTORS 16
129
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300130#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
131#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
132#define EDMA_CONT_PARAMS_ANY 1001
133#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
134#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300136/* PaRAM slots are laid out like this */
137struct edmacc_param {
138 u32 opt;
139 u32 src;
140 u32 a_b_cnt;
141 u32 dst;
142 u32 src_dst_bidx;
143 u32 link_bcntrld;
144 u32 src_dst_cidx;
145 u32 ccnt;
146} __packed;
147
148/* fields in edmacc_param.opt */
149#define SAM BIT(0)
150#define DAM BIT(1)
151#define SYNCDIM BIT(2)
152#define STATIC BIT(3)
153#define EDMA_FWID (0x07 << 8)
154#define TCCMODE BIT(11)
155#define EDMA_TCC(t) ((t) << 12)
156#define TCINTEN BIT(20)
157#define ITCINTEN BIT(21)
158#define TCCHEN BIT(22)
159#define ITCCHEN BIT(23)
160
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500161struct edma_pset {
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500162 u32 len;
163 dma_addr_t addr;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500164 struct edmacc_param param;
165};
166
Matt Porterc2dde5f2012-08-22 21:09:34 -0400167struct edma_desc {
168 struct virt_dma_desc vdesc;
169 struct list_head node;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500170 enum dma_transfer_direction direction;
Joel Fernandes50a9c702013-10-31 16:31:23 -0500171 int cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400172 int absync;
173 int pset_nr;
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500174 struct edma_chan *echan;
Joel Fernandes04361d82014-04-28 15:19:31 -0500175 int processed;
176
177 /*
178 * The following 4 elements are used for residue accounting.
179 *
180 * - processed_stat: the number of SG elements we have traversed
181 * so far to cover accounting. This is updated directly to processed
182 * during edma_callback and is always <= processed, because processed
183 * refers to the number of pending transfer (programmed to EDMA
184 * controller), where as processed_stat tracks number of transfers
185 * accounted for so far.
186 *
187 * - residue: The amount of bytes we have left to transfer for this desc
188 *
189 * - residue_stat: The residue in bytes of data we have covered
190 * so far for accounting. This is updated directly to residue
191 * during callbacks to keep it current.
192 *
193 * - sg_len: Tracks the length of the current intermediate transfer,
194 * this is required to update the residue during intermediate transfer
195 * completion callback.
196 */
197 int processed_stat;
198 u32 sg_len;
199 u32 residue;
200 u32 residue_stat;
201
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500202 struct edma_pset pset[0];
Matt Porterc2dde5f2012-08-22 21:09:34 -0400203};
204
205struct edma_cc;
206
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300207struct edma_tc {
208 struct device_node *node;
209 u16 id;
210};
211
Matt Porterc2dde5f2012-08-22 21:09:34 -0400212struct edma_chan {
213 struct virt_dma_chan vchan;
214 struct list_head node;
215 struct edma_desc *edesc;
216 struct edma_cc *ecc;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300217 struct edma_tc *tc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400218 int ch_num;
219 bool alloced;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300220 bool hw_triggered;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400221 int slot[EDMA_MAX_SLOTS];
Joel Fernandesc5f47992013-08-29 18:05:43 -0500222 int missed;
Matt Porter661f7cb2013-01-10 13:41:04 -0500223 struct dma_slave_config cfg;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400224};
225
226struct edma_cc {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300227 struct device *dev;
228 struct edma_soc_info *info;
229 void __iomem *base;
230 int id;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300231 bool legacy_mode;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300232
233 /* eDMA3 resource information */
234 unsigned num_channels;
Peter Ujfalusi633e42b2015-10-16 10:18:04 +0300235 unsigned num_qchannels;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300236 unsigned num_region;
237 unsigned num_slots;
238 unsigned num_tc;
Peter Ujfalusi4ab54f62015-10-14 14:43:04 +0300239 bool chmap_exist;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300240 enum dma_event_q default_queue;
241
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300242 /*
243 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
244 * in use by Linux or if it is allocated to be used by DSP.
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300245 */
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300246 unsigned long *slot_inuse;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300247
Matt Porterc2dde5f2012-08-22 21:09:34 -0400248 struct dma_device dma_slave;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300249 struct dma_device *dma_memcpy;
Peter Ujfalusicb782052015-10-14 14:42:54 +0300250 struct edma_chan *slave_chans;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300251 struct edma_tc *tc_list;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400252 int dummy_slot;
253};
254
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300255/* dummy param set used to (re)initialize parameter RAM slots */
256static const struct edmacc_param dummy_paramset = {
257 .link_bcntrld = 0xffff,
258 .ccnt = 1,
259};
260
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300261#define EDMA_BINDING_LEGACY 0
262#define EDMA_BINDING_TPCC 1
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300263static const struct of_device_id edma_of_ids[] = {
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300264 {
265 .compatible = "ti,edma3",
266 .data = (void *)EDMA_BINDING_LEGACY,
267 },
268 {
269 .compatible = "ti,edma3-tpcc",
270 .data = (void *)EDMA_BINDING_TPCC,
271 },
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300272 {}
273};
274
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +0200275static const struct of_device_id edma_tptc_of_ids[] = {
276 { .compatible = "ti,edma3-tptc", },
277 {}
278};
279
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300280static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
281{
282 return (unsigned int)__raw_readl(ecc->base + offset);
283}
284
285static inline void edma_write(struct edma_cc *ecc, int offset, int val)
286{
287 __raw_writel(val, ecc->base + offset);
288}
289
290static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
291 unsigned or)
292{
293 unsigned val = edma_read(ecc, offset);
294
295 val &= and;
296 val |= or;
297 edma_write(ecc, offset, val);
298}
299
300static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
301{
302 unsigned val = edma_read(ecc, offset);
303
304 val &= and;
305 edma_write(ecc, offset, val);
306}
307
308static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
309{
310 unsigned val = edma_read(ecc, offset);
311
312 val |= or;
313 edma_write(ecc, offset, val);
314}
315
316static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
317 int i)
318{
319 return edma_read(ecc, offset + (i << 2));
320}
321
322static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
323 unsigned val)
324{
325 edma_write(ecc, offset + (i << 2), val);
326}
327
328static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
329 unsigned and, unsigned or)
330{
331 edma_modify(ecc, offset + (i << 2), and, or);
332}
333
334static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
335 unsigned or)
336{
337 edma_or(ecc, offset + (i << 2), or);
338}
339
340static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
341 unsigned or)
342{
343 edma_or(ecc, offset + ((i * 2 + j) << 2), or);
344}
345
346static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
347 int j, unsigned val)
348{
349 edma_write(ecc, offset + ((i * 2 + j) << 2), val);
350}
351
352static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
353{
354 return edma_read(ecc, EDMA_SHADOW0 + offset);
355}
356
357static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
358 int offset, int i)
359{
360 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
361}
362
363static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
364 unsigned val)
365{
366 edma_write(ecc, EDMA_SHADOW0 + offset, val);
367}
368
369static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
370 int i, unsigned val)
371{
372 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
373}
374
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300375static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
376 int param_no)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300377{
378 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
379}
380
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300381static inline void edma_param_write(struct edma_cc *ecc, int offset,
382 int param_no, unsigned val)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300383{
384 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
385}
386
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300387static inline void edma_param_modify(struct edma_cc *ecc, int offset,
388 int param_no, unsigned and, unsigned or)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300389{
390 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
391}
392
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300393static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
394 unsigned and)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300395{
396 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
397}
398
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300399static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
400 unsigned or)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300401{
402 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
403}
404
405static inline void set_bits(int offset, int len, unsigned long *p)
406{
407 for (; len > 0; len--)
408 set_bit(offset + (len - 1), p);
409}
410
411static inline void clear_bits(int offset, int len, unsigned long *p)
412{
413 for (; len > 0; len--)
414 clear_bit(offset + (len - 1), p);
415}
416
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300417static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
418 int priority)
419{
420 int bit = queue_no * 4;
421
422 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
423}
424
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300425static void edma_set_chmap(struct edma_chan *echan, int slot)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300426{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300427 struct edma_cc *ecc = echan->ecc;
428 int channel = EDMA_CHAN_SLOT(echan->ch_num);
429
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300430 if (ecc->chmap_exist) {
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300431 slot = EDMA_CHAN_SLOT(slot);
432 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
433 }
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300434}
435
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300436static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300437{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300438 struct edma_cc *ecc = echan->ecc;
439 int channel = EDMA_CHAN_SLOT(echan->ch_num);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300440
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +0300441 if (enable) {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300442 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
443 BIT(channel & 0x1f));
444 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
445 BIT(channel & 0x1f));
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +0300446 } else {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300447 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
448 BIT(channel & 0x1f));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300449 }
450}
451
452/*
Peter Ujfalusi11c15732015-10-14 14:43:00 +0300453 * paRAM slot management functions
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300454 */
455static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
456 const struct edmacc_param *param)
457{
458 slot = EDMA_CHAN_SLOT(slot);
459 if (slot >= ecc->num_slots)
460 return;
461 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
462}
463
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300464static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
465 struct edmacc_param *param)
466{
467 slot = EDMA_CHAN_SLOT(slot);
468 if (slot >= ecc->num_slots)
469 return;
470 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
471}
472
473/**
474 * edma_alloc_slot - allocate DMA parameter RAM
475 * @ecc: pointer to edma_cc struct
476 * @slot: specific slot to allocate; negative for "any unused slot"
477 *
478 * This allocates a parameter RAM slot, initializing it to hold a
479 * dummy transfer. Slots allocated using this routine have not been
480 * mapped to a hardware DMA channel, and will normally be used by
481 * linking to them from a slot associated with a DMA channel.
482 *
483 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
484 * slots may be allocated on behalf of DSP firmware.
485 *
486 * Returns the number of the slot, else negative errno.
487 */
488static int edma_alloc_slot(struct edma_cc *ecc, int slot)
489{
Peter Ujfalusid20313b2016-01-11 10:38:01 +0200490 if (slot >= 0) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300491 slot = EDMA_CHAN_SLOT(slot);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300492 /* Requesting entry paRAM slot for a HW triggered channel. */
493 if (ecc->chmap_exist && slot < ecc->num_channels)
494 slot = EDMA_SLOT_ANY;
495 }
496
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300497 if (slot < 0) {
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300498 if (ecc->chmap_exist)
499 slot = 0;
500 else
501 slot = ecc->num_channels;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300502 for (;;) {
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300503 slot = find_next_zero_bit(ecc->slot_inuse,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300504 ecc->num_slots,
505 slot);
506 if (slot == ecc->num_slots)
507 return -ENOMEM;
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300508 if (!test_and_set_bit(slot, ecc->slot_inuse))
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300509 break;
510 }
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300511 } else if (slot >= ecc->num_slots) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300512 return -EINVAL;
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300513 } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300514 return -EBUSY;
515 }
516
517 edma_write_slot(ecc, slot, &dummy_paramset);
518
519 return EDMA_CTLR_CHAN(ecc->id, slot);
520}
521
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300522static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
523{
524 slot = EDMA_CHAN_SLOT(slot);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300525 if (slot >= ecc->num_slots)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300526 return;
527
528 edma_write_slot(ecc, slot, &dummy_paramset);
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300529 clear_bit(slot, ecc->slot_inuse);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300530}
531
532/**
533 * edma_link - link one parameter RAM slot to another
534 * @ecc: pointer to edma_cc struct
535 * @from: parameter RAM slot originating the link
536 * @to: parameter RAM slot which is the link target
537 *
538 * The originating slot should not be part of any active DMA transfer.
539 */
540static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
541{
Peter Ujfalusifc014092015-10-14 14:42:59 +0300542 if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
543 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
544
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300545 from = EDMA_CHAN_SLOT(from);
546 to = EDMA_CHAN_SLOT(to);
547 if (from >= ecc->num_slots || to >= ecc->num_slots)
548 return;
549
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300550 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
551 PARM_OFFSET(to));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300552}
553
554/**
555 * edma_get_position - returns the current transfer point
556 * @ecc: pointer to edma_cc struct
557 * @slot: parameter RAM slot being examined
558 * @dst: true selects the dest position, false the source
559 *
560 * Returns the position of the current active slot
561 */
562static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
563 bool dst)
564{
565 u32 offs;
566
567 slot = EDMA_CHAN_SLOT(slot);
568 offs = PARM_OFFSET(slot);
569 offs += dst ? PARM_DST : PARM_SRC;
570
571 return edma_read(ecc, offs);
572}
573
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300574/*
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300575 * Channels with event associations will be triggered by their hardware
576 * events, and channels without such associations will be triggered by
577 * software. (At this writing there is no interface for using software
578 * triggers except with channels that don't support hardware triggers.)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300579 */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300580static void edma_start(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300581{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300582 struct edma_cc *ecc = echan->ecc;
583 int channel = EDMA_CHAN_SLOT(echan->ch_num);
584 int j = (channel >> 5);
585 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300586
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300587 if (!echan->hw_triggered) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300588 /* EDMA channels without event association */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300589 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
590 edma_shadow0_read_array(ecc, SH_ESR, j));
591 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
592 } else {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300593 /* EDMA channel with event association */
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300594 dev_dbg(ecc->dev, "ER%d %08x\n", j,
595 edma_shadow0_read_array(ecc, SH_ER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300596 /* Clear any pending event or error */
597 edma_write_array(ecc, EDMA_ECR, j, mask);
598 edma_write_array(ecc, EDMA_EMCR, j, mask);
599 /* Clear any SER */
600 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
601 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300602 dev_dbg(ecc->dev, "EER%d %08x\n", j,
603 edma_shadow0_read_array(ecc, SH_EER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300604 }
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300605}
606
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300607static void edma_stop(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300608{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300609 struct edma_cc *ecc = echan->ecc;
610 int channel = EDMA_CHAN_SLOT(echan->ch_num);
611 int j = (channel >> 5);
612 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300613
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300614 edma_shadow0_write_array(ecc, SH_EECR, j, mask);
615 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
616 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
617 edma_write_array(ecc, EDMA_EMCR, j, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300618
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300619 /* clear possibly pending completion interrupt */
620 edma_shadow0_write_array(ecc, SH_ICR, j, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300621
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300622 dev_dbg(ecc->dev, "EER%d %08x\n", j,
623 edma_shadow0_read_array(ecc, SH_EER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300624
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300625 /* REVISIT: consider guarding against inappropriate event
626 * chaining by overwriting with dummy_paramset.
627 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300628}
629
Peter Ujfalusi11c15732015-10-14 14:43:00 +0300630/*
631 * Temporarily disable EDMA hardware events on the specified channel,
632 * preventing them from triggering new transfers
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300633 */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300634static void edma_pause(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300635{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300636 int channel = EDMA_CHAN_SLOT(echan->ch_num);
637 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300638
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300639 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300640}
641
Peter Ujfalusi11c15732015-10-14 14:43:00 +0300642/* Re-enable EDMA hardware events on the specified channel. */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300643static void edma_resume(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300644{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300645 int channel = EDMA_CHAN_SLOT(echan->ch_num);
646 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300647
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300648 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300649}
650
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300651static void edma_trigger_channel(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300652{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300653 struct edma_cc *ecc = echan->ecc;
654 int channel = EDMA_CHAN_SLOT(echan->ch_num);
655 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300656
657 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
658
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300659 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
660 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300661}
662
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300663static void edma_clean_channel(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300664{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300665 struct edma_cc *ecc = echan->ecc;
666 int channel = EDMA_CHAN_SLOT(echan->ch_num);
667 int j = (channel >> 5);
668 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300669
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300670 dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
671 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
672 /* Clear the corresponding EMR bits */
673 edma_write_array(ecc, EDMA_EMCR, j, mask);
674 /* Clear any SER */
675 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
676 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300677}
678
Peter Ujfalusif9425de2015-10-16 10:18:03 +0300679/* Move channel to a specific event queue */
680static void edma_assign_channel_eventq(struct edma_chan *echan,
681 enum dma_event_q eventq_no)
682{
683 struct edma_cc *ecc = echan->ecc;
684 int channel = EDMA_CHAN_SLOT(echan->ch_num);
685 int bit = (channel & 0x7) * 4;
686
687 /* default to low priority queue */
688 if (eventq_no == EVENTQ_DEFAULT)
689 eventq_no = ecc->default_queue;
690 if (eventq_no >= ecc->num_tc)
691 return;
692
693 eventq_no &= 7;
694 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
695 eventq_no << bit);
696}
697
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300698static int edma_alloc_channel(struct edma_chan *echan,
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +0300699 enum dma_event_q eventq_no)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300700{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300701 struct edma_cc *ecc = echan->ecc;
702 int channel = EDMA_CHAN_SLOT(echan->ch_num);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300703
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300704 /* ensure access through shadow region 0 */
705 edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
706
707 /* ensure no events are pending */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300708 edma_stop(echan);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300709
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300710 edma_setup_interrupt(echan, true);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300711
Peter Ujfalusif9425de2015-10-16 10:18:03 +0300712 edma_assign_channel_eventq(echan, eventq_no);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300713
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300714 return 0;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300715}
716
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300717static void edma_free_channel(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300718{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300719 /* ensure no events are pending */
720 edma_stop(echan);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300721 /* REVISIT should probably take out of shadow region 0 */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300722 edma_setup_interrupt(echan, false);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300723}
724
Matt Porterc2dde5f2012-08-22 21:09:34 -0400725static inline struct edma_cc *to_edma_cc(struct dma_device *d)
726{
727 return container_of(d, struct edma_cc, dma_slave);
728}
729
730static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
731{
732 return container_of(c, struct edma_chan, vchan.chan);
733}
734
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300735static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400736{
737 return container_of(tx, struct edma_desc, vdesc.tx);
738}
739
740static void edma_desc_free(struct virt_dma_desc *vdesc)
741{
742 kfree(container_of(vdesc, struct edma_desc, vdesc));
743}
744
745/* Dispatch a queued descriptor to the controller (caller holds lock) */
746static void edma_execute(struct edma_chan *echan)
747{
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300748 struct edma_cc *ecc = echan->ecc;
Joel Fernandes53407062013-09-03 10:02:46 -0500749 struct virt_dma_desc *vdesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400750 struct edma_desc *edesc;
Joel Fernandes53407062013-09-03 10:02:46 -0500751 struct device *dev = echan->vchan.chan.device->dev;
752 int i, j, left, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400753
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300754 if (!echan->edesc) {
755 /* Setup is needed for the first transfer */
Joel Fernandes53407062013-09-03 10:02:46 -0500756 vdesc = vchan_next_desc(&echan->vchan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300757 if (!vdesc)
Joel Fernandes53407062013-09-03 10:02:46 -0500758 return;
Joel Fernandes53407062013-09-03 10:02:46 -0500759 list_del(&vdesc->node);
760 echan->edesc = to_edma_desc(&vdesc->tx);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400761 }
762
Joel Fernandes53407062013-09-03 10:02:46 -0500763 edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400764
Joel Fernandes53407062013-09-03 10:02:46 -0500765 /* Find out how many left */
766 left = edesc->pset_nr - edesc->processed;
767 nslots = min(MAX_NR_SG, left);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500768 edesc->sg_len = 0;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400769
770 /* Write descriptor PaRAM set(s) */
Joel Fernandes53407062013-09-03 10:02:46 -0500771 for (i = 0; i < nslots; i++) {
772 j = i + edesc->processed;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300773 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500774 edesc->sg_len += edesc->pset[j].len;
Peter Ujfalusi907f74a2015-10-14 14:42:56 +0300775 dev_vdbg(dev,
776 "\n pset[%d]:\n"
777 " chnum\t%d\n"
778 " slot\t%d\n"
779 " opt\t%08x\n"
780 " src\t%08x\n"
781 " dst\t%08x\n"
782 " abcnt\t%08x\n"
783 " ccnt\t%08x\n"
784 " bidx\t%08x\n"
785 " cidx\t%08x\n"
786 " lkrld\t%08x\n",
787 j, echan->ch_num, echan->slot[i],
788 edesc->pset[j].param.opt,
789 edesc->pset[j].param.src,
790 edesc->pset[j].param.dst,
791 edesc->pset[j].param.a_b_cnt,
792 edesc->pset[j].param.ccnt,
793 edesc->pset[j].param.src_dst_bidx,
794 edesc->pset[j].param.src_dst_cidx,
795 edesc->pset[j].param.link_bcntrld);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400796 /* Link to the previous slot if not the last set */
Joel Fernandes53407062013-09-03 10:02:46 -0500797 if (i != (nslots - 1))
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300798 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400799 }
800
Joel Fernandes53407062013-09-03 10:02:46 -0500801 edesc->processed += nslots;
802
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500803 /*
804 * If this is either the last set in a set of SG-list transactions
805 * then setup a link to the dummy slot, this results in all future
806 * events being absorbed and that's OK because we're done
807 */
Joel Fernandes50a9c702013-10-31 16:31:23 -0500808 if (edesc->processed == edesc->pset_nr) {
809 if (edesc->cyclic)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300810 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500811 else
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300812 edma_link(ecc, echan->slot[nslots - 1],
Joel Fernandes50a9c702013-10-31 16:31:23 -0500813 echan->ecc->dummy_slot);
814 }
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500815
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300816 if (echan->missed) {
817 /*
818 * This happens due to setup times between intermediate
819 * transfers in long SG lists which have to be broken up into
820 * transfers of MAX_NR_SG
821 */
822 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300823 edma_clean_channel(echan);
824 edma_stop(echan);
825 edma_start(echan);
826 edma_trigger_channel(echan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300827 echan->missed = 0;
828 } else if (edesc->processed <= MAX_NR_SG) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300829 dev_dbg(dev, "first transfer starting on channel %d\n",
830 echan->ch_num);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300831 edma_start(echan);
Sekhar Nori5fc68a62014-03-19 11:25:50 +0530832 } else {
833 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
834 echan->ch_num, edesc->processed);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300835 edma_resume(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500836 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400837}
838
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100839static int edma_terminate_all(struct dma_chan *chan)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400840{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100841 struct edma_chan *echan = to_edma_chan(chan);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400842 unsigned long flags;
843 LIST_HEAD(head);
844
845 spin_lock_irqsave(&echan->vchan.lock, flags);
846
847 /*
848 * Stop DMA activity: we assume the callback will not be called
849 * after edma_dma() returns (even if it does, it will see
850 * echan->edesc is NULL and exit.)
851 */
852 if (echan->edesc) {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300853 edma_stop(echan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300854 /* Move the cyclic channel back to default queue */
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300855 if (!echan->tc && echan->edesc->cyclic)
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300856 edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
Petr Kulhavy5ca9e7c2015-03-27 13:35:51 +0200857 /*
858 * free the running request descriptor
859 * since it is not in any of the vdesc lists
860 */
861 edma_desc_free(&echan->edesc->vdesc);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400862 echan->edesc = NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400863 }
864
865 vchan_get_all_descriptors(&echan->vchan, &head);
866 spin_unlock_irqrestore(&echan->vchan.lock, flags);
867 vchan_dma_desc_free_list(&echan->vchan, &head);
868
869 return 0;
870}
871
Peter Ujfalusib84730f2016-02-11 11:08:42 +0200872static void edma_synchronize(struct dma_chan *chan)
873{
874 struct edma_chan *echan = to_edma_chan(chan);
875
876 vchan_synchronize(&echan->vchan);
877}
878
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100879static int edma_slave_config(struct dma_chan *chan,
Matt Porter661f7cb2013-01-10 13:41:04 -0500880 struct dma_slave_config *cfg)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400881{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100882 struct edma_chan *echan = to_edma_chan(chan);
883
Matt Porter661f7cb2013-01-10 13:41:04 -0500884 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
885 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400886 return -EINVAL;
887
Matt Porter661f7cb2013-01-10 13:41:04 -0500888 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400889
890 return 0;
891}
892
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100893static int edma_dma_pause(struct dma_chan *chan)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300894{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100895 struct edma_chan *echan = to_edma_chan(chan);
896
John Ogness02ec6042015-04-27 13:52:25 +0200897 if (!echan->edesc)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300898 return -EINVAL;
899
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300900 edma_pause(echan);
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300901 return 0;
902}
903
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100904static int edma_dma_resume(struct dma_chan *chan)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300905{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100906 struct edma_chan *echan = to_edma_chan(chan);
907
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300908 edma_resume(echan);
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300909 return 0;
910}
911
Joel Fernandesfd009032013-09-23 18:05:13 -0500912/*
913 * A PaRAM set configuration abstraction used by other modes
914 * @chan: Channel who's PaRAM set we're configuring
915 * @pset: PaRAM set to initialize and setup.
916 * @src_addr: Source address of the DMA
917 * @dst_addr: Destination address of the DMA
918 * @burst: In units of dev_width, how much to send
919 * @dev_width: How much is the dev_width
920 * @dma_length: Total length of the DMA transfer
921 * @direction: Direction of the transfer
922 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500923static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300924 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
Peter Ujfalusidf6694f2015-10-16 10:18:00 +0300925 unsigned int acnt, unsigned int dma_length,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300926 enum dma_transfer_direction direction)
Joel Fernandesfd009032013-09-23 18:05:13 -0500927{
928 struct edma_chan *echan = to_edma_chan(chan);
929 struct device *dev = chan->device->dev;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500930 struct edmacc_param *param = &epset->param;
Peter Ujfalusidf6694f2015-10-16 10:18:00 +0300931 int bcnt, ccnt, cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -0500932 int src_bidx, dst_bidx, src_cidx, dst_cidx;
933 int absync;
934
Peter Ujfalusib2b617d2014-04-14 14:41:58 +0300935 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
936 if (!burst)
937 burst = 1;
Joel Fernandesfd009032013-09-23 18:05:13 -0500938 /*
939 * If the maxburst is equal to the fifo width, use
940 * A-synced transfers. This allows for large contiguous
941 * buffer transfers using only one PaRAM set.
942 */
943 if (burst == 1) {
944 /*
945 * For the A-sync case, bcnt and ccnt are the remainder
946 * and quotient respectively of the division of:
947 * (dma_length / acnt) by (SZ_64K -1). This is so
948 * that in case bcnt over flows, we have ccnt to use.
949 * Note: In A-sync tranfer only, bcntrld is used, but it
950 * only applies for sg_dma_len(sg) >= SZ_64K.
951 * In this case, the best way adopted is- bccnt for the
952 * first frame will be the remainder below. Then for
953 * every successive frame, bcnt will be SZ_64K-1. This
954 * is assured as bcntrld = 0xffff in end of function.
955 */
956 absync = false;
957 ccnt = dma_length / acnt / (SZ_64K - 1);
958 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
959 /*
960 * If bcnt is non-zero, we have a remainder and hence an
961 * extra frame to transfer, so increment ccnt.
962 */
963 if (bcnt)
964 ccnt++;
965 else
966 bcnt = SZ_64K - 1;
967 cidx = acnt;
968 } else {
969 /*
970 * If maxburst is greater than the fifo address_width,
971 * use AB-synced transfers where A count is the fifo
972 * address_width and B count is the maxburst. In this
973 * case, we are limited to transfers of C count frames
974 * of (address_width * maxburst) where C count is limited
975 * to SZ_64K-1. This places an upper bound on the length
976 * of an SG segment that can be handled.
977 */
978 absync = true;
979 bcnt = burst;
980 ccnt = dma_length / (acnt * bcnt);
981 if (ccnt > (SZ_64K - 1)) {
982 dev_err(dev, "Exceeded max SG segment size\n");
983 return -EINVAL;
984 }
985 cidx = acnt * bcnt;
986 }
987
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500988 epset->len = dma_length;
989
Joel Fernandesfd009032013-09-23 18:05:13 -0500990 if (direction == DMA_MEM_TO_DEV) {
991 src_bidx = acnt;
992 src_cidx = cidx;
993 dst_bidx = 0;
994 dst_cidx = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500995 epset->addr = src_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -0500996 } else if (direction == DMA_DEV_TO_MEM) {
997 src_bidx = 0;
998 src_cidx = 0;
999 dst_bidx = acnt;
1000 dst_cidx = cidx;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001001 epset->addr = dst_addr;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001002 } else if (direction == DMA_MEM_TO_MEM) {
1003 src_bidx = acnt;
1004 src_cidx = cidx;
1005 dst_bidx = acnt;
1006 dst_cidx = cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -05001007 } else {
1008 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1009 return -EINVAL;
1010 }
1011
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001012 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
Joel Fernandesfd009032013-09-23 18:05:13 -05001013 /* Configure A or AB synchronized transfers */
1014 if (absync)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001015 param->opt |= SYNCDIM;
Joel Fernandesfd009032013-09-23 18:05:13 -05001016
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001017 param->src = src_addr;
1018 param->dst = dst_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -05001019
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001020 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1021 param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -05001022
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001023 param->a_b_cnt = bcnt << 16 | acnt;
1024 param->ccnt = ccnt;
Joel Fernandesfd009032013-09-23 18:05:13 -05001025 /*
1026 * Only time when (bcntrld) auto reload is required is for
1027 * A-sync case, and in this case, a requirement of reload value
1028 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1029 * and then later will be populated by edma_execute.
1030 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001031 param->link_bcntrld = 0xffffffff;
Joel Fernandesfd009032013-09-23 18:05:13 -05001032 return absync;
1033}
1034
Matt Porterc2dde5f2012-08-22 21:09:34 -04001035static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1036 struct dma_chan *chan, struct scatterlist *sgl,
1037 unsigned int sg_len, enum dma_transfer_direction direction,
1038 unsigned long tx_flags, void *context)
1039{
1040 struct edma_chan *echan = to_edma_chan(chan);
1041 struct device *dev = chan->device->dev;
1042 struct edma_desc *edesc;
Joel Fernandesfd009032013-09-23 18:05:13 -05001043 dma_addr_t src_addr = 0, dst_addr = 0;
Matt Porter661f7cb2013-01-10 13:41:04 -05001044 enum dma_slave_buswidth dev_width;
1045 u32 burst;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001046 struct scatterlist *sg;
Joel Fernandesfd009032013-09-23 18:05:13 -05001047 int i, nslots, ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001048
1049 if (unlikely(!echan || !sgl || !sg_len))
1050 return NULL;
1051
Matt Porter661f7cb2013-01-10 13:41:04 -05001052 if (direction == DMA_DEV_TO_MEM) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001053 src_addr = echan->cfg.src_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -05001054 dev_width = echan->cfg.src_addr_width;
1055 burst = echan->cfg.src_maxburst;
1056 } else if (direction == DMA_MEM_TO_DEV) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001057 dst_addr = echan->cfg.dst_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -05001058 dev_width = echan->cfg.dst_addr_width;
1059 burst = echan->cfg.dst_maxburst;
1060 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +03001061 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Matt Porter661f7cb2013-01-10 13:41:04 -05001062 return NULL;
1063 }
1064
1065 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001066 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001067 return NULL;
1068 }
1069
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001070 edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1071 GFP_ATOMIC);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001072 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001073 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001074 return NULL;
1075 }
1076
1077 edesc->pset_nr = sg_len;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001078 edesc->residue = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001079 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001080 edesc->echan = echan;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001081
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001082 /* Allocate a PaRAM slot, if needed */
1083 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1084
1085 for (i = 0; i < nslots; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -04001086 if (echan->slot[i] < 0) {
1087 echan->slot[i] =
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001088 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001089 if (echan->slot[i] < 0) {
Valentin Ilie4b6271a2013-10-24 16:14:22 +03001090 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +03001091 dev_err(dev, "%s: Failed to allocate slot\n",
1092 __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001093 return NULL;
1094 }
1095 }
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001096 }
1097
1098 /* Configure PaRAM sets for each SG */
1099 for_each_sg(sgl, sg, sg_len, i) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001100 /* Get address for each SG */
1101 if (direction == DMA_DEV_TO_MEM)
1102 dst_addr = sg_dma_address(sg);
1103 else
1104 src_addr = sg_dma_address(sg);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001105
Joel Fernandesfd009032013-09-23 18:05:13 -05001106 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1107 dst_addr, burst, dev_width,
1108 sg_dma_len(sg), direction);
Vinod Koulb967aec2013-10-30 13:07:18 +05301109 if (ret < 0) {
1110 kfree(edesc);
Joel Fernandesfd009032013-09-23 18:05:13 -05001111 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001112 }
1113
Joel Fernandesfd009032013-09-23 18:05:13 -05001114 edesc->absync = ret;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001115 edesc->residue += sg_dma_len(sg);
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001116
1117 /* If this is the last in a current SG set of transactions,
1118 enable interrupts so that next set is processed */
1119 if (!((i+1) % MAX_NR_SG))
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001120 edesc->pset[i].param.opt |= TCINTEN;
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001121
Matt Porterc2dde5f2012-08-22 21:09:34 -04001122 /* If this is the last set, enable completion interrupt flag */
1123 if (i == sg_len - 1)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001124 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001125 }
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001126 edesc->residue_stat = edesc->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001127
Matt Porterc2dde5f2012-08-22 21:09:34 -04001128 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1129}
Matt Porterc2dde5f2012-08-22 21:09:34 -04001130
Lad, Prabhakarb7a4fd52015-02-04 13:03:27 +00001131static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001132 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1133 size_t len, unsigned long tx_flags)
1134{
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001135 int ret, nslots;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001136 struct edma_desc *edesc;
1137 struct device *dev = chan->device->dev;
1138 struct edma_chan *echan = to_edma_chan(chan);
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001139 unsigned int width, pset_len;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001140
1141 if (unlikely(!echan || !len))
1142 return NULL;
1143
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001144 if (len < SZ_64K) {
1145 /*
1146 * Transfer size less than 64K can be handled with one paRAM
1147 * slot and with one burst.
1148 * ACNT = length
1149 */
1150 width = len;
1151 pset_len = len;
1152 nslots = 1;
1153 } else {
1154 /*
1155 * Transfer size bigger than 64K will be handled with maximum of
1156 * two paRAM slots.
1157 * slot1: (full_length / 32767) times 32767 bytes bursts.
1158 * ACNT = 32767, length1: (full_length / 32767) * 32767
1159 * slot2: the remaining amount of data after slot1.
1160 * ACNT = full_length - length1, length2 = ACNT
1161 *
1162 * When the full_length is multibple of 32767 one slot can be
1163 * used to complete the transfer.
1164 */
1165 width = SZ_32K - 1;
1166 pset_len = rounddown(len, width);
1167 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1168 if (unlikely(pset_len == len))
1169 nslots = 1;
1170 else
1171 nslots = 2;
1172 }
1173
1174 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1175 GFP_ATOMIC);
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001176 if (!edesc) {
1177 dev_dbg(dev, "Failed to allocate a descriptor\n");
1178 return NULL;
1179 }
1180
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001181 edesc->pset_nr = nslots;
1182 edesc->residue = edesc->residue_stat = len;
1183 edesc->direction = DMA_MEM_TO_MEM;
1184 edesc->echan = echan;
Peter Ujfalusi21a31842015-10-16 10:17:59 +03001185
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001186 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001187 width, pset_len, DMA_MEM_TO_MEM);
1188 if (ret < 0) {
1189 kfree(edesc);
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001190 return NULL;
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001191 }
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001192
1193 edesc->absync = ret;
1194
Joel Fernandesb0cce4c2014-04-28 15:30:32 -05001195 edesc->pset[0].param.opt |= ITCCHEN;
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001196 if (nslots == 1) {
1197 /* Enable transfer complete interrupt */
1198 edesc->pset[0].param.opt |= TCINTEN;
1199 } else {
1200 /* Enable transfer complete chaining for the first slot */
1201 edesc->pset[0].param.opt |= TCCHEN;
1202
1203 if (echan->slot[1] < 0) {
1204 echan->slot[1] = edma_alloc_slot(echan->ecc,
1205 EDMA_SLOT_ANY);
1206 if (echan->slot[1] < 0) {
1207 kfree(edesc);
1208 dev_err(dev, "%s: Failed to allocate slot\n",
1209 __func__);
1210 return NULL;
1211 }
1212 }
1213 dest += pset_len;
1214 src += pset_len;
1215 pset_len = width = len % (SZ_32K - 1);
1216
1217 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1218 width, pset_len, DMA_MEM_TO_MEM);
1219 if (ret < 0) {
1220 kfree(edesc);
1221 return NULL;
1222 }
1223
1224 edesc->pset[1].param.opt |= ITCCHEN;
1225 edesc->pset[1].param.opt |= TCINTEN;
1226 }
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001227
1228 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1229}
1230
Joel Fernandes50a9c702013-10-31 16:31:23 -05001231static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1232 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1233 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02001234 unsigned long tx_flags)
Joel Fernandes50a9c702013-10-31 16:31:23 -05001235{
1236 struct edma_chan *echan = to_edma_chan(chan);
1237 struct device *dev = chan->device->dev;
1238 struct edma_desc *edesc;
1239 dma_addr_t src_addr, dst_addr;
1240 enum dma_slave_buswidth dev_width;
John Ognessa482f4e2016-04-06 13:01:47 +03001241 bool use_intermediate = false;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001242 u32 burst;
1243 int i, ret, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001244
Joel Fernandes50a9c702013-10-31 16:31:23 -05001245 if (unlikely(!echan || !buf_len || !period_len))
1246 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001247
Joel Fernandes50a9c702013-10-31 16:31:23 -05001248 if (direction == DMA_DEV_TO_MEM) {
1249 src_addr = echan->cfg.src_addr;
1250 dst_addr = buf_addr;
1251 dev_width = echan->cfg.src_addr_width;
1252 burst = echan->cfg.src_maxburst;
1253 } else if (direction == DMA_MEM_TO_DEV) {
1254 src_addr = buf_addr;
1255 dst_addr = echan->cfg.dst_addr;
1256 dev_width = echan->cfg.dst_addr_width;
1257 burst = echan->cfg.dst_maxburst;
1258 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +03001259 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001260 return NULL;
1261 }
1262
1263 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001264 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001265 return NULL;
1266 }
1267
1268 if (unlikely(buf_len % period_len)) {
1269 dev_err(dev, "Period should be multiple of Buffer length\n");
1270 return NULL;
1271 }
1272
1273 nslots = (buf_len / period_len) + 1;
1274
1275 /*
1276 * Cyclic DMA users such as audio cannot tolerate delays introduced
1277 * by cases where the number of periods is more than the maximum
1278 * number of SGs the EDMA driver can handle at a time. For DMA types
1279 * such as Slave SGs, such delays are tolerable and synchronized,
1280 * but the synchronization is difficult to achieve with Cyclic and
1281 * cannot be guaranteed, so we error out early.
1282 */
John Ognessa482f4e2016-04-06 13:01:47 +03001283 if (nslots > MAX_NR_SG) {
1284 /*
1285 * If the burst and period sizes are the same, we can put
1286 * the full buffer into a single period and activate
1287 * intermediate interrupts. This will produce interrupts
1288 * after each burst, which is also after each desired period.
1289 */
1290 if (burst == period_len) {
1291 period_len = buf_len;
1292 nslots = 2;
1293 use_intermediate = true;
1294 } else {
1295 return NULL;
1296 }
1297 }
Joel Fernandes50a9c702013-10-31 16:31:23 -05001298
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001299 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1300 GFP_ATOMIC);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001301 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001302 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001303 return NULL;
1304 }
1305
1306 edesc->cyclic = 1;
1307 edesc->pset_nr = nslots;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001308 edesc->residue = edesc->residue_stat = buf_len;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001309 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001310 edesc->echan = echan;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001311
Peter Ujfalusi83bb3122014-04-14 14:42:02 +03001312 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1313 __func__, echan->ch_num, nslots, period_len, buf_len);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001314
1315 for (i = 0; i < nslots; i++) {
1316 /* Allocate a PaRAM slot, if needed */
1317 if (echan->slot[i] < 0) {
1318 echan->slot[i] =
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001319 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001320 if (echan->slot[i] < 0) {
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001321 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +03001322 dev_err(dev, "%s: Failed to allocate slot\n",
1323 __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001324 return NULL;
1325 }
1326 }
1327
1328 if (i == nslots - 1) {
1329 memcpy(&edesc->pset[i], &edesc->pset[0],
1330 sizeof(edesc->pset[0]));
1331 break;
1332 }
1333
1334 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1335 dst_addr, burst, dev_width, period_len,
1336 direction);
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001337 if (ret < 0) {
1338 kfree(edesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001339 return NULL;
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001340 }
Joel Fernandes50a9c702013-10-31 16:31:23 -05001341
1342 if (direction == DMA_DEV_TO_MEM)
1343 dst_addr += period_len;
1344 else
1345 src_addr += period_len;
1346
Peter Ujfalusi83bb3122014-04-14 14:42:02 +03001347 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1348 dev_vdbg(dev,
Joel Fernandes50a9c702013-10-31 16:31:23 -05001349 "\n pset[%d]:\n"
1350 " chnum\t%d\n"
1351 " slot\t%d\n"
1352 " opt\t%08x\n"
1353 " src\t%08x\n"
1354 " dst\t%08x\n"
1355 " abcnt\t%08x\n"
1356 " ccnt\t%08x\n"
1357 " bidx\t%08x\n"
1358 " cidx\t%08x\n"
1359 " lkrld\t%08x\n",
1360 i, echan->ch_num, echan->slot[i],
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001361 edesc->pset[i].param.opt,
1362 edesc->pset[i].param.src,
1363 edesc->pset[i].param.dst,
1364 edesc->pset[i].param.a_b_cnt,
1365 edesc->pset[i].param.ccnt,
1366 edesc->pset[i].param.src_dst_bidx,
1367 edesc->pset[i].param.src_dst_cidx,
1368 edesc->pset[i].param.link_bcntrld);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001369
1370 edesc->absync = ret;
1371
1372 /*
Peter Ujfalusia1f146f2014-07-16 15:29:21 +03001373 * Enable period interrupt only if it is requested
Joel Fernandes50a9c702013-10-31 16:31:23 -05001374 */
John Ognessa482f4e2016-04-06 13:01:47 +03001375 if (tx_flags & DMA_PREP_INTERRUPT) {
Peter Ujfalusia1f146f2014-07-16 15:29:21 +03001376 edesc->pset[i].param.opt |= TCINTEN;
John Ognessa482f4e2016-04-06 13:01:47 +03001377
1378 /* Also enable intermediate interrupts if necessary */
1379 if (use_intermediate)
1380 edesc->pset[i].param.opt |= ITCINTEN;
1381 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001382 }
1383
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +03001384 /* Place the cyclic channel to highest priority queue */
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001385 if (!echan->tc)
1386 edma_assign_channel_eventq(echan, EVENTQ_0);
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +03001387
Matt Porterc2dde5f2012-08-22 21:09:34 -04001388 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1389}
1390
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001391static void edma_completion_handler(struct edma_chan *echan)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001392{
Matt Porterc2dde5f2012-08-22 21:09:34 -04001393 struct device *dev = echan->vchan.chan.device->dev;
Peter Ujfalusie4d88172016-02-11 15:17:48 +02001394 struct edma_desc *edesc;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001395
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001396 spin_lock(&echan->vchan.lock);
Peter Ujfalusie4d88172016-02-11 15:17:48 +02001397 edesc = echan->edesc;
1398 if (edesc) {
1399 if (edesc->cyclic) {
1400 vchan_cyclic_callback(&edesc->vdesc);
1401 spin_unlock(&echan->vchan.lock);
1402 return;
1403 } else if (edesc->processed == edesc->pset_nr) {
1404 edesc->residue = 0;
1405 edma_stop(echan);
1406 vchan_cookie_complete(&edesc->vdesc);
1407 echan->edesc = NULL;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001408
Peter Ujfalusie4d88172016-02-11 15:17:48 +02001409 dev_dbg(dev, "Transfer completed on channel %d\n",
1410 echan->ch_num);
1411 } else {
1412 dev_dbg(dev, "Sub transfer completed on channel %d\n",
1413 echan->ch_num);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001414
Peter Ujfalusie4d88172016-02-11 15:17:48 +02001415 edma_pause(echan);
Joel Fernandesc5f47992013-08-29 18:05:43 -05001416
Peter Ujfalusie4d88172016-02-11 15:17:48 +02001417 /* Update statistics for tx_status */
1418 edesc->residue -= edesc->sg_len;
1419 edesc->residue_stat = edesc->residue;
1420 edesc->processed_stat = edesc->processed;
1421 }
1422 edma_execute(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001423 }
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001424
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001425 spin_unlock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001426}
1427
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001428/* eDMA interrupt handler */
1429static irqreturn_t dma_irq_handler(int irq, void *data)
1430{
1431 struct edma_cc *ecc = data;
1432 int ctlr;
1433 u32 sh_ier;
1434 u32 sh_ipr;
1435 u32 bank;
1436
1437 ctlr = ecc->id;
1438 if (ctlr < 0)
1439 return IRQ_NONE;
1440
1441 dev_vdbg(ecc->dev, "dma_irq_handler\n");
1442
1443 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1444 if (!sh_ipr) {
1445 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1446 if (!sh_ipr)
1447 return IRQ_NONE;
1448 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1449 bank = 1;
1450 } else {
1451 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1452 bank = 0;
1453 }
1454
1455 do {
1456 u32 slot;
1457 u32 channel;
1458
1459 slot = __ffs(sh_ipr);
1460 sh_ipr &= ~(BIT(slot));
1461
1462 if (sh_ier & BIT(slot)) {
1463 channel = (bank << 5) | slot;
1464 /* Clear the corresponding IPR bits */
1465 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1466 edma_completion_handler(&ecc->slave_chans[channel]);
1467 }
1468 } while (sh_ipr);
1469
1470 edma_shadow0_write(ecc, SH_IEVAL, 1);
1471 return IRQ_HANDLED;
1472}
1473
1474static void edma_error_handler(struct edma_chan *echan)
1475{
1476 struct edma_cc *ecc = echan->ecc;
1477 struct device *dev = echan->vchan.chan.device->dev;
1478 struct edmacc_param p;
1479
1480 if (!echan->edesc)
1481 return;
1482
1483 spin_lock(&echan->vchan.lock);
1484
1485 edma_read_slot(ecc, echan->slot[0], &p);
1486 /*
1487 * Issue later based on missed flag which will be sure
1488 * to happen as:
1489 * (1) we finished transmitting an intermediate slot and
1490 * edma_execute is coming up.
1491 * (2) or we finished current transfer and issue will
1492 * call edma_execute.
1493 *
1494 * Important note: issuing can be dangerous here and
1495 * lead to some nasty recursion when we are in a NULL
1496 * slot. So we avoid doing so and set the missed flag.
1497 */
1498 if (p.a_b_cnt == 0 && p.ccnt == 0) {
1499 dev_dbg(dev, "Error on null slot, setting miss\n");
1500 echan->missed = 1;
1501 } else {
1502 /*
1503 * The slot is already programmed but the event got
1504 * missed, so its safe to issue it here.
1505 */
1506 dev_dbg(dev, "Missed event, TRIGGERING\n");
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001507 edma_clean_channel(echan);
1508 edma_stop(echan);
1509 edma_start(echan);
1510 edma_trigger_channel(echan);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001511 }
1512 spin_unlock(&echan->vchan.lock);
1513}
1514
Peter Ujfalusi7c3b8b32015-10-14 14:43:02 +03001515static inline bool edma_error_pending(struct edma_cc *ecc)
1516{
1517 if (edma_read_array(ecc, EDMA_EMR, 0) ||
1518 edma_read_array(ecc, EDMA_EMR, 1) ||
1519 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1520 return true;
1521
1522 return false;
1523}
1524
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001525/* eDMA error interrupt handler */
1526static irqreturn_t dma_ccerr_handler(int irq, void *data)
1527{
1528 struct edma_cc *ecc = data;
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001529 int i, j;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001530 int ctlr;
1531 unsigned int cnt = 0;
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001532 unsigned int val;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001533
1534 ctlr = ecc->id;
1535 if (ctlr < 0)
1536 return IRQ_NONE;
1537
1538 dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1539
Peter Ujfalusi3b2bc8a2016-05-10 13:40:54 +03001540 if (!edma_error_pending(ecc)) {
1541 /*
1542 * The registers indicate no pending error event but the irq
1543 * handler has been called.
1544 * Ask eDMA to re-evaluate the error registers.
1545 */
1546 dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
1547 __func__);
1548 edma_write(ecc, EDMA_EEVAL, 1);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001549 return IRQ_NONE;
Peter Ujfalusi3b2bc8a2016-05-10 13:40:54 +03001550 }
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001551
1552 while (1) {
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001553 /* Event missed register(s) */
1554 for (j = 0; j < 2; j++) {
1555 unsigned long emr;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001556
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001557 val = edma_read_array(ecc, EDMA_EMR, j);
1558 if (!val)
1559 continue;
1560
1561 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1562 emr = val;
1563 for (i = find_next_bit(&emr, 32, 0); i < 32;
1564 i = find_next_bit(&emr, 32, i + 1)) {
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001565 int k = (j << 5) + i;
1566
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001567 /* Clear the corresponding EMR bits */
1568 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1569 /* Clear any SER */
1570 edma_shadow0_write_array(ecc, SH_SECR, j,
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001571 BIT(i));
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001572 edma_error_handler(&ecc->slave_chans[k]);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001573 }
1574 }
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001575
1576 val = edma_read(ecc, EDMA_QEMR);
1577 if (val) {
1578 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1579 /* Not reported, just clear the interrupt reason. */
1580 edma_write(ecc, EDMA_QEMCR, val);
1581 edma_shadow0_write(ecc, SH_QSECR, val);
1582 }
1583
1584 val = edma_read(ecc, EDMA_CCERR);
1585 if (val) {
1586 dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1587 /* Not reported, just clear the interrupt reason. */
1588 edma_write(ecc, EDMA_CCERRCLR, val);
1589 }
1590
Peter Ujfalusi7c3b8b32015-10-14 14:43:02 +03001591 if (!edma_error_pending(ecc))
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001592 break;
1593 cnt++;
1594 if (cnt > 10)
1595 break;
1596 }
1597 edma_write(ecc, EDMA_EEVAL, 1);
1598 return IRQ_HANDLED;
1599}
1600
Matt Porterc2dde5f2012-08-22 21:09:34 -04001601/* Alloc channel resources */
1602static int edma_alloc_chan_resources(struct dma_chan *chan)
1603{
1604 struct edma_chan *echan = to_edma_chan(chan);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001605 struct edma_cc *ecc = echan->ecc;
1606 struct device *dev = ecc->dev;
1607 enum dma_event_q eventq_no = EVENTQ_DEFAULT;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001608 int ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001609
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001610 if (echan->tc) {
1611 eventq_no = echan->tc->id;
1612 } else if (ecc->tc_list) {
1613 /* memcpy channel */
1614 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1615 eventq_no = echan->tc->id;
1616 }
1617
1618 ret = edma_alloc_channel(echan, eventq_no);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001619 if (ret)
1620 return ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001621
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001622 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001623 if (echan->slot[0] < 0) {
1624 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1625 EDMA_CHAN_SLOT(echan->ch_num));
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001626 goto err_slot;
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001627 }
1628
1629 /* Set up channel -> slot mapping for the entry slot */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001630 edma_set_chmap(echan, echan->slot[0]);
1631 echan->alloced = true;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001632
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001633 dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1634 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1635 echan->hw_triggered ? "HW" : "SW");
1636
Matt Porterc2dde5f2012-08-22 21:09:34 -04001637 return 0;
1638
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001639err_slot:
1640 edma_free_channel(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001641 return ret;
1642}
1643
1644/* Free channel resources */
1645static void edma_free_chan_resources(struct dma_chan *chan)
1646{
1647 struct edma_chan *echan = to_edma_chan(chan);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001648 struct device *dev = echan->ecc->dev;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001649 int i;
1650
1651 /* Terminate transfers */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001652 edma_stop(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001653
1654 vchan_free_chan_resources(&echan->vchan);
1655
1656 /* Free EDMA PaRAM slots */
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001657 for (i = 0; i < EDMA_MAX_SLOTS; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -04001658 if (echan->slot[i] >= 0) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001659 edma_free_slot(echan->ecc, echan->slot[i]);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001660 echan->slot[i] = -1;
1661 }
1662 }
1663
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001664 /* Set entry slot to the dummy slot */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001665 edma_set_chmap(echan, echan->ecc->dummy_slot);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001666
Matt Porterc2dde5f2012-08-22 21:09:34 -04001667 /* Free EDMA channel */
1668 if (echan->alloced) {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001669 edma_free_channel(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001670 echan->alloced = false;
1671 }
1672
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001673 echan->tc = NULL;
1674 echan->hw_triggered = false;
1675
1676 dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1677 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001678}
1679
1680/* Send pending descriptor to hardware */
1681static void edma_issue_pending(struct dma_chan *chan)
1682{
1683 struct edma_chan *echan = to_edma_chan(chan);
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&echan->vchan.lock, flags);
1687 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1688 edma_execute(echan);
1689 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1690}
1691
John Ogness4ac31d12016-01-28 11:29:08 +01001692/*
1693 * This limit exists to avoid a possible infinite loop when waiting for proof
1694 * that a particular transfer is completed. This limit can be hit if there
1695 * are large bursts to/from slow devices or the CPU is never able to catch
1696 * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1697 * RX-FIFO, as many as 55 loops have been seen.
1698 */
1699#define EDMA_MAX_TR_WAIT_LOOPS 1000
1700
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001701static u32 edma_residue(struct edma_desc *edesc)
1702{
1703 bool dst = edesc->direction == DMA_DEV_TO_MEM;
John Ogness4ac31d12016-01-28 11:29:08 +01001704 int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1705 struct edma_chan *echan = edesc->echan;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001706 struct edma_pset *pset = edesc->pset;
1707 dma_addr_t done, pos;
1708 int i;
1709
1710 /*
1711 * We always read the dst/src position from the first RamPar
1712 * pset. That's the one which is active now.
1713 */
John Ogness4ac31d12016-01-28 11:29:08 +01001714 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1715
1716 /*
1717 * "pos" may represent a transfer request that is still being
1718 * processed by the EDMACC or EDMATC. We will busy wait until
1719 * any one of the situations occurs:
1720 * 1. the DMA hardware is idle
1721 * 2. a new transfer request is setup
1722 * 3. we hit the loop limit
1723 */
1724 while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
1725 /* check if a new transfer request is setup */
1726 if (edma_get_position(echan->ecc,
1727 echan->slot[0], dst) != pos) {
1728 break;
1729 }
1730
1731 if (!--loop_count) {
1732 dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1733 "%s: timeout waiting for PaRAM update\n",
1734 __func__);
1735 break;
1736 }
1737
1738 cpu_relax();
1739 }
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001740
1741 /*
1742 * Cyclic is simple. Just subtract pset[0].addr from pos.
1743 *
1744 * We never update edesc->residue in the cyclic case, so we
1745 * can tell the remaining room to the end of the circular
1746 * buffer.
1747 */
1748 if (edesc->cyclic) {
1749 done = pos - pset->addr;
1750 edesc->residue_stat = edesc->residue - done;
1751 return edesc->residue_stat;
1752 }
1753
1754 /*
1755 * For SG operation we catch up with the last processed
1756 * status.
1757 */
1758 pset += edesc->processed_stat;
1759
1760 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1761 /*
1762 * If we are inside this pset address range, we know
1763 * this is the active one. Get the current delta and
1764 * stop walking the psets.
1765 */
1766 if (pos >= pset->addr && pos < pset->addr + pset->len)
1767 return edesc->residue_stat - (pos - pset->addr);
1768
1769 /* Otherwise mark it done and update residue_stat. */
1770 edesc->processed_stat++;
1771 edesc->residue_stat -= pset->len;
1772 }
1773 return edesc->residue_stat;
1774}
1775
Matt Porterc2dde5f2012-08-22 21:09:34 -04001776/* Check request completion status */
1777static enum dma_status edma_tx_status(struct dma_chan *chan,
1778 dma_cookie_t cookie,
1779 struct dma_tx_state *txstate)
1780{
1781 struct edma_chan *echan = to_edma_chan(chan);
1782 struct virt_dma_desc *vdesc;
1783 enum dma_status ret;
1784 unsigned long flags;
1785
1786 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul9d386ec2013-10-16 13:42:15 +05301787 if (ret == DMA_COMPLETE || !txstate)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001788 return ret;
1789
1790 spin_lock_irqsave(&echan->vchan.lock, flags);
Thomas Gleixnerde135932014-04-28 14:19:51 -05001791 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001792 txstate->residue = edma_residue(echan->edesc);
Thomas Gleixnerde135932014-04-28 14:19:51 -05001793 else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1794 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001795 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1796
1797 return ret;
1798}
1799
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02001800static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001801{
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001802 if (!memcpy_channels)
1803 return false;
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02001804 while (*memcpy_channels != -1) {
1805 if (*memcpy_channels == ch_num)
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001806 return true;
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02001807 memcpy_channels++;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001808 }
1809 return false;
1810}
1811
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001812#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1813 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
Peter Ujfalusie4a899d2014-07-03 07:51:56 +03001814 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001815 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1816
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001817static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001818{
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001819 struct dma_device *s_ddev = &ecc->dma_slave;
1820 struct dma_device *m_ddev = NULL;
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02001821 s32 *memcpy_channels = ecc->info->memcpy_channels;
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001822 int i, j;
Maxime Ripard9f59cd02014-11-17 14:42:47 +01001823
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001824 dma_cap_zero(s_ddev->cap_mask);
1825 dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1826 dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1827 if (ecc->legacy_mode && !memcpy_channels) {
1828 dev_warn(ecc->dev,
1829 "Legacy memcpy is enabled, things might not work\n");
Maxime Ripard9f59cd02014-11-17 14:42:47 +01001830
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001831 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1832 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1833 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1834 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001835
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001836 s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1837 s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1838 s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1839 s_ddev->device_free_chan_resources = edma_free_chan_resources;
1840 s_ddev->device_issue_pending = edma_issue_pending;
1841 s_ddev->device_tx_status = edma_tx_status;
1842 s_ddev->device_config = edma_slave_config;
1843 s_ddev->device_pause = edma_dma_pause;
1844 s_ddev->device_resume = edma_dma_resume;
1845 s_ddev->device_terminate_all = edma_terminate_all;
Peter Ujfalusib84730f2016-02-11 11:08:42 +02001846 s_ddev->device_synchronize = edma_synchronize;
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001847
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001848 s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1849 s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1850 s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1851 s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001852
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001853 s_ddev->dev = ecc->dev;
1854 INIT_LIST_HEAD(&s_ddev->channels);
1855
1856 if (memcpy_channels) {
1857 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1858 ecc->dma_memcpy = m_ddev;
1859
1860 dma_cap_zero(m_ddev->cap_mask);
1861 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1862
1863 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1864 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1865 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1866 m_ddev->device_issue_pending = edma_issue_pending;
1867 m_ddev->device_tx_status = edma_tx_status;
1868 m_ddev->device_config = edma_slave_config;
1869 m_ddev->device_pause = edma_dma_pause;
1870 m_ddev->device_resume = edma_dma_resume;
1871 m_ddev->device_terminate_all = edma_terminate_all;
Peter Ujfalusib84730f2016-02-11 11:08:42 +02001872 m_ddev->device_synchronize = edma_synchronize;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001873
1874 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1875 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1876 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1877 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1878
1879 m_ddev->dev = ecc->dev;
1880 INIT_LIST_HEAD(&m_ddev->channels);
1881 } else if (!ecc->legacy_mode) {
1882 dev_info(ecc->dev, "memcpy is disabled\n");
1883 }
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001884
1885 for (i = 0; i < ecc->num_channels; i++) {
1886 struct edma_chan *echan = &ecc->slave_chans[i];
1887 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1888 echan->ecc = ecc;
1889 echan->vchan.desc_free = edma_desc_free;
1890
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001891 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1892 vchan_init(&echan->vchan, m_ddev);
1893 else
1894 vchan_init(&echan->vchan, s_ddev);
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001895
1896 INIT_LIST_HEAD(&echan->node);
1897 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1898 echan->slot[j] = -1;
1899 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001900}
1901
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001902static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1903 struct edma_cc *ecc)
1904{
1905 int i;
1906 u32 value, cccfg;
1907 s8 (*queue_priority_map)[2];
1908
1909 /* Decode the eDMA3 configuration from CCCFG register */
1910 cccfg = edma_read(ecc, EDMA_CCCFG);
1911
1912 value = GET_NUM_REGN(cccfg);
1913 ecc->num_region = BIT(value);
1914
1915 value = GET_NUM_DMACH(cccfg);
1916 ecc->num_channels = BIT(value + 1);
1917
Peter Ujfalusi633e42b2015-10-16 10:18:04 +03001918 value = GET_NUM_QDMACH(cccfg);
1919 ecc->num_qchannels = value * 2;
1920
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001921 value = GET_NUM_PAENTRY(cccfg);
1922 ecc->num_slots = BIT(value + 4);
1923
1924 value = GET_NUM_EVQUE(cccfg);
1925 ecc->num_tc = value + 1;
1926
Peter Ujfalusi4ab54f62015-10-14 14:43:04 +03001927 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1928
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001929 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1930 dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1931 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
Peter Ujfalusi633e42b2015-10-16 10:18:04 +03001932 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001933 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1934 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
Peter Ujfalusi4ab54f62015-10-14 14:43:04 +03001935 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001936
1937 /* Nothing need to be done if queue priority is provided */
1938 if (pdata->queue_priority_mapping)
1939 return 0;
1940
1941 /*
1942 * Configure TC/queue priority as follows:
1943 * Q0 - priority 0
1944 * Q1 - priority 1
1945 * Q2 - priority 2
1946 * ...
1947 * The meaning of priority numbers: 0 highest priority, 7 lowest
1948 * priority. So Q0 is the highest priority queue and the last queue has
1949 * the lowest priority.
1950 */
Peter Ujfalusi547c6e22015-10-14 14:42:55 +03001951 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001952 GFP_KERNEL);
1953 if (!queue_priority_map)
1954 return -ENOMEM;
1955
1956 for (i = 0; i < ecc->num_tc; i++) {
1957 queue_priority_map[i][0] = i;
1958 queue_priority_map[i][1] = i;
1959 }
1960 queue_priority_map[i][0] = -1;
1961 queue_priority_map[i][1] = -1;
1962
1963 pdata->queue_priority_mapping = queue_priority_map;
1964 /* Default queue has the lowest priority */
1965 pdata->default_queue = i - 1;
1966
1967 return 0;
1968}
1969
1970#if IS_ENABLED(CONFIG_OF)
1971static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1972 size_t sz)
1973{
1974 const char pname[] = "ti,edma-xbar-event-map";
1975 struct resource res;
1976 void __iomem *xbar;
1977 s16 (*xbar_chans)[2];
1978 size_t nelm = sz / sizeof(s16);
1979 u32 shift, offset, mux;
1980 int ret, i;
1981
Peter Ujfalusi547c6e22015-10-14 14:42:55 +03001982 xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001983 if (!xbar_chans)
1984 return -ENOMEM;
1985
1986 ret = of_address_to_resource(dev->of_node, 1, &res);
1987 if (ret)
1988 return -ENOMEM;
1989
1990 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1991 if (!xbar)
1992 return -ENOMEM;
1993
1994 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
1995 nelm);
1996 if (ret)
1997 return -EIO;
1998
1999 /* Invalidate last entry for the other user of this mess */
2000 nelm >>= 1;
2001 xbar_chans[nelm][0] = -1;
2002 xbar_chans[nelm][1] = -1;
2003
2004 for (i = 0; i < nelm; i++) {
2005 shift = (xbar_chans[i][1] & 0x03) << 3;
2006 offset = xbar_chans[i][1] & 0xfffffffc;
2007 mux = readl(xbar + offset);
2008 mux &= ~(0xff << shift);
2009 mux |= xbar_chans[i][0] << shift;
2010 writel(mux, (xbar + offset));
2011 }
2012
2013 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2014 return 0;
2015}
2016
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002017static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2018 bool legacy_mode)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002019{
2020 struct edma_soc_info *info;
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03002021 struct property *prop;
2022 size_t sz;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002023 int ret;
2024
2025 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2026 if (!info)
2027 return ERR_PTR(-ENOMEM);
2028
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002029 if (legacy_mode) {
2030 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
2031 &sz);
2032 if (prop) {
2033 ret = edma_xbar_event_map(dev, info, sz);
2034 if (ret)
2035 return ERR_PTR(ret);
2036 }
2037 return info;
2038 }
2039
2040 /* Get the list of channels allocated to be used for memcpy */
2041 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03002042 if (prop) {
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002043 const char pname[] = "ti,edma-memcpy-channels";
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02002044 size_t nelm = sz / sizeof(s32);
2045 s32 *memcpy_ch;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002046
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02002047 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002048 GFP_KERNEL);
2049 if (!memcpy_ch)
2050 return ERR_PTR(-ENOMEM);
2051
Peter Ujfalusiecb7dec2015-12-09 10:18:10 +02002052 ret = of_property_read_u32_array(dev->of_node, pname,
2053 (u32 *)memcpy_ch, nelm);
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03002054 if (ret)
2055 return ERR_PTR(ret);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002056
2057 memcpy_ch[nelm] = -1;
2058 info->memcpy_channels = memcpy_ch;
2059 }
2060
2061 prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2062 &sz);
2063 if (prop) {
2064 const char pname[] = "ti,edma-reserved-slot-ranges";
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002065 u32 (*tmp)[2];
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002066 s16 (*rsv_slots)[2];
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002067 size_t nelm = sz / sizeof(*tmp);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002068 struct edma_rsv_info *rsv_info;
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002069 int i;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002070
2071 if (!nelm)
2072 return info;
2073
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002074 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2075 if (!tmp)
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002076 return ERR_PTR(-ENOMEM);
2077
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002078 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2079 if (!rsv_info) {
2080 kfree(tmp);
2081 return ERR_PTR(-ENOMEM);
2082 }
2083
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002084 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2085 GFP_KERNEL);
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002086 if (!rsv_slots) {
2087 kfree(tmp);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002088 return ERR_PTR(-ENOMEM);
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002089 }
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002090
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002091 ret = of_property_read_u32_array(dev->of_node, pname,
2092 (u32 *)tmp, nelm * 2);
2093 if (ret) {
2094 kfree(tmp);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002095 return ERR_PTR(ret);
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002096 }
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002097
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002098 for (i = 0; i < nelm; i++) {
2099 rsv_slots[i][0] = tmp[i][0];
2100 rsv_slots[i][1] = tmp[i][1];
2101 }
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002102 rsv_slots[nelm][0] = -1;
2103 rsv_slots[nelm][1] = -1;
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002104
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002105 info->rsv = rsv_info;
2106 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
Peter Ujfalusiae0add72015-12-09 10:18:11 +02002107
2108 kfree(tmp);
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03002109 }
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002110
2111 return info;
2112}
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002113
2114static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2115 struct of_dma *ofdma)
2116{
2117 struct edma_cc *ecc = ofdma->of_dma_data;
2118 struct dma_chan *chan = NULL;
2119 struct edma_chan *echan;
2120 int i;
2121
2122 if (!ecc || dma_spec->args_count < 1)
2123 return NULL;
2124
2125 for (i = 0; i < ecc->num_channels; i++) {
2126 echan = &ecc->slave_chans[i];
2127 if (echan->ch_num == dma_spec->args[0]) {
2128 chan = &echan->vchan.chan;
2129 break;
2130 }
2131 }
2132
2133 if (!chan)
2134 return NULL;
2135
2136 if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2137 goto out;
2138
2139 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2140 dma_spec->args[1] < echan->ecc->num_tc) {
2141 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2142 goto out;
2143 }
2144
2145 return NULL;
2146out:
2147 /* The channel is going to be used as HW synchronized */
2148 echan->hw_triggered = true;
2149 return dma_get_slave_channel(chan);
2150}
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002151#else
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002152static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2153 bool legacy_mode)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002154{
2155 return ERR_PTR(-EINVAL);
2156}
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002157
2158static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2159 struct of_dma *ofdma)
2160{
2161 return NULL;
2162}
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002163#endif
2164
Bill Pemberton463a1f82012-11-19 13:22:55 -05002165static int edma_probe(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04002166{
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002167 struct edma_soc_info *info = pdev->dev.platform_data;
2168 s8 (*queue_priority_mapping)[2];
2169 int i, off, ln;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002170 const s16 (*rsv_slots)[2];
2171 const s16 (*xbar_chans)[2];
2172 int irq;
2173 char *irq_name;
2174 struct resource *mem;
2175 struct device_node *node = pdev->dev.of_node;
2176 struct device *dev = &pdev->dev;
2177 struct edma_cc *ecc;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002178 bool legacy_mode = true;
Matt Porterc2dde5f2012-08-22 21:09:34 -04002179 int ret;
2180
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002181 if (node) {
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002182 const struct of_device_id *match;
2183
2184 match = of_match_node(edma_of_ids, node);
2185 if (match && (u32)match->data == EDMA_BINDING_TPCC)
2186 legacy_mode = false;
2187
2188 info = edma_setup_info_from_dt(dev, legacy_mode);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002189 if (IS_ERR(info)) {
2190 dev_err(dev, "failed to get DT data\n");
2191 return PTR_ERR(info);
2192 }
2193 }
2194
2195 if (!info)
2196 return -ENODEV;
2197
2198 pm_runtime_enable(dev);
2199 ret = pm_runtime_get_sync(dev);
2200 if (ret < 0) {
2201 dev_err(dev, "pm_runtime_get_sync() failed\n");
2202 return ret;
2203 }
2204
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002205 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
Russell King94cb0e72013-06-27 13:45:16 +01002206 if (ret)
2207 return ret;
2208
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002209 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002210 if (!ecc) {
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002211 dev_err(dev, "Can't allocate controller\n");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002212 return -ENOMEM;
2213 }
2214
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002215 ecc->dev = dev;
2216 ecc->id = pdev->id;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002217 ecc->legacy_mode = legacy_mode;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002218 /* When booting with DT the pdev->id is -1 */
2219 if (ecc->id < 0)
2220 ecc->id = 0;
Peter Ujfalusica304fa2015-10-14 14:42:49 +03002221
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002222 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2223 if (!mem) {
2224 dev_dbg(dev, "mem resource not found, using index 0\n");
2225 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2226 if (!mem) {
2227 dev_err(dev, "no mem resource?\n");
2228 return -ENODEV;
2229 }
2230 }
2231 ecc->base = devm_ioremap_resource(dev, mem);
2232 if (IS_ERR(ecc->base))
2233 return PTR_ERR(ecc->base);
Peter Ujfalusib2c843a2015-10-14 14:42:50 +03002234
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002235 platform_set_drvdata(pdev, ecc);
2236
2237 /* Get eDMA3 configuration from IP */
2238 ret = edma_setup_from_hw(dev, info, ecc);
2239 if (ret)
2240 return ret;
2241
Peter Ujfalusicb782052015-10-14 14:42:54 +03002242 /* Allocate memory based on the information we got from the IP */
2243 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2244 sizeof(*ecc->slave_chans), GFP_KERNEL);
2245 if (!ecc->slave_chans)
2246 return -ENOMEM;
2247
Peter Ujfalusi7a73b132015-10-14 14:43:05 +03002248 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
Peter Ujfalusicb782052015-10-14 14:42:54 +03002249 sizeof(unsigned long), GFP_KERNEL);
Peter Ujfalusi7a73b132015-10-14 14:43:05 +03002250 if (!ecc->slot_inuse)
Peter Ujfalusicb782052015-10-14 14:42:54 +03002251 return -ENOMEM;
2252
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002253 ecc->default_queue = info->default_queue;
2254
2255 for (i = 0; i < ecc->num_slots; i++)
2256 edma_write_slot(ecc, i, &dummy_paramset);
2257
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002258 if (info->rsv) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002259 /* Set the reserved slots in inuse list */
2260 rsv_slots = info->rsv->rsv_slots;
2261 if (rsv_slots) {
2262 for (i = 0; rsv_slots[i][0] != -1; i++) {
2263 off = rsv_slots[i][0];
2264 ln = rsv_slots[i][1];
Peter Ujfalusi7a73b132015-10-14 14:43:05 +03002265 set_bits(off, ln, ecc->slot_inuse);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002266 }
2267 }
2268 }
2269
2270 /* Clear the xbar mapped channels in unused list */
2271 xbar_chans = info->xbar_chans;
2272 if (xbar_chans) {
2273 for (i = 0; xbar_chans[i][1] != -1; i++) {
2274 off = xbar_chans[i][1];
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002275 }
2276 }
2277
2278 irq = platform_get_irq_byname(pdev, "edma3_ccint");
2279 if (irq < 0 && node)
2280 irq = irq_of_parse_and_map(node, 0);
2281
2282 if (irq >= 0) {
2283 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2284 dev_name(dev));
2285 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2286 ecc);
2287 if (ret) {
2288 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2289 return ret;
2290 }
2291 }
2292
2293 irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2294 if (irq < 0 && node)
2295 irq = irq_of_parse_and_map(node, 2);
2296
2297 if (irq >= 0) {
2298 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2299 dev_name(dev));
2300 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2301 ecc);
2302 if (ret) {
2303 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2304 return ret;
2305 }
2306 }
2307
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002308 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2309 if (ecc->dummy_slot < 0) {
2310 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2311 return ecc->dummy_slot;
2312 }
2313
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002314 queue_priority_mapping = info->queue_priority_mapping;
2315
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002316 if (!ecc->legacy_mode) {
2317 int lowest_priority = 0;
2318 struct of_phandle_args tc_args;
2319
2320 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2321 sizeof(*ecc->tc_list), GFP_KERNEL);
2322 if (!ecc->tc_list)
2323 return -ENOMEM;
2324
2325 for (i = 0;; i++) {
2326 ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2327 1, i, &tc_args);
2328 if (ret || i == ecc->num_tc)
2329 break;
2330
2331 ecc->tc_list[i].node = tc_args.np;
2332 ecc->tc_list[i].id = i;
2333 queue_priority_mapping[i][1] = tc_args.args[0];
2334 if (queue_priority_mapping[i][1] > lowest_priority) {
2335 lowest_priority = queue_priority_mapping[i][1];
2336 info->default_queue = i;
2337 }
2338 }
2339 }
2340
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002341 /* Event queue priority mapping */
2342 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2343 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2344 queue_priority_mapping[i][1]);
2345
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002346 for (i = 0; i < ecc->num_region; i++) {
2347 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2348 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2349 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2350 }
2351 ecc->info = info;
2352
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03002353 /* Init the dma device and channels */
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002354 edma_dma_init(ecc, legacy_mode);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002355
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002356 for (i = 0; i < ecc->num_channels; i++) {
2357 /* Assign all channels to the default queue */
Peter Ujfalusif9425de2015-10-16 10:18:03 +03002358 edma_assign_channel_eventq(&ecc->slave_chans[i],
2359 info->default_queue);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002360 /* Set entry slot to the dummy slot */
2361 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2362 }
2363
Peter Ujfalusi23e67232015-12-14 22:47:41 +02002364 ecc->dma_slave.filter.map = info->slave_map;
2365 ecc->dma_slave.filter.mapcnt = info->slavecnt;
2366 ecc->dma_slave.filter.fn = edma_filter_fn;
2367
Matt Porterc2dde5f2012-08-22 21:09:34 -04002368 ret = dma_async_device_register(&ecc->dma_slave);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002369 if (ret) {
2370 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002371 goto err_reg1;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002372 }
2373
2374 if (ecc->dma_memcpy) {
2375 ret = dma_async_device_register(ecc->dma_memcpy);
2376 if (ret) {
2377 dev_err(dev, "memcpy ddev registration failed (%d)\n",
2378 ret);
2379 dma_async_device_unregister(&ecc->dma_slave);
2380 goto err_reg1;
2381 }
2382 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04002383
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002384 if (node)
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002385 of_dma_controller_register(node, of_edma_xlate, ecc);
Peter Ujfalusidc9b60552015-10-14 14:42:47 +03002386
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002387 dev_info(dev, "TI EDMA DMA engine driver\n");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002388
2389 return 0;
2390
2391err_reg1:
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002392 edma_free_slot(ecc, ecc->dummy_slot);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002393 return ret;
2394}
2395
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08002396static int edma_remove(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04002397{
2398 struct device *dev = &pdev->dev;
2399 struct edma_cc *ecc = dev_get_drvdata(dev);
2400
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002401 if (dev->of_node)
2402 of_dma_controller_free(dev->of_node);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002403 dma_async_device_unregister(&ecc->dma_slave);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002404 if (ecc->dma_memcpy)
2405 dma_async_device_unregister(ecc->dma_memcpy);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002406 edma_free_slot(ecc, ecc->dummy_slot);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002407
2408 return 0;
2409}
2410
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002411#ifdef CONFIG_PM_SLEEP
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002412static int edma_pm_suspend(struct device *dev)
2413{
2414 struct edma_cc *ecc = dev_get_drvdata(dev);
2415 struct edma_chan *echan = ecc->slave_chans;
2416 int i;
2417
2418 for (i = 0; i < ecc->num_channels; i++) {
Peter Ujfalusi23f49fd2016-04-06 13:01:46 +03002419 if (echan[i].alloced)
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002420 edma_setup_interrupt(&echan[i], false);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002421 }
2422
2423 return 0;
2424}
2425
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002426static int edma_pm_resume(struct device *dev)
2427{
2428 struct edma_cc *ecc = dev_get_drvdata(dev);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002429 struct edma_chan *echan = ecc->slave_chans;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002430 int i;
2431 s8 (*queue_priority_mapping)[2];
2432
2433 queue_priority_mapping = ecc->info->queue_priority_mapping;
2434
2435 /* Event queue priority mapping */
2436 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2437 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2438 queue_priority_mapping[i][1]);
2439
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002440 for (i = 0; i < ecc->num_channels; i++) {
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002441 if (echan[i].alloced) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002442 /* ensure access through shadow region 0 */
2443 edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2444 BIT(i & 0x1f));
2445
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002446 edma_setup_interrupt(&echan[i], true);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002447
2448 /* Set up channel -> slot mapping for the entry slot */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002449 edma_set_chmap(&echan[i], echan[i].slot[0]);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002450 }
2451 }
2452
2453 return 0;
2454}
2455#endif
2456
2457static const struct dev_pm_ops edma_pm_ops = {
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002458 SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002459};
2460
Matt Porterc2dde5f2012-08-22 21:09:34 -04002461static struct platform_driver edma_driver = {
2462 .probe = edma_probe,
Bill Pembertona7d6e3e2012-11-19 13:20:04 -05002463 .remove = edma_remove,
Matt Porterc2dde5f2012-08-22 21:09:34 -04002464 .driver = {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002465 .name = "edma",
2466 .pm = &edma_pm_ops,
2467 .of_match_table = edma_of_ids,
Matt Porterc2dde5f2012-08-22 21:09:34 -04002468 },
2469};
2470
Peter Ujfalusi4fa2d092015-12-16 15:19:05 +02002471static int edma_tptc_probe(struct platform_device *pdev)
2472{
Peter Ujfalusi23f49fd2016-04-06 13:01:46 +03002473 pm_runtime_enable(&pdev->dev);
2474 return pm_runtime_get_sync(&pdev->dev);
Peter Ujfalusi4fa2d092015-12-16 15:19:05 +02002475}
2476
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002477static struct platform_driver edma_tptc_driver = {
Peter Ujfalusi4fa2d092015-12-16 15:19:05 +02002478 .probe = edma_tptc_probe,
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002479 .driver = {
2480 .name = "edma3-tptc",
2481 .of_match_table = edma_tptc_of_ids,
2482 },
2483};
2484
Matt Porterc2dde5f2012-08-22 21:09:34 -04002485bool edma_filter_fn(struct dma_chan *chan, void *param)
2486{
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002487 bool match = false;
2488
Matt Porterc2dde5f2012-08-22 21:09:34 -04002489 if (chan->device->dev->driver == &edma_driver.driver) {
2490 struct edma_chan *echan = to_edma_chan(chan);
2491 unsigned ch_req = *(unsigned *)param;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002492 if (ch_req == echan->ch_num) {
2493 /* The channel is going to be used as HW synchronized */
2494 echan->hw_triggered = true;
2495 match = true;
2496 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04002497 }
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002498 return match;
Matt Porterc2dde5f2012-08-22 21:09:34 -04002499}
2500EXPORT_SYMBOL(edma_filter_fn);
2501
Matt Porterc2dde5f2012-08-22 21:09:34 -04002502static int edma_init(void)
2503{
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002504 int ret;
2505
2506 ret = platform_driver_register(&edma_tptc_driver);
2507 if (ret)
2508 return ret;
2509
Arnd Bergmann5305e4d2014-10-24 18:14:01 +02002510 return platform_driver_register(&edma_driver);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002511}
2512subsys_initcall(edma_init);
2513
2514static void __exit edma_exit(void)
2515{
Matt Porterc2dde5f2012-08-22 21:09:34 -04002516 platform_driver_unregister(&edma_driver);
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002517 platform_driver_unregister(&edma_tptc_driver);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002518}
2519module_exit(edma_exit);
2520
Josh Boyerd71505b2013-09-04 10:32:50 -04002521MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002522MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2523MODULE_LICENSE("GPL v2");