Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /*------------------------------------------------------------------------ |
| 2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. |
| 3 | . |
| 4 | . Copyright (C) 1996 by Erik Stahlman |
| 5 | . Copyright (C) 2001 Standard Microsystems Corporation |
| 6 | . Developed by Simple Network Magic Corporation |
| 7 | . Copyright (C) 2003 Monta Vista Software, Inc. |
| 8 | . Unified SMC91x driver by Nicolas Pitre |
| 9 | . |
| 10 | . This program is free software; you can redistribute it and/or modify |
| 11 | . it under the terms of the GNU General Public License as published by |
| 12 | . the Free Software Foundation; either version 2 of the License, or |
| 13 | . (at your option) any later version. |
| 14 | . |
| 15 | . This program is distributed in the hope that it will be useful, |
| 16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | . GNU General Public License for more details. |
| 19 | . |
| 20 | . You should have received a copy of the GNU General Public License |
| 21 | . along with this program; if not, write to the Free Software |
| 22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 23 | . |
| 24 | . Information contained in this file was obtained from the LAN91C111 |
| 25 | . manual from SMC. To get a copy, if you really want one, you can find |
| 26 | . information under www.smsc.com. |
| 27 | . |
| 28 | . Authors |
| 29 | . Erik Stahlman <erik@vt.edu> |
| 30 | . Daris A Nevil <dnevil@snmc.com> |
| 31 | . Nicolas Pitre <nico@cam.org> |
| 32 | . |
| 33 | ---------------------------------------------------------------------------*/ |
| 34 | #ifndef _SMC91X_H_ |
| 35 | #define _SMC91X_H_ |
| 36 | |
| 37 | |
| 38 | /* |
| 39 | * Define your architecture specific bus configuration parameters here. |
| 40 | */ |
| 41 | |
| 42 | #if defined(CONFIG_ARCH_LUBBOCK) |
| 43 | |
| 44 | /* We can only do 16-bit reads and writes in the static memory space. */ |
| 45 | #define SMC_CAN_USE_8BIT 0 |
| 46 | #define SMC_CAN_USE_16BIT 1 |
| 47 | #define SMC_CAN_USE_32BIT 0 |
| 48 | #define SMC_NOWAIT 1 |
| 49 | |
| 50 | /* The first two address lines aren't connected... */ |
| 51 | #define SMC_IO_SHIFT 2 |
| 52 | |
| 53 | #define SMC_inw(a, r) readw((a) + (r)) |
| 54 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
| 55 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
| 56 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) |
| 57 | |
| 58 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) |
| 59 | |
| 60 | /* We can only do 16-bit reads and writes in the static memory space. */ |
| 61 | #define SMC_CAN_USE_8BIT 0 |
| 62 | #define SMC_CAN_USE_16BIT 1 |
| 63 | #define SMC_CAN_USE_32BIT 0 |
| 64 | #define SMC_NOWAIT 1 |
| 65 | |
| 66 | #define SMC_IO_SHIFT 0 |
| 67 | |
| 68 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) |
| 69 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) |
| 70 | #define SMC_insw(a, r, p, l) \ |
| 71 | do { \ |
| 72 | unsigned long __port = (a) + (r); \ |
| 73 | u16 *__p = (u16 *)(p); \ |
| 74 | int __l = (l); \ |
| 75 | insw(__port, __p, __l); \ |
| 76 | while (__l > 0) { \ |
| 77 | *__p = swab16(*__p); \ |
| 78 | __p++; \ |
| 79 | __l--; \ |
| 80 | } \ |
| 81 | } while (0) |
| 82 | #define SMC_outsw(a, r, p, l) \ |
| 83 | do { \ |
| 84 | unsigned long __port = (a) + (r); \ |
| 85 | u16 *__p = (u16 *)(p); \ |
| 86 | int __l = (l); \ |
| 87 | while (__l > 0) { \ |
| 88 | /* Believe it or not, the swab isn't needed. */ \ |
| 89 | outw( /* swab16 */ (*__p++), __port); \ |
| 90 | __l--; \ |
| 91 | } \ |
| 92 | } while (0) |
| 93 | #define set_irq_type(irq, type) |
| 94 | |
| 95 | #elif defined(CONFIG_SA1100_PLEB) |
| 96 | /* We can only do 16-bit reads and writes in the static memory space. */ |
| 97 | #define SMC_CAN_USE_8BIT 1 |
| 98 | #define SMC_CAN_USE_16BIT 1 |
| 99 | #define SMC_CAN_USE_32BIT 0 |
| 100 | #define SMC_IO_SHIFT 0 |
| 101 | #define SMC_NOWAIT 1 |
| 102 | |
| 103 | #define SMC_inb(a, r) inb((a) + (r)) |
| 104 | #define SMC_insb(a, r, p, l) insb((a) + (r), p, (l)) |
| 105 | #define SMC_inw(a, r) inw((a) + (r)) |
| 106 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) |
| 107 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) |
| 108 | #define SMC_outsb(a, r, p, l) outsb((a) + (r), p, (l)) |
| 109 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) |
| 110 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) |
| 111 | |
| 112 | #define set_irq_type(irq, type) do {} while (0) |
| 113 | |
| 114 | #elif defined(CONFIG_SA1100_ASSABET) |
| 115 | |
| 116 | #include <asm/arch/neponset.h> |
| 117 | |
| 118 | /* We can only do 8-bit reads and writes in the static memory space. */ |
| 119 | #define SMC_CAN_USE_8BIT 1 |
| 120 | #define SMC_CAN_USE_16BIT 0 |
| 121 | #define SMC_CAN_USE_32BIT 0 |
| 122 | #define SMC_NOWAIT 1 |
| 123 | |
| 124 | /* The first two address lines aren't connected... */ |
| 125 | #define SMC_IO_SHIFT 2 |
| 126 | |
| 127 | #define SMC_inb(a, r) readb((a) + (r)) |
| 128 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) |
| 129 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) |
| 130 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) |
| 131 | |
| 132 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
| 133 | defined(CONFIG_MACH_MAINSTONE) || \ |
| 134 | defined(CONFIG_ARCH_PXA_IDP) || \ |
| 135 | defined(CONFIG_ARCH_RAMSES) |
| 136 | |
| 137 | #define SMC_CAN_USE_8BIT 1 |
| 138 | #define SMC_CAN_USE_16BIT 1 |
| 139 | #define SMC_CAN_USE_32BIT 1 |
| 140 | #define SMC_IO_SHIFT 0 |
| 141 | #define SMC_NOWAIT 1 |
| 142 | #define SMC_USE_PXA_DMA 1 |
| 143 | |
| 144 | #define SMC_inb(a, r) readb((a) + (r)) |
| 145 | #define SMC_inw(a, r) readw((a) + (r)) |
| 146 | #define SMC_inl(a, r) readl((a) + (r)) |
| 147 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) |
| 148 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) |
| 149 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
| 150 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) |
| 151 | |
| 152 | /* We actually can't write halfwords properly if not word aligned */ |
| 153 | static inline void |
Nicolas Pitre | eb1d698 | 2005-05-12 20:19:09 -0400 | [diff] [blame] | 154 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | { |
| 156 | if (reg & 2) { |
| 157 | unsigned int v = val << 16; |
| 158 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; |
| 159 | writel(v, ioaddr + (reg & ~2)); |
| 160 | } else { |
| 161 | writew(val, ioaddr + reg); |
| 162 | } |
| 163 | } |
| 164 | |
| 165 | #elif defined(CONFIG_ARCH_OMAP) |
| 166 | |
| 167 | /* We can only do 16-bit reads and writes in the static memory space. */ |
| 168 | #define SMC_CAN_USE_8BIT 0 |
| 169 | #define SMC_CAN_USE_16BIT 1 |
| 170 | #define SMC_CAN_USE_32BIT 0 |
| 171 | #define SMC_IO_SHIFT 0 |
| 172 | #define SMC_NOWAIT 1 |
| 173 | |
| 174 | #define SMC_inb(a, r) readb((a) + (r)) |
| 175 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) |
| 176 | #define SMC_inw(a, r) readw((a) + (r)) |
| 177 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
| 178 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
| 179 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) |
| 180 | #define SMC_inl(a, r) readl((a) + (r)) |
| 181 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) |
| 182 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
| 183 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) |
| 184 | |
David Brownell | 5f13e7e | 2005-05-16 08:53:52 -0700 | [diff] [blame] | 185 | #include <asm/mach-types.h> |
| 186 | #include <asm/arch/cpu.h> |
| 187 | |
| 188 | #define SMC_IRQ_TRIGGER_TYPE (( \ |
| 189 | machine_is_omap_h2() \ |
| 190 | || machine_is_omap_h3() \ |
Tony Lindgren | af44f5b | 2005-06-30 06:40:18 -0700 | [diff] [blame^] | 191 | || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ |
David Brownell | 5f13e7e | 2005-05-16 08:53:52 -0700 | [diff] [blame] | 192 | ) ? IRQT_FALLING : IRQT_RISING) |
| 193 | |
| 194 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
| 196 | |
| 197 | #define SMC_CAN_USE_8BIT 0 |
| 198 | #define SMC_CAN_USE_16BIT 1 |
| 199 | #define SMC_CAN_USE_32BIT 0 |
| 200 | |
| 201 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) |
| 202 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) |
| 203 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) |
| 204 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) |
| 205 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) |
| 206 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) |
| 207 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) |
| 208 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) |
| 209 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) |
| 210 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) |
| 211 | |
| 212 | #define set_irq_type(irq, type) do {} while(0) |
| 213 | |
| 214 | #elif defined(CONFIG_ISA) |
| 215 | |
| 216 | #define SMC_CAN_USE_8BIT 1 |
| 217 | #define SMC_CAN_USE_16BIT 1 |
| 218 | #define SMC_CAN_USE_32BIT 0 |
| 219 | |
| 220 | #define SMC_inb(a, r) inb((a) + (r)) |
| 221 | #define SMC_inw(a, r) inw((a) + (r)) |
| 222 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) |
| 223 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) |
| 224 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) |
| 225 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) |
| 226 | |
| 227 | #elif defined(CONFIG_M32R) |
| 228 | |
| 229 | #define SMC_CAN_USE_8BIT 0 |
| 230 | #define SMC_CAN_USE_16BIT 1 |
| 231 | #define SMC_CAN_USE_32BIT 0 |
| 232 | |
| 233 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) |
| 234 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) |
| 235 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) |
| 236 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) |
| 237 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) |
| 238 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) |
| 239 | |
| 240 | #define set_irq_type(irq, type) do {} while(0) |
| 241 | |
| 242 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX |
| 243 | #define RPC_LSB_DEFAULT RPC_LED_100_10 |
| 244 | |
| 245 | #elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404) |
| 246 | |
| 247 | /* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between |
| 248 | * the way that the CPU handles chip selects and the way that the SMC |
| 249 | * chip expects the chip select to operate. Refer to |
| 250 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
| 251 | * IOBARRIER is a byte as a least-common denominator of possible |
| 252 | * regions to use as the barrier. It would be wasteful to read 32 |
| 253 | * bits from a byte oriented region. |
| 254 | * |
| 255 | * There is no explicit protection against interrupts intervening |
| 256 | * between the writew and the IOBARRIER. In SMC ISR there is a |
| 257 | * preamble that performs an IOBARRIER in the extremely unlikely event |
| 258 | * that the driver interrupts itself between a writew to the chip an |
| 259 | * the IOBARRIER that follows *and* the cache is large enough that the |
| 260 | * first off-chip access while handing the interrupt is to the SMC |
| 261 | * chip. Other devices in the same address space as the SMC chip must |
| 262 | * be aware of the potential for trouble and perform a similar |
| 263 | * IOBARRIER on entry to their ISR. |
| 264 | */ |
| 265 | |
| 266 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ |
| 267 | |
| 268 | #define SMC_CAN_USE_8BIT 0 |
| 269 | #define SMC_CAN_USE_16BIT 1 |
| 270 | #define SMC_CAN_USE_32BIT 0 |
| 271 | #define SMC_NOWAIT 0 |
| 272 | #define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT) |
| 273 | |
| 274 | #define SMC_inw(a,r) readw ((void*) ((a) + (r))) |
| 275 | #define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l) |
| 276 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; }) |
| 277 | |
| 278 | static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l) |
| 279 | { |
| 280 | unsigned short* ps = (unsigned short*) p; |
| 281 | while (l-- > 0) { |
| 282 | writew (*ps++, a + r); |
| 283 | LPD7A40X_IOBARRIER; |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | #define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER |
| 288 | |
| 289 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX |
| 290 | #define RPC_LSB_DEFAULT RPC_LED_100_10 |
| 291 | |
| 292 | #else |
| 293 | |
| 294 | #define SMC_CAN_USE_8BIT 1 |
| 295 | #define SMC_CAN_USE_16BIT 1 |
| 296 | #define SMC_CAN_USE_32BIT 1 |
| 297 | #define SMC_NOWAIT 1 |
| 298 | |
| 299 | #define SMC_inb(a, r) readb((a) + (r)) |
| 300 | #define SMC_inw(a, r) readw((a) + (r)) |
| 301 | #define SMC_inl(a, r) readl((a) + (r)) |
| 302 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) |
| 303 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
| 304 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) |
| 305 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
| 306 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) |
| 307 | |
| 308 | #define RPC_LSA_DEFAULT RPC_LED_100_10 |
| 309 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX |
| 310 | |
| 311 | #endif |
| 312 | |
David Brownell | 5f13e7e | 2005-05-16 08:53:52 -0700 | [diff] [blame] | 313 | #ifndef SMC_IRQ_TRIGGER_TYPE |
| 314 | #define SMC_IRQ_TRIGGER_TYPE IRQT_RISING |
| 315 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | |
| 317 | #ifdef SMC_USE_PXA_DMA |
| 318 | /* |
| 319 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is |
| 320 | * always happening in irq context so no need to worry about races. TX is |
| 321 | * different and probably not worth it for that reason, and not as critical |
| 322 | * as RX which can overrun memory and lose packets. |
| 323 | */ |
| 324 | #include <linux/dma-mapping.h> |
| 325 | #include <asm/dma.h> |
| 326 | #include <asm/arch/pxa-regs.h> |
| 327 | |
| 328 | #ifdef SMC_insl |
| 329 | #undef SMC_insl |
| 330 | #define SMC_insl(a, r, p, l) \ |
| 331 | smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) |
| 332 | static inline void |
Nicolas Pitre | eb1d698 | 2005-05-12 20:19:09 -0400 | [diff] [blame] | 333 | smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | u_char *buf, int len) |
| 335 | { |
| 336 | dma_addr_t dmabuf; |
| 337 | |
| 338 | /* fallback if no DMA available */ |
| 339 | if (dma == (unsigned char)-1) { |
| 340 | readsl(ioaddr + reg, buf, len); |
| 341 | return; |
| 342 | } |
| 343 | |
| 344 | /* 64 bit alignment is required for memory to memory DMA */ |
| 345 | if ((long)buf & 4) { |
| 346 | *((u32 *)buf) = SMC_inl(ioaddr, reg); |
| 347 | buf += 4; |
| 348 | len--; |
| 349 | } |
| 350 | |
| 351 | len *= 4; |
| 352 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); |
| 353 | DCSR(dma) = DCSR_NODESC; |
| 354 | DTADR(dma) = dmabuf; |
| 355 | DSADR(dma) = physaddr + reg; |
| 356 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | |
| 357 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); |
| 358 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; |
| 359 | while (!(DCSR(dma) & DCSR_STOPSTATE)) |
| 360 | cpu_relax(); |
| 361 | DCSR(dma) = 0; |
| 362 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); |
| 363 | } |
| 364 | #endif |
| 365 | |
| 366 | #ifdef SMC_insw |
| 367 | #undef SMC_insw |
| 368 | #define SMC_insw(a, r, p, l) \ |
| 369 | smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) |
| 370 | static inline void |
Nicolas Pitre | eb1d698 | 2005-05-12 20:19:09 -0400 | [diff] [blame] | 371 | smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | u_char *buf, int len) |
| 373 | { |
| 374 | dma_addr_t dmabuf; |
| 375 | |
| 376 | /* fallback if no DMA available */ |
| 377 | if (dma == (unsigned char)-1) { |
| 378 | readsw(ioaddr + reg, buf, len); |
| 379 | return; |
| 380 | } |
| 381 | |
| 382 | /* 64 bit alignment is required for memory to memory DMA */ |
| 383 | while ((long)buf & 6) { |
| 384 | *((u16 *)buf) = SMC_inw(ioaddr, reg); |
| 385 | buf += 2; |
| 386 | len--; |
| 387 | } |
| 388 | |
| 389 | len *= 2; |
| 390 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); |
| 391 | DCSR(dma) = DCSR_NODESC; |
| 392 | DTADR(dma) = dmabuf; |
| 393 | DSADR(dma) = physaddr + reg; |
| 394 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | |
| 395 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); |
| 396 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; |
| 397 | while (!(DCSR(dma) & DCSR_STOPSTATE)) |
| 398 | cpu_relax(); |
| 399 | DCSR(dma) = 0; |
| 400 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); |
| 401 | } |
| 402 | #endif |
| 403 | |
| 404 | static void |
| 405 | smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) |
| 406 | { |
| 407 | DCSR(dma) = 0; |
| 408 | } |
| 409 | #endif /* SMC_USE_PXA_DMA */ |
| 410 | |
| 411 | |
| 412 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ |
| 413 | #ifndef SMC_IO_SHIFT |
| 414 | #define SMC_IO_SHIFT 0 |
| 415 | #endif |
| 416 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
| 417 | #define SMC_DATA_EXTENT (4) |
| 418 | |
| 419 | /* |
| 420 | . Bank Select Register: |
| 421 | . |
| 422 | . yyyy yyyy 0000 00xx |
| 423 | . xx = bank number |
| 424 | . yyyy yyyy = 0x33, for identification purposes. |
| 425 | */ |
| 426 | #define BANK_SELECT (14 << SMC_IO_SHIFT) |
| 427 | |
| 428 | |
| 429 | // Transmit Control Register |
| 430 | /* BANK 0 */ |
| 431 | #define TCR_REG SMC_REG(0x0000, 0) |
| 432 | #define TCR_ENABLE 0x0001 // When 1 we can transmit |
| 433 | #define TCR_LOOP 0x0002 // Controls output pin LBK |
| 434 | #define TCR_FORCOL 0x0004 // When 1 will force a collision |
| 435 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 |
| 436 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames |
| 437 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier |
| 438 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation |
| 439 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error |
| 440 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback |
| 441 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode |
| 442 | |
| 443 | #define TCR_CLEAR 0 /* do NOTHING */ |
| 444 | /* the default settings for the TCR register : */ |
| 445 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) |
| 446 | |
| 447 | |
| 448 | // EPH Status Register |
| 449 | /* BANK 0 */ |
| 450 | #define EPH_STATUS_REG SMC_REG(0x0002, 0) |
| 451 | #define ES_TX_SUC 0x0001 // Last TX was successful |
| 452 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx |
| 453 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx |
| 454 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast |
| 455 | #define ES_16COL 0x0010 // 16 Collisions Reached |
| 456 | #define ES_SQET 0x0020 // Signal Quality Error Test |
| 457 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast |
| 458 | #define ES_TXDEFR 0x0080 // Transmit Deferred |
| 459 | #define ES_LATCOL 0x0200 // Late collision detected on last tx |
| 460 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense |
| 461 | #define ES_EXC_DEF 0x0800 // Excessive Deferral |
| 462 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication |
| 463 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin |
| 464 | #define ES_TXUNRN 0x8000 // Tx Underrun |
| 465 | |
| 466 | |
| 467 | // Receive Control Register |
| 468 | /* BANK 0 */ |
| 469 | #define RCR_REG SMC_REG(0x0004, 0) |
| 470 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted |
| 471 | #define RCR_PRMS 0x0002 // Enable promiscuous mode |
| 472 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames |
| 473 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets |
| 474 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets |
| 475 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision |
| 476 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier |
| 477 | #define RCR_SOFTRST 0x8000 // resets the chip |
| 478 | |
| 479 | /* the normal settings for the RCR register : */ |
| 480 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) |
| 481 | #define RCR_CLEAR 0x0 // set it to a base state |
| 482 | |
| 483 | |
| 484 | // Counter Register |
| 485 | /* BANK 0 */ |
| 486 | #define COUNTER_REG SMC_REG(0x0006, 0) |
| 487 | |
| 488 | |
| 489 | // Memory Information Register |
| 490 | /* BANK 0 */ |
| 491 | #define MIR_REG SMC_REG(0x0008, 0) |
| 492 | |
| 493 | |
| 494 | // Receive/Phy Control Register |
| 495 | /* BANK 0 */ |
| 496 | #define RPC_REG SMC_REG(0x000A, 0) |
| 497 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. |
| 498 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode |
| 499 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode |
| 500 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb |
| 501 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb |
| 502 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect |
| 503 | #define RPC_LED_RES (0x01) // LED = Reserved |
| 504 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect |
| 505 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode |
| 506 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred |
| 507 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect |
| 508 | #define RPC_LED_TX (0x06) // LED = TX packet occurred |
| 509 | #define RPC_LED_RX (0x07) // LED = RX packet occurred |
| 510 | |
| 511 | #ifndef RPC_LSA_DEFAULT |
| 512 | #define RPC_LSA_DEFAULT RPC_LED_100 |
| 513 | #endif |
| 514 | #ifndef RPC_LSB_DEFAULT |
| 515 | #define RPC_LSB_DEFAULT RPC_LED_FD |
| 516 | #endif |
| 517 | |
| 518 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| 519 | |
| 520 | |
| 521 | /* Bank 0 0x0C is reserved */ |
| 522 | |
| 523 | // Bank Select Register |
| 524 | /* All Banks */ |
| 525 | #define BSR_REG 0x000E |
| 526 | |
| 527 | |
| 528 | // Configuration Reg |
| 529 | /* BANK 1 */ |
| 530 | #define CONFIG_REG SMC_REG(0x0000, 1) |
| 531 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy |
| 532 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL |
| 533 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus |
| 534 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. |
| 535 | |
| 536 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low |
| 537 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) |
| 538 | |
| 539 | |
| 540 | // Base Address Register |
| 541 | /* BANK 1 */ |
| 542 | #define BASE_REG SMC_REG(0x0002, 1) |
| 543 | |
| 544 | |
| 545 | // Individual Address Registers |
| 546 | /* BANK 1 */ |
| 547 | #define ADDR0_REG SMC_REG(0x0004, 1) |
| 548 | #define ADDR1_REG SMC_REG(0x0006, 1) |
| 549 | #define ADDR2_REG SMC_REG(0x0008, 1) |
| 550 | |
| 551 | |
| 552 | // General Purpose Register |
| 553 | /* BANK 1 */ |
| 554 | #define GP_REG SMC_REG(0x000A, 1) |
| 555 | |
| 556 | |
| 557 | // Control Register |
| 558 | /* BANK 1 */ |
| 559 | #define CTL_REG SMC_REG(0x000C, 1) |
| 560 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received |
| 561 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically |
| 562 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt |
| 563 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt |
| 564 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt |
| 565 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store |
| 566 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers |
| 567 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM |
| 568 | |
| 569 | |
| 570 | // MMU Command Register |
| 571 | /* BANK 2 */ |
| 572 | #define MMU_CMD_REG SMC_REG(0x0000, 2) |
| 573 | #define MC_BUSY 1 // When 1 the last release has not completed |
| 574 | #define MC_NOP (0<<5) // No Op |
| 575 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets |
| 576 | #define MC_RESET (2<<5) // Reset MMU to initial state |
| 577 | #define MC_REMOVE (3<<5) // Remove the current rx packet |
| 578 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet |
| 579 | #define MC_FREEPKT (5<<5) // Release packet in PNR register |
| 580 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit |
| 581 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs |
| 582 | |
| 583 | |
| 584 | // Packet Number Register |
| 585 | /* BANK 2 */ |
| 586 | #define PN_REG SMC_REG(0x0002, 2) |
| 587 | |
| 588 | |
| 589 | // Allocation Result Register |
| 590 | /* BANK 2 */ |
| 591 | #define AR_REG SMC_REG(0x0003, 2) |
| 592 | #define AR_FAILED 0x80 // Alocation Failed |
| 593 | |
| 594 | |
| 595 | // TX FIFO Ports Register |
| 596 | /* BANK 2 */ |
| 597 | #define TXFIFO_REG SMC_REG(0x0004, 2) |
| 598 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty |
| 599 | |
| 600 | // RX FIFO Ports Register |
| 601 | /* BANK 2 */ |
| 602 | #define RXFIFO_REG SMC_REG(0x0005, 2) |
| 603 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty |
| 604 | |
| 605 | #define FIFO_REG SMC_REG(0x0004, 2) |
| 606 | |
| 607 | // Pointer Register |
| 608 | /* BANK 2 */ |
| 609 | #define PTR_REG SMC_REG(0x0006, 2) |
| 610 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area |
| 611 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access |
| 612 | #define PTR_READ 0x2000 // When 1 the operation is a read |
| 613 | |
| 614 | |
| 615 | // Data Register |
| 616 | /* BANK 2 */ |
| 617 | #define DATA_REG SMC_REG(0x0008, 2) |
| 618 | |
| 619 | |
| 620 | // Interrupt Status/Acknowledge Register |
| 621 | /* BANK 2 */ |
| 622 | #define INT_REG SMC_REG(0x000C, 2) |
| 623 | |
| 624 | |
| 625 | // Interrupt Mask Register |
| 626 | /* BANK 2 */ |
| 627 | #define IM_REG SMC_REG(0x000D, 2) |
| 628 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt |
| 629 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt |
| 630 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section |
| 631 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns |
| 632 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed |
| 633 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty |
| 634 | #define IM_TX_INT 0x02 // Transmit Interrupt |
| 635 | #define IM_RCV_INT 0x01 // Receive Interrupt |
| 636 | |
| 637 | |
| 638 | // Multicast Table Registers |
| 639 | /* BANK 3 */ |
| 640 | #define MCAST_REG1 SMC_REG(0x0000, 3) |
| 641 | #define MCAST_REG2 SMC_REG(0x0002, 3) |
| 642 | #define MCAST_REG3 SMC_REG(0x0004, 3) |
| 643 | #define MCAST_REG4 SMC_REG(0x0006, 3) |
| 644 | |
| 645 | |
| 646 | // Management Interface Register (MII) |
| 647 | /* BANK 3 */ |
| 648 | #define MII_REG SMC_REG(0x0008, 3) |
| 649 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup |
| 650 | #define MII_MDOE 0x0008 // MII Output Enable |
| 651 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK |
| 652 | #define MII_MDI 0x0002 // MII Input, pin MDI |
| 653 | #define MII_MDO 0x0001 // MII Output, pin MDO |
| 654 | |
| 655 | |
| 656 | // Revision Register |
| 657 | /* BANK 3 */ |
| 658 | /* ( hi: chip id low: rev # ) */ |
| 659 | #define REV_REG SMC_REG(0x000A, 3) |
| 660 | |
| 661 | |
| 662 | // Early RCV Register |
| 663 | /* BANK 3 */ |
| 664 | /* this is NOT on SMC9192 */ |
| 665 | #define ERCV_REG SMC_REG(0x000C, 3) |
| 666 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received |
| 667 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask |
| 668 | |
| 669 | |
| 670 | // External Register |
| 671 | /* BANK 7 */ |
| 672 | #define EXT_REG SMC_REG(0x0000, 7) |
| 673 | |
| 674 | |
| 675 | #define CHIP_9192 3 |
| 676 | #define CHIP_9194 4 |
| 677 | #define CHIP_9195 5 |
| 678 | #define CHIP_9196 6 |
| 679 | #define CHIP_91100 7 |
| 680 | #define CHIP_91100FD 8 |
| 681 | #define CHIP_91111FD 9 |
| 682 | |
| 683 | static const char * chip_ids[ 16 ] = { |
| 684 | NULL, NULL, NULL, |
| 685 | /* 3 */ "SMC91C90/91C92", |
| 686 | /* 4 */ "SMC91C94", |
| 687 | /* 5 */ "SMC91C95", |
| 688 | /* 6 */ "SMC91C96", |
| 689 | /* 7 */ "SMC91C100", |
| 690 | /* 8 */ "SMC91C100FD", |
| 691 | /* 9 */ "SMC91C11xFD", |
| 692 | NULL, NULL, NULL, |
| 693 | NULL, NULL, NULL}; |
| 694 | |
| 695 | |
| 696 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | . Receive status bits |
| 698 | */ |
| 699 | #define RS_ALGNERR 0x8000 |
| 700 | #define RS_BRODCAST 0x4000 |
| 701 | #define RS_BADCRC 0x2000 |
| 702 | #define RS_ODDFRAME 0x1000 |
| 703 | #define RS_TOOLONG 0x0800 |
| 704 | #define RS_TOOSHORT 0x0400 |
| 705 | #define RS_MULTICAST 0x0001 |
| 706 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
| 707 | |
| 708 | |
| 709 | /* |
| 710 | * PHY IDs |
| 711 | * LAN83C183 == LAN91C111 Internal PHY |
| 712 | */ |
| 713 | #define PHY_LAN83C183 0x0016f840 |
| 714 | #define PHY_LAN83C180 0x02821c50 |
| 715 | |
| 716 | /* |
| 717 | * PHY Register Addresses (LAN91C111 Internal PHY) |
| 718 | * |
| 719 | * Generic PHY registers can be found in <linux/mii.h> |
| 720 | * |
| 721 | * These phy registers are specific to our on-board phy. |
| 722 | */ |
| 723 | |
| 724 | // PHY Configuration Register 1 |
| 725 | #define PHY_CFG1_REG 0x10 |
| 726 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled |
| 727 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled |
| 728 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down |
| 729 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler |
| 730 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable |
| 731 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled |
| 732 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) |
| 733 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db |
| 734 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust |
| 735 | #define PHY_CFG1_TLVL_MASK 0x003C |
| 736 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time |
| 737 | |
| 738 | |
| 739 | // PHY Configuration Register 2 |
| 740 | #define PHY_CFG2_REG 0x11 |
| 741 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled |
| 742 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled |
| 743 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) |
| 744 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo |
| 745 | |
| 746 | // PHY Status Output (and Interrupt status) Register |
| 747 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) |
| 748 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read |
| 749 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected |
| 750 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync |
| 751 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx |
| 752 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx |
| 753 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx |
| 754 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected |
| 755 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected |
| 756 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode |
| 757 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex |
| 758 | |
| 759 | // PHY Interrupt/Status Mask Register |
| 760 | #define PHY_MASK_REG 0x13 // Interrupt Mask |
| 761 | // Uses the same bit definitions as PHY_INT_REG |
| 762 | |
| 763 | |
| 764 | /* |
| 765 | * SMC91C96 ethernet config and status registers. |
| 766 | * These are in the "attribute" space. |
| 767 | */ |
| 768 | #define ECOR 0x8000 |
| 769 | #define ECOR_RESET 0x80 |
| 770 | #define ECOR_LEVEL_IRQ 0x40 |
| 771 | #define ECOR_WR_ATTRIB 0x04 |
| 772 | #define ECOR_ENABLE 0x01 |
| 773 | |
| 774 | #define ECSR 0x8002 |
| 775 | #define ECSR_IOIS8 0x20 |
| 776 | #define ECSR_PWRDWN 0x04 |
| 777 | #define ECSR_INT 0x02 |
| 778 | |
| 779 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) |
| 780 | |
| 781 | |
| 782 | /* |
| 783 | * Macros to abstract register access according to the data bus |
| 784 | * capabilities. Please use those and not the in/out primitives. |
| 785 | * Note: the following macros do *not* select the bank -- this must |
| 786 | * be done separately as needed in the main code. The SMC_REG() macro |
| 787 | * only uses the bank argument for debugging purposes (when enabled). |
| 788 | */ |
| 789 | |
| 790 | #if SMC_DEBUG > 0 |
| 791 | #define SMC_REG(reg, bank) \ |
| 792 | ({ \ |
| 793 | int __b = SMC_CURRENT_BANK(); \ |
| 794 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ |
| 795 | printk( "%s: bank reg screwed (0x%04x)\n", \ |
| 796 | CARDNAME, __b ); \ |
| 797 | BUG(); \ |
| 798 | } \ |
| 799 | reg<<SMC_IO_SHIFT; \ |
| 800 | }) |
| 801 | #else |
| 802 | #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) |
| 803 | #endif |
| 804 | |
| 805 | #if SMC_CAN_USE_8BIT |
| 806 | #define SMC_GET_PN() SMC_inb( ioaddr, PN_REG ) |
| 807 | #define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG ) |
| 808 | #define SMC_GET_AR() SMC_inb( ioaddr, AR_REG ) |
| 809 | #define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG ) |
| 810 | #define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG ) |
| 811 | #define SMC_GET_INT() SMC_inb( ioaddr, INT_REG ) |
| 812 | #define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG ) |
| 813 | #define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG ) |
| 814 | #define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG ) |
| 815 | #else |
| 816 | #define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF) |
| 817 | #define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG ) |
| 818 | #define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8) |
| 819 | #define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF) |
| 820 | #define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8) |
| 821 | #define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF) |
| 822 | #define SMC_ACK_INT(x) \ |
| 823 | do { \ |
| 824 | unsigned long __flags; \ |
| 825 | int __mask; \ |
| 826 | local_irq_save(__flags); \ |
| 827 | __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ |
| 828 | SMC_outw( __mask | (x), ioaddr, INT_REG ); \ |
| 829 | local_irq_restore(__flags); \ |
| 830 | } while (0) |
| 831 | #define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8) |
| 832 | #define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG ) |
| 833 | #endif |
| 834 | |
| 835 | #define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT ) |
| 836 | #define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT ) |
| 837 | #define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG ) |
| 838 | #define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG ) |
| 839 | #define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG ) |
| 840 | #define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG ) |
| 841 | #define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG ) |
| 842 | #define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG ) |
| 843 | #define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG ) |
| 844 | #define SMC_GET_MII() SMC_inw( ioaddr, MII_REG ) |
| 845 | #define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG ) |
| 846 | #define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG ) |
| 847 | #define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG ) |
| 848 | #define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG ) |
| 849 | #define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG ) |
| 850 | #define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG ) |
| 851 | #define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG ) |
| 852 | #define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG ) |
Nicolas Pitre | 8de9011 | 2005-04-12 16:21:11 -0400 | [diff] [blame] | 853 | #define SMC_GET_EPH_STATUS() SMC_inw( ioaddr, EPH_STATUS_REG ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | #define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG ) |
| 855 | #define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG ) |
| 856 | #define SMC_GET_REV() SMC_inw( ioaddr, REV_REG ) |
| 857 | #define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG ) |
| 858 | #define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG ) |
| 859 | #define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG ) |
| 860 | #define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG ) |
| 861 | |
| 862 | #ifndef SMC_GET_MAC_ADDR |
| 863 | #define SMC_GET_MAC_ADDR(addr) \ |
| 864 | do { \ |
| 865 | unsigned int __v; \ |
| 866 | __v = SMC_inw( ioaddr, ADDR0_REG ); \ |
| 867 | addr[0] = __v; addr[1] = __v >> 8; \ |
| 868 | __v = SMC_inw( ioaddr, ADDR1_REG ); \ |
| 869 | addr[2] = __v; addr[3] = __v >> 8; \ |
| 870 | __v = SMC_inw( ioaddr, ADDR2_REG ); \ |
| 871 | addr[4] = __v; addr[5] = __v >> 8; \ |
| 872 | } while (0) |
| 873 | #endif |
| 874 | |
| 875 | #define SMC_SET_MAC_ADDR(addr) \ |
| 876 | do { \ |
| 877 | SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ |
| 878 | SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ |
| 879 | SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ |
| 880 | } while (0) |
| 881 | |
| 882 | #define SMC_SET_MCAST(x) \ |
| 883 | do { \ |
| 884 | const unsigned char *mt = (x); \ |
| 885 | SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ |
| 886 | SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ |
| 887 | SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ |
| 888 | SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ |
| 889 | } while (0) |
| 890 | |
| 891 | #if SMC_CAN_USE_32BIT |
| 892 | /* |
| 893 | * Some setups just can't write 8 or 16 bits reliably when not aligned |
| 894 | * to a 32 bit boundary. I tell you that exists! |
| 895 | * We re-do the ones here that can be easily worked around if they can have |
| 896 | * their low parts written to 0 without adverse effects. |
| 897 | */ |
| 898 | #undef SMC_SELECT_BANK |
| 899 | #define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT ) |
| 900 | #undef SMC_SET_RPC |
| 901 | #define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) ) |
| 902 | #undef SMC_SET_PN |
| 903 | #define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) ) |
| 904 | #undef SMC_SET_PTR |
| 905 | #define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) ) |
| 906 | #endif |
| 907 | |
| 908 | #if SMC_CAN_USE_32BIT |
| 909 | #define SMC_PUT_PKT_HDR(status, length) \ |
| 910 | SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG ) |
| 911 | #define SMC_GET_PKT_HDR(status, length) \ |
| 912 | do { \ |
| 913 | unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \ |
| 914 | (status) = __val & 0xffff; \ |
| 915 | (length) = __val >> 16; \ |
| 916 | } while (0) |
| 917 | #else |
| 918 | #define SMC_PUT_PKT_HDR(status, length) \ |
| 919 | do { \ |
| 920 | SMC_outw( status, ioaddr, DATA_REG ); \ |
| 921 | SMC_outw( length, ioaddr, DATA_REG ); \ |
| 922 | } while (0) |
| 923 | #define SMC_GET_PKT_HDR(status, length) \ |
| 924 | do { \ |
| 925 | (status) = SMC_inw( ioaddr, DATA_REG ); \ |
| 926 | (length) = SMC_inw( ioaddr, DATA_REG ); \ |
| 927 | } while (0) |
| 928 | #endif |
| 929 | |
| 930 | #if SMC_CAN_USE_32BIT |
| 931 | #define _SMC_PUSH_DATA(p, l) \ |
| 932 | do { \ |
| 933 | char *__ptr = (p); \ |
| 934 | int __len = (l); \ |
| 935 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
| 936 | __len -= 2; \ |
| 937 | SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \ |
| 938 | __ptr += 2; \ |
| 939 | } \ |
| 940 | SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \ |
| 941 | if (__len & 2) { \ |
| 942 | __ptr += (__len & ~3); \ |
| 943 | SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ |
| 944 | } \ |
| 945 | } while (0) |
| 946 | #define _SMC_PULL_DATA(p, l) \ |
| 947 | do { \ |
| 948 | char *__ptr = (p); \ |
| 949 | int __len = (l); \ |
| 950 | if ((unsigned long)__ptr & 2) { \ |
| 951 | /* \ |
| 952 | * We want 32bit alignment here. \ |
| 953 | * Since some buses perform a full 32bit \ |
| 954 | * fetch even for 16bit data we can't use \ |
| 955 | * SMC_inw() here. Back both source (on chip \ |
| 956 | * and destination) pointers of 2 bytes. \ |
| 957 | */ \ |
| 958 | __ptr -= 2; \ |
| 959 | __len += 2; \ |
| 960 | SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ |
| 961 | } \ |
| 962 | __len += 2; \ |
| 963 | SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \ |
| 964 | } while (0) |
| 965 | #elif SMC_CAN_USE_16BIT |
| 966 | #define _SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 ) |
| 967 | #define _SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 ) |
| 968 | #elif SMC_CAN_USE_8BIT |
| 969 | #define _SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l ) |
| 970 | #define _SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l ) |
| 971 | #endif |
| 972 | |
| 973 | #if ! SMC_CAN_USE_16BIT |
| 974 | #define SMC_outw(x, ioaddr, reg) \ |
| 975 | do { \ |
| 976 | unsigned int __val16 = (x); \ |
| 977 | SMC_outb( __val16, ioaddr, reg ); \ |
| 978 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ |
| 979 | } while (0) |
| 980 | #define SMC_inw(ioaddr, reg) \ |
| 981 | ({ \ |
| 982 | unsigned int __val16; \ |
| 983 | __val16 = SMC_inb( ioaddr, reg ); \ |
| 984 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ |
| 985 | __val16; \ |
| 986 | }) |
| 987 | #endif |
| 988 | |
| 989 | #if SMC_CAN_USE_DATACS |
| 990 | #define SMC_PUSH_DATA(p, l) \ |
| 991 | if ( lp->datacs ) { \ |
| 992 | unsigned char *__ptr = (p); \ |
| 993 | int __len = (l); \ |
| 994 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
| 995 | __len -= 2; \ |
| 996 | SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ |
| 997 | __ptr += 2; \ |
| 998 | } \ |
| 999 | outsl(lp->datacs, __ptr, __len >> 2); \ |
| 1000 | if (__len & 2) { \ |
| 1001 | __ptr += (__len & ~3); \ |
| 1002 | SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ |
| 1003 | } \ |
| 1004 | } else { \ |
| 1005 | _SMC_PUSH_DATA(p, l); \ |
| 1006 | } |
| 1007 | |
| 1008 | #define SMC_PULL_DATA(p, l) \ |
| 1009 | if ( lp->datacs ) { \ |
| 1010 | unsigned char *__ptr = (p); \ |
| 1011 | int __len = (l); \ |
| 1012 | if ((unsigned long)__ptr & 2) { \ |
| 1013 | /* \ |
| 1014 | * We want 32bit alignment here. \ |
| 1015 | * Since some buses perform a full 32bit \ |
| 1016 | * fetch even for 16bit data we can't use \ |
| 1017 | * SMC_inw() here. Back both source (on chip \ |
| 1018 | * and destination) pointers of 2 bytes. \ |
| 1019 | */ \ |
| 1020 | __ptr -= 2; \ |
| 1021 | __len += 2; \ |
| 1022 | SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ |
| 1023 | } \ |
| 1024 | __len += 2; \ |
| 1025 | insl( lp->datacs, __ptr, __len >> 2); \ |
| 1026 | } else { \ |
| 1027 | _SMC_PULL_DATA(p, l); \ |
| 1028 | } |
| 1029 | #else |
| 1030 | #define SMC_PUSH_DATA(p, l) _SMC_PUSH_DATA(p, l) |
| 1031 | #define SMC_PULL_DATA(p, l) _SMC_PULL_DATA(p, l) |
| 1032 | #endif |
| 1033 | |
| 1034 | #if !defined (SMC_INTERRUPT_PREAMBLE) |
| 1035 | # define SMC_INTERRUPT_PREAMBLE |
| 1036 | #endif |
| 1037 | |
| 1038 | #endif /* _SMC91X_H_ */ |