Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 1 | /* |
| 2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs |
| 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. |
| 5 | * Copyright (C) 2009 NVIDIA Corporation |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/platform_data/tegra_usb.h> |
| 22 | #include <linux/irq.h> |
| 23 | #include <linux/usb/otg.h> |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/of.h> |
| 26 | #include <linux/of_gpio.h> |
| 27 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 28 | #include <mach/usb_phy.h> |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 29 | #include <mach/iomap.h> |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 30 | |
Robert Morell | fbf9865 | 2011-03-09 16:28:57 -0800 | [diff] [blame] | 31 | #define TEGRA_USB_DMA_ALIGN 32 |
| 32 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 33 | struct tegra_ehci_hcd { |
| 34 | struct ehci_hcd *ehci; |
| 35 | struct tegra_usb_phy *phy; |
| 36 | struct clk *clk; |
| 37 | struct clk *emc_clk; |
Heikki Krogerus | 8675381 | 2012-02-13 13:24:02 +0200 | [diff] [blame] | 38 | struct usb_phy *transceiver; |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 39 | int host_resumed; |
| 40 | int bus_suspended; |
| 41 | int port_resuming; |
| 42 | int power_down_on_bus_suspend; |
| 43 | enum tegra_usb_phy_port_speed port_speed; |
| 44 | }; |
| 45 | |
| 46 | static void tegra_ehci_power_up(struct usb_hcd *hcd) |
| 47 | { |
| 48 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 49 | |
| 50 | clk_enable(tegra->emc_clk); |
| 51 | clk_enable(tegra->clk); |
| 52 | tegra_usb_phy_power_on(tegra->phy); |
| 53 | tegra->host_resumed = 1; |
| 54 | } |
| 55 | |
| 56 | static void tegra_ehci_power_down(struct usb_hcd *hcd) |
| 57 | { |
| 58 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 59 | |
| 60 | tegra->host_resumed = 0; |
| 61 | tegra_usb_phy_power_off(tegra->phy); |
| 62 | clk_disable(tegra->clk); |
| 63 | clk_disable(tegra->emc_clk); |
| 64 | } |
| 65 | |
Jim Lin | 1f594b6 | 2011-04-17 11:58:25 +0300 | [diff] [blame] | 66 | static int tegra_ehci_internal_port_reset( |
| 67 | struct ehci_hcd *ehci, |
| 68 | u32 __iomem *portsc_reg |
| 69 | ) |
| 70 | { |
| 71 | u32 temp; |
| 72 | unsigned long flags; |
| 73 | int retval = 0; |
| 74 | int i, tries; |
| 75 | u32 saved_usbintr; |
| 76 | |
| 77 | spin_lock_irqsave(&ehci->lock, flags); |
| 78 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); |
| 79 | /* disable USB interrupt */ |
| 80 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
| 81 | spin_unlock_irqrestore(&ehci->lock, flags); |
| 82 | |
| 83 | /* |
| 84 | * Here we have to do Port Reset at most twice for |
| 85 | * Port Enable bit to be set. |
| 86 | */ |
| 87 | for (i = 0; i < 2; i++) { |
| 88 | temp = ehci_readl(ehci, portsc_reg); |
| 89 | temp |= PORT_RESET; |
| 90 | ehci_writel(ehci, temp, portsc_reg); |
| 91 | mdelay(10); |
| 92 | temp &= ~PORT_RESET; |
| 93 | ehci_writel(ehci, temp, portsc_reg); |
| 94 | mdelay(1); |
| 95 | tries = 100; |
| 96 | do { |
| 97 | mdelay(1); |
| 98 | /* |
| 99 | * Up to this point, Port Enable bit is |
| 100 | * expected to be set after 2 ms waiting. |
| 101 | * USB1 usually takes extra 45 ms, for safety, |
| 102 | * we take 100 ms as timeout. |
| 103 | */ |
| 104 | temp = ehci_readl(ehci, portsc_reg); |
| 105 | } while (!(temp & PORT_PE) && tries--); |
| 106 | if (temp & PORT_PE) |
| 107 | break; |
| 108 | } |
| 109 | if (i == 2) |
| 110 | retval = -ETIMEDOUT; |
| 111 | |
| 112 | /* |
| 113 | * Clear Connect Status Change bit if it's set. |
| 114 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. |
| 115 | */ |
| 116 | if (temp & PORT_CSC) |
| 117 | ehci_writel(ehci, PORT_CSC, portsc_reg); |
| 118 | |
| 119 | /* |
| 120 | * Write to clear any interrupt status bits that might be set |
| 121 | * during port reset. |
| 122 | */ |
| 123 | temp = ehci_readl(ehci, &ehci->regs->status); |
| 124 | ehci_writel(ehci, temp, &ehci->regs->status); |
| 125 | |
| 126 | /* restore original interrupt enable bits */ |
| 127 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); |
| 128 | return retval; |
| 129 | } |
| 130 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 131 | static int tegra_ehci_hub_control( |
| 132 | struct usb_hcd *hcd, |
| 133 | u16 typeReq, |
| 134 | u16 wValue, |
| 135 | u16 wIndex, |
| 136 | char *buf, |
| 137 | u16 wLength |
| 138 | ) |
| 139 | { |
| 140 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
| 141 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 142 | u32 __iomem *status_reg; |
| 143 | u32 temp; |
| 144 | unsigned long flags; |
| 145 | int retval = 0; |
| 146 | |
| 147 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; |
| 148 | |
| 149 | spin_lock_irqsave(&ehci->lock, flags); |
| 150 | |
| 151 | /* |
| 152 | * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits |
| 153 | * that are write on clear, by writing back the register read value, so |
| 154 | * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits |
| 155 | */ |
| 156 | if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) { |
| 157 | temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS; |
| 158 | ehci_writel(ehci, temp & ~PORT_PE, status_reg); |
| 159 | goto done; |
| 160 | } |
| 161 | |
| 162 | else if (typeReq == GetPortStatus) { |
| 163 | temp = ehci_readl(ehci, status_reg); |
| 164 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { |
| 165 | /* Resume completed, re-enable disconnect detection */ |
| 166 | tegra->port_resuming = 0; |
| 167 | tegra_usb_phy_postresume(tegra->phy); |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { |
| 172 | temp = ehci_readl(ehci, status_reg); |
| 173 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { |
| 174 | retval = -EPIPE; |
| 175 | goto done; |
| 176 | } |
| 177 | |
| 178 | temp &= ~PORT_WKCONN_E; |
| 179 | temp |= PORT_WKDISC_E | PORT_WKOC_E; |
| 180 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); |
| 181 | |
| 182 | /* |
| 183 | * If a transaction is in progress, there may be a delay in |
| 184 | * suspending the port. Poll until the port is suspended. |
| 185 | */ |
| 186 | if (handshake(ehci, status_reg, PORT_SUSPEND, |
| 187 | PORT_SUSPEND, 5000)) |
| 188 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); |
| 189 | |
| 190 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); |
| 191 | goto done; |
| 192 | } |
| 193 | |
Jim Lin | 1f594b6 | 2011-04-17 11:58:25 +0300 | [diff] [blame] | 194 | /* For USB1 port we need to issue Port Reset twice internally */ |
| 195 | if (tegra->phy->instance == 0 && |
| 196 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { |
| 197 | spin_unlock_irqrestore(&ehci->lock, flags); |
| 198 | return tegra_ehci_internal_port_reset(ehci, status_reg); |
| 199 | } |
| 200 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 201 | /* |
| 202 | * Tegra host controller will time the resume operation to clear the bit |
| 203 | * when the port control state switches to HS or FS Idle. This behavior |
| 204 | * is different from EHCI where the host controller driver is required |
| 205 | * to set this bit to a zero after the resume duration is timed in the |
| 206 | * driver. |
| 207 | */ |
| 208 | else if (typeReq == ClearPortFeature && |
| 209 | wValue == USB_PORT_FEAT_SUSPEND) { |
| 210 | temp = ehci_readl(ehci, status_reg); |
| 211 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { |
| 212 | retval = -EPIPE; |
| 213 | goto done; |
| 214 | } |
| 215 | |
| 216 | if (!(temp & PORT_SUSPEND)) |
| 217 | goto done; |
| 218 | |
| 219 | /* Disable disconnect detection during port resume */ |
| 220 | tegra_usb_phy_preresume(tegra->phy); |
| 221 | |
| 222 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); |
| 223 | |
| 224 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); |
| 225 | /* start resume signalling */ |
| 226 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); |
Alan Stern | a448e4d | 2012-04-03 15:24:30 -0400 | [diff] [blame] | 227 | set_bit(wIndex-1, &ehci->resuming_ports); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 228 | |
| 229 | spin_unlock_irqrestore(&ehci->lock, flags); |
| 230 | msleep(20); |
| 231 | spin_lock_irqsave(&ehci->lock, flags); |
| 232 | |
| 233 | /* Poll until the controller clears RESUME and SUSPEND */ |
| 234 | if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) |
| 235 | pr_err("%s: timeout waiting for RESUME\n", __func__); |
| 236 | if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) |
| 237 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); |
| 238 | |
| 239 | ehci->reset_done[wIndex-1] = 0; |
Alan Stern | a448e4d | 2012-04-03 15:24:30 -0400 | [diff] [blame] | 240 | clear_bit(wIndex-1, &ehci->resuming_ports); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 241 | |
| 242 | tegra->port_resuming = 1; |
| 243 | goto done; |
| 244 | } |
| 245 | |
| 246 | spin_unlock_irqrestore(&ehci->lock, flags); |
| 247 | |
| 248 | /* Handle the hub control events here */ |
| 249 | return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); |
| 250 | done: |
| 251 | spin_unlock_irqrestore(&ehci->lock, flags); |
| 252 | return retval; |
| 253 | } |
| 254 | |
| 255 | static void tegra_ehci_restart(struct usb_hcd *hcd) |
| 256 | { |
| 257 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
| 258 | |
| 259 | ehci_reset(ehci); |
| 260 | |
| 261 | /* setup the frame list and Async q heads */ |
| 262 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
| 263 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); |
| 264 | /* setup the command register and set the controller in RUN mode */ |
| 265 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
| 266 | ehci->command |= CMD_RUN; |
| 267 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
| 268 | |
| 269 | down_write(&ehci_cf_port_reset_rwsem); |
| 270 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
| 271 | /* flush posted writes */ |
| 272 | ehci_readl(ehci, &ehci->regs->command); |
| 273 | up_write(&ehci_cf_port_reset_rwsem); |
| 274 | } |
| 275 | |
| 276 | static int tegra_usb_suspend(struct usb_hcd *hcd) |
| 277 | { |
| 278 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 279 | struct ehci_regs __iomem *hw = tegra->ehci->regs; |
| 280 | unsigned long flags; |
| 281 | |
| 282 | spin_lock_irqsave(&tegra->ehci->lock, flags); |
| 283 | |
| 284 | tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; |
| 285 | ehci_halt(tegra->ehci); |
| 286 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
| 287 | |
| 288 | spin_unlock_irqrestore(&tegra->ehci->lock, flags); |
| 289 | |
| 290 | tegra_ehci_power_down(hcd); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | static int tegra_usb_resume(struct usb_hcd *hcd) |
| 295 | { |
| 296 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 297 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
| 298 | struct ehci_regs __iomem *hw = ehci->regs; |
| 299 | unsigned long val; |
| 300 | |
| 301 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
| 302 | tegra_ehci_power_up(hcd); |
| 303 | |
| 304 | if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { |
| 305 | /* Wait for the phy to detect new devices |
| 306 | * before we restart the controller */ |
| 307 | msleep(10); |
| 308 | goto restart; |
| 309 | } |
| 310 | |
| 311 | /* Force the phy to keep data lines in suspend state */ |
| 312 | tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed); |
| 313 | |
| 314 | /* Enable host mode */ |
| 315 | tdi_reset(ehci); |
| 316 | |
| 317 | /* Enable Port Power */ |
| 318 | val = readl(&hw->port_status[0]); |
| 319 | val |= PORT_POWER; |
| 320 | writel(val, &hw->port_status[0]); |
| 321 | udelay(10); |
| 322 | |
| 323 | /* Check if the phy resume from LP0. When the phy resume from LP0 |
| 324 | * USB register will be reset. */ |
| 325 | if (!readl(&hw->async_next)) { |
| 326 | /* Program the field PTC based on the saved speed mode */ |
| 327 | val = readl(&hw->port_status[0]); |
| 328 | val &= ~PORT_TEST(~0); |
| 329 | if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) |
| 330 | val |= PORT_TEST_FORCE; |
| 331 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) |
| 332 | val |= PORT_TEST(6); |
| 333 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) |
| 334 | val |= PORT_TEST(7); |
| 335 | writel(val, &hw->port_status[0]); |
| 336 | udelay(10); |
| 337 | |
| 338 | /* Disable test mode by setting PTC field to NORMAL_OP */ |
| 339 | val = readl(&hw->port_status[0]); |
| 340 | val &= ~PORT_TEST(~0); |
| 341 | writel(val, &hw->port_status[0]); |
| 342 | udelay(10); |
| 343 | } |
| 344 | |
| 345 | /* Poll until CCS is enabled */ |
| 346 | if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, |
| 347 | PORT_CONNECT, 2000)) { |
| 348 | pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); |
| 349 | goto restart; |
| 350 | } |
| 351 | |
| 352 | /* Poll until PE is enabled */ |
| 353 | if (handshake(ehci, &hw->port_status[0], PORT_PE, |
| 354 | PORT_PE, 2000)) { |
| 355 | pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); |
| 356 | goto restart; |
| 357 | } |
| 358 | |
| 359 | /* Clear the PCI status, to avoid an interrupt taken upon resume */ |
| 360 | val = readl(&hw->status); |
| 361 | val |= STS_PCD; |
| 362 | writel(val, &hw->status); |
| 363 | |
| 364 | /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ |
| 365 | val = readl(&hw->port_status[0]); |
| 366 | if ((val & PORT_POWER) && (val & PORT_PE)) { |
| 367 | val |= PORT_SUSPEND; |
| 368 | writel(val, &hw->port_status[0]); |
| 369 | |
| 370 | /* Wait until port suspend completes */ |
| 371 | if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, |
| 372 | PORT_SUSPEND, 1000)) { |
| 373 | pr_err("%s: timeout waiting for PORT_SUSPEND\n", |
| 374 | __func__); |
| 375 | goto restart; |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | tegra_ehci_phy_restore_end(tegra->phy); |
| 380 | return 0; |
| 381 | |
| 382 | restart: |
| 383 | if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) |
| 384 | tegra_ehci_phy_restore_end(tegra->phy); |
| 385 | |
| 386 | tegra_ehci_restart(hcd); |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | static void tegra_ehci_shutdown(struct usb_hcd *hcd) |
| 391 | { |
| 392 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 393 | |
| 394 | /* ehci_shutdown touches the USB controller registers, make sure |
| 395 | * controller has clocks to it */ |
| 396 | if (!tegra->host_resumed) |
| 397 | tegra_ehci_power_up(hcd); |
| 398 | |
| 399 | ehci_shutdown(hcd); |
| 400 | } |
| 401 | |
| 402 | static int tegra_ehci_setup(struct usb_hcd *hcd) |
| 403 | { |
| 404 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
| 405 | int retval; |
| 406 | |
| 407 | /* EHCI registers start at offset 0x100 */ |
| 408 | ehci->caps = hcd->regs + 0x100; |
| 409 | ehci->regs = hcd->regs + 0x100 + |
Jan Andersson | c430131 | 2011-05-03 20:11:57 +0200 | [diff] [blame] | 410 | HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 411 | |
| 412 | dbg_hcs_params(ehci, "reset"); |
| 413 | dbg_hcc_params(ehci, "reset"); |
| 414 | |
| 415 | /* cache this readonly data; minimize chip reads */ |
| 416 | ehci->hcs_params = readl(&ehci->caps->hcs_params); |
| 417 | |
| 418 | /* switch to host mode */ |
| 419 | hcd->has_tt = 1; |
| 420 | ehci_reset(ehci); |
| 421 | |
| 422 | retval = ehci_halt(ehci); |
| 423 | if (retval) |
| 424 | return retval; |
| 425 | |
| 426 | /* data structure init */ |
| 427 | retval = ehci_init(hcd); |
| 428 | if (retval) |
| 429 | return retval; |
| 430 | |
| 431 | ehci->sbrn = 0x20; |
| 432 | |
| 433 | ehci_port_power(ehci, 1); |
| 434 | return retval; |
| 435 | } |
| 436 | |
| 437 | #ifdef CONFIG_PM |
| 438 | static int tegra_ehci_bus_suspend(struct usb_hcd *hcd) |
| 439 | { |
| 440 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 441 | int error_status = 0; |
| 442 | |
| 443 | error_status = ehci_bus_suspend(hcd); |
| 444 | if (!error_status && tegra->power_down_on_bus_suspend) { |
| 445 | tegra_usb_suspend(hcd); |
| 446 | tegra->bus_suspended = 1; |
| 447 | } |
| 448 | |
| 449 | return error_status; |
| 450 | } |
| 451 | |
| 452 | static int tegra_ehci_bus_resume(struct usb_hcd *hcd) |
| 453 | { |
| 454 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); |
| 455 | |
| 456 | if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) { |
| 457 | tegra_usb_resume(hcd); |
| 458 | tegra->bus_suspended = 0; |
| 459 | } |
| 460 | |
| 461 | tegra_usb_phy_preresume(tegra->phy); |
| 462 | tegra->port_resuming = 1; |
| 463 | return ehci_bus_resume(hcd); |
| 464 | } |
| 465 | #endif |
| 466 | |
Robert Morell | fbf9865 | 2011-03-09 16:28:57 -0800 | [diff] [blame] | 467 | struct temp_buffer { |
| 468 | void *kmalloc_ptr; |
| 469 | void *old_xfer_buffer; |
| 470 | u8 data[0]; |
| 471 | }; |
| 472 | |
| 473 | static void free_temp_buffer(struct urb *urb) |
| 474 | { |
| 475 | enum dma_data_direction dir; |
| 476 | struct temp_buffer *temp; |
| 477 | |
| 478 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) |
| 479 | return; |
| 480 | |
| 481 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; |
| 482 | |
| 483 | temp = container_of(urb->transfer_buffer, struct temp_buffer, |
| 484 | data); |
| 485 | |
| 486 | if (dir == DMA_FROM_DEVICE) |
| 487 | memcpy(temp->old_xfer_buffer, temp->data, |
| 488 | urb->transfer_buffer_length); |
| 489 | urb->transfer_buffer = temp->old_xfer_buffer; |
| 490 | kfree(temp->kmalloc_ptr); |
| 491 | |
| 492 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; |
| 493 | } |
| 494 | |
| 495 | static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) |
| 496 | { |
| 497 | enum dma_data_direction dir; |
| 498 | struct temp_buffer *temp, *kmalloc_ptr; |
| 499 | size_t kmalloc_size; |
| 500 | |
| 501 | if (urb->num_sgs || urb->sg || |
| 502 | urb->transfer_buffer_length == 0 || |
| 503 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) |
| 504 | return 0; |
| 505 | |
| 506 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; |
| 507 | |
| 508 | /* Allocate a buffer with enough padding for alignment */ |
| 509 | kmalloc_size = urb->transfer_buffer_length + |
| 510 | sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1; |
| 511 | |
| 512 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); |
| 513 | if (!kmalloc_ptr) |
| 514 | return -ENOMEM; |
| 515 | |
| 516 | /* Position our struct temp_buffer such that data is aligned */ |
| 517 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; |
| 518 | |
| 519 | temp->kmalloc_ptr = kmalloc_ptr; |
| 520 | temp->old_xfer_buffer = urb->transfer_buffer; |
| 521 | if (dir == DMA_TO_DEVICE) |
| 522 | memcpy(temp->data, urb->transfer_buffer, |
| 523 | urb->transfer_buffer_length); |
| 524 | urb->transfer_buffer = temp->data; |
| 525 | |
| 526 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, |
| 532 | gfp_t mem_flags) |
| 533 | { |
| 534 | int ret; |
| 535 | |
| 536 | ret = alloc_temp_buffer(urb, mem_flags); |
| 537 | if (ret) |
| 538 | return ret; |
| 539 | |
| 540 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); |
| 541 | if (ret) |
| 542 | free_temp_buffer(urb); |
| 543 | |
| 544 | return ret; |
| 545 | } |
| 546 | |
| 547 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) |
| 548 | { |
| 549 | usb_hcd_unmap_urb_for_dma(hcd, urb); |
| 550 | free_temp_buffer(urb); |
| 551 | } |
| 552 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 553 | static const struct hc_driver tegra_ehci_hc_driver = { |
| 554 | .description = hcd_name, |
| 555 | .product_desc = "Tegra EHCI Host Controller", |
| 556 | .hcd_priv_size = sizeof(struct ehci_hcd), |
| 557 | |
| 558 | .flags = HCD_USB2 | HCD_MEMORY, |
| 559 | |
| 560 | .reset = tegra_ehci_setup, |
| 561 | .irq = ehci_irq, |
| 562 | |
| 563 | .start = ehci_run, |
| 564 | .stop = ehci_stop, |
| 565 | .shutdown = tegra_ehci_shutdown, |
| 566 | .urb_enqueue = ehci_urb_enqueue, |
| 567 | .urb_dequeue = ehci_urb_dequeue, |
Robert Morell | fbf9865 | 2011-03-09 16:28:57 -0800 | [diff] [blame] | 568 | .map_urb_for_dma = tegra_ehci_map_urb_for_dma, |
| 569 | .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 570 | .endpoint_disable = ehci_endpoint_disable, |
| 571 | .endpoint_reset = ehci_endpoint_reset, |
| 572 | .get_frame_number = ehci_get_frame, |
| 573 | .hub_status_data = ehci_hub_status_data, |
| 574 | .hub_control = tegra_ehci_hub_control, |
| 575 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
| 576 | #ifdef CONFIG_PM |
| 577 | .bus_suspend = tegra_ehci_bus_suspend, |
| 578 | .bus_resume = tegra_ehci_bus_resume, |
| 579 | #endif |
| 580 | .relinquish_port = ehci_relinquish_port, |
| 581 | .port_handed_over = ehci_port_handed_over, |
| 582 | }; |
| 583 | |
Stephen Warren | 434103a | 2012-03-16 16:06:07 -0600 | [diff] [blame] | 584 | static int setup_vbus_gpio(struct platform_device *pdev, |
| 585 | struct tegra_ehci_platform_data *pdata) |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 586 | { |
| 587 | int err = 0; |
| 588 | int gpio; |
| 589 | |
Stephen Warren | 434103a | 2012-03-16 16:06:07 -0600 | [diff] [blame] | 590 | gpio = pdata->vbus_gpio; |
| 591 | if (!gpio_is_valid(gpio)) |
| 592 | gpio = of_get_named_gpio(pdev->dev.of_node, |
| 593 | "nvidia,vbus-gpio", 0); |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 594 | if (!gpio_is_valid(gpio)) |
| 595 | return 0; |
| 596 | |
| 597 | err = gpio_request(gpio, "vbus_gpio"); |
| 598 | if (err) { |
| 599 | dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); |
| 600 | return err; |
| 601 | } |
| 602 | err = gpio_direction_output(gpio, 1); |
| 603 | if (err) { |
| 604 | dev_err(&pdev->dev, "can't enable vbus\n"); |
| 605 | return err; |
| 606 | } |
| 607 | gpio_set_value(gpio, 1); |
| 608 | |
| 609 | return err; |
| 610 | } |
| 611 | |
| 612 | static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); |
| 613 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 614 | static int tegra_ehci_probe(struct platform_device *pdev) |
| 615 | { |
| 616 | struct resource *res; |
| 617 | struct usb_hcd *hcd; |
| 618 | struct tegra_ehci_hcd *tegra; |
| 619 | struct tegra_ehci_platform_data *pdata; |
| 620 | int err = 0; |
| 621 | int irq; |
| 622 | int instance = pdev->id; |
| 623 | |
| 624 | pdata = pdev->dev.platform_data; |
| 625 | if (!pdata) { |
| 626 | dev_err(&pdev->dev, "Platform data missing\n"); |
| 627 | return -EINVAL; |
| 628 | } |
| 629 | |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 630 | /* Right now device-tree probed devices don't get dma_mask set. |
| 631 | * Since shared usb code relies on it, set it here for now. |
| 632 | * Once we have dma capability bindings this can go away. |
| 633 | */ |
| 634 | if (!pdev->dev.dma_mask) |
| 635 | pdev->dev.dma_mask = &tegra_ehci_dma_mask; |
| 636 | |
Stephen Warren | 434103a | 2012-03-16 16:06:07 -0600 | [diff] [blame] | 637 | setup_vbus_gpio(pdev, pdata); |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 638 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 639 | tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); |
| 640 | if (!tegra) |
| 641 | return -ENOMEM; |
| 642 | |
| 643 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, |
| 644 | dev_name(&pdev->dev)); |
| 645 | if (!hcd) { |
| 646 | dev_err(&pdev->dev, "Unable to create HCD\n"); |
| 647 | err = -ENOMEM; |
| 648 | goto fail_hcd; |
| 649 | } |
| 650 | |
| 651 | platform_set_drvdata(pdev, tegra); |
| 652 | |
| 653 | tegra->clk = clk_get(&pdev->dev, NULL); |
| 654 | if (IS_ERR(tegra->clk)) { |
| 655 | dev_err(&pdev->dev, "Can't get ehci clock\n"); |
| 656 | err = PTR_ERR(tegra->clk); |
| 657 | goto fail_clk; |
| 658 | } |
| 659 | |
| 660 | err = clk_enable(tegra->clk); |
| 661 | if (err) |
| 662 | goto fail_clken; |
| 663 | |
| 664 | tegra->emc_clk = clk_get(&pdev->dev, "emc"); |
| 665 | if (IS_ERR(tegra->emc_clk)) { |
| 666 | dev_err(&pdev->dev, "Can't get emc clock\n"); |
| 667 | err = PTR_ERR(tegra->emc_clk); |
| 668 | goto fail_emc_clk; |
| 669 | } |
| 670 | |
| 671 | clk_enable(tegra->emc_clk); |
| 672 | clk_set_rate(tegra->emc_clk, 400000000); |
| 673 | |
| 674 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 675 | if (!res) { |
| 676 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); |
| 677 | err = -ENXIO; |
| 678 | goto fail_io; |
| 679 | } |
| 680 | hcd->rsrc_start = res->start; |
| 681 | hcd->rsrc_len = resource_size(res); |
| 682 | hcd->regs = ioremap(res->start, resource_size(res)); |
| 683 | if (!hcd->regs) { |
| 684 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); |
| 685 | err = -ENOMEM; |
| 686 | goto fail_io; |
| 687 | } |
| 688 | |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 689 | /* This is pretty ugly and needs to be fixed when we do only |
| 690 | * device-tree probing. Old code relies on the platform_device |
| 691 | * numbering that we lack for device-tree-instantiated devices. |
| 692 | */ |
| 693 | if (instance < 0) { |
| 694 | switch (res->start) { |
| 695 | case TEGRA_USB_BASE: |
| 696 | instance = 0; |
| 697 | break; |
| 698 | case TEGRA_USB2_BASE: |
| 699 | instance = 1; |
| 700 | break; |
| 701 | case TEGRA_USB3_BASE: |
| 702 | instance = 2; |
| 703 | break; |
| 704 | default: |
| 705 | err = -ENODEV; |
| 706 | dev_err(&pdev->dev, "unknown usb instance\n"); |
| 707 | goto fail_phy; |
| 708 | } |
| 709 | } |
| 710 | |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 711 | tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs, |
| 712 | pdata->phy_config, |
| 713 | TEGRA_USB_PHY_MODE_HOST); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 714 | if (IS_ERR(tegra->phy)) { |
| 715 | dev_err(&pdev->dev, "Failed to open USB phy\n"); |
| 716 | err = -ENXIO; |
| 717 | goto fail_phy; |
| 718 | } |
| 719 | |
| 720 | err = tegra_usb_phy_power_on(tegra->phy); |
| 721 | if (err) { |
| 722 | dev_err(&pdev->dev, "Failed to power on the phy\n"); |
| 723 | goto fail; |
| 724 | } |
| 725 | |
| 726 | tegra->host_resumed = 1; |
| 727 | tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend; |
| 728 | tegra->ehci = hcd_to_ehci(hcd); |
| 729 | |
| 730 | irq = platform_get_irq(pdev, 0); |
| 731 | if (!irq) { |
| 732 | dev_err(&pdev->dev, "Failed to get IRQ\n"); |
| 733 | err = -ENODEV; |
| 734 | goto fail; |
| 735 | } |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 736 | |
| 737 | #ifdef CONFIG_USB_OTG_UTILS |
| 738 | if (pdata->operating_mode == TEGRA_USB_OTG) { |
Heikki Krogerus | b96d3b0 | 2012-02-13 13:24:18 +0200 | [diff] [blame] | 739 | tegra->transceiver = usb_get_transceiver(); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 740 | if (tegra->transceiver) |
Heikki Krogerus | 6e13c65 | 2012-02-13 13:24:20 +0200 | [diff] [blame] | 741 | otg_set_host(tegra->transceiver->otg, &hcd->self); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 742 | } |
| 743 | #endif |
| 744 | |
Yong Zhang | b5dd18d | 2011-09-07 16:10:52 +0800 | [diff] [blame] | 745 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 746 | if (err) { |
| 747 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); |
| 748 | goto fail; |
| 749 | } |
| 750 | |
| 751 | return err; |
| 752 | |
| 753 | fail: |
| 754 | #ifdef CONFIG_USB_OTG_UTILS |
| 755 | if (tegra->transceiver) { |
Heikki Krogerus | 6e13c65 | 2012-02-13 13:24:20 +0200 | [diff] [blame] | 756 | otg_set_host(tegra->transceiver->otg, NULL); |
Heikki Krogerus | b96d3b0 | 2012-02-13 13:24:18 +0200 | [diff] [blame] | 757 | usb_put_transceiver(tegra->transceiver); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 758 | } |
| 759 | #endif |
| 760 | tegra_usb_phy_close(tegra->phy); |
| 761 | fail_phy: |
| 762 | iounmap(hcd->regs); |
| 763 | fail_io: |
| 764 | clk_disable(tegra->emc_clk); |
| 765 | clk_put(tegra->emc_clk); |
| 766 | fail_emc_clk: |
| 767 | clk_disable(tegra->clk); |
| 768 | fail_clken: |
| 769 | clk_put(tegra->clk); |
| 770 | fail_clk: |
| 771 | usb_put_hcd(hcd); |
| 772 | fail_hcd: |
| 773 | kfree(tegra); |
| 774 | return err; |
| 775 | } |
| 776 | |
| 777 | #ifdef CONFIG_PM |
| 778 | static int tegra_ehci_resume(struct platform_device *pdev) |
| 779 | { |
| 780 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); |
| 781 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); |
| 782 | |
| 783 | if (tegra->bus_suspended) |
| 784 | return 0; |
| 785 | |
| 786 | return tegra_usb_resume(hcd); |
| 787 | } |
| 788 | |
| 789 | static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state) |
| 790 | { |
| 791 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); |
| 792 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); |
| 793 | |
| 794 | if (tegra->bus_suspended) |
| 795 | return 0; |
| 796 | |
| 797 | if (time_before(jiffies, tegra->ehci->next_statechange)) |
| 798 | msleep(10); |
| 799 | |
| 800 | return tegra_usb_suspend(hcd); |
| 801 | } |
| 802 | #endif |
| 803 | |
| 804 | static int tegra_ehci_remove(struct platform_device *pdev) |
| 805 | { |
| 806 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); |
| 807 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); |
| 808 | |
| 809 | if (tegra == NULL || hcd == NULL) |
| 810 | return -EINVAL; |
| 811 | |
| 812 | #ifdef CONFIG_USB_OTG_UTILS |
| 813 | if (tegra->transceiver) { |
Heikki Krogerus | 6e13c65 | 2012-02-13 13:24:20 +0200 | [diff] [blame] | 814 | otg_set_host(tegra->transceiver->otg, NULL); |
Heikki Krogerus | b96d3b0 | 2012-02-13 13:24:18 +0200 | [diff] [blame] | 815 | usb_put_transceiver(tegra->transceiver); |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 816 | } |
| 817 | #endif |
| 818 | |
| 819 | usb_remove_hcd(hcd); |
| 820 | usb_put_hcd(hcd); |
| 821 | |
| 822 | tegra_usb_phy_close(tegra->phy); |
| 823 | iounmap(hcd->regs); |
| 824 | |
| 825 | clk_disable(tegra->clk); |
| 826 | clk_put(tegra->clk); |
| 827 | |
| 828 | clk_disable(tegra->emc_clk); |
| 829 | clk_put(tegra->emc_clk); |
| 830 | |
| 831 | kfree(tegra); |
| 832 | return 0; |
| 833 | } |
| 834 | |
| 835 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) |
| 836 | { |
| 837 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); |
| 838 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); |
| 839 | |
| 840 | if (hcd->driver->shutdown) |
| 841 | hcd->driver->shutdown(hcd); |
| 842 | } |
| 843 | |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 844 | static struct of_device_id tegra_ehci_of_match[] __devinitdata = { |
| 845 | { .compatible = "nvidia,tegra20-ehci", }, |
| 846 | { }, |
| 847 | }; |
| 848 | |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 849 | static struct platform_driver tegra_ehci_driver = { |
| 850 | .probe = tegra_ehci_probe, |
| 851 | .remove = tegra_ehci_remove, |
| 852 | #ifdef CONFIG_PM |
| 853 | .suspend = tegra_ehci_suspend, |
| 854 | .resume = tegra_ehci_resume, |
| 855 | #endif |
| 856 | .shutdown = tegra_ehci_hcd_shutdown, |
| 857 | .driver = { |
| 858 | .name = "tegra-ehci", |
Olof Johansson | 4a53f4e | 2011-11-04 09:12:40 +0000 | [diff] [blame] | 859 | .of_match_table = tegra_ehci_of_match, |
Benoit Goby | 79ad3b5 | 2011-03-09 16:28:56 -0800 | [diff] [blame] | 860 | } |
| 861 | }; |