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Thomas Petazzonic27f29b2016-02-19 14:34:43 +01001
2* Marvell ODMI for MSI support
3
4Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5which can be used by on-board peripheral for MSI interrupts.
6
7Required properties:
8
Thomas Petazzonib009b092016-02-24 16:24:54 +01009- compatible : The value here should contain:
10
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
Thomas Petazzonic27f29b2016-02-19 14:34:43 +010012
13- interrupt,controller : Identifies the node as an interrupt controller.
14
15- msi-controller : Identifies the node as an MSI controller.
16
17- marvell,odmi-frames : Number of ODMI frames available. Each frame
18 provides a number of events.
19
20- reg : List of register definitions, one for each
21 ODMI frame.
22
23- marvell,spi-base : List of GIC base SPI interrupts, one for each
24 ODMI frame. Those SPI interrupts are 0-based,
25 i.e marvell,spi-base = <128> will use SPI #96.
26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
27 for details about the GIC Device Tree binding.
28
29- interrupt-parent : Reference to the parent interrupt controller.
30
31Example:
32
33 odmi: odmi@300000 {
Thomas Petazzonib009b092016-02-24 16:24:54 +010034 compatible = "marvell,ap806-odm-controller",
35 "marvell,odmi-controller";
Thomas Petazzonic27f29b2016-02-19 14:34:43 +010036 interrupt-controller;
37 msi-controller;
38 marvell,odmi-frames = <4>;
39 reg = <0x300000 0x4000>,
40 <0x304000 0x4000>,
41 <0x308000 0x4000>,
42 <0x30C000 0x4000>;
43 marvell,spi-base = <128>, <136>, <144>, <152>;
44 };