blob: 523f04c90dea45826af4a3de70a43d54896f6043 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
Dave Airlieab2c0672009-12-04 10:55:24 +100023#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
Keith Packarda4fc5ed2009-04-07 16:16:42 -070025
Jesse Barnes9f0e7ff2010-10-07 16:01:14 -070026#include <linux/types.h>
27#include <linux/i2c.h>
Daniel Vetter1a644cd2012-10-18 15:32:40 +020028#include <linux/delay.h>
Jesse Barnes9f0e7ff2010-10-07 16:01:14 -070029
Adam Jacksona477f4f2012-09-20 16:42:44 -040030/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
Dave Airlie3c8a0922014-05-02 11:05:21 +100040 * MST: Multistream Transport - part of DP 1.2a
Adam Jacksona477f4f2012-09-20 16:42:44 -040041 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -070044
Simon Farnsworth1d002fa2015-02-10 18:38:08 +000045#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
Thierry Reding6b27f7f2013-12-16 17:01:29 +010047#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
49#define DP_AUX_I2C_STATUS 0x2
50#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
Keith Packarda4fc5ed2009-04-07 16:16:42 -070053
Thierry Reding6b27f7f2013-12-16 17:01:29 +010054#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -070058
Thierry Reding6b27f7f2013-12-16 17:01:29 +010059#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
Keith Packarda4fc5ed2009-04-07 16:16:42 -070063
64/* AUX CH addresses */
Alex Deucher5801ead2009-11-24 13:32:59 -050065/* DPCD */
66#define DP_DPCD_REV 0x000
Dave Airlie746c1aa2009-12-08 07:07:28 +100067
Alex Deucher5801ead2009-11-24 13:32:59 -050068#define DP_MAX_LINK_RATE 0x001
69
70#define DP_MAX_LANE_COUNT 0x002
71# define DP_MAX_LANE_COUNT_MASK 0x1f
Adam Jacksona477f4f2012-09-20 16:42:44 -040072# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
Alex Deucher5801ead2009-11-24 13:32:59 -050073# define DP_ENHANCED_FRAME_CAP (1 << 7)
74
75#define DP_MAX_DOWNSPREAD 0x003
76# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
77
78#define DP_NORP 0x004
79
80#define DP_DOWNSTREAMPORT_PRESENT 0x005
81# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
82# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
Jani Nikula3d2e4232013-09-27 14:48:41 +030083# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
84# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
85# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
86# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
Alex Deucher5801ead2009-11-24 13:32:59 -050087# define DP_FORMAT_CONVERSION (1 << 3)
Adam Jacksona477f4f2012-09-20 16:42:44 -040088# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
Alex Deucher5801ead2009-11-24 13:32:59 -050089
90#define DP_MAIN_LINK_CHANNEL_CODING 0x006
91
Adam Jacksonde44d972012-05-14 16:05:46 -040092#define DP_DOWN_STREAM_PORT_COUNT 0x007
Adam Jacksone89861d2012-09-18 10:58:48 -040093# define DP_PORT_COUNT_MASK 0x0f
Adam Jacksona477f4f2012-09-20 16:42:44 -040094# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
Adam Jacksone89861d2012-09-18 10:58:48 -040095# define DP_OUI_SUPPORT (1 << 7)
96
Jani Nikula94746752015-02-27 13:10:38 +020097#define DP_RECEIVE_PORT_0_CAP_0 0x008
98# define DP_LOCAL_EDID_PRESENT (1 << 1)
99# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
100
101#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
102
103#define DP_RECEIVE_PORT_1_CAP_0 0x00a
104#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
105
Adam Jacksona477f4f2012-09-20 16:42:44 -0400106#define DP_I2C_SPEED_CAP 0x00c /* DPI */
Adam Jacksone89861d2012-09-18 10:58:48 -0400107# define DP_I2C_SPEED_1K 0x01
108# define DP_I2C_SPEED_5K 0x02
109# define DP_I2C_SPEED_10K 0x04
110# define DP_I2C_SPEED_100K 0x08
111# define DP_I2C_SPEED_400K 0x10
112# define DP_I2C_SPEED_1M 0x20
Adam Jacksonde44d972012-05-14 16:05:46 -0400113
Adam Jacksona477f4f2012-09-20 16:42:44 -0400114#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
Jani Nikula94746752015-02-27 13:10:38 +0200115# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
116# define DP_FRAMING_CHANGE_CAP (1 << 1)
Sonika Jindale045d202015-02-19 13:16:44 +0530117# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
Jani Nikulabd5da992015-02-25 14:46:51 +0200118
Adam Jacksona477f4f2012-09-20 16:42:44 -0400119#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
Alex Deucher428c4b52011-05-20 04:34:25 -0400120
Jani Nikula94746752015-02-27 13:10:38 +0200121#define DP_ADAPTER_CAP 0x00f /* 1.2 */
122# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
123# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
124
Jani Nikulabd5da992015-02-25 14:46:51 +0200125#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
126# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
127
Adam Jacksone89861d2012-09-18 10:58:48 -0400128/* Multiple stream transport */
Dave Airlie3c8a0922014-05-02 11:05:21 +1000129#define DP_FAUX_CAP 0x020 /* 1.2 */
130# define DP_FAUX_CAP_1 (1 << 0)
131
Adam Jacksona477f4f2012-09-20 16:42:44 -0400132#define DP_MSTM_CAP 0x021 /* 1.2 */
Adam Jacksone89861d2012-09-18 10:58:48 -0400133# define DP_MST_CAP (1 << 0)
134
Jani Nikula94746752015-02-27 13:10:38 +0200135#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
136
137/* AV_SYNC_DATA_BLOCK 1.2 */
138#define DP_AV_GRANULARITY 0x023
139# define DP_AG_FACTOR_MASK (0xf << 0)
140# define DP_AG_FACTOR_3MS (0 << 0)
141# define DP_AG_FACTOR_2MS (1 << 0)
142# define DP_AG_FACTOR_1MS (2 << 0)
143# define DP_AG_FACTOR_500US (3 << 0)
144# define DP_AG_FACTOR_200US (4 << 0)
145# define DP_AG_FACTOR_100US (5 << 0)
146# define DP_AG_FACTOR_10US (6 << 0)
147# define DP_AG_FACTOR_1US (7 << 0)
148# define DP_VG_FACTOR_MASK (0xf << 4)
149# define DP_VG_FACTOR_3MS (0 << 4)
150# define DP_VG_FACTOR_2MS (1 << 4)
151# define DP_VG_FACTOR_1MS (2 << 4)
152# define DP_VG_FACTOR_500US (3 << 4)
153# define DP_VG_FACTOR_200US (4 << 4)
154# define DP_VG_FACTOR_100US (5 << 4)
155
156#define DP_AUD_DEC_LAT0 0x024
157#define DP_AUD_DEC_LAT1 0x025
158
159#define DP_AUD_PP_LAT0 0x026
160#define DP_AUD_PP_LAT1 0x027
161
162#define DP_VID_INTER_LAT 0x028
163
164#define DP_VID_PROG_LAT 0x029
165
166#define DP_REP_LAT 0x02a
167
168#define DP_AUD_DEL_INS0 0x02b
169#define DP_AUD_DEL_INS1 0x02c
170#define DP_AUD_DEL_INS2 0x02d
171/* End of AV_SYNC_DATA_BLOCK */
172
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200173#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
174# define DP_ALPM_CAP (1 << 0)
175
176#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
177# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
178
Dave Airlie3c8a0922014-05-02 11:05:21 +1000179#define DP_GUID 0x030 /* 1.2 */
180
Adam Jacksona477f4f2012-09-20 16:42:44 -0400181#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700182# define DP_PSR_IS_SUPPORTED 1
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200183# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
184
Adam Jacksona477f4f2012-09-20 16:42:44 -0400185#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700186# define DP_PSR_NO_TRAIN_ON_EXIT 1
187# define DP_PSR_SETUP_TIME_330 (0 << 1)
188# define DP_PSR_SETUP_TIME_275 (1 << 1)
189# define DP_PSR_SETUP_TIME_220 (2 << 1)
190# define DP_PSR_SETUP_TIME_165 (3 << 1)
191# define DP_PSR_SETUP_TIME_110 (4 << 1)
192# define DP_PSR_SETUP_TIME_55 (5 << 1)
193# define DP_PSR_SETUP_TIME_0 (6 << 1)
194# define DP_PSR_SETUP_TIME_MASK (7 << 1)
195# define DP_PSR_SETUP_TIME_SHIFT 1
196
Adam Jacksone89861d2012-09-18 10:58:48 -0400197/*
198 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
199 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
200 * each port's descriptor is one byte wide. If it was set, each port's is
201 * four bytes wide, starting with the one byte from the base info. As of
202 * DP interop v1.1a only VGA defines additional detail.
203 */
204
205/* offset 0 */
206#define DP_DOWNSTREAM_PORT_0 0x80
207# define DP_DS_PORT_TYPE_MASK (7 << 0)
208# define DP_DS_PORT_TYPE_DP 0
209# define DP_DS_PORT_TYPE_VGA 1
210# define DP_DS_PORT_TYPE_DVI 2
211# define DP_DS_PORT_TYPE_HDMI 3
212# define DP_DS_PORT_TYPE_NON_EDID 4
213# define DP_DS_PORT_HPD (1 << 3)
214/* offset 1 for VGA is maximum megapixels per second / 8 */
215/* offset 2 */
216# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
217# define DP_DS_VGA_8BPC 0
218# define DP_DS_VGA_10BPC 1
219# define DP_DS_VGA_12BPC 2
220# define DP_DS_VGA_16BPC 3
221
Alex Deucher5801ead2009-11-24 13:32:59 -0500222/* link configuration */
223#define DP_LINK_BW_SET 0x100
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200224# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700225# define DP_LINK_BW_1_62 0x06
226# define DP_LINK_BW_2_7 0x0a
Adam Jacksona477f4f2012-09-20 16:42:44 -0400227# define DP_LINK_BW_5_4 0x14 /* 1.2 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700228
Alex Deucher5801ead2009-11-24 13:32:59 -0500229#define DP_LANE_COUNT_SET 0x101
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700230# define DP_LANE_COUNT_MASK 0x0f
231# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
232
Alex Deucher5801ead2009-11-24 13:32:59 -0500233#define DP_TRAINING_PATTERN_SET 0x102
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700234# define DP_TRAINING_PATTERN_DISABLE 0
235# define DP_TRAINING_PATTERN_1 1
236# define DP_TRAINING_PATTERN_2 2
Adam Jacksona477f4f2012-09-20 16:42:44 -0400237# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700238# define DP_TRAINING_PATTERN_MASK 0x3
239
Jani Nikula94746752015-02-27 13:10:38 +0200240/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
241# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
242# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
243# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
244# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
245# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700246
247# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
248# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
249
250# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
251# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
252# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
253# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
254
255#define DP_TRAINING_LANE0_SET 0x103
256#define DP_TRAINING_LANE1_SET 0x104
257#define DP_TRAINING_LANE2_SET 0x105
258#define DP_TRAINING_LANE3_SET 0x106
259
260# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
261# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
262# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530263# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530264# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530265# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530266# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700267
268# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530269# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530270# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530271# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530272# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700273
274# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
275# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
276
277#define DP_DOWNSPREAD_CTRL 0x107
278# define DP_SPREAD_AMP_0_5 (1 << 4)
Adam Jacksona477f4f2012-09-20 16:42:44 -0400279# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700280
281#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
282# define DP_SET_ANSI_8B10B (1 << 0)
283
Adam Jacksona477f4f2012-09-20 16:42:44 -0400284#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
Adam Jacksone89861d2012-09-18 10:58:48 -0400285/* bitmask as for DP_I2C_SPEED_CAP */
286
Adam Jacksona477f4f2012-09-20 16:42:44 -0400287#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
Jani Nikula94746752015-02-27 13:10:38 +0200288# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
289# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
290# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
291
292#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
293#define DP_LINK_QUAL_LANE1_SET 0x10c
294#define DP_LINK_QUAL_LANE2_SET 0x10d
295#define DP_LINK_QUAL_LANE3_SET 0x10e
296# define DP_LINK_QUAL_PATTERN_DISABLE 0
297# define DP_LINK_QUAL_PATTERN_D10_2 1
298# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
299# define DP_LINK_QUAL_PATTERN_PRBS7 3
300# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
301# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
302# define DP_LINK_QUAL_PATTERN_MASK 7
303
304#define DP_TRAINING_LANE0_1_SET2 0x10f
305#define DP_TRAINING_LANE2_3_SET2 0x110
306# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
307# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
308# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
309# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
Adam Jacksone89861d2012-09-18 10:58:48 -0400310
Adam Jacksona477f4f2012-09-20 16:42:44 -0400311#define DP_MSTM_CTRL 0x111 /* 1.2 */
Adam Jacksone89861d2012-09-18 10:58:48 -0400312# define DP_MST_EN (1 << 0)
313# define DP_UP_REQ_EN (1 << 1)
314# define DP_UPSTREAM_IS_SRC (1 << 2)
315
Jani Nikula94746752015-02-27 13:10:38 +0200316#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
317#define DP_AUDIO_DELAY1 0x113
318#define DP_AUDIO_DELAY2 0x114
319
Jani Nikulabd5da992015-02-25 14:46:51 +0200320#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200321# define DP_LINK_RATE_SET_SHIFT 0
322# define DP_LINK_RATE_SET_MASK (7 << 0)
323
324#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
325# define DP_ALPM_ENABLE (1 << 0)
326# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
327
328#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
329# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
330# define DP_IRQ_HPD_ENABLE (1 << 1)
Sonika Jindale045d202015-02-19 13:16:44 +0530331
Jani Nikula94746752015-02-27 13:10:38 +0200332#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
333# define DP_PWR_NOT_NEEDED (1 << 0)
334
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200335#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
336# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
337
Adam Jacksona477f4f2012-09-20 16:42:44 -0400338#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700339# define DP_PSR_ENABLE (1 << 0)
340# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
341# define DP_PSR_CRC_VERIFICATION (1 << 2)
342# define DP_PSR_FRAME_CAPTURE (1 << 3)
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200343# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
344# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
Ben Widawskyb73fe582011-10-04 15:16:48 -0700345
Dave Airlie3c8a0922014-05-02 11:05:21 +1000346#define DP_ADAPTER_CTRL 0x1a0
347# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
348
349#define DP_BRANCH_DEVICE_CTRL 0x1a1
350# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
351
352#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
353#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
354#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
355
Adam Jacksone89861d2012-09-18 10:58:48 -0400356#define DP_SINK_COUNT 0x200
Adam Jacksonda131a42012-09-20 16:42:45 -0400357/* prior to 1.2 bit 7 was reserved mbz */
358# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
Adam Jacksone89861d2012-09-18 10:58:48 -0400359# define DP_SINK_CP_READY (1 << 6)
360
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700361#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
362# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
363# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
364# define DP_CP_IRQ (1 << 2)
Dave Airlie3c8a0922014-05-02 11:05:21 +1000365# define DP_MCCS_IRQ (1 << 3)
366# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
367# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700368# define DP_SINK_SPECIFIC_IRQ (1 << 6)
369
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700370#define DP_LANE0_1_STATUS 0x202
371#define DP_LANE2_3_STATUS 0x203
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700372# define DP_LANE_CR_DONE (1 << 0)
373# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
374# define DP_LANE_SYMBOL_LOCKED (1 << 2)
375
Alex Deucher5801ead2009-11-24 13:32:59 -0500376#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
377 DP_LANE_CHANNEL_EQ_DONE | \
378 DP_LANE_SYMBOL_LOCKED)
379
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700380#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
381
382#define DP_INTERLANE_ALIGN_DONE (1 << 0)
383#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
384#define DP_LINK_STATUS_UPDATED (1 << 7)
385
386#define DP_SINK_STATUS 0x205
387
388#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
389#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
390
391#define DP_ADJUST_REQUEST_LANE0_1 0x206
392#define DP_ADJUST_REQUEST_LANE2_3 0x207
Alex Deucher5801ead2009-11-24 13:32:59 -0500393# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
394# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
395# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
396# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
397# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
398# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
399# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
400# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700401
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700402#define DP_TEST_REQUEST 0x218
403# define DP_TEST_LINK_TRAINING (1 << 0)
Todd Previtefe3c7032013-10-04 12:59:03 -0700404# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700405# define DP_TEST_LINK_EDID_READ (1 << 2)
406# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
Todd Previtefe3c7032013-10-04 12:59:03 -0700407# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700408
409#define DP_TEST_LINK_RATE 0x219
410# define DP_LINK_RATE_162 (0x6)
411# define DP_LINK_RATE_27 (0xa)
412
413#define DP_TEST_LANE_COUNT 0x220
414
415#define DP_TEST_PATTERN 0x221
416
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200417#define DP_TEST_CRC_R_CR 0x240
418#define DP_TEST_CRC_G_Y 0x242
419#define DP_TEST_CRC_B_CB 0x244
420
421#define DP_TEST_SINK_MISC 0x246
Rodrigo Viviad9dc912014-09-16 19:18:12 -0400422# define DP_TEST_CRC_SUPPORTED (1 << 5)
423# define DP_TEST_COUNT_MASK 0x7
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200424
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700425#define DP_TEST_RESPONSE 0x260
426# define DP_TEST_ACK (1 << 0)
427# define DP_TEST_NAK (1 << 1)
428# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
429
Jingoo Han073ea2a2014-05-07 20:44:51 +0900430#define DP_TEST_EDID_CHECKSUM 0x261
431
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200432#define DP_TEST_SINK 0x270
Rodrigo Viviad9dc912014-09-16 19:18:12 -0400433# define DP_TEST_SINK_START (1 << 0)
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200434
Dave Airlie3c8a0922014-05-02 11:05:21 +1000435#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
436# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
437# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
438
439#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
440/* up to ID_SLOT_63 at 0x2ff */
441
Adam Jackson86c3c3b2012-05-14 16:05:45 -0400442#define DP_SOURCE_OUI 0x300
443#define DP_SINK_OUI 0x400
444#define DP_BRANCH_OUI 0x500
445
Alex Deucher1a66c952009-11-20 19:40:13 -0500446#define DP_SET_POWER 0x600
Alex Deucher5801ead2009-11-24 13:32:59 -0500447# define DP_SET_POWER_D0 0x1
448# define DP_SET_POWER_D3 0x2
Thierry Reding516c0f72013-12-09 11:47:55 +0100449# define DP_SET_POWER_MASK 0x3
Alex Deucher1a66c952009-11-20 19:40:13 -0500450
Jani Nikulabd5da992015-02-25 14:46:51 +0200451#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200452# define DP_EDP_11 0x00
453# define DP_EDP_12 0x01
454# define DP_EDP_13 0x02
455# define DP_EDP_14 0x03
Sonika Jindale045d202015-02-19 13:16:44 +0530456
Jani Nikula0e712442015-02-25 14:46:53 +0200457#define DP_EDP_GENERAL_CAP_1 0x701
458
459#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
460
461#define DP_EDP_GENERAL_CAP_2 0x703
462
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200463#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
464
Jani Nikula0e712442015-02-25 14:46:53 +0200465#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
466
467#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
468
469#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
470#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
471
472#define DP_EDP_PWMGEN_BIT_COUNT 0x724
473#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
474#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
475
476#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
477
478#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
479
480#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
481#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
482#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
483
484#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
485#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
486#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
487
488#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
489#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
490
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200491#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
492#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
493
Dave Airlie3c8a0922014-05-02 11:05:21 +1000494#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
495#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
496#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
497#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
498
499#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
500/* 0-5 sink count */
501# define DP_SINK_COUNT_CP_READY (1 << 6)
502
503#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
504
505#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
506
507#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
508
Adam Jacksona477f4f2012-09-20 16:42:44 -0400509#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700510# define DP_PSR_LINK_CRC_ERROR (1 << 0)
511# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200512# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700513
Adam Jacksona477f4f2012-09-20 16:42:44 -0400514#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700515# define DP_PSR_CAPS_CHANGE (1 << 0)
516
Adam Jacksona477f4f2012-09-20 16:42:44 -0400517#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700518# define DP_PSR_SINK_INACTIVE 0
519# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
520# define DP_PSR_SINK_ACTIVE_RFB 2
521# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
522# define DP_PSR_SINK_ACTIVE_RESYNC 4
523# define DP_PSR_SINK_INTERNAL_ERROR 7
524# define DP_PSR_SINK_STATE_MASK 0x07
525
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200526#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
527# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
528
Dave Airlie3c8a0922014-05-02 11:05:21 +1000529/* DP 1.2 Sideband message defines */
530/* peer device type - DP 1.2a Table 2-92 */
531#define DP_PEER_DEVICE_NONE 0x0
532#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
533#define DP_PEER_DEVICE_MST_BRANCHING 0x2
534#define DP_PEER_DEVICE_SST_SINK 0x3
535#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
536
537/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
538#define DP_LINK_ADDRESS 0x01
539#define DP_CONNECTION_STATUS_NOTIFY 0x02
540#define DP_ENUM_PATH_RESOURCES 0x10
541#define DP_ALLOCATE_PAYLOAD 0x11
542#define DP_QUERY_PAYLOAD 0x12
543#define DP_RESOURCE_STATUS_NOTIFY 0x13
544#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
545#define DP_REMOTE_DPCD_READ 0x20
546#define DP_REMOTE_DPCD_WRITE 0x21
547#define DP_REMOTE_I2C_READ 0x22
548#define DP_REMOTE_I2C_WRITE 0x23
549#define DP_POWER_UP_PHY 0x24
550#define DP_POWER_DOWN_PHY 0x25
551#define DP_SINK_EVENT_NOTIFY 0x30
552#define DP_QUERY_STREAM_ENC_STATUS 0x38
553
554/* DP 1.2 MST sideband nak reasons - table 2.84 */
555#define DP_NAK_WRITE_FAILURE 0x01
556#define DP_NAK_INVALID_READ 0x02
557#define DP_NAK_CRC_FAILURE 0x03
558#define DP_NAK_BAD_PARAM 0x04
559#define DP_NAK_DEFER 0x05
560#define DP_NAK_LINK_FAILURE 0x06
561#define DP_NAK_NO_RESOURCES 0x07
562#define DP_NAK_DPCD_FAIL 0x08
563#define DP_NAK_I2C_NAK 0x09
564#define DP_NAK_ALLOCATE_FAIL 0x0a
565
Dave Airlieab2c0672009-12-04 10:55:24 +1000566#define MODE_I2C_START 1
567#define MODE_I2C_WRITE 2
568#define MODE_I2C_READ 4
569#define MODE_I2C_STOP 8
570
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200571#define DP_LINK_STATUS_SIZE 6
Jani Nikula0aec2882013-09-27 19:01:01 +0300572bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200573 int lane_count);
Jani Nikula0aec2882013-09-27 19:01:01 +0300574bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter01916272012-10-18 10:15:25 +0200575 int lane_count);
Jani Nikula0aec2882013-09-27 19:01:01 +0300576u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter0f037bd2012-10-18 10:15:27 +0200577 int lane);
Jani Nikula0aec2882013-09-27 19:01:01 +0300578u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter0f037bd2012-10-18 10:15:27 +0200579 int lane);
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200580
Shobhit Kumar52604b12013-07-11 18:44:55 -0300581#define DP_RECEIVER_CAP_SIZE 0xf
582#define EDP_PSR_RECEIVER_CAP_SIZE 2
583
Jani Nikula0aec2882013-09-27 19:01:01 +0300584void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
585void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200586
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200587u8 drm_dp_link_rate_to_bw_code(int link_rate);
588int drm_dp_bw_code_to_link_rate(u8 link_bw);
589
Shobhit Kumar52604b12013-07-11 18:44:55 -0300590struct edp_sdp_header {
591 u8 HB0; /* Secondary Data Packet ID */
592 u8 HB1; /* Secondary Data Packet Type */
593 u8 HB2; /* 7:5 reserved, 4:0 revision number */
594 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
595} __packed;
596
597#define EDP_SDP_HEADER_REVISION_MASK 0x1F
598#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
599
600struct edp_vsc_psr {
601 struct edp_sdp_header sdp_header;
602 u8 DB0; /* Stereo Interface */
603 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
604 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
605 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
606 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
607 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
608 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
609 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
610 u8 DB8_31[24]; /* Reserved */
611} __packed;
612
613#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
614#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
615#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
616
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200617static inline int
Jani Nikula0aec2882013-09-27 19:01:01 +0300618drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200619{
620 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
621}
Daniel Vetter397fe152012-10-22 22:56:43 +0200622
623static inline u8
Jani Nikula0aec2882013-09-27 19:01:01 +0300624drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
Daniel Vetter397fe152012-10-22 22:56:43 +0200625{
626 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
627}
628
Jani Nikula58704e62013-10-04 15:08:08 +0300629static inline bool
630drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
631{
632 return dpcd[DP_DPCD_REV] >= 0x11 &&
633 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
634}
635
Thierry Redingc197db72013-11-28 11:31:00 +0100636/*
637 * DisplayPort AUX channel
638 */
639
640/**
641 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
642 * @address: address of the (first) register to access
643 * @request: contains the type of transaction (see DP_AUX_* macros)
644 * @reply: upon completion, contains the reply type of the transaction
645 * @buffer: pointer to a transmission or reception buffer
646 * @size: size of @buffer
647 */
648struct drm_dp_aux_msg {
649 unsigned int address;
650 u8 request;
651 u8 reply;
652 void *buffer;
653 size_t size;
654};
655
656/**
657 * struct drm_dp_aux - DisplayPort AUX channel
Thierry Redingb8380582014-04-23 15:49:04 +0200658 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
Thierry Reding88759682013-12-12 09:57:53 +0100659 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
Thierry Redingc197db72013-11-28 11:31:00 +0100660 * @dev: pointer to struct device that is the parent for this AUX channel
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000661 * @hw_mutex: internal mutex used for locking transfers
Thierry Redingc197db72013-11-28 11:31:00 +0100662 * @transfer: transfers a message representing a single AUX transaction
663 *
664 * The .dev field should be set to a pointer to the device that implements
665 * the AUX channel.
666 *
Jani Nikula9dc40562014-03-14 16:51:12 +0200667 * The .name field may be used to specify the name of the I2C adapter. If set to
668 * NULL, dev_name() of .dev will be used.
669 *
Thierry Redingc197db72013-11-28 11:31:00 +0100670 * Drivers provide a hardware-specific implementation of how transactions
671 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
672 * structure describing the transaction is passed into this function. Upon
673 * success, the implementation should return the number of payload bytes
674 * that were transferred, or a negative error-code on failure. Helpers
675 * propagate errors from the .transfer() function, with the exception of
676 * the -EBUSY error, which causes a transaction to be retried. On a short,
677 * helpers will return -EPROTO to make it simpler to check for failure.
Thierry Reding88759682013-12-12 09:57:53 +0100678 *
679 * An AUX channel can also be used to transport I2C messages to a sink. A
680 * typical application of that is to access an EDID that's present in the
681 * sink device. The .transfer() function can also be used to execute such
682 * transactions. The drm_dp_aux_register_i2c_bus() function registers an
683 * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
684 * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter.
Simon Farnsworth1d002fa2015-02-10 18:38:08 +0000685 * The I2C adapter uses long transfers by default; if a partial response is
686 * received, the adapter will drop down to the size given by the partial
687 * response for this transaction only.
Alex Deucher732d50b2014-04-07 10:33:45 -0400688 *
689 * Note that the aux helper code assumes that the .transfer() function
690 * only modifies the reply field of the drm_dp_aux_msg structure. The
691 * retry logic and i2c helpers assume this is the case.
Thierry Redingc197db72013-11-28 11:31:00 +0100692 */
693struct drm_dp_aux {
Jani Nikula9dc40562014-03-14 16:51:12 +0200694 const char *name;
Thierry Reding88759682013-12-12 09:57:53 +0100695 struct i2c_adapter ddc;
Thierry Redingc197db72013-11-28 11:31:00 +0100696 struct device *dev;
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000697 struct mutex hw_mutex;
Thierry Redingc197db72013-11-28 11:31:00 +0100698 ssize_t (*transfer)(struct drm_dp_aux *aux,
699 struct drm_dp_aux_msg *msg);
Todd Previtee9cf6192014-11-04 15:17:35 -0700700 unsigned i2c_nack_count, i2c_defer_count;
Thierry Redingc197db72013-11-28 11:31:00 +0100701};
702
703ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
704 void *buffer, size_t size);
705ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
706 void *buffer, size_t size);
707
708/**
709 * drm_dp_dpcd_readb() - read a single byte from the DPCD
710 * @aux: DisplayPort AUX channel
711 * @offset: address of the register to read
712 * @valuep: location where the value of the register will be stored
713 *
714 * Returns the number of bytes transferred (1) on success, or a negative
715 * error code on failure.
716 */
717static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
718 unsigned int offset, u8 *valuep)
719{
720 return drm_dp_dpcd_read(aux, offset, valuep, 1);
721}
722
723/**
724 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
725 * @aux: DisplayPort AUX channel
726 * @offset: address of the register to write
727 * @value: value to write to the register
728 *
729 * Returns the number of bytes transferred (1) on success, or a negative
730 * error code on failure.
731 */
732static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
733 unsigned int offset, u8 value)
734{
735 return drm_dp_dpcd_write(aux, offset, &value, 1);
736}
737
Thierry Reding8d4adc62013-11-22 16:37:57 +0100738int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
739 u8 status[DP_LINK_STATUS_SIZE]);
740
Thierry Reding516c0f72013-12-09 11:47:55 +0100741/*
742 * DisplayPort link
743 */
744#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
745
746struct drm_dp_link {
747 unsigned char revision;
748 unsigned int rate;
749 unsigned int num_lanes;
750 unsigned long capabilities;
751};
752
753int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
754int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
Rob Clarkd816f072014-12-02 10:43:07 -0500755int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
Thierry Reding516c0f72013-12-09 11:47:55 +0100756int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
757
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000758int drm_dp_aux_register(struct drm_dp_aux *aux);
759void drm_dp_aux_unregister(struct drm_dp_aux *aux);
Thierry Reding88759682013-12-12 09:57:53 +0100760
Dave Airlieab2c0672009-12-04 10:55:24 +1000761#endif /* _DRM_DP_HELPER_H_ */