Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / b0a3eae2b943ef62cb8265aa604c78bb6565a2cd / . / arch / mips / include / uapi / asm / inst.h
blob: 044123bfab907746ccc11783987255aecc67c20d [file] [log] [blame]
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]1/*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]11 * Copyright (C) 2014 Imagination Technologies Ltd.
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]12 */
13#ifndef _UAPI_ASM_INST_H
14#define _UAPI_ASM_INST_H
15
16/*
17 * Major opcodes; before MIPS IV cop1x was called cop3.
18 */
19enum major_op {
20 spec_op, bcond_op, j_op, jal_op,
21 beq_op, bne_op, blez_op, bgtz_op,
22 addi_op, addiu_op, slti_op, sltiu_op,
23 andi_op, ori_op, xori_op, lui_op,
24 cop0_op, cop1_op, cop2_op, cop1x_op,
25 beql_op, bnel_op, blezl_op, bgtzl_op,
26 daddi_op, daddiu_op, ldl_op, ldr_op,
27 spec2_op, jalx_op, mdmx_op, spec3_op,
28 lb_op, lh_op, lwl_op, lw_op,
29 lbu_op, lhu_op, lwr_op, lwu_op,
30 sb_op, sh_op, swl_op, sw_op,
31 sdl_op, sdr_op, swr_op, cache_op,
32 ll_op, lwc1_op, lwc2_op, pref_op,
33 lld_op, ldc1_op, ldc2_op, ld_op,
34 sc_op, swc1_op, swc2_op, major_3b_op,
35 scd_op, sdc1_op, sdc2_op, sd_op
36};
37
38/*
39 * func field of spec opcode.
40 */
41enum spec_op {
42 sll_op, movc_op, srl_op, sra_op,
43 sllv_op, pmon_op, srlv_op, srav_op,
44 jr_op, jalr_op, movz_op, movn_op,
45 syscall_op, break_op, spim_op, sync_op,
46 mfhi_op, mthi_op, mflo_op, mtlo_op,
47 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
48 mult_op, multu_op, div_op, divu_op,
49 dmult_op, dmultu_op, ddiv_op, ddivu_op,
50 add_op, addu_op, sub_op, subu_op,
51 and_op, or_op, xor_op, nor_op,
52 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
53 dadd_op, daddu_op, dsub_op, dsubu_op,
54 tge_op, tgeu_op, tlt_op, tltu_op,
55 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
56 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
57 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
58};
59
60/*
61 * func field of spec2 opcode.
62 */
63enum spec2_op {
64 madd_op, maddu_op, mul_op, spec2_3_unused_op,
65 msub_op, msubu_op, /* more unused ops */
66 clz_op = 0x20, clo_op,
67 dclz_op = 0x24, dclo_op,
68 sdbpp_op = 0x3f
69};
70
71/*
72 * func field of spec3 opcode.
73 */
74enum spec3_op {
75 ext_op, dextm_op, dextu_op, dext_op,
76 ins_op, dinsm_op, dinsu_op, dins_op,
Leonid Yegoshina442c9e2013-12-04 11:00:27 +0000[diff] [blame]77 lx_op = 0x0a, lwle_op = 0x19,
78 lwre_op = 0x1a, cachee_op = 0x1b,
79 sbe_op = 0x1c, she_op = 0x1d,
80 sce_op = 0x1e, swe_op = 0x1f,
81 bshfl_op = 0x20, swle_op = 0x21,
82 swre_op = 0x22, prefe_op = 0x23,
83 dbshfl_op = 0x24, lbue_op = 0x28,
84 lhue_op = 0x29, lbe_op = 0x2c,
85 lhe_op = 0x2d, lle_op = 0x2e,
86 lwe_op = 0x2f, rdhwr_op = 0x3b
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]87};
88
89/*
90 * rt field of bcond opcodes.
91 */
92enum rt_op {
93 bltz_op, bgez_op, bltzl_op, bgezl_op,
94 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
95 tgei_op, tgeiu_op, tlti_op, tltiu_op,
96 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
97 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
98 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
99 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
100 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
101};
102
103/*
104 * rs field of cop opcodes.
105 */
106enum cop_op {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]107 mfc_op = 0x00, dmfc_op = 0x01,
Leonid Yegoshin1ac944002013-11-07 12:48:28 +0000[diff] [blame]108 cfc_op = 0x02, mfhc_op = 0x03,
109 mtc_op = 0x04, dmtc_op = 0x05,
110 ctc_op = 0x06, mthc_op = 0x07,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]111 bc_op = 0x08, cop_op = 0x10,
112 copm_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]113};
114
115/*
116 * rt field of cop.bc_op opcodes
117 */
118enum bcop_op {
119 bcf_op, bct_op, bcfl_op, bctl_op
120};
121
122/*
123 * func field of cop0 coi opcodes.
124 */
125enum cop0_coi_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]126 tlbr_op = 0x01, tlbwi_op = 0x02,
127 tlbwr_op = 0x06, tlbp_op = 0x08,
Paul Burtonb0a3eae2013-12-24 03:44:28 +0000[diff] [blame^]128 rfe_op = 0x10, eret_op = 0x18,
129 wait_op = 0x20,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]130};
131
132/*
133 * func field of cop0 com opcodes.
134 */
135enum cop0_com_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]136 tlbr1_op = 0x01, tlbw_op = 0x02,
137 tlbp1_op = 0x08, dctr_op = 0x09,
138 dctw_op = 0x0a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]139};
140
141/*
142 * fmt field of cop1 opcodes.
143 */
144enum cop1_fmt {
145 s_fmt, d_fmt, e_fmt, q_fmt,
146 w_fmt, l_fmt
147};
148
149/*
150 * func field of cop1 instructions using d, s or w format.
151 */
152enum cop1_sdw_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]153 fadd_op = 0x00, fsub_op = 0x01,
154 fmul_op = 0x02, fdiv_op = 0x03,
155 fsqrt_op = 0x04, fabs_op = 0x05,
156 fmov_op = 0x06, fneg_op = 0x07,
157 froundl_op = 0x08, ftruncl_op = 0x09,
158 fceill_op = 0x0a, ffloorl_op = 0x0b,
159 fround_op = 0x0c, ftrunc_op = 0x0d,
160 fceil_op = 0x0e, ffloor_op = 0x0f,
161 fmovc_op = 0x11, fmovz_op = 0x12,
162 fmovn_op = 0x13, frecip_op = 0x15,
163 frsqrt_op = 0x16, fcvts_op = 0x20,
164 fcvtd_op = 0x21, fcvte_op = 0x22,
165 fcvtw_op = 0x24, fcvtl_op = 0x25,
166 fcmp_op = 0x30
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]167};
168
169/*
170 * func field of cop1x opcodes (MIPS IV).
171 */
172enum cop1x_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]173 lwxc1_op = 0x00, ldxc1_op = 0x01,
Deng-Cheng Zhu51061b82014-03-06 17:05:27 -0800[diff] [blame]174 swxc1_op = 0x08, sdxc1_op = 0x09,
175 pfetch_op = 0x0f, madd_s_op = 0x20,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]176 madd_d_op = 0x21, madd_e_op = 0x22,
177 msub_s_op = 0x28, msub_d_op = 0x29,
178 msub_e_op = 0x2a, nmadd_s_op = 0x30,
179 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
180 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
181 nmsub_e_op = 0x3a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]182};
183
184/*
185 * func field for mad opcodes (MIPS IV).
186 */
187enum mad_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]188 madd_fp_op = 0x08, msub_fp_op = 0x0a,
189 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]190};
191
192/*
193 * func field for special3 lx opcodes (Cavium Octeon).
194 */
195enum lx_func {
196 lwx_op = 0x00,
197 lhx_op = 0x04,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]198 lbux_op = 0x06,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]199 ldx_op = 0x08,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]200 lwux_op = 0x10,
201 lhux_op = 0x14,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]202 lbx_op = 0x16,
203};
204
205/*
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]206 * (microMIPS) Major opcodes.
207 */
208enum mm_major_op {
209 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
210 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
211 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
212 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
213 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
214 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
215 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
216 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
217 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
218 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
219 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
220 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
221 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
222 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
223 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
224 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
225};
226
227/*
228 * (microMIPS) POOL32I minor opcodes.
229 */
230enum mm_32i_minor_op {
231 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
232 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
233 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
234 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
235 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
236 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
237 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
238 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
239 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
240};
241
242/*
243 * (microMIPS) POOL32A minor opcodes.
244 */
245enum mm_32a_minor_op {
246 mm_sll32_op = 0x000,
247 mm_ins_op = 0x00c,
248 mm_ext_op = 0x02c,
249 mm_pool32axf_op = 0x03c,
250 mm_srl32_op = 0x040,
251 mm_sra_op = 0x080,
252 mm_rotr_op = 0x0c0,
253 mm_lwxs_op = 0x118,
254 mm_addu32_op = 0x150,
255 mm_subu32_op = 0x1d0,
256 mm_and_op = 0x250,
257 mm_or32_op = 0x290,
258 mm_xor32_op = 0x310,
259};
260
261/*
262 * (microMIPS) POOL32B functions.
263 */
264enum mm_32b_func {
265 mm_lwc2_func = 0x0,
266 mm_lwp_func = 0x1,
267 mm_ldc2_func = 0x2,
268 mm_ldp_func = 0x4,
269 mm_lwm32_func = 0x5,
270 mm_cache_func = 0x6,
271 mm_ldm_func = 0x7,
272 mm_swc2_func = 0x8,
273 mm_swp_func = 0x9,
274 mm_sdc2_func = 0xa,
275 mm_sdp_func = 0xc,
276 mm_swm32_func = 0xd,
277 mm_sdm_func = 0xf,
278};
279
280/*
281 * (microMIPS) POOL32C functions.
282 */
283enum mm_32c_func {
284 mm_pref_func = 0x2,
285 mm_ll_func = 0x3,
286 mm_swr_func = 0x9,
287 mm_sc_func = 0xb,
288 mm_lwu_func = 0xe,
289};
290
291/*
292 * (microMIPS) POOL32AXF minor opcodes.
293 */
294enum mm_32axf_minor_op {
295 mm_mfc0_op = 0x003,
296 mm_mtc0_op = 0x00b,
297 mm_tlbp_op = 0x00d,
298 mm_jalr_op = 0x03c,
299 mm_tlbr_op = 0x04d,
300 mm_jalrhb_op = 0x07c,
301 mm_tlbwi_op = 0x08d,
302 mm_tlbwr_op = 0x0cd,
303 mm_jalrs_op = 0x13c,
304 mm_jalrshb_op = 0x17c,
305 mm_syscall_op = 0x22d,
306 mm_eret_op = 0x3cd,
307};
308
309/*
310 * (microMIPS) POOL32F minor opcodes.
311 */
312enum mm_32f_minor_op {
313 mm_32f_00_op = 0x00,
314 mm_32f_01_op = 0x01,
315 mm_32f_02_op = 0x02,
316 mm_32f_10_op = 0x08,
317 mm_32f_11_op = 0x09,
318 mm_32f_12_op = 0x0a,
319 mm_32f_20_op = 0x10,
320 mm_32f_30_op = 0x18,
321 mm_32f_40_op = 0x20,
322 mm_32f_41_op = 0x21,
323 mm_32f_42_op = 0x22,
324 mm_32f_50_op = 0x28,
325 mm_32f_51_op = 0x29,
326 mm_32f_52_op = 0x2a,
327 mm_32f_60_op = 0x30,
328 mm_32f_70_op = 0x38,
329 mm_32f_73_op = 0x3b,
330 mm_32f_74_op = 0x3c,
331};
332
333/*
334 * (microMIPS) POOL32F secondary minor opcodes.
335 */
336enum mm_32f_10_minor_op {
337 mm_lwxc1_op = 0x1,
338 mm_swxc1_op,
339 mm_ldxc1_op,
340 mm_sdxc1_op,
341 mm_luxc1_op,
342 mm_suxc1_op,
343};
344
345enum mm_32f_func {
346 mm_lwxc1_func = 0x048,
347 mm_swxc1_func = 0x088,
348 mm_ldxc1_func = 0x0c8,
349 mm_sdxc1_func = 0x108,
350};
351
352/*
353 * (microMIPS) POOL32F secondary minor opcodes.
354 */
355enum mm_32f_40_minor_op {
356 mm_fmovf_op,
357 mm_fmovt_op,
358};
359
360/*
361 * (microMIPS) POOL32F secondary minor opcodes.
362 */
363enum mm_32f_60_minor_op {
364 mm_fadd_op,
365 mm_fsub_op,
366 mm_fmul_op,
367 mm_fdiv_op,
368};
369
370/*
371 * (microMIPS) POOL32F secondary minor opcodes.
372 */
373enum mm_32f_70_minor_op {
374 mm_fmovn_op,
375 mm_fmovz_op,
376};
377
378/*
379 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
380 */
381enum mm_32f_73_minor_op {
382 mm_fmov0_op = 0x01,
383 mm_fcvtl_op = 0x04,
384 mm_movf0_op = 0x05,
385 mm_frsqrt_op = 0x08,
386 mm_ffloorl_op = 0x0c,
387 mm_fabs0_op = 0x0d,
388 mm_fcvtw_op = 0x24,
389 mm_movt0_op = 0x25,
390 mm_fsqrt_op = 0x28,
391 mm_ffloorw_op = 0x2c,
392 mm_fneg0_op = 0x2d,
393 mm_cfc1_op = 0x40,
394 mm_frecip_op = 0x48,
395 mm_fceill_op = 0x4c,
396 mm_fcvtd0_op = 0x4d,
397 mm_ctc1_op = 0x60,
398 mm_fceilw_op = 0x6c,
399 mm_fcvts0_op = 0x6d,
400 mm_mfc1_op = 0x80,
401 mm_fmov1_op = 0x81,
402 mm_movf1_op = 0x85,
403 mm_ftruncl_op = 0x8c,
404 mm_fabs1_op = 0x8d,
405 mm_mtc1_op = 0xa0,
406 mm_movt1_op = 0xa5,
407 mm_ftruncw_op = 0xac,
408 mm_fneg1_op = 0xad,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame]409 mm_mfhc1_op = 0xc0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]410 mm_froundl_op = 0xcc,
411 mm_fcvtd1_op = 0xcd,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame]412 mm_mthc1_op = 0xe0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]413 mm_froundw_op = 0xec,
414 mm_fcvts1_op = 0xed,
415};
416
417/*
418 * (microMIPS) POOL16C minor opcodes.
419 */
420enum mm_16c_minor_op {
421 mm_lwm16_op = 0x04,
422 mm_swm16_op = 0x05,
Tony Wudfb033f2013-06-20 12:32:30 +0000[diff] [blame]423 mm_jr16_op = 0x0c,
424 mm_jrc_op = 0x0d,
425 mm_jalr16_op = 0x0e,
426 mm_jalrs16_op = 0x0f,
427 mm_jraddiusp_op = 0x18,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]428};
429
430/*
431 * (microMIPS) POOL16D minor opcodes.
432 */
433enum mm_16d_minor_op {
434 mm_addius5_func,
435 mm_addiusp_func,
436};
437
438/*
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]439 * (MIPS16e) opcodes.
440 */
441enum MIPS16e_ops {
442 MIPS16e_jal_op = 003,
443 MIPS16e_ld_op = 007,
444 MIPS16e_i8_op = 014,
445 MIPS16e_sd_op = 017,
446 MIPS16e_lb_op = 020,
447 MIPS16e_lh_op = 021,
448 MIPS16e_lwsp_op = 022,
449 MIPS16e_lw_op = 023,
450 MIPS16e_lbu_op = 024,
451 MIPS16e_lhu_op = 025,
452 MIPS16e_lwpc_op = 026,
453 MIPS16e_lwu_op = 027,
454 MIPS16e_sb_op = 030,
455 MIPS16e_sh_op = 031,
456 MIPS16e_swsp_op = 032,
457 MIPS16e_sw_op = 033,
458 MIPS16e_rr_op = 035,
459 MIPS16e_extend_op = 036,
460 MIPS16e_i64_op = 037,
461};
462
463enum MIPS16e_i64_func {
464 MIPS16e_ldsp_func,
465 MIPS16e_sdsp_func,
466 MIPS16e_sdrasp_func,
467 MIPS16e_dadjsp_func,
468 MIPS16e_ldpc_func,
469};
470
471enum MIPS16e_rr_func {
472 MIPS16e_jr_func,
473};
474
475enum MIPS6e_i8_func {
476 MIPS16e_swrasp_func = 02,
477};
478
479/*
Leonid Yegoshin102cedc2013-03-25 12:09:02 -0500[diff] [blame]480 * (microMIPS & MIPS16e) NOP instruction.
481 */
482#define MM_NOP16 0x0c00
483
484/*
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]485 * Damn ... bitfields depend from byteorder :-(
486 */
487#ifdef __MIPSEB__
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]488#define BITFIELD_FIELD(field, more) \
489 field; \
490 more
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]491
492#elif defined(__MIPSEL__)
493
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]494#define BITFIELD_FIELD(field, more) \
495 more \
496 field;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]497
498#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
499#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
500#endif
501
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]502struct j_format {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]503 BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]504 BITFIELD_FIELD(unsigned int target : 26,
505 ;))
506};
507
508struct i_format { /* signed immediate format */
509 BITFIELD_FIELD(unsigned int opcode : 6,
510 BITFIELD_FIELD(unsigned int rs : 5,
511 BITFIELD_FIELD(unsigned int rt : 5,
512 BITFIELD_FIELD(signed int simmediate : 16,
513 ;))))
514};
515
516struct u_format { /* unsigned immediate format */
517 BITFIELD_FIELD(unsigned int opcode : 6,
518 BITFIELD_FIELD(unsigned int rs : 5,
519 BITFIELD_FIELD(unsigned int rt : 5,
520 BITFIELD_FIELD(unsigned int uimmediate : 16,
521 ;))))
522};
523
524struct c_format { /* Cache (>= R6000) format */
525 BITFIELD_FIELD(unsigned int opcode : 6,
526 BITFIELD_FIELD(unsigned int rs : 5,
527 BITFIELD_FIELD(unsigned int c_op : 3,
528 BITFIELD_FIELD(unsigned int cache : 2,
529 BITFIELD_FIELD(unsigned int simmediate : 16,
530 ;)))))
531};
532
533struct r_format { /* Register format */
534 BITFIELD_FIELD(unsigned int opcode : 6,
535 BITFIELD_FIELD(unsigned int rs : 5,
536 BITFIELD_FIELD(unsigned int rt : 5,
537 BITFIELD_FIELD(unsigned int rd : 5,
538 BITFIELD_FIELD(unsigned int re : 5,
539 BITFIELD_FIELD(unsigned int func : 6,
540 ;))))))
541};
542
543struct p_format { /* Performance counter format (R10000) */
544 BITFIELD_FIELD(unsigned int opcode : 6,
545 BITFIELD_FIELD(unsigned int rs : 5,
546 BITFIELD_FIELD(unsigned int rt : 5,
547 BITFIELD_FIELD(unsigned int rd : 5,
548 BITFIELD_FIELD(unsigned int re : 5,
549 BITFIELD_FIELD(unsigned int func : 6,
550 ;))))))
551};
552
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]553struct f_format { /* FPU register format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]554 BITFIELD_FIELD(unsigned int opcode : 6,
555 BITFIELD_FIELD(unsigned int : 1,
556 BITFIELD_FIELD(unsigned int fmt : 4,
557 BITFIELD_FIELD(unsigned int rt : 5,
558 BITFIELD_FIELD(unsigned int rd : 5,
559 BITFIELD_FIELD(unsigned int re : 5,
560 BITFIELD_FIELD(unsigned int func : 6,
561 ;)))))))
562};
563
564struct ma_format { /* FPU multiply and add format (MIPS IV) */
565 BITFIELD_FIELD(unsigned int opcode : 6,
566 BITFIELD_FIELD(unsigned int fr : 5,
567 BITFIELD_FIELD(unsigned int ft : 5,
568 BITFIELD_FIELD(unsigned int fs : 5,
569 BITFIELD_FIELD(unsigned int fd : 5,
570 BITFIELD_FIELD(unsigned int func : 4,
571 BITFIELD_FIELD(unsigned int fmt : 2,
572 ;)))))))
573};
574
575struct b_format { /* BREAK and SYSCALL */
576 BITFIELD_FIELD(unsigned int opcode : 6,
577 BITFIELD_FIELD(unsigned int code : 20,
578 BITFIELD_FIELD(unsigned int func : 6,
579 ;)))
580};
581
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]582struct ps_format { /* MIPS-3D / paired single format */
583 BITFIELD_FIELD(unsigned int opcode : 6,
584 BITFIELD_FIELD(unsigned int rs : 5,
585 BITFIELD_FIELD(unsigned int ft : 5,
586 BITFIELD_FIELD(unsigned int fs : 5,
587 BITFIELD_FIELD(unsigned int fd : 5,
588 BITFIELD_FIELD(unsigned int func : 6,
589 ;))))))
590};
591
592struct v_format { /* MDMX vector format */
593 BITFIELD_FIELD(unsigned int opcode : 6,
594 BITFIELD_FIELD(unsigned int sel : 4,
595 BITFIELD_FIELD(unsigned int fmt : 1,
596 BITFIELD_FIELD(unsigned int vt : 5,
597 BITFIELD_FIELD(unsigned int vs : 5,
598 BITFIELD_FIELD(unsigned int vd : 5,
599 BITFIELD_FIELD(unsigned int func : 6,
600 ;)))))))
601};
602
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]603struct spec3_format { /* SPEC3 */
604 BITFIELD_FIELD(unsigned int opcode:6,
605 BITFIELD_FIELD(unsigned int rs:5,
606 BITFIELD_FIELD(unsigned int rt:5,
607 BITFIELD_FIELD(signed int simmediate:9,
608 BITFIELD_FIELD(unsigned int func:7,
609 ;)))))
610};
611
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]612/*
613 * microMIPS instruction formats (32-bit length)
614 *
615 * NOTE:
616 * Parenthesis denote whether the format is a microMIPS instruction or
617 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
618 */
619struct fb_format { /* FPU branch format (MIPS32) */
620 BITFIELD_FIELD(unsigned int opcode : 6,
621 BITFIELD_FIELD(unsigned int bc : 5,
622 BITFIELD_FIELD(unsigned int cc : 3,
623 BITFIELD_FIELD(unsigned int flag : 2,
624 BITFIELD_FIELD(signed int simmediate : 16,
625 ;)))))
626};
627
628struct fp0_format { /* FPU multiply and add format (MIPS32) */
629 BITFIELD_FIELD(unsigned int opcode : 6,
630 BITFIELD_FIELD(unsigned int fmt : 5,
631 BITFIELD_FIELD(unsigned int ft : 5,
632 BITFIELD_FIELD(unsigned int fs : 5,
633 BITFIELD_FIELD(unsigned int fd : 5,
634 BITFIELD_FIELD(unsigned int func : 6,
635 ;))))))
636};
637
638struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
639 BITFIELD_FIELD(unsigned int opcode : 6,
640 BITFIELD_FIELD(unsigned int ft : 5,
641 BITFIELD_FIELD(unsigned int fs : 5,
642 BITFIELD_FIELD(unsigned int fd : 5,
643 BITFIELD_FIELD(unsigned int fmt : 3,
644 BITFIELD_FIELD(unsigned int op : 2,
645 BITFIELD_FIELD(unsigned int func : 6,
646 ;)))))))
647};
648
649struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
650 BITFIELD_FIELD(unsigned int opcode : 6,
651 BITFIELD_FIELD(unsigned int op : 5,
652 BITFIELD_FIELD(unsigned int rt : 5,
653 BITFIELD_FIELD(unsigned int fs : 5,
654 BITFIELD_FIELD(unsigned int fd : 5,
655 BITFIELD_FIELD(unsigned int func : 6,
656 ;))))))
657};
658
659struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
660 BITFIELD_FIELD(unsigned int opcode : 6,
661 BITFIELD_FIELD(unsigned int rt : 5,
662 BITFIELD_FIELD(unsigned int fs : 5,
663 BITFIELD_FIELD(unsigned int fmt : 2,
664 BITFIELD_FIELD(unsigned int op : 8,
665 BITFIELD_FIELD(unsigned int func : 6,
666 ;))))))
667};
668
669struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
670 BITFIELD_FIELD(unsigned int opcode : 6,
671 BITFIELD_FIELD(unsigned int fd : 5,
672 BITFIELD_FIELD(unsigned int fs : 5,
673 BITFIELD_FIELD(unsigned int cc : 3,
674 BITFIELD_FIELD(unsigned int zero : 2,
675 BITFIELD_FIELD(unsigned int fmt : 2,
676 BITFIELD_FIELD(unsigned int op : 3,
677 BITFIELD_FIELD(unsigned int func : 6,
678 ;))))))))
679};
680
681struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
682 BITFIELD_FIELD(unsigned int opcode : 6,
683 BITFIELD_FIELD(unsigned int rt : 5,
684 BITFIELD_FIELD(unsigned int fs : 5,
685 BITFIELD_FIELD(unsigned int fmt : 3,
686 BITFIELD_FIELD(unsigned int op : 7,
687 BITFIELD_FIELD(unsigned int func : 6,
688 ;))))))
689};
690
691struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
692 BITFIELD_FIELD(unsigned int opcode : 6,
693 BITFIELD_FIELD(unsigned int rt : 5,
694 BITFIELD_FIELD(unsigned int fs : 5,
695 BITFIELD_FIELD(unsigned int cc : 3,
696 BITFIELD_FIELD(unsigned int fmt : 3,
697 BITFIELD_FIELD(unsigned int cond : 4,
698 BITFIELD_FIELD(unsigned int func : 6,
699 ;)))))))
700};
701
702struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
703 BITFIELD_FIELD(unsigned int opcode : 6,
704 BITFIELD_FIELD(unsigned int index : 5,
705 BITFIELD_FIELD(unsigned int base : 5,
706 BITFIELD_FIELD(unsigned int fd : 5,
707 BITFIELD_FIELD(unsigned int op : 5,
708 BITFIELD_FIELD(unsigned int func : 6,
709 ;))))))
710};
711
712struct fp6_format { /* FPU madd and msub format (MIPS IV) */
713 BITFIELD_FIELD(unsigned int opcode : 6,
714 BITFIELD_FIELD(unsigned int fr : 5,
715 BITFIELD_FIELD(unsigned int ft : 5,
716 BITFIELD_FIELD(unsigned int fs : 5,
717 BITFIELD_FIELD(unsigned int fd : 5,
718 BITFIELD_FIELD(unsigned int func : 6,
719 ;))))))
720};
721
722struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
723 BITFIELD_FIELD(unsigned int opcode : 6,
724 BITFIELD_FIELD(unsigned int ft : 5,
725 BITFIELD_FIELD(unsigned int fs : 5,
726 BITFIELD_FIELD(unsigned int fd : 5,
727 BITFIELD_FIELD(unsigned int fr : 5,
728 BITFIELD_FIELD(unsigned int func : 6,
729 ;))))))
730};
731
732struct mm_i_format { /* Immediate format (microMIPS) */
733 BITFIELD_FIELD(unsigned int opcode : 6,
734 BITFIELD_FIELD(unsigned int rt : 5,
735 BITFIELD_FIELD(unsigned int rs : 5,
736 BITFIELD_FIELD(signed int simmediate : 16,
737 ;))))
738};
739
740struct mm_m_format { /* Multi-word load/store format (microMIPS) */
741 BITFIELD_FIELD(unsigned int opcode : 6,
742 BITFIELD_FIELD(unsigned int rd : 5,
743 BITFIELD_FIELD(unsigned int base : 5,
744 BITFIELD_FIELD(unsigned int func : 4,
745 BITFIELD_FIELD(signed int simmediate : 12,
746 ;)))))
747};
748
749struct mm_x_format { /* Scaled indexed load format (microMIPS) */
750 BITFIELD_FIELD(unsigned int opcode : 6,
751 BITFIELD_FIELD(unsigned int index : 5,
752 BITFIELD_FIELD(unsigned int base : 5,
753 BITFIELD_FIELD(unsigned int rd : 5,
754 BITFIELD_FIELD(unsigned int func : 11,
755 ;)))))
756};
757
758/*
759 * microMIPS instruction formats (16-bit length)
760 */
761struct mm_b0_format { /* Unconditional branch format (microMIPS) */
762 BITFIELD_FIELD(unsigned int opcode : 6,
763 BITFIELD_FIELD(signed int simmediate : 10,
764 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
765 ;)))
766};
767
768struct mm_b1_format { /* Conditional branch format (microMIPS) */
769 BITFIELD_FIELD(unsigned int opcode : 6,
770 BITFIELD_FIELD(unsigned int rs : 3,
771 BITFIELD_FIELD(signed int simmediate : 7,
772 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
773 ;))))
774};
775
776struct mm16_m_format { /* Multi-word load/store format */
777 BITFIELD_FIELD(unsigned int opcode : 6,
778 BITFIELD_FIELD(unsigned int func : 4,
779 BITFIELD_FIELD(unsigned int rlist : 2,
780 BITFIELD_FIELD(unsigned int imm : 4,
781 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
782 ;)))))
783};
784
785struct mm16_rb_format { /* Signed immediate format */
786 BITFIELD_FIELD(unsigned int opcode : 6,
787 BITFIELD_FIELD(unsigned int rt : 3,
788 BITFIELD_FIELD(unsigned int base : 3,
789 BITFIELD_FIELD(signed int simmediate : 4,
790 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
791 ;)))))
792};
793
794struct mm16_r3_format { /* Load from global pointer format */
795 BITFIELD_FIELD(unsigned int opcode : 6,
796 BITFIELD_FIELD(unsigned int rt : 3,
797 BITFIELD_FIELD(signed int simmediate : 7,
798 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
799 ;))))
800};
801
802struct mm16_r5_format { /* Load/store from stack pointer format */
803 BITFIELD_FIELD(unsigned int opcode : 6,
804 BITFIELD_FIELD(unsigned int rt : 5,
805 BITFIELD_FIELD(signed int simmediate : 5,
806 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
807 ;))))
808};
809
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]810/*
811 * MIPS16e instruction formats (16-bit length)
812 */
813struct m16e_rr {
814 BITFIELD_FIELD(unsigned int opcode : 5,
815 BITFIELD_FIELD(unsigned int rx : 3,
816 BITFIELD_FIELD(unsigned int nd : 1,
817 BITFIELD_FIELD(unsigned int l : 1,
818 BITFIELD_FIELD(unsigned int ra : 1,
819 BITFIELD_FIELD(unsigned int func : 5,
820 ;))))))
821};
822
823struct m16e_jal {
824 BITFIELD_FIELD(unsigned int opcode : 5,
825 BITFIELD_FIELD(unsigned int x : 1,
826 BITFIELD_FIELD(unsigned int imm20_16 : 5,
827 BITFIELD_FIELD(signed int imm25_21 : 5,
828 ;))))
829};
830
831struct m16e_i64 {
832 BITFIELD_FIELD(unsigned int opcode : 5,
833 BITFIELD_FIELD(unsigned int func : 3,
834 BITFIELD_FIELD(unsigned int imm : 8,
835 ;)))
836};
837
838struct m16e_ri64 {
839 BITFIELD_FIELD(unsigned int opcode : 5,
840 BITFIELD_FIELD(unsigned int func : 3,
841 BITFIELD_FIELD(unsigned int ry : 3,
842 BITFIELD_FIELD(unsigned int imm : 5,
843 ;))))
844};
845
846struct m16e_ri {
847 BITFIELD_FIELD(unsigned int opcode : 5,
848 BITFIELD_FIELD(unsigned int rx : 3,
849 BITFIELD_FIELD(unsigned int imm : 8,
850 ;)))
851};
852
853struct m16e_rri {
854 BITFIELD_FIELD(unsigned int opcode : 5,
855 BITFIELD_FIELD(unsigned int rx : 3,
856 BITFIELD_FIELD(unsigned int ry : 3,
857 BITFIELD_FIELD(unsigned int imm : 5,
858 ;))))
859};
860
861struct m16e_i8 {
862 BITFIELD_FIELD(unsigned int opcode : 5,
863 BITFIELD_FIELD(unsigned int func : 3,
864 BITFIELD_FIELD(unsigned int imm : 8,
865 ;)))
866};
867
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]868union mips_instruction {
869 unsigned int word;
870 unsigned short halfword[2];
871 unsigned char byte[4];
872 struct j_format j_format;
873 struct i_format i_format;
874 struct u_format u_format;
875 struct c_format c_format;
876 struct r_format r_format;
877 struct p_format p_format;
878 struct f_format f_format;
879 struct ma_format ma_format;
880 struct b_format b_format;
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]881 struct ps_format ps_format;
882 struct v_format v_format;
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]883 struct spec3_format spec3_format;
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]884 struct fb_format fb_format;
885 struct fp0_format fp0_format;
886 struct mm_fp0_format mm_fp0_format;
887 struct fp1_format fp1_format;
888 struct mm_fp1_format mm_fp1_format;
889 struct mm_fp2_format mm_fp2_format;
890 struct mm_fp3_format mm_fp3_format;
891 struct mm_fp4_format mm_fp4_format;
892 struct mm_fp5_format mm_fp5_format;
893 struct fp6_format fp6_format;
894 struct mm_fp6_format mm_fp6_format;
895 struct mm_i_format mm_i_format;
896 struct mm_m_format mm_m_format;
897 struct mm_x_format mm_x_format;
898 struct mm_b0_format mm_b0_format;
899 struct mm_b1_format mm_b1_format;
900 struct mm16_m_format mm16_m_format ;
901 struct mm16_rb_format mm16_rb_format;
902 struct mm16_r3_format mm16_r3_format;
903 struct mm16_r5_format mm16_r5_format;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]904};
905
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]906union mips16e_instruction {
907 unsigned int full : 16;
908 struct m16e_rr rr;
909 struct m16e_jal jal;
910 struct m16e_i64 i64;
911 struct m16e_ri64 ri64;
912 struct m16e_ri ri;
913 struct m16e_rri rri;
914 struct m16e_i8 i8;
915};
916
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]917#endif /* _UAPI_ASM_INST_H */