blob: e44d675a30eca1714f1b8b6a18e1503c5cc322ee [file] [log] [blame]
Olliver Schinaglc5754b52014-02-22 16:53:36 +01001/*
2 * Allwinner sunxi AHCI SATA platform driver
3 * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
4 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
5 *
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
7 * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
8 * Daniel Wang <danielwang@allwinnertech.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 */
19
20#include <linux/ahci_platform.h>
21#include <linux/clk.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/consumer.h>
28#include "ahci.h"
29
Bartlomiej Zolnierkiewiczcdf457a2014-03-17 14:08:12 +010030#define AHCI_BISTAFR 0x00a0
31#define AHCI_BISTCR 0x00a4
32#define AHCI_BISTFCTR 0x00a8
33#define AHCI_BISTSR 0x00ac
34#define AHCI_BISTDECR 0x00b0
35#define AHCI_DIAGNR0 0x00b4
36#define AHCI_DIAGNR1 0x00b8
37#define AHCI_OOBR 0x00bc
38#define AHCI_PHYCS0R 0x00c0
39#define AHCI_PHYCS1R 0x00c4
40#define AHCI_PHYCS2R 0x00c8
41#define AHCI_TIMER1MS 0x00e0
42#define AHCI_GPARAM1R 0x00e8
43#define AHCI_GPARAM2R 0x00ec
44#define AHCI_PPARAMR 0x00f0
45#define AHCI_TESTR 0x00f4
46#define AHCI_VERSIONR 0x00f8
47#define AHCI_IDR 0x00fc
48#define AHCI_RWCR 0x00fc
49#define AHCI_P0DMACR 0x0170
50#define AHCI_P0PHYCR 0x0178
51#define AHCI_P0PHYSR 0x017c
Olliver Schinaglc5754b52014-02-22 16:53:36 +010052
53static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
54{
55 u32 reg_val;
56
57 reg_val = readl(reg);
58 reg_val &= ~(clr_val);
59 writel(reg_val, reg);
60}
61
62static void sunxi_setbits(void __iomem *reg, u32 set_val)
63{
64 u32 reg_val;
65
66 reg_val = readl(reg);
67 reg_val |= set_val;
68 writel(reg_val, reg);
69}
70
71static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
72{
73 u32 reg_val;
74
75 reg_val = readl(reg);
76 reg_val &= ~(clr_val);
77 reg_val |= set_val;
78 writel(reg_val, reg);
79}
80
81static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
82{
83 return (readl(reg) >> shift) & mask;
84}
85
86static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
87{
88 u32 reg_val;
89 int timeout;
90
91 /* This magic is from the original code */
92 writel(0, reg_base + AHCI_RWCR);
Hans de Goeded2ec1472014-02-23 12:52:41 +010093 msleep(5);
Olliver Schinaglc5754b52014-02-22 16:53:36 +010094
95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
97 (0x7 << 24),
98 (0x5 << 24) | BIT(23) | BIT(18));
99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
100 (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
101 (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
105 (0x7 << 20), (0x3 << 20));
106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
107 (0x1f << 5), (0x19 << 5));
Hans de Goeded2ec1472014-02-23 12:52:41 +0100108 msleep(5);
Olliver Schinaglc5754b52014-02-22 16:53:36 +0100109
110 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
111
112 timeout = 250; /* Power up takes aprox 50 us */
113 do {
114 reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
115 if (reg_val == 0x02)
116 break;
117
118 if (--timeout == 0) {
119 dev_err(dev, "PHY power up failed.\n");
120 return -EIO;
121 }
122 udelay(1);
123 } while (1);
124
125 sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
126
127 timeout = 100; /* Calibration takes aprox 10 us */
128 do {
129 reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
130 if (reg_val == 0x00)
131 break;
132
133 if (--timeout == 0) {
134 dev_err(dev, "PHY calibration failed.\n");
135 return -EIO;
136 }
137 udelay(1);
138 } while (1);
139
Hans de Goeded2ec1472014-02-23 12:52:41 +0100140 msleep(15);
Olliver Schinaglc5754b52014-02-22 16:53:36 +0100141
142 writel(0x7, reg_base + AHCI_RWCR);
143
144 return 0;
145}
146
147static void ahci_sunxi_start_engine(struct ata_port *ap)
148{
149 void __iomem *port_mmio = ahci_port_base(ap);
150 struct ahci_host_priv *hpriv = ap->host->private_data;
151
152 /* Setup DMA before DMA start */
153 sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
154
155 /* Start DMA */
156 sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
157}
158
159static const struct ata_port_info ahci_sunxi_port_info = {
Olliver Schinaglc5754b52014-02-22 16:53:36 +0100160 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_platform_ops,
164};
165
166static int ahci_sunxi_probe(struct platform_device *pdev)
167{
168 struct device *dev = &pdev->dev;
169 struct ahci_host_priv *hpriv;
170 int rc;
171
172 hpriv = ahci_platform_get_resources(pdev);
173 if (IS_ERR(hpriv))
174 return PTR_ERR(hpriv);
175
176 hpriv->start_engine = ahci_sunxi_start_engine;
177
178 rc = ahci_platform_enable_resources(hpriv);
179 if (rc)
180 return rc;
181
182 rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
183 if (rc)
184 goto disable_resources;
185
Antoine Ténart725c7b52014-07-30 20:13:56 +0200186 hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
187 AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
Kefeng Wangf9f36912014-05-14 14:13:41 +0800188
Antoine Ténart725c7b52014-07-30 20:13:56 +0200189 rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info);
Olliver Schinaglc5754b52014-02-22 16:53:36 +0100190 if (rc)
191 goto disable_resources;
192
193 return 0;
194
195disable_resources:
196 ahci_platform_disable_resources(hpriv);
197 return rc;
198}
199
200#ifdef CONFIG_PM_SLEEP
Bartlomiej Zolnierkiewicz1bf9d882014-03-17 14:06:57 +0100201static int ahci_sunxi_resume(struct device *dev)
Olliver Schinaglc5754b52014-02-22 16:53:36 +0100202{
203 struct ata_host *host = dev_get_drvdata(dev);
204 struct ahci_host_priv *hpriv = host->private_data;
205 int rc;
206
207 rc = ahci_platform_enable_resources(hpriv);
208 if (rc)
209 return rc;
210
211 rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
212 if (rc)
213 goto disable_resources;
214
215 rc = ahci_platform_resume_host(dev);
216 if (rc)
217 goto disable_resources;
218
219 return 0;
220
221disable_resources:
222 ahci_platform_disable_resources(hpriv);
223 return rc;
224}
225#endif
226
227static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
228 ahci_sunxi_resume);
229
230static const struct of_device_id ahci_sunxi_of_match[] = {
231 { .compatible = "allwinner,sun4i-a10-ahci", },
232 { },
233};
234MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
235
236static struct platform_driver ahci_sunxi_driver = {
237 .probe = ahci_sunxi_probe,
238 .remove = ata_platform_remove_one,
239 .driver = {
240 .name = "ahci-sunxi",
241 .owner = THIS_MODULE,
242 .of_match_table = ahci_sunxi_of_match,
243 .pm = &ahci_sunxi_pm_ops,
244 },
245};
246module_platform_driver(ahci_sunxi_driver);
247
248MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
249MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
250MODULE_LICENSE("GPL");