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Li Yangfaf0b2e2007-10-16 20:58:38 +08001/*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08009 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
Li Yangfaf0b2e2007-10-16 20:58:38 +080010 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Li Yangfaf0b2e2007-10-16 20:58:38 +080022
23#include <scsi/scsi_host.h>
24#include <scsi/scsi_cmnd.h>
25#include <linux/libata.h>
26#include <asm/io.h>
Rob Herring5af50732013-09-17 14:28:33 -050027#include <linux/of_address.h>
28#include <linux/of_irq.h>
Li Yangfaf0b2e2007-10-16 20:58:38 +080029#include <linux/of_platform.h>
30
Qiang Liu6b4b8fc2012-02-15 15:40:34 +080031static unsigned int intr_coalescing_count;
32module_param(intr_coalescing_count, int, S_IRUGO);
33MODULE_PARM_DESC(intr_coalescing_count,
34 "INT coalescing count threshold (1..31)");
35
36static unsigned int intr_coalescing_ticks;
37module_param(intr_coalescing_ticks, int, S_IRUGO);
38MODULE_PARM_DESC(intr_coalescing_ticks,
39 "INT coalescing timer threshold in AHB ticks");
Li Yangfaf0b2e2007-10-16 20:58:38 +080040/* Controller information */
41enum {
42 SATA_FSL_QUEUE_DEPTH = 16,
43 SATA_FSL_MAX_PRD = 63,
44 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
45 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
46
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +030047 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
48 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
Li Yangfaf0b2e2007-10-16 20:58:38 +080049
50 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
51 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
52 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
53
54 /*
55 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
Lucas De Marchi25985ed2011-03-30 22:57:33 -030056 * chained indirect PRDEs up to a max count of 63.
André Goddard Rosaaf901ca2009-11-14 13:09:05 -020057 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
Li Yangfaf0b2e2007-10-16 20:58:38 +080058 * be setup as an indirect descriptor, pointing to it's next
André Goddard Rosaaf901ca2009-11-14 13:09:05 -020059 * (contiguous) PRDE. Though chained indirect PRDE arrays are
Li Yangfaf0b2e2007-10-16 20:58:38 +080060 * supported,it will be more efficient to use a direct PRDT and
61 * a single chain/link to indirect PRDE array/PRDT.
62 */
63
64 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
65 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
66 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
67 SATA_FSL_CMD_DESC_RSRVD = 16,
68
69 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
70 SATA_FSL_CMD_DESC_SFIS_SZ +
71 SATA_FSL_CMD_DESC_ACMD_SZ +
72 SATA_FSL_CMD_DESC_RSRVD +
73 SATA_FSL_MAX_PRD * 16),
74
75 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
76 (SATA_FSL_CMD_DESC_CFIS_SZ +
77 SATA_FSL_CMD_DESC_SFIS_SZ +
78 SATA_FSL_CMD_DESC_ACMD_SZ +
79 SATA_FSL_CMD_DESC_RSRVD),
80
81 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
82 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
83 SATA_FSL_CMD_DESC_AR_SZ),
84
85 /*
86 * MPC8315 has two SATA controllers, SATA1 & SATA2
87 * (one port per controller)
88 * MPC837x has 2/4 controllers, one port per controller
89 */
90
91 SATA_FSL_MAX_PORTS = 1,
92
93 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
94};
95
96/*
Qiang Liu6b4b8fc2012-02-15 15:40:34 +080097 * Interrupt Coalescing Control Register bitdefs */
98enum {
99 ICC_MIN_INT_COUNT_THRESHOLD = 1,
100 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
101 ICC_MIN_INT_TICKS_THRESHOLD = 0,
102 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
103 ICC_SAFE_INT_TICKS = 1,
104};
105
106/*
Li Yangfaf0b2e2007-10-16 20:58:38 +0800107* Host Controller command register set - per port
108*/
109enum {
110 CQ = 0,
111 CA = 8,
112 CC = 0x10,
113 CE = 0x18,
114 DE = 0x20,
115 CHBA = 0x24,
116 HSTATUS = 0x28,
117 HCONTROL = 0x2C,
118 CQPMP = 0x30,
119 SIGNATURE = 0x34,
120 ICC = 0x38,
121
122 /*
123 * Host Status Register (HStatus) bitdefs
124 */
125 ONLINE = (1 << 31),
126 GOING_OFFLINE = (1 << 30),
127 BIST_ERR = (1 << 29),
Shaohui Xie100f5862012-09-11 10:48:53 +0800128 CLEAR_ERROR = (1 << 27),
Li Yangfaf0b2e2007-10-16 20:58:38 +0800129
130 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
131 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
132 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
133 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
134 FATAL_ERR_DATA_OVERRUN = (1 << 12),
135 FATAL_ERR_CRC_ERR_TX = (1 << 11),
136 FATAL_ERR_CRC_ERR_RX = (1 << 10),
137 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
138 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
139
140 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
141 FATAL_ERR_PARITY_ERR_TX |
142 FATAL_ERR_PARITY_ERR_RX |
143 FATAL_ERR_DATA_UNDERRUN |
144 FATAL_ERR_DATA_OVERRUN |
145 FATAL_ERR_CRC_ERR_TX |
146 FATAL_ERR_CRC_ERR_RX |
147 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
148
Shaohui Xie100f5862012-09-11 10:48:53 +0800149 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
Li Yangfaf0b2e2007-10-16 20:58:38 +0800150 INT_ON_FATAL_ERR = (1 << 5),
151 INT_ON_PHYRDY_CHG = (1 << 4),
152
153 INT_ON_SIGNATURE_UPDATE = (1 << 3),
154 INT_ON_SNOTIFY_UPDATE = (1 << 2),
155 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
156 INT_ON_CMD_COMPLETE = 1,
157
ashish kalrafd6c29e2009-07-01 20:59:43 +0530158 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
Li Yangfaf0b2e2007-10-16 20:58:38 +0800159 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
160
161 /*
162 * Host Control Register (HControl) bitdefs
163 */
164 HCONTROL_ONLINE_PHY_RST = (1 << 31),
165 HCONTROL_FORCE_OFFLINE = (1 << 30),
Jerry Huang93272b12011-12-20 14:50:27 +0800166 HCONTROL_LEGACY = (1 << 28),
Li Yangfaf0b2e2007-10-16 20:58:38 +0800167 HCONTROL_PARITY_PROT_MOD = (1 << 14),
168 HCONTROL_DPATH_PARITY = (1 << 12),
169 HCONTROL_SNOOP_ENABLE = (1 << 10),
170 HCONTROL_PMP_ATTACHED = (1 << 9),
171 HCONTROL_COPYOUT_STATFIS = (1 << 8),
172 IE_ON_FATAL_ERR = (1 << 5),
173 IE_ON_PHYRDY_CHG = (1 << 4),
174 IE_ON_SIGNATURE_UPDATE = (1 << 3),
175 IE_ON_SNOTIFY_UPDATE = (1 << 2),
176 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
177 IE_ON_CMD_COMPLETE = 1,
178
179 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
ashish kalrafd6c29e2009-07-01 20:59:43 +0530180 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
Li Yangfaf0b2e2007-10-16 20:58:38 +0800181 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
182
183 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
Xulei2f957fc2011-01-19 17:07:29 +0800184 DATA_SNOOP_ENABLE_V1 = (1 << 22),
185 DATA_SNOOP_ENABLE_V2 = (1 << 28),
Li Yangfaf0b2e2007-10-16 20:58:38 +0800186};
187
188/*
189 * SATA Superset Registers
190 */
191enum {
192 SSTATUS = 0,
193 SERROR = 4,
194 SCONTROL = 8,
195 SNOTIFY = 0xC,
196};
197
198/*
199 * Control Status Register Set
200 */
201enum {
202 TRANSCFG = 0,
203 TRANSSTATUS = 4,
204 LINKCFG = 8,
205 LINKCFG1 = 0xC,
206 LINKCFG2 = 0x10,
207 LINKSTATUS = 0x14,
208 LINKSTATUS1 = 0x18,
209 PHYCTRLCFG = 0x1C,
210 COMMANDSTAT = 0x20,
211};
212
Prabhakar Kushwaha578ca872011-03-07 09:28:10 +0530213/* TRANSCFG (transport-layer) configuration control */
214enum {
215 TRANSCFG_RX_WATER_MARK = (1 << 4),
216};
217
Li Yangfaf0b2e2007-10-16 20:58:38 +0800218/* PHY (link-layer) configuration control */
219enum {
220 PHY_BIST_ENABLE = 0x01,
221};
222
223/*
224 * Command Header Table entry, i.e, command slot
225 * 4 Dwords per command slot, command header size == 64 Dwords.
226 */
227struct cmdhdr_tbl_entry {
228 u32 cda;
229 u32 prde_fis_len;
230 u32 ttl;
231 u32 desc_info;
232};
233
234/*
235 * Description information bitdefs
236 */
237enum {
Dave Liud3587242009-05-14 09:47:07 -0500238 CMD_DESC_RES = (1 << 11),
Li Yangfaf0b2e2007-10-16 20:58:38 +0800239 VENDOR_SPECIFIC_BIST = (1 << 10),
240 CMD_DESC_SNOOP_ENABLE = (1 << 9),
241 FPDMA_QUEUED_CMD = (1 << 8),
242 SRST_CMD = (1 << 7),
243 BIST = (1 << 6),
244 ATAPI_CMD = (1 << 5),
245};
246
247/*
248 * Command Descriptor
249 */
250struct command_desc {
251 u8 cfis[8 * 4];
252 u8 sfis[8 * 4];
253 u8 acmd[4 * 4];
254 u8 fill[4 * 4];
255 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
256 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
257};
258
259/*
260 * Physical region table descriptor(PRD)
261 */
262
263struct prde {
264 u32 dba;
265 u8 fill[2 * 4];
266 u32 ddc_and_ext;
267};
268
269/*
270 * ata_port private data
271 * This is our per-port instance data.
272 */
273struct sata_fsl_port_priv {
274 struct cmdhdr_tbl_entry *cmdslot;
275 dma_addr_t cmdslot_paddr;
276 struct command_desc *cmdentry;
277 dma_addr_t cmdentry_paddr;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800278};
279
280/*
281 * ata_port->host_set private data
282 */
283struct sata_fsl_host_priv {
284 void __iomem *hcr_base;
285 void __iomem *ssr_base;
286 void __iomem *csr_base;
Li Yang79b3edc2007-10-31 19:27:55 +0800287 int irq;
Xulei2f957fc2011-01-19 17:07:29 +0800288 int data_snoop;
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800289 struct device_attribute intr_coalescing;
Qiang Liu7551c402013-03-04 15:20:23 +0800290 struct device_attribute rx_watermark;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800291};
292
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800293static void fsl_sata_set_irq_coalescing(struct ata_host *host,
294 unsigned int count, unsigned int ticks)
295{
296 struct sata_fsl_host_priv *host_priv = host->private_data;
297 void __iomem *hcr_base = host_priv->hcr_base;
Anthony Foiani99bbdfa2013-08-19 19:20:30 -0600298 unsigned long flags;
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800299
300 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
301 count = ICC_MAX_INT_COUNT_THRESHOLD;
302 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
303 count = ICC_MIN_INT_COUNT_THRESHOLD;
304
305 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
306 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
307 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
308 (count > ICC_MIN_INT_COUNT_THRESHOLD))
309 ticks = ICC_SAFE_INT_TICKS;
310
Anthony Foiani99bbdfa2013-08-19 19:20:30 -0600311 spin_lock_irqsave(&host->lock, flags);
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800312 iowrite32((count << 24 | ticks), hcr_base + ICC);
313
314 intr_coalescing_count = count;
315 intr_coalescing_ticks = ticks;
Anthony Foiani99bbdfa2013-08-19 19:20:30 -0600316 spin_unlock_irqrestore(&host->lock, flags);
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800317
Masanari Iida07f42252013-03-20 11:00:34 +0900318 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800319 intr_coalescing_count, intr_coalescing_ticks);
320 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
321 hcr_base, ioread32(hcr_base + ICC));
322}
323
324static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
325 struct device_attribute *attr, char *buf)
326{
327 return sprintf(buf, "%d %d\n",
328 intr_coalescing_count, intr_coalescing_ticks);
329}
330
331static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
332 struct device_attribute *attr,
333 const char *buf, size_t count)
334{
335 unsigned int coalescing_count, coalescing_ticks;
336
337 if (sscanf(buf, "%d%d",
338 &coalescing_count,
339 &coalescing_ticks) != 2) {
340 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
341 return -EINVAL;
342 }
343
344 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
345 coalescing_count, coalescing_ticks);
346
347 return strlen(buf);
348}
349
Qiang Liu7551c402013-03-04 15:20:23 +0800350static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
351 struct device_attribute *attr, char *buf)
352{
353 unsigned int rx_watermark;
354 unsigned long flags;
355 struct ata_host *host = dev_get_drvdata(dev);
356 struct sata_fsl_host_priv *host_priv = host->private_data;
357 void __iomem *csr_base = host_priv->csr_base;
358
359 spin_lock_irqsave(&host->lock, flags);
360 rx_watermark = ioread32(csr_base + TRANSCFG);
361 rx_watermark &= 0x1f;
362
363 spin_unlock_irqrestore(&host->lock, flags);
364 return sprintf(buf, "%d\n", rx_watermark);
365}
366
367static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
368 struct device_attribute *attr,
369 const char *buf, size_t count)
370{
371 unsigned int rx_watermark;
372 unsigned long flags;
373 struct ata_host *host = dev_get_drvdata(dev);
374 struct sata_fsl_host_priv *host_priv = host->private_data;
375 void __iomem *csr_base = host_priv->csr_base;
376 u32 temp;
377
378 if (sscanf(buf, "%d", &rx_watermark) != 1) {
379 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
380 return -EINVAL;
381 }
382
383 spin_lock_irqsave(&host->lock, flags);
384 temp = ioread32(csr_base + TRANSCFG);
385 temp &= 0xffffffe0;
386 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
387
388 spin_unlock_irqrestore(&host->lock, flags);
389 return strlen(buf);
390}
391
Li Yangfaf0b2e2007-10-16 20:58:38 +0800392static inline unsigned int sata_fsl_tag(unsigned int tag,
Li Yang520d3a12007-10-31 19:28:01 +0800393 void __iomem *hcr_base)
Li Yangfaf0b2e2007-10-16 20:58:38 +0800394{
395 /* We let libATA core do actual (queue) tag allocation */
396
397 /* all non NCQ/queued commands should have tag#0 */
398 if (ata_tag_internal(tag)) {
399 DPRINTK("mapping internal cmds to tag#0\n");
400 return 0;
401 }
402
403 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
404 DPRINTK("tag %d invalid : out of range\n", tag);
405 return 0;
406 }
407
408 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
409 DPRINTK("tag %d invalid : in use!!\n", tag);
410 return 0;
411 }
412
413 return tag;
414}
415
416static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
417 unsigned int tag, u32 desc_info,
418 u32 data_xfer_len, u8 num_prde,
419 u8 fis_len)
420{
421 dma_addr_t cmd_descriptor_address;
422
423 cmd_descriptor_address = pp->cmdentry_paddr +
424 tag * SATA_FSL_CMD_DESC_SIZE;
425
426 /* NOTE: both data_xfer_len & fis_len are Dword counts */
427
428 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
429 pp->cmdslot[tag].prde_fis_len =
430 cpu_to_le32((num_prde << 16) | (fis_len << 2));
431 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
Li Yang520d3a12007-10-31 19:28:01 +0800432 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
Li Yangfaf0b2e2007-10-16 20:58:38 +0800433
434 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
435 pp->cmdslot[tag].cda,
436 pp->cmdslot[tag].prde_fis_len,
437 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
438
439}
440
441static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
Xulei2f957fc2011-01-19 17:07:29 +0800442 u32 *ttl, dma_addr_t cmd_desc_paddr,
443 int data_snoop)
Li Yangfaf0b2e2007-10-16 20:58:38 +0800444{
445 struct scatterlist *sg;
446 unsigned int num_prde = 0;
447 u32 ttl_dwords = 0;
448
449 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200450 * NOTE : direct & indirect prdt's are contiguously allocated
Li Yangfaf0b2e2007-10-16 20:58:38 +0800451 */
452 struct prde *prd = (struct prde *)&((struct command_desc *)
453 cmd_desc)->prdt;
454
455 struct prde *prd_ptr_to_indirect_ext = NULL;
456 unsigned indirect_ext_segment_sz = 0;
457 dma_addr_t indirect_ext_segment_paddr;
Tejun Heoff2aeb12007-12-05 16:43:11 +0900458 unsigned int si;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800459
Anton Vorontsovb1f5dc42008-02-22 19:54:25 +0300460 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800461
462 indirect_ext_segment_paddr = cmd_desc_paddr +
463 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
464
Tejun Heoff2aeb12007-12-05 16:43:11 +0900465 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Li Yangfaf0b2e2007-10-16 20:58:38 +0800466 dma_addr_t sg_addr = sg_dma_address(sg);
467 u32 sg_len = sg_dma_len(sg);
468
Kumar Galaf48c0192009-05-13 22:10:50 -0500469 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
470 (unsigned long long)sg_addr, sg_len);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800471
472 /* warn if each s/g element is not dword aligned */
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800473 if (unlikely(sg_addr & 0x03))
Joe Perchesa9a79df2011-04-15 15:51:59 -0700474 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
475 (unsigned long long)sg_addr);
Qiang Liu6b4b8fc2012-02-15 15:40:34 +0800476 if (unlikely(sg_len & 0x03))
Joe Perchesa9a79df2011-04-15 15:51:59 -0700477 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
478 sg_len);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800479
James Bottomley37198e32008-02-05 14:06:27 +0900480 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
481 sg_next(sg) != NULL) {
Li Yangfaf0b2e2007-10-16 20:58:38 +0800482 VPRINTK("setting indirect prde\n");
483 prd_ptr_to_indirect_ext = prd;
484 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
485 indirect_ext_segment_sz = 0;
486 ++prd;
487 ++num_prde;
488 }
489
490 ttl_dwords += sg_len;
491 prd->dba = cpu_to_le32(sg_addr);
Xulei2f957fc2011-01-19 17:07:29 +0800492 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
Li Yangfaf0b2e2007-10-16 20:58:38 +0800493
494 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
495 ttl_dwords, prd->dba, prd->ddc_and_ext);
496
497 ++num_prde;
498 ++prd;
499 if (prd_ptr_to_indirect_ext)
500 indirect_ext_segment_sz += sg_len;
501 }
502
503 if (prd_ptr_to_indirect_ext) {
504 /* set indirect extension flag along with indirect ext. size */
505 prd_ptr_to_indirect_ext->ddc_and_ext =
506 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
Xulei2f957fc2011-01-19 17:07:29 +0800507 data_snoop |
Li Yangfaf0b2e2007-10-16 20:58:38 +0800508 (indirect_ext_segment_sz & ~0x03)));
509 }
510
511 *ttl = ttl_dwords;
512 return num_prde;
513}
514
515static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
516{
517 struct ata_port *ap = qc->ap;
518 struct sata_fsl_port_priv *pp = ap->private_data;
519 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
520 void __iomem *hcr_base = host_priv->hcr_base;
521 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
522 struct command_desc *cd;
Dave Liud3587242009-05-14 09:47:07 -0500523 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800524 u32 num_prde = 0;
525 u32 ttl_dwords = 0;
526 dma_addr_t cd_paddr;
527
528 cd = (struct command_desc *)pp->cmdentry + tag;
529 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
530
Ashish Kalra034d8e82008-05-20 00:19:45 -0500531 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800532
533 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
534 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
535
536 if (qc->tf.protocol == ATA_PROT_NCQ) {
537 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
538 cd->cfis[3], cd->cfis[11]);
539 }
540
541 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
Tejun Heo405e66b2007-11-27 19:28:53 +0900542 if (ata_is_atapi(qc->tf.protocol)) {
Li Yangfaf0b2e2007-10-16 20:58:38 +0800543 desc_info |= ATAPI_CMD;
544 memset((void *)&cd->acmd, 0, 32);
545 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
546 }
547
548 if (qc->flags & ATA_QCFLAG_DMAMAP)
549 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
Xulei2f957fc2011-01-19 17:07:29 +0800550 &ttl_dwords, cd_paddr,
551 host_priv->data_snoop);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800552
553 if (qc->tf.protocol == ATA_PROT_NCQ)
554 desc_info |= FPDMA_QUEUED_CMD;
555
556 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
557 num_prde, 5);
558
559 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
560 desc_info, ttl_dwords, num_prde);
561}
562
563static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
564{
565 struct ata_port *ap = qc->ap;
566 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
567 void __iomem *hcr_base = host_priv->hcr_base;
568 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
569
570 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
571 ioread32(CQ + hcr_base),
572 ioread32(CA + hcr_base),
573 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
574
Ashish Kalra034d8e82008-05-20 00:19:45 -0500575 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
576
Li Yangfaf0b2e2007-10-16 20:58:38 +0800577 /* Simply queue command to the controller/device */
578 iowrite32(1 << tag, CQ + hcr_base);
579
580 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
581 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
582
583 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
584 ioread32(CE + hcr_base),
585 ioread32(DE + hcr_base),
Anton Vorontsovb1f5dc42008-02-22 19:54:25 +0300586 ioread32(CC + hcr_base),
587 ioread32(COMMANDSTAT + host_priv->csr_base));
Li Yangfaf0b2e2007-10-16 20:58:38 +0800588
589 return 0;
590}
591
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900592static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
593{
594 struct sata_fsl_port_priv *pp = qc->ap->private_data;
595 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
596 void __iomem *hcr_base = host_priv->hcr_base;
597 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
598 struct command_desc *cd;
599
600 cd = pp->cmdentry + tag;
601
602 ata_tf_from_fis(cd->sfis, &qc->result_tf);
603 return true;
604}
605
Tejun Heo82ef04f2008-07-31 17:02:40 +0900606static int sata_fsl_scr_write(struct ata_link *link,
607 unsigned int sc_reg_in, u32 val)
Li Yangfaf0b2e2007-10-16 20:58:38 +0800608{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900609 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800610 void __iomem *ssr_base = host_priv->ssr_base;
611 unsigned int sc_reg;
612
613 switch (sc_reg_in) {
614 case SCR_STATUS:
Li Yangfaf0b2e2007-10-16 20:58:38 +0800615 case SCR_ERROR:
Li Yangfaf0b2e2007-10-16 20:58:38 +0800616 case SCR_CONTROL:
Li Yangfaf0b2e2007-10-16 20:58:38 +0800617 case SCR_ACTIVE:
Jeff Garzik9465d532007-10-31 19:27:57 +0800618 sc_reg = sc_reg_in;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800619 break;
620 default:
621 return -EINVAL;
622 }
623
624 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
625
Jeff Garzik2a52e8d2007-10-31 19:27:58 +0800626 iowrite32(val, ssr_base + (sc_reg * 4));
Li Yangfaf0b2e2007-10-16 20:58:38 +0800627 return 0;
628}
629
Tejun Heo82ef04f2008-07-31 17:02:40 +0900630static int sata_fsl_scr_read(struct ata_link *link,
631 unsigned int sc_reg_in, u32 *val)
Li Yangfaf0b2e2007-10-16 20:58:38 +0800632{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900633 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800634 void __iomem *ssr_base = host_priv->ssr_base;
635 unsigned int sc_reg;
636
637 switch (sc_reg_in) {
638 case SCR_STATUS:
Li Yangfaf0b2e2007-10-16 20:58:38 +0800639 case SCR_ERROR:
Li Yangfaf0b2e2007-10-16 20:58:38 +0800640 case SCR_CONTROL:
Li Yangfaf0b2e2007-10-16 20:58:38 +0800641 case SCR_ACTIVE:
Jeff Garzik9465d532007-10-31 19:27:57 +0800642 sc_reg = sc_reg_in;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800643 break;
644 default:
645 return -EINVAL;
646 }
647
648 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
649
Jeff Garzik2a52e8d2007-10-31 19:27:58 +0800650 *val = ioread32(ssr_base + (sc_reg * 4));
Li Yangfaf0b2e2007-10-16 20:58:38 +0800651 return 0;
652}
653
654static void sata_fsl_freeze(struct ata_port *ap)
655{
656 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
657 void __iomem *hcr_base = host_priv->hcr_base;
658 u32 temp;
659
660 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
661 ioread32(CQ + hcr_base),
662 ioread32(CA + hcr_base),
663 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
Anton Vorontsovb1f5dc42008-02-22 19:54:25 +0300664 VPRINTK("CmdStat = 0x%x\n",
665 ioread32(host_priv->csr_base + COMMANDSTAT));
Li Yangfaf0b2e2007-10-16 20:58:38 +0800666
667 /* disable interrupts on the controller/port */
668 temp = ioread32(hcr_base + HCONTROL);
669 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
670
671 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
672 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
673}
674
675static void sata_fsl_thaw(struct ata_port *ap)
676{
677 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
678 void __iomem *hcr_base = host_priv->hcr_base;
679 u32 temp;
680
681 /* ack. any pending IRQs for this controller/port */
682 temp = ioread32(hcr_base + HSTATUS);
683
684 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
685
686 if (temp & 0x3F)
687 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
688
689 /* enable interrupts on the controller/port */
690 temp = ioread32(hcr_base + HCONTROL);
691 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
692
693 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
694 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
695}
696
Ashish Kalra034d8e82008-05-20 00:19:45 -0500697static void sata_fsl_pmp_attach(struct ata_port *ap)
698{
699 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
700 void __iomem *hcr_base = host_priv->hcr_base;
701 u32 temp;
702
703 temp = ioread32(hcr_base + HCONTROL);
704 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
705}
706
707static void sata_fsl_pmp_detach(struct ata_port *ap)
708{
709 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
710 void __iomem *hcr_base = host_priv->hcr_base;
711 u32 temp;
712
713 temp = ioread32(hcr_base + HCONTROL);
714 temp &= ~HCONTROL_PMP_ATTACHED;
715 iowrite32(temp, hcr_base + HCONTROL);
716
717 /* enable interrupts on the controller/port */
718 temp = ioread32(hcr_base + HCONTROL);
719 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
720
721}
722
Li Yangfaf0b2e2007-10-16 20:58:38 +0800723static int sata_fsl_port_start(struct ata_port *ap)
724{
725 struct device *dev = ap->host->dev;
726 struct sata_fsl_port_priv *pp;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800727 void *mem;
728 dma_addr_t mem_dma;
729 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
730 void __iomem *hcr_base = host_priv->hcr_base;
731 u32 temp;
732
733 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
734 if (!pp)
735 return -ENOMEM;
736
Joe Perches94463a9c2014-06-15 13:37:32 -0700737 mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
738 GFP_KERNEL);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800739 if (!mem) {
Li Yangfaf0b2e2007-10-16 20:58:38 +0800740 kfree(pp);
741 return -ENOMEM;
742 }
Li Yangfaf0b2e2007-10-16 20:58:38 +0800743
744 pp->cmdslot = mem;
745 pp->cmdslot_paddr = mem_dma;
746
747 mem += SATA_FSL_CMD_SLOT_SIZE;
748 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
749
750 pp->cmdentry = mem;
751 pp->cmdentry_paddr = mem_dma;
752
753 ap->private_data = pp;
754
755 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
756 pp->cmdslot_paddr, pp->cmdentry_paddr);
757
758 /* Now, update the CHBA register in host controller cmd register set */
759 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
760
761 /*
762 * Now, we can bring the controller on-line & also initiate
763 * the COMINIT sequence, we simply return here and the boot-probing
764 * & device discovery process is re-initiated by libATA using a
765 * Softreset EH (dummy) session. Hence, boot probing and device
766 * discovey will be part of sata_fsl_softreset() callback.
767 */
768
769 temp = ioread32(hcr_base + HCONTROL);
770 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
771
772 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
773 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
774 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
775
Li Yangfaf0b2e2007-10-16 20:58:38 +0800776 return 0;
777}
778
779static void sata_fsl_port_stop(struct ata_port *ap)
780{
781 struct device *dev = ap->host->dev;
782 struct sata_fsl_port_priv *pp = ap->private_data;
783 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
784 void __iomem *hcr_base = host_priv->hcr_base;
785 u32 temp;
786
787 /*
788 * Force host controller to go off-line, aborting current operations
789 */
790 temp = ioread32(hcr_base + HCONTROL);
791 temp &= ~HCONTROL_ONLINE_PHY_RST;
792 temp |= HCONTROL_FORCE_OFFLINE;
793 iowrite32(temp, hcr_base + HCONTROL);
794
795 /* Poll for controller to go offline - should happen immediately */
Tejun Heo97750ce2010-09-06 17:56:29 +0200796 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800797
798 ap->private_data = NULL;
799 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
800 pp->cmdslot, pp->cmdslot_paddr);
801
Li Yangfaf0b2e2007-10-16 20:58:38 +0800802 kfree(pp);
803}
804
805static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
806{
807 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
808 void __iomem *hcr_base = host_priv->hcr_base;
809 struct ata_taskfile tf;
810 u32 temp;
811
812 temp = ioread32(hcr_base + SIGNATURE);
813
814 VPRINTK("raw sig = 0x%x\n", temp);
815 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
816 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
817
818 tf.lbah = (temp >> 24) & 0xff;
819 tf.lbam = (temp >> 16) & 0xff;
820 tf.lbal = (temp >> 8) & 0xff;
821 tf.nsect = temp & 0xff;
822
823 return ata_dev_classify(&tf);
824}
825
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400826static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
Ashish Kalra034d8e82008-05-20 00:19:45 -0500827 unsigned long deadline)
Li Yangfaf0b2e2007-10-16 20:58:38 +0800828{
Li Yang1bf617b2007-10-31 19:27:53 +0800829 struct ata_port *ap = link->ap;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800830 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
831 void __iomem *hcr_base = host_priv->hcr_base;
832 u32 temp;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800833 int i = 0;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800834 unsigned long start_jiffies;
835
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400836 DPRINTK("in xx_hardreset\n");
Ashish Kalra034d8e82008-05-20 00:19:45 -0500837
Li Yangfaf0b2e2007-10-16 20:58:38 +0800838try_offline_again:
839 /*
840 * Force host controller to go off-line, aborting current operations
841 */
842 temp = ioread32(hcr_base + HCONTROL);
843 temp &= ~HCONTROL_ONLINE_PHY_RST;
844 iowrite32(temp, hcr_base + HCONTROL);
845
846 /* Poll for controller to go offline */
Tejun Heo97750ce2010-09-06 17:56:29 +0200847 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
848 1, 500);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800849
850 if (temp & ONLINE) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700851 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800852
853 /*
854 * Try to offline controller atleast twice
855 */
856 i++;
857 if (i == 2)
858 goto err;
859 else
860 goto try_offline_again;
861 }
862
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400863 DPRINTK("hardreset, controller off-lined\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +0800864 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
865 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
866
867 /*
868 * PHY reset should remain asserted for atleast 1ms
869 */
Tejun Heo97750ce2010-09-06 17:56:29 +0200870 ata_msleep(ap, 1);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800871
872 /*
873 * Now, bring the host controller online again, this can take time
874 * as PHY reset and communication establishment, 1st D2H FIS and
875 * device signature update is done, on safe side assume 500ms
876 * NOTE : Host online status may be indicated immediately!!
877 */
878
879 temp = ioread32(hcr_base + HCONTROL);
880 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
Ashish Kalra034d8e82008-05-20 00:19:45 -0500881 temp |= HCONTROL_PMP_ATTACHED;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800882 iowrite32(temp, hcr_base + HCONTROL);
883
Tejun Heo97750ce2010-09-06 17:56:29 +0200884 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800885
886 if (!(temp & ONLINE)) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700887 ata_port_err(ap, "Hardreset failed, not on-lined\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +0800888 goto err;
889 }
890
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400891 DPRINTK("hardreset, controller off-lined & on-lined\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +0800892 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
893 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
894
895 /*
896 * First, wait for the PHYRDY change to occur before waiting for
897 * the signature, and also verify if SStatus indicates device
898 * presence
899 */
900
Tejun Heo97750ce2010-09-06 17:56:29 +0200901 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
Li Yang1bf617b2007-10-31 19:27:53 +0800902 if ((!(temp & 0x10)) || ata_link_offline(link)) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700903 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
904 ioread32(hcr_base + HSTATUS));
Ashish Kalra034d8e82008-05-20 00:19:45 -0500905 *class = ATA_DEV_NONE;
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400906 return 0;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800907 }
908
909 /*
910 * Wait for the first D2H from device,i.e,signature update notification
911 */
912 start_jiffies = jiffies;
Tejun Heo97750ce2010-09-06 17:56:29 +0200913 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
Li Yangfaf0b2e2007-10-16 20:58:38 +0800914 500, jiffies_to_msecs(deadline - start_jiffies));
915
916 if ((temp & 0xFF) != 0x18) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700917 ata_port_warn(ap, "No Signature Update\n");
Ashish Kalra034d8e82008-05-20 00:19:45 -0500918 *class = ATA_DEV_NONE;
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400919 goto do_followup_srst;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800920 } else {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700921 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
922 jiffies_to_msecs(jiffies - start_jiffies));
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400923 *class = sata_fsl_dev_classify(ap);
924 return 0;
925 }
926
927do_followup_srst:
928 /*
929 * request libATA to perform follow-up softreset
930 */
931 return -EAGAIN;
932
933err:
934 return -EIO;
935}
936
937static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
938 unsigned long deadline)
939{
940 struct ata_port *ap = link->ap;
941 struct sata_fsl_port_priv *pp = ap->private_data;
942 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
943 void __iomem *hcr_base = host_priv->hcr_base;
944 int pmp = sata_srst_pmp(link);
945 u32 temp;
946 struct ata_taskfile tf;
947 u8 *cfis;
948 u32 Serror;
949
950 DPRINTK("in xx_softreset\n");
951
952 if (ata_link_offline(link)) {
953 DPRINTK("PHY reports no device\n");
954 *class = ATA_DEV_NONE;
955 return 0;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800956 }
957
958 /*
959 * Send a device reset (SRST) explicitly on command slot #0
960 * Check : will the command queue (reg) be cleared during offlining ??
961 * Also we will be online only if Phy commn. has been established
962 * and device presence has been detected, therefore if we have
963 * reached here, we can send a command to the target device
964 */
965
Li Yangfaf0b2e2007-10-16 20:58:38 +0800966 DPRINTK("Sending SRST/device reset\n");
967
Li Yang1bf617b2007-10-31 19:27:53 +0800968 ata_tf_init(link->device, &tf);
Li Yang520d3a12007-10-31 19:28:01 +0800969 cfis = (u8 *) &pp->cmdentry->cfis;
Li Yangfaf0b2e2007-10-16 20:58:38 +0800970
971 /* device reset/SRST is a control register update FIS, uses tag0 */
972 sata_fsl_setup_cmd_hdr_entry(pp, 0,
Dave Liud3587242009-05-14 09:47:07 -0500973 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800974
975 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
Ashish Kalra034d8e82008-05-20 00:19:45 -0500976 ata_tf_to_fis(&tf, pmp, 0, cfis);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800977
978 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
979 cfis[0], cfis[1], cfis[2], cfis[3]);
980
981 /*
982 * Queue SRST command to the controller/device, ensure that no
983 * other commands are active on the controller/device
984 */
985
986 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
987 ioread32(CQ + hcr_base),
988 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
989
990 iowrite32(0xFFFF, CC + hcr_base);
Jiang Yutanga0a74d12009-10-16 20:44:36 +0400991 if (pmp != SATA_PMP_CTRL_PORT)
992 iowrite32(pmp, CQPMP + hcr_base);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800993 iowrite32(1, CQ + hcr_base);
994
Tejun Heo97750ce2010-09-06 17:56:29 +0200995 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
Li Yangfaf0b2e2007-10-16 20:58:38 +0800996 if (temp & 0x1) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700997 ata_port_warn(ap, "ATA_SRST issue failed\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +0800998
999 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1000 ioread32(CQ + hcr_base),
1001 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1002
Tejun Heo82ef04f2008-07-31 17:02:40 +09001003 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001004
1005 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1006 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1007 DPRINTK("Serror = 0x%x\n", Serror);
1008 goto err;
1009 }
1010
Tejun Heo97750ce2010-09-06 17:56:29 +02001011 ata_msleep(ap, 1);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001012
1013 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001014 * SATA device enters reset state after receiving a Control register
Li Yangfaf0b2e2007-10-16 20:58:38 +08001015 * FIS with SRST bit asserted and it awaits another H2D Control reg.
1016 * FIS with SRST bit cleared, then the device does internal diags &
1017 * initialization, followed by indicating it's initialization status
1018 * using ATA signature D2H register FIS to the host controller.
1019 */
1020
Dave Liud3587242009-05-14 09:47:07 -05001021 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1022 0, 0, 5);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001023
1024 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
Ashish Kalra034d8e82008-05-20 00:19:45 -05001025 ata_tf_to_fis(&tf, pmp, 0, cfis);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001026
Ashish Kalra034d8e82008-05-20 00:19:45 -05001027 if (pmp != SATA_PMP_CTRL_PORT)
1028 iowrite32(pmp, CQPMP + hcr_base);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001029 iowrite32(1, CQ + hcr_base);
Tejun Heo97750ce2010-09-06 17:56:29 +02001030 ata_msleep(ap, 150); /* ?? */
Li Yangfaf0b2e2007-10-16 20:58:38 +08001031
1032 /*
1033 * The above command would have signalled an interrupt on command
1034 * complete, which needs special handling, by clearing the Nth
1035 * command bit of the CCreg
1036 */
1037 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
Li Yangfaf0b2e2007-10-16 20:58:38 +08001038
1039 DPRINTK("SATA FSL : Now checking device signature\n");
1040
1041 *class = ATA_DEV_NONE;
1042
1043 /* Verify if SStatus indicates device presence */
Li Yang1bf617b2007-10-31 19:27:53 +08001044 if (ata_link_online(link)) {
Li Yangfaf0b2e2007-10-16 20:58:38 +08001045 /*
1046 * if we are here, device presence has been detected,
1047 * 1st D2H FIS would have been received, but sfis in
1048 * command desc. is not updated, but signature register
1049 * would have been updated
1050 */
1051
1052 *class = sata_fsl_dev_classify(ap);
1053
1054 DPRINTK("class = %d\n", *class);
1055 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1056 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1057 }
1058
1059 return 0;
1060
1061err:
1062 return -EIO;
1063}
1064
Ashish Kalra034d8e82008-05-20 00:19:45 -05001065static void sata_fsl_error_handler(struct ata_port *ap)
1066{
1067
1068 DPRINTK("in xx_error_handler\n");
1069 sata_pmp_error_handler(ap);
1070
1071}
1072
Li Yangfaf0b2e2007-10-16 20:58:38 +08001073static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1074{
1075 if (qc->flags & ATA_QCFLAG_FAILED)
1076 qc->err_mask |= AC_ERR_OTHER;
1077
1078 if (qc->err_mask) {
1079 /* make DMA engine forget about the failed command */
1080
1081 }
1082}
1083
Li Yangfaf0b2e2007-10-16 20:58:38 +08001084static void sata_fsl_error_intr(struct ata_port *ap)
1085{
Li Yangfaf0b2e2007-10-16 20:58:38 +08001086 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1087 void __iomem *hcr_base = host_priv->hcr_base;
Ashish Kalra034d8e82008-05-20 00:19:45 -05001088 u32 hstatus, dereg=0, cereg = 0, SError = 0;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001089 unsigned int err_mask = 0, action = 0;
Ashish Kalra034d8e82008-05-20 00:19:45 -05001090 int freeze = 0, abort=0;
1091 struct ata_link *link = NULL;
1092 struct ata_queued_cmd *qc = NULL;
1093 struct ata_eh_info *ehi;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001094
1095 hstatus = ioread32(hcr_base + HSTATUS);
1096 cereg = ioread32(hcr_base + CE);
1097
Ashish Kalra034d8e82008-05-20 00:19:45 -05001098 /* first, analyze and record host port events */
1099 link = &ap->link;
1100 ehi = &link->eh_info;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001101 ata_ehi_clear_desc(ehi);
1102
1103 /*
1104 * Handle & Clear SError
1105 */
1106
Tejun Heo82ef04f2008-07-31 17:02:40 +09001107 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
ashish kalrafd6c29e2009-07-01 20:59:43 +05301108 if (unlikely(SError & 0xFFFF0000))
Tejun Heo82ef04f2008-07-31 17:02:40 +09001109 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001110
1111 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1112 hstatus, cereg, ioread32(hcr_base + DE), SError);
1113
Ashish Kalra034d8e82008-05-20 00:19:45 -05001114 /* handle fatal errors */
1115 if (hstatus & FATAL_ERROR_DECODE) {
1116 ehi->err_mask |= AC_ERR_ATA_BUS;
1117 ehi->action |= ATA_EH_SOFTRESET;
1118
Ashish Kalra034d8e82008-05-20 00:19:45 -05001119 freeze = 1;
1120 }
1121
ashish kalrafd6c29e2009-07-01 20:59:43 +05301122 /* Handle SDB FIS receive & notify update */
1123 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1124 sata_async_notification(ap);
1125
Ashish Kalra034d8e82008-05-20 00:19:45 -05001126 /* Handle PHYRDY change notification */
1127 if (hstatus & INT_ON_PHYRDY_CHG) {
1128 DPRINTK("SATA FSL: PHYRDY change indication\n");
1129
1130 /* Setup a soft-reset EH action */
1131 ata_ehi_hotplugged(ehi);
1132 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1133 freeze = 1;
1134 }
1135
Li Yangfaf0b2e2007-10-16 20:58:38 +08001136 /* handle single device errors */
1137 if (cereg) {
1138 /*
1139 * clear the command error, also clears queue to the device
1140 * in error, and we can (re)issue commands to this device.
1141 * When a device is in error all commands queued into the
1142 * host controller and at the device are considered aborted
1143 * and the queue for that device is stopped. Now, after
1144 * clearing the device error, we can issue commands to the
1145 * device to interrogate it to find the source of the error.
1146 */
Ashish Kalra034d8e82008-05-20 00:19:45 -05001147 abort = 1;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001148
1149 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1150 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
Li Yangfaf0b2e2007-10-16 20:58:38 +08001151
Ashish Kalra034d8e82008-05-20 00:19:45 -05001152 /* find out the offending link and qc */
1153 if (ap->nr_pmp_links) {
Prabhakar Kushwaha4ac7534a2011-03-09 12:47:18 +05301154 unsigned int dev_num;
1155
Ashish Kalra034d8e82008-05-20 00:19:45 -05001156 dereg = ioread32(hcr_base + DE);
1157 iowrite32(dereg, hcr_base + DE);
1158 iowrite32(cereg, hcr_base + CE);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001159
Prabhakar Kushwaha4ac7534a2011-03-09 12:47:18 +05301160 dev_num = ffs(dereg) - 1;
1161 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1162 link = &ap->pmp_link[dev_num];
Ashish Kalra034d8e82008-05-20 00:19:45 -05001163 ehi = &link->eh_info;
1164 qc = ata_qc_from_tag(ap, link->active_tag);
1165 /*
1166 * We should consider this as non fatal error,
1167 * and TF must be updated as done below.
1168 */
Li Yangfaf0b2e2007-10-16 20:58:38 +08001169
Ashish Kalra034d8e82008-05-20 00:19:45 -05001170 err_mask |= AC_ERR_DEV;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001171
Ashish Kalra034d8e82008-05-20 00:19:45 -05001172 } else {
1173 err_mask |= AC_ERR_HSM;
1174 action |= ATA_EH_HARDRESET;
1175 freeze = 1;
1176 }
1177 } else {
1178 dereg = ioread32(hcr_base + DE);
1179 iowrite32(dereg, hcr_base + DE);
1180 iowrite32(cereg, hcr_base + CE);
1181
1182 qc = ata_qc_from_tag(ap, link->active_tag);
1183 /*
1184 * We should consider this as non fatal error,
1185 * and TF must be updated as done below.
1186 */
1187 err_mask |= AC_ERR_DEV;
1188 }
Li Yangfaf0b2e2007-10-16 20:58:38 +08001189 }
1190
1191 /* record error info */
ashish kalrafd6c29e2009-07-01 20:59:43 +05301192 if (qc)
Li Yangfaf0b2e2007-10-16 20:58:38 +08001193 qc->err_mask |= err_mask;
ashish kalrafd6c29e2009-07-01 20:59:43 +05301194 else
Li Yangfaf0b2e2007-10-16 20:58:38 +08001195 ehi->err_mask |= err_mask;
1196
1197 ehi->action |= action;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001198
1199 /* freeze or abort */
1200 if (freeze)
1201 ata_port_freeze(ap);
Ashish Kalra034d8e82008-05-20 00:19:45 -05001202 else if (abort) {
1203 if (qc)
1204 ata_link_abort(qc->dev->link);
1205 else
1206 ata_port_abort(ap);
1207 }
Li Yangfaf0b2e2007-10-16 20:58:38 +08001208}
1209
Li Yangfaf0b2e2007-10-16 20:58:38 +08001210static void sata_fsl_host_intr(struct ata_port *ap)
1211{
1212 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1213 void __iomem *hcr_base = host_priv->hcr_base;
Tejun Heo752e3862010-06-25 15:02:59 +02001214 u32 hstatus, done_mask = 0;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001215 struct ata_queued_cmd *qc;
1216 u32 SError;
Shaohui Xie100f5862012-09-11 10:48:53 +08001217 u32 tag;
1218 u32 status_mask = INT_ON_ERROR;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001219
1220 hstatus = ioread32(hcr_base + HSTATUS);
1221
Tejun Heo82ef04f2008-07-31 17:02:40 +09001222 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001223
Shaohui Xie100f5862012-09-11 10:48:53 +08001224 /* Read command completed register */
1225 done_mask = ioread32(hcr_base + CC);
1226
1227 /* Workaround for data length mismatch errata */
1228 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1229 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1230 qc = ata_qc_from_tag(ap, tag);
1231 if (qc && ata_is_atapi(qc->tf.protocol)) {
1232 u32 hcontrol;
1233 /* Set HControl[27] to clear error registers */
1234 hcontrol = ioread32(hcr_base + HCONTROL);
1235 iowrite32(hcontrol | CLEAR_ERROR,
1236 hcr_base + HCONTROL);
1237
1238 /* Clear HControl[27] */
1239 iowrite32(hcontrol & ~CLEAR_ERROR,
1240 hcr_base + HCONTROL);
1241
1242 /* Clear SError[E] bit */
1243 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1244 SError);
1245
1246 /* Ignore fatal error and device error */
1247 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1248 | INT_ON_FATAL_ERR);
1249 break;
1250 }
1251 }
1252 }
1253
Li Yangfaf0b2e2007-10-16 20:58:38 +08001254 if (unlikely(SError & 0xFFFF0000)) {
1255 DPRINTK("serror @host_intr : 0x%x\n", SError);
1256 sata_fsl_error_intr(ap);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001257 }
1258
Shaohui Xie100f5862012-09-11 10:48:53 +08001259 if (unlikely(hstatus & status_mask)) {
Li Yangfaf0b2e2007-10-16 20:58:38 +08001260 DPRINTK("error interrupt!!\n");
1261 sata_fsl_error_intr(ap);
1262 return;
1263 }
1264
Ashish Kalra034d8e82008-05-20 00:19:45 -05001265 VPRINTK("Status of all queues :\n");
Tejun Heo752e3862010-06-25 15:02:59 +02001266 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1267 done_mask,
Ashish Kalra034d8e82008-05-20 00:19:45 -05001268 ioread32(hcr_base + CA),
1269 ioread32(hcr_base + CE),
1270 ioread32(hcr_base + CQ),
1271 ap->qc_active);
1272
Tejun Heo752e3862010-06-25 15:02:59 +02001273 if (done_mask & ap->qc_active) {
Li Yangfaf0b2e2007-10-16 20:58:38 +08001274 int i;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001275 /* clear CC bit, this will also complete the interrupt */
Tejun Heo752e3862010-06-25 15:02:59 +02001276 iowrite32(done_mask, hcr_base + CC);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001277
1278 DPRINTK("Status of all queues :\n");
Tejun Heo752e3862010-06-25 15:02:59 +02001279 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1280 done_mask, ioread32(hcr_base + CA),
Li Yangfaf0b2e2007-10-16 20:58:38 +08001281 ioread32(hcr_base + CE));
1282
1283 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001284 if (done_mask & (1 << i))
Li Yangfaf0b2e2007-10-16 20:58:38 +08001285 DPRINTK
1286 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1287 i, ioread32(hcr_base + CC),
1288 ioread32(hcr_base + CA));
Li Yangfaf0b2e2007-10-16 20:58:38 +08001289 }
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001290 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001291 return;
1292
Ashish Kalra034d8e82008-05-20 00:19:45 -05001293 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
Li Yangfaf0b2e2007-10-16 20:58:38 +08001294 iowrite32(1, hcr_base + CC);
Ashish Kalra034d8e82008-05-20 00:19:45 -05001295 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001296
Ashish Kalra034d8e82008-05-20 00:19:45 -05001297 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1298 ioread32(hcr_base + CC));
Li Yangfaf0b2e2007-10-16 20:58:38 +08001299
Ashish Kalra034d8e82008-05-20 00:19:45 -05001300 if (qc) {
Li Yangfaf0b2e2007-10-16 20:58:38 +08001301 ata_qc_complete(qc);
Ashish Kalra034d8e82008-05-20 00:19:45 -05001302 }
Li Yangfaf0b2e2007-10-16 20:58:38 +08001303 } else {
1304 /* Spurious Interrupt!! */
1305 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1306 ioread32(hcr_base + CC));
Tejun Heo752e3862010-06-25 15:02:59 +02001307 iowrite32(done_mask, hcr_base + CC);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001308 return;
1309 }
1310}
1311
1312static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1313{
1314 struct ata_host *host = dev_instance;
1315 struct sata_fsl_host_priv *host_priv = host->private_data;
1316 void __iomem *hcr_base = host_priv->hcr_base;
1317 u32 interrupt_enables;
1318 unsigned handled = 0;
1319 struct ata_port *ap;
1320
1321 /* ack. any pending IRQs for this controller/port */
1322 interrupt_enables = ioread32(hcr_base + HSTATUS);
1323 interrupt_enables &= 0x3F;
1324
1325 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1326
1327 if (!interrupt_enables)
1328 return IRQ_NONE;
1329
1330 spin_lock(&host->lock);
1331
1332 /* Assuming one port per host controller */
1333
1334 ap = host->ports[0];
1335 if (ap) {
1336 sata_fsl_host_intr(ap);
1337 } else {
Joe Perchesa44fec12011-04-15 15:51:58 -07001338 dev_warn(host->dev, "interrupt on disabled port 0\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +08001339 }
1340
1341 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1342 handled = 1;
1343
1344 spin_unlock(&host->lock);
1345
1346 return IRQ_RETVAL(handled);
1347}
1348
1349/*
1350 * Multiple ports are represented by multiple SATA controllers with
1351 * one port per controller
1352 */
1353static int sata_fsl_init_controller(struct ata_host *host)
1354{
1355 struct sata_fsl_host_priv *host_priv = host->private_data;
1356 void __iomem *hcr_base = host_priv->hcr_base;
1357 u32 temp;
1358
1359 /*
1360 * NOTE : We cannot bring the controller online before setting
1361 * the CHBA, hence main controller initialization is done as
1362 * part of the port_start() callback
1363 */
1364
Jerry Huang93272b12011-12-20 14:50:27 +08001365 /* sata controller to operate in enterprise mode */
1366 temp = ioread32(hcr_base + HCONTROL);
1367 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1368
Li Yangfaf0b2e2007-10-16 20:58:38 +08001369 /* ack. any pending IRQs for this controller/port */
1370 temp = ioread32(hcr_base + HSTATUS);
1371 if (temp & 0x3F)
1372 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1373
1374 /* Keep interrupts disabled on the controller */
1375 temp = ioread32(hcr_base + HCONTROL);
1376 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1377
1378 /* Disable interrupt coalescing control(icc), for the moment */
1379 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1380 iowrite32(0x01000000, hcr_base + ICC);
1381
1382 /* clear error registers, SError is cleared by libATA */
1383 iowrite32(0x00000FFFF, hcr_base + CE);
1384 iowrite32(0x00000FFFF, hcr_base + DE);
1385
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001386 /*
1387 * reset the number of command complete bits which will cause the
1388 * interrupt to be signaled
1389 */
1390 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1391 intr_coalescing_ticks);
1392
Li Yangfaf0b2e2007-10-16 20:58:38 +08001393 /*
1394 * host controller will be brought on-line, during xx_port_start()
1395 * callback, that should also initiate the OOB, COMINIT sequence
1396 */
1397
1398 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1399 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1400
1401 return 0;
1402}
1403
1404/*
1405 * scsi mid-layer and libata interface structures
1406 */
1407static struct scsi_host_template sata_fsl_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +09001408 ATA_NCQ_SHT("sata_fsl"),
Li Yangfaf0b2e2007-10-16 20:58:38 +08001409 .can_queue = SATA_FSL_QUEUE_DEPTH,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001410 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001411 .dma_boundary = ATA_DMA_BOUNDARY,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001412};
1413
Ashish Kalra034d8e82008-05-20 00:19:45 -05001414static struct ata_port_operations sata_fsl_ops = {
1415 .inherits = &sata_pmp_port_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +09001416
Ashish Kalraf90f6132009-07-29 21:15:49 +05301417 .qc_defer = ata_std_qc_defer,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001418 .qc_prep = sata_fsl_qc_prep,
1419 .qc_issue = sata_fsl_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09001420 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001421
1422 .scr_read = sata_fsl_scr_read,
1423 .scr_write = sata_fsl_scr_write,
1424
1425 .freeze = sata_fsl_freeze,
1426 .thaw = sata_fsl_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +09001427 .softreset = sata_fsl_softreset,
Jiang Yutanga0a74d12009-10-16 20:44:36 +04001428 .hardreset = sata_fsl_hardreset,
Ashish Kalra034d8e82008-05-20 00:19:45 -05001429 .pmp_softreset = sata_fsl_softreset,
1430 .error_handler = sata_fsl_error_handler,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001431 .post_internal_cmd = sata_fsl_post_internal_cmd,
1432
1433 .port_start = sata_fsl_port_start,
1434 .port_stop = sata_fsl_port_stop,
Ashish Kalra034d8e82008-05-20 00:19:45 -05001435
1436 .pmp_attach = sata_fsl_pmp_attach,
1437 .pmp_detach = sata_fsl_pmp_detach,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001438};
1439
1440static const struct ata_port_info sata_fsl_port_info[] = {
1441 {
1442 .flags = SATA_FSL_HOST_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +01001443 .pio_mask = ATA_PIO4,
1444 .udma_mask = ATA_UDMA6,
Li Yangfaf0b2e2007-10-16 20:58:38 +08001445 .port_ops = &sata_fsl_ops,
1446 },
1447};
1448
Grant Likely1c48a5c2011-02-17 02:43:24 -07001449static int sata_fsl_probe(struct platform_device *ofdev)
Li Yangfaf0b2e2007-10-16 20:58:38 +08001450{
Michal Sojkae4ac5222009-01-14 14:02:38 +01001451 int retval = -ENXIO;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001452 void __iomem *hcr_base = NULL;
1453 void __iomem *ssr_base = NULL;
1454 void __iomem *csr_base = NULL;
1455 struct sata_fsl_host_priv *host_priv = NULL;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001456 int irq;
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001457 struct ata_host *host = NULL;
Prabhakar Kushwaha578ca872011-03-07 09:28:10 +05301458 u32 temp;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001459
1460 struct ata_port_info pi = sata_fsl_port_info[0];
1461 const struct ata_port_info *ppi[] = { &pi, NULL };
1462
Joe Perchesa44fec12011-04-15 15:51:58 -07001463 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +08001464
Grant Likely61c7a082010-04-13 16:12:29 -07001465 hcr_base = of_iomap(ofdev->dev.of_node, 0);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001466 if (!hcr_base)
1467 goto error_exit_with_cleanup;
1468
1469 ssr_base = hcr_base + 0x100;
1470 csr_base = hcr_base + 0x140;
1471
Prabhakar Kushwaha578ca872011-03-07 09:28:10 +05301472 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1473 temp = ioread32(csr_base + TRANSCFG);
1474 temp = temp & 0xffffffe0;
1475 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1476 }
1477
Li Yangfaf0b2e2007-10-16 20:58:38 +08001478 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1479 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1480 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1481
1482 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1483 if (!host_priv)
1484 goto error_exit_with_cleanup;
1485
1486 host_priv->hcr_base = hcr_base;
1487 host_priv->ssr_base = ssr_base;
1488 host_priv->csr_base = csr_base;
1489
Grant Likely61c7a082010-04-13 16:12:29 -07001490 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001491 if (irq < 0) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001492 dev_err(&ofdev->dev, "invalid irq from platform\n");
Li Yangfaf0b2e2007-10-16 20:58:38 +08001493 goto error_exit_with_cleanup;
1494 }
Li Yang79b3edc2007-10-31 19:27:55 +08001495 host_priv->irq = irq;
Li Yangfaf0b2e2007-10-16 20:58:38 +08001496
Xulei2f957fc2011-01-19 17:07:29 +08001497 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1498 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1499 else
1500 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1501
Li Yangfaf0b2e2007-10-16 20:58:38 +08001502 /* allocate host structure */
1503 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001504 if (!host) {
1505 retval = -ENOMEM;
1506 goto error_exit_with_cleanup;
1507 }
Li Yangfaf0b2e2007-10-16 20:58:38 +08001508
1509 /* host->iomap is not used currently */
1510 host->private_data = host_priv;
1511
Li Yangfaf0b2e2007-10-16 20:58:38 +08001512 /* initialize host controller */
1513 sata_fsl_init_controller(host);
1514
1515 /*
1516 * Now, register with libATA core, this will also initiate the
1517 * device discovery process, invoking our port_start() handler &
1518 * error_handler() to execute a dummy Softreset EH session
1519 */
1520 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1521 &sata_fsl_sht);
1522
Jingoo Hand89995d2013-05-23 19:41:21 +09001523 platform_set_drvdata(ofdev, host);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001524
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001525 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1526 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1527 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1528 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1529 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1530 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1531 if (retval)
1532 goto error_exit_with_cleanup;
1533
Qiang Liu7551c402013-03-04 15:20:23 +08001534 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1535 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1536 sysfs_attr_init(&host_priv->rx_watermark.attr);
1537 host_priv->rx_watermark.attr.name = "rx_watermark";
1538 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1539 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1540 if (retval) {
1541 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1542 goto error_exit_with_cleanup;
1543 }
1544
Li Yangfaf0b2e2007-10-16 20:58:38 +08001545 return 0;
1546
1547error_exit_with_cleanup:
1548
Jingoo Hand89995d2013-05-23 19:41:21 +09001549 if (host)
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001550 ata_host_detach(host);
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001551
Li Yangfaf0b2e2007-10-16 20:58:38 +08001552 if (hcr_base)
1553 iounmap(hcr_base);
Syam Sidhardhanc99cc9a2013-02-25 04:44:07 +05301554 kfree(host_priv);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001555
1556 return retval;
1557}
1558
Grant Likely2dc11582010-08-06 09:25:50 -06001559static int sata_fsl_remove(struct platform_device *ofdev)
Li Yangfaf0b2e2007-10-16 20:58:38 +08001560{
Jingoo Hand89995d2013-05-23 19:41:21 +09001561 struct ata_host *host = platform_get_drvdata(ofdev);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001562 struct sata_fsl_host_priv *host_priv = host->private_data;
1563
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001564 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
Qiang Liu7551c402013-03-04 15:20:23 +08001565 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
Qiang Liu6b4b8fc2012-02-15 15:40:34 +08001566
Li Yangfaf0b2e2007-10-16 20:58:38 +08001567 ata_host_detach(host);
1568
Li Yang79b3edc2007-10-31 19:27:55 +08001569 irq_dispose_mapping(host_priv->irq);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001570 iounmap(host_priv->hcr_base);
1571 kfree(host_priv);
1572
1573 return 0;
1574}
1575
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +02001576#ifdef CONFIG_PM_SLEEP
Grant Likely2dc11582010-08-06 09:25:50 -06001577static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
Dave Liudc77ad42009-06-10 22:53:37 -05001578{
Jingoo Hand89995d2013-05-23 19:41:21 +09001579 struct ata_host *host = platform_get_drvdata(op);
Dave Liudc77ad42009-06-10 22:53:37 -05001580 return ata_host_suspend(host, state);
1581}
1582
Grant Likely2dc11582010-08-06 09:25:50 -06001583static int sata_fsl_resume(struct platform_device *op)
Dave Liudc77ad42009-06-10 22:53:37 -05001584{
Jingoo Hand89995d2013-05-23 19:41:21 +09001585 struct ata_host *host = platform_get_drvdata(op);
Dave Liudc77ad42009-06-10 22:53:37 -05001586 struct sata_fsl_host_priv *host_priv = host->private_data;
1587 int ret;
1588 void __iomem *hcr_base = host_priv->hcr_base;
1589 struct ata_port *ap = host->ports[0];
1590 struct sata_fsl_port_priv *pp = ap->private_data;
1591
1592 ret = sata_fsl_init_controller(host);
1593 if (ret) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001594 dev_err(&op->dev, "Error initializing hardware\n");
Dave Liudc77ad42009-06-10 22:53:37 -05001595 return ret;
1596 }
1597
1598 /* Recovery the CHBA register in host controller cmd register set */
1599 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1600
Jerry Huang93272b12011-12-20 14:50:27 +08001601 iowrite32((ioread32(hcr_base + HCONTROL)
1602 | HCONTROL_ONLINE_PHY_RST
1603 | HCONTROL_SNOOP_ENABLE
1604 | HCONTROL_PMP_ATTACHED),
1605 hcr_base + HCONTROL);
1606
Dave Liudc77ad42009-06-10 22:53:37 -05001607 ata_host_resume(host);
1608 return 0;
1609}
1610#endif
1611
Li Yangfaf0b2e2007-10-16 20:58:38 +08001612static struct of_device_id fsl_sata_match[] = {
1613 {
Kim Phillips96ce1b62008-03-28 10:51:33 -05001614 .compatible = "fsl,pq-sata",
Li Yangfaf0b2e2007-10-16 20:58:38 +08001615 },
Xulei2f957fc2011-01-19 17:07:29 +08001616 {
1617 .compatible = "fsl,pq-sata-v2",
1618 },
Li Yangfaf0b2e2007-10-16 20:58:38 +08001619 {},
1620};
1621
1622MODULE_DEVICE_TABLE(of, fsl_sata_match);
1623
Grant Likely1c48a5c2011-02-17 02:43:24 -07001624static struct platform_driver fsl_sata_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001625 .driver = {
1626 .name = "fsl-sata",
1627 .owner = THIS_MODULE,
1628 .of_match_table = fsl_sata_match,
1629 },
Li Yangfaf0b2e2007-10-16 20:58:38 +08001630 .probe = sata_fsl_probe,
1631 .remove = sata_fsl_remove,
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +02001632#ifdef CONFIG_PM_SLEEP
Dave Liudc77ad42009-06-10 22:53:37 -05001633 .suspend = sata_fsl_suspend,
1634 .resume = sata_fsl_resume,
1635#endif
Li Yangfaf0b2e2007-10-16 20:58:38 +08001636};
1637
Axel Lin99c8ea32011-11-27 14:44:26 +08001638module_platform_driver(fsl_sata_driver);
Li Yangfaf0b2e2007-10-16 20:58:38 +08001639
1640MODULE_LICENSE("GPL");
1641MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1642MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1643MODULE_VERSION("1.10");