blob: 61eb6d77dac7f507403578a283eade305378f566 [file] [log] [blame]
Vladimir Barinov163cf81d2013-02-20 23:10:29 +03001/*
2 * Renesas R-Car SATA driver
3 *
4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/ata.h>
17#include <linux/libata.h>
Valentine Barshake67adb42013-11-08 16:09:29 +040018#include <linux/of_device.h>
Vladimir Barinov163cf81d2013-02-20 23:10:29 +030019#include <linux/platform_device.h>
20#include <linux/clk.h>
Sachin Kamat2de1d5e2013-04-04 14:56:36 +053021#include <linux/err.h>
Vladimir Barinov163cf81d2013-02-20 23:10:29 +030022
23#define DRV_NAME "sata_rcar"
24
25/* SH-Navi2G/ATAPI-ATA compatible task registers */
26#define DATA_REG 0x100
27#define SDEVCON_REG 0x138
28
29/* SH-Navi2G/ATAPI module compatible control registers */
30#define ATAPI_CONTROL1_REG 0x180
31#define ATAPI_STATUS_REG 0x184
32#define ATAPI_INT_ENABLE_REG 0x188
33#define ATAPI_DTB_ADR_REG 0x198
34#define ATAPI_DMA_START_ADR_REG 0x19C
35#define ATAPI_DMA_TRANS_CNT_REG 0x1A0
36#define ATAPI_CONTROL2_REG 0x1A4
37#define ATAPI_SIG_ST_REG 0x1B0
38#define ATAPI_BYTE_SWAP_REG 0x1BC
39
40/* ATAPI control 1 register (ATAPI_CONTROL1) bits */
41#define ATAPI_CONTROL1_ISM BIT(16)
42#define ATAPI_CONTROL1_DTA32M BIT(11)
43#define ATAPI_CONTROL1_RESET BIT(7)
44#define ATAPI_CONTROL1_DESE BIT(3)
45#define ATAPI_CONTROL1_RW BIT(2)
46#define ATAPI_CONTROL1_STOP BIT(1)
47#define ATAPI_CONTROL1_START BIT(0)
48
49/* ATAPI status register (ATAPI_STATUS) bits */
50#define ATAPI_STATUS_SATAINT BIT(11)
51#define ATAPI_STATUS_DNEND BIT(6)
52#define ATAPI_STATUS_DEVTRM BIT(5)
53#define ATAPI_STATUS_DEVINT BIT(4)
54#define ATAPI_STATUS_ERR BIT(2)
55#define ATAPI_STATUS_NEND BIT(1)
56#define ATAPI_STATUS_ACT BIT(0)
57
58/* Interrupt enable register (ATAPI_INT_ENABLE) bits */
59#define ATAPI_INT_ENABLE_SATAINT BIT(11)
60#define ATAPI_INT_ENABLE_DNEND BIT(6)
61#define ATAPI_INT_ENABLE_DEVTRM BIT(5)
62#define ATAPI_INT_ENABLE_DEVINT BIT(4)
63#define ATAPI_INT_ENABLE_ERR BIT(2)
64#define ATAPI_INT_ENABLE_NEND BIT(1)
65#define ATAPI_INT_ENABLE_ACT BIT(0)
66
67/* Access control registers for physical layer control register */
68#define SATAPHYADDR_REG 0x200
69#define SATAPHYWDATA_REG 0x204
70#define SATAPHYACCEN_REG 0x208
71#define SATAPHYRESET_REG 0x20C
72#define SATAPHYRDATA_REG 0x210
73#define SATAPHYACK_REG 0x214
74
75/* Physical layer control address command register (SATAPHYADDR) bits */
76#define SATAPHYADDR_PHYRATEMODE BIT(10)
77#define SATAPHYADDR_PHYCMD_READ BIT(9)
78#define SATAPHYADDR_PHYCMD_WRITE BIT(8)
79
80/* Physical layer control enable register (SATAPHYACCEN) bits */
81#define SATAPHYACCEN_PHYLANE BIT(0)
82
83/* Physical layer control reset register (SATAPHYRESET) bits */
84#define SATAPHYRESET_PHYRST BIT(1)
85#define SATAPHYRESET_PHYSRES BIT(0)
86
87/* Physical layer control acknowledge register (SATAPHYACK) bits */
88#define SATAPHYACK_PHYACK BIT(0)
89
90/* Serial-ATA HOST control registers */
91#define BISTCONF_REG 0x102C
92#define SDATA_REG 0x1100
93#define SSDEVCON_REG 0x1204
94
95#define SCRSSTS_REG 0x1400
96#define SCRSERR_REG 0x1404
97#define SCRSCON_REG 0x1408
98#define SCRSACT_REG 0x140C
99
100#define SATAINTSTAT_REG 0x1508
101#define SATAINTMASK_REG 0x150C
102
103/* SATA INT status register (SATAINTSTAT) bits */
104#define SATAINTSTAT_SERR BIT(3)
105#define SATAINTSTAT_ATA BIT(0)
106
107/* SATA INT mask register (SATAINTSTAT) bits */
108#define SATAINTMASK_SERRMSK BIT(3)
109#define SATAINTMASK_ERRMSK BIT(2)
110#define SATAINTMASK_ERRCRTMSK BIT(1)
111#define SATAINTMASK_ATAMSK BIT(0)
112
113#define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
114 SATAINTMASK_ATAMSK)
115
116/* Physical Layer Control Registers */
117#define SATAPCTLR1_REG 0x43
118#define SATAPCTLR2_REG 0x52
119#define SATAPCTLR3_REG 0x5A
120#define SATAPCTLR4_REG 0x60
121
122/* Descriptor table word 0 bit (when DTA32M = 1) */
123#define SATA_RCAR_DTEND BIT(0)
124
Sergei Shtylyov8bfbeed2013-05-28 02:45:08 +0400125#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
126
Valentine Barshake67adb42013-11-08 16:09:29 +0400127/* Gen2 Physical Layer Control Registers */
128#define RCAR_GEN2_PHY_CTL1_REG 0x1704
129#define RCAR_GEN2_PHY_CTL1 0x34180002
130#define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */
131
132#define RCAR_GEN2_PHY_CTL2_REG 0x170C
133#define RCAR_GEN2_PHY_CTL2 0x00002303
134
135#define RCAR_GEN2_PHY_CTL3_REG 0x171C
136#define RCAR_GEN2_PHY_CTL3 0x000B0194
137
138#define RCAR_GEN2_PHY_CTL4_REG 0x1724
139#define RCAR_GEN2_PHY_CTL4 0x00030994
140
141#define RCAR_GEN2_PHY_CTL5_REG 0x1740
142#define RCAR_GEN2_PHY_CTL5 0x03004001
143#define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */
144#define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */
145
146enum sata_rcar_type {
147 RCAR_GEN1_SATA,
148 RCAR_GEN2_SATA,
149};
150
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300151struct sata_rcar_priv {
152 void __iomem *base;
153 struct clk *clk;
Valentine Barshake67adb42013-11-08 16:09:29 +0400154 enum sata_rcar_type type;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300155};
156
Valentine Barshake67adb42013-11-08 16:09:29 +0400157static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300158{
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400159 void __iomem *base = priv->base;
160
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300161 /* idle state */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400162 iowrite32(0, base + SATAPHYADDR_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300163 /* reset */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400164 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300165 udelay(10);
166 /* deassert reset */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400167 iowrite32(0, base + SATAPHYRESET_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300168}
169
Valentine Barshake67adb42013-11-08 16:09:29 +0400170static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
171 u32 val, int group)
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300172{
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400173 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300174 int timeout;
175
176 /* deassert reset */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400177 iowrite32(0, base + SATAPHYRESET_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300178 /* lane 1 */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400179 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300180 /* write phy register value */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400181 iowrite32(val, base + SATAPHYWDATA_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300182 /* set register group */
183 if (group)
184 reg |= SATAPHYADDR_PHYRATEMODE;
185 /* write command */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400186 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300187 /* wait for ack */
188 for (timeout = 0; timeout < 100; timeout++) {
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400189 val = ioread32(base + SATAPHYACK_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300190 if (val & SATAPHYACK_PHYACK)
191 break;
192 }
193 if (timeout >= 100)
194 pr_err("%s timeout\n", __func__);
195 /* idle state */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400196 iowrite32(0, base + SATAPHYADDR_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300197}
198
Valentine Barshake67adb42013-11-08 16:09:29 +0400199static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
200{
201 sata_rcar_gen1_phy_preinit(priv);
202 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
203 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
204 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
205 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
206 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
207 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
208}
209
210static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
211{
212 void __iomem *base = priv->base;
213
214 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
215 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
216 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
217 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
218 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
219 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
220}
221
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300222static void sata_rcar_freeze(struct ata_port *ap)
223{
224 struct sata_rcar_priv *priv = ap->host->private_data;
225
226 /* mask */
227 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
228
229 ata_sff_freeze(ap);
230}
231
232static void sata_rcar_thaw(struct ata_port *ap)
233{
234 struct sata_rcar_priv *priv = ap->host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400235 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300236
237 /* ack */
Tejun Heo5a0a6a42013-07-02 19:54:16 -0700238 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300239
240 ata_sff_thaw(ap);
241
242 /* unmask */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400243 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300244}
245
246static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
247{
248 u16 *ptr = buffer;
249
250 while (count--) {
251 u16 data = ioread32(reg);
252
253 *ptr++ = data;
254 }
255}
256
257static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
258{
259 const u16 *ptr = buffer;
260
261 while (count--)
262 iowrite32(*ptr++, reg);
263}
264
265static u8 sata_rcar_check_status(struct ata_port *ap)
266{
267 return ioread32(ap->ioaddr.status_addr);
268}
269
270static u8 sata_rcar_check_altstatus(struct ata_port *ap)
271{
272 return ioread32(ap->ioaddr.altstatus_addr);
273}
274
275static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
276{
277 iowrite32(ctl, ap->ioaddr.ctl_addr);
278}
279
280static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
281{
282 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
283 ata_sff_pause(ap); /* needed; also flushes, for mmio */
284}
285
286static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
287 unsigned int device)
288{
289 struct ata_ioports *ioaddr = &ap->ioaddr;
290 u8 nsect, lbal;
291
292 sata_rcar_dev_select(ap, device);
293
294 iowrite32(0x55, ioaddr->nsect_addr);
295 iowrite32(0xaa, ioaddr->lbal_addr);
296
297 iowrite32(0xaa, ioaddr->nsect_addr);
298 iowrite32(0x55, ioaddr->lbal_addr);
299
300 iowrite32(0x55, ioaddr->nsect_addr);
301 iowrite32(0xaa, ioaddr->lbal_addr);
302
303 nsect = ioread32(ioaddr->nsect_addr);
304 lbal = ioread32(ioaddr->lbal_addr);
305
306 if (nsect == 0x55 && lbal == 0xaa)
307 return 1; /* found a device */
308
309 return 0; /* nothing found */
310}
311
312static int sata_rcar_wait_after_reset(struct ata_link *link,
313 unsigned long deadline)
314{
315 struct ata_port *ap = link->ap;
316
317 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
318
319 return ata_sff_wait_ready(link, deadline);
320}
321
322static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
323{
324 struct ata_ioports *ioaddr = &ap->ioaddr;
325
326 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
327
328 /* software reset. causes dev0 to be selected */
329 iowrite32(ap->ctl, ioaddr->ctl_addr);
330 udelay(20);
331 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
332 udelay(20);
333 iowrite32(ap->ctl, ioaddr->ctl_addr);
334 ap->last_ctl = ap->ctl;
335
336 /* wait the port to become ready */
337 return sata_rcar_wait_after_reset(&ap->link, deadline);
338}
339
340static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
341 unsigned long deadline)
342{
343 struct ata_port *ap = link->ap;
344 unsigned int devmask = 0;
345 int rc;
346 u8 err;
347
348 /* determine if device 0 is present */
349 if (sata_rcar_ata_devchk(ap, 0))
350 devmask |= 1 << 0;
351
352 /* issue bus reset */
353 DPRINTK("about to softreset, devmask=%x\n", devmask);
354 rc = sata_rcar_bus_softreset(ap, deadline);
355 /* if link is occupied, -ENODEV too is an error */
356 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
357 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
358 return rc;
359 }
360
361 /* determine by signature whether we have ATA or ATAPI devices */
362 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
363
364 DPRINTK("classes[0]=%u\n", classes[0]);
365 return 0;
366}
367
368static void sata_rcar_tf_load(struct ata_port *ap,
369 const struct ata_taskfile *tf)
370{
371 struct ata_ioports *ioaddr = &ap->ioaddr;
372 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
373
374 if (tf->ctl != ap->last_ctl) {
375 iowrite32(tf->ctl, ioaddr->ctl_addr);
376 ap->last_ctl = tf->ctl;
377 ata_wait_idle(ap);
378 }
379
380 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
381 iowrite32(tf->hob_feature, ioaddr->feature_addr);
382 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
383 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
384 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
385 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
386 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
387 tf->hob_feature,
388 tf->hob_nsect,
389 tf->hob_lbal,
390 tf->hob_lbam,
391 tf->hob_lbah);
392 }
393
394 if (is_addr) {
395 iowrite32(tf->feature, ioaddr->feature_addr);
396 iowrite32(tf->nsect, ioaddr->nsect_addr);
397 iowrite32(tf->lbal, ioaddr->lbal_addr);
398 iowrite32(tf->lbam, ioaddr->lbam_addr);
399 iowrite32(tf->lbah, ioaddr->lbah_addr);
400 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
401 tf->feature,
402 tf->nsect,
403 tf->lbal,
404 tf->lbam,
405 tf->lbah);
406 }
407
408 if (tf->flags & ATA_TFLAG_DEVICE) {
409 iowrite32(tf->device, ioaddr->device_addr);
410 VPRINTK("device 0x%X\n", tf->device);
411 }
412
413 ata_wait_idle(ap);
414}
415
416static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
417{
418 struct ata_ioports *ioaddr = &ap->ioaddr;
419
420 tf->command = sata_rcar_check_status(ap);
421 tf->feature = ioread32(ioaddr->error_addr);
422 tf->nsect = ioread32(ioaddr->nsect_addr);
423 tf->lbal = ioread32(ioaddr->lbal_addr);
424 tf->lbam = ioread32(ioaddr->lbam_addr);
425 tf->lbah = ioread32(ioaddr->lbah_addr);
426 tf->device = ioread32(ioaddr->device_addr);
427
428 if (tf->flags & ATA_TFLAG_LBA48) {
429 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
430 tf->hob_feature = ioread32(ioaddr->error_addr);
431 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
432 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
433 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
434 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
435 iowrite32(tf->ctl, ioaddr->ctl_addr);
436 ap->last_ctl = tf->ctl;
437 }
438}
439
440static void sata_rcar_exec_command(struct ata_port *ap,
441 const struct ata_taskfile *tf)
442{
443 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
444
445 iowrite32(tf->command, ap->ioaddr.command_addr);
446 ata_sff_pause(ap);
447}
448
449static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
450 unsigned char *buf,
451 unsigned int buflen, int rw)
452{
453 struct ata_port *ap = dev->link->ap;
454 void __iomem *data_addr = ap->ioaddr.data_addr;
455 unsigned int words = buflen >> 1;
456
457 /* Transfer multiple of 2 bytes */
458 if (rw == READ)
459 sata_rcar_ioread16_rep(data_addr, buf, words);
460 else
461 sata_rcar_iowrite16_rep(data_addr, buf, words);
462
463 /* Transfer trailing byte, if any. */
464 if (unlikely(buflen & 0x01)) {
465 unsigned char pad[2] = { };
466
467 /* Point buf to the tail of buffer */
468 buf += buflen - 1;
469
470 /*
471 * Use io*16_rep() accessors here as well to avoid pointlessly
472 * swapping bytes to and from on the big endian machines...
473 */
474 if (rw == READ) {
475 sata_rcar_ioread16_rep(data_addr, pad, 1);
476 *buf = pad[0];
477 } else {
478 pad[0] = *buf;
479 sata_rcar_iowrite16_rep(data_addr, pad, 1);
480 }
481 words++;
482 }
483
484 return words << 1;
485}
486
487static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
488{
489 int count;
490 struct ata_port *ap;
491
492 /* We only need to flush incoming data when a command was running */
493 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
494 return;
495
496 ap = qc->ap;
497 /* Drain up to 64K of data before we give up this recovery method */
498 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
499 count < 65536; count += 2)
500 ioread32(ap->ioaddr.data_addr);
501
502 /* Can become DEBUG later */
503 if (count)
504 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
505}
506
507static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
508 u32 *val)
509{
510 if (sc_reg > SCR_ACTIVE)
511 return -EINVAL;
512
513 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
514 return 0;
515}
516
517static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
518 u32 val)
519{
520 if (sc_reg > SCR_ACTIVE)
521 return -EINVAL;
522
523 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
524 return 0;
525}
526
527static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
528{
529 struct ata_port *ap = qc->ap;
530 struct ata_bmdma_prd *prd = ap->bmdma_prd;
531 struct scatterlist *sg;
Sergei Shtylyov333279c2013-05-28 02:43:23 +0400532 unsigned int si;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300533
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300534 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Sergei Shtylyov333279c2013-05-28 02:43:23 +0400535 u32 addr, sg_len;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300536
537 /*
538 * Note: h/w doesn't support 64-bit, so we unconditionally
539 * truncate dma_addr_t to u32.
540 */
541 addr = (u32)sg_dma_address(sg);
542 sg_len = sg_dma_len(sg);
543
Sergei Shtylyov333279c2013-05-28 02:43:23 +0400544 prd[si].addr = cpu_to_le32(addr);
545 prd[si].flags_len = cpu_to_le32(sg_len);
546 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300547 }
548
549 /* end-of-table flag */
Sergei Shtylyov333279c2013-05-28 02:43:23 +0400550 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300551}
552
553static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
554{
555 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
556 return;
557
558 sata_rcar_bmdma_fill_sg(qc);
559}
560
561static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
562{
563 struct ata_port *ap = qc->ap;
564 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300565 struct sata_rcar_priv *priv = ap->host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400566 void __iomem *base = priv->base;
567 u32 dmactl;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300568
569 /* load PRD table addr. */
570 mb(); /* make sure PRD table writes are visible to controller */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400571 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300572
573 /* specify data direction, triple-check start bit is clear */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400574 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300575 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
576 if (dmactl & ATAPI_CONTROL1_START) {
577 dmactl &= ~ATAPI_CONTROL1_START;
578 dmactl |= ATAPI_CONTROL1_STOP;
579 }
580 if (!rw)
581 dmactl |= ATAPI_CONTROL1_RW;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400582 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300583
584 /* issue r/w command */
585 ap->ops->sff_exec_command(ap, &qc->tf);
586}
587
588static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
589{
590 struct ata_port *ap = qc->ap;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300591 struct sata_rcar_priv *priv = ap->host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400592 void __iomem *base = priv->base;
593 u32 dmactl;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300594
595 /* start host DMA transaction */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400596 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
Sergei Shtylyovdf7e1312013-05-21 23:07:54 +0400597 dmactl &= ~ATAPI_CONTROL1_STOP;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300598 dmactl |= ATAPI_CONTROL1_START;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400599 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300600}
601
602static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
603{
604 struct ata_port *ap = qc->ap;
605 struct sata_rcar_priv *priv = ap->host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400606 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300607 u32 dmactl;
608
609 /* force termination of DMA transfer if active */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400610 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300611 if (dmactl & ATAPI_CONTROL1_START) {
612 dmactl &= ~ATAPI_CONTROL1_START;
613 dmactl |= ATAPI_CONTROL1_STOP;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400614 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300615 }
616
617 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
618 ata_sff_dma_pause(ap);
619}
620
621static u8 sata_rcar_bmdma_status(struct ata_port *ap)
622{
623 struct sata_rcar_priv *priv = ap->host->private_data;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300624 u8 host_stat = 0;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400625 u32 status;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300626
627 status = ioread32(priv->base + ATAPI_STATUS_REG);
628 if (status & ATAPI_STATUS_DEVINT)
629 host_stat |= ATA_DMA_INTR;
630 if (status & ATAPI_STATUS_ACT)
631 host_stat |= ATA_DMA_ACTIVE;
632
633 return host_stat;
634}
635
636static struct scsi_host_template sata_rcar_sht = {
Sergei Shtylyov8bfbeed2013-05-28 02:45:08 +0400637 ATA_BASE_SHT(DRV_NAME),
638 /*
639 * This controller allows transfer chunks up to 512MB which cross 64KB
640 * boundaries, therefore the DMA limits are more relaxed than standard
641 * ATA SFF.
642 */
643 .sg_tablesize = ATA_MAX_PRD,
644 .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300645};
646
647static struct ata_port_operations sata_rcar_port_ops = {
648 .inherits = &ata_bmdma_port_ops,
649
650 .freeze = sata_rcar_freeze,
651 .thaw = sata_rcar_thaw,
652 .softreset = sata_rcar_softreset,
653
654 .scr_read = sata_rcar_scr_read,
655 .scr_write = sata_rcar_scr_write,
656
657 .sff_dev_select = sata_rcar_dev_select,
658 .sff_set_devctl = sata_rcar_set_devctl,
659 .sff_check_status = sata_rcar_check_status,
660 .sff_check_altstatus = sata_rcar_check_altstatus,
661 .sff_tf_load = sata_rcar_tf_load,
662 .sff_tf_read = sata_rcar_tf_read,
663 .sff_exec_command = sata_rcar_exec_command,
664 .sff_data_xfer = sata_rcar_data_xfer,
665 .sff_drain_fifo = sata_rcar_drain_fifo,
666
667 .qc_prep = sata_rcar_qc_prep,
668
669 .bmdma_setup = sata_rcar_bmdma_setup,
670 .bmdma_start = sata_rcar_bmdma_start,
671 .bmdma_stop = sata_rcar_bmdma_stop,
672 .bmdma_status = sata_rcar_bmdma_status,
673};
674
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400675static void sata_rcar_serr_interrupt(struct ata_port *ap)
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300676{
677 struct sata_rcar_priv *priv = ap->host->private_data;
678 struct ata_eh_info *ehi = &ap->link.eh_info;
679 int freeze = 0;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300680 u32 serror;
681
682 serror = ioread32(priv->base + SCRSERR_REG);
683 if (!serror)
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400684 return;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300685
686 DPRINTK("SError @host_intr: 0x%x\n", serror);
687
688 /* first, analyze and record host port events */
689 ata_ehi_clear_desc(ehi);
690
691 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
692 /* Setup a soft-reset EH action */
693 ata_ehi_hotplugged(ehi);
694 ata_ehi_push_desc(ehi, "%s", "hotplug");
695
696 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300697 }
698
699 /* freeze or abort */
700 if (freeze)
701 ata_port_freeze(ap);
702 else
703 ata_port_abort(ap);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300704}
705
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400706static void sata_rcar_ata_interrupt(struct ata_port *ap)
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300707{
708 struct ata_queued_cmd *qc;
709 int handled = 0;
710
711 qc = ata_qc_from_tag(ap, ap->link.active_tag);
712 if (qc)
713 handled |= ata_bmdma_port_intr(ap, qc);
714
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400715 /* be sure to clear ATA interrupt */
716 if (!handled)
717 sata_rcar_check_status(ap);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300718}
719
720static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
721{
722 struct ata_host *host = dev_instance;
723 struct sata_rcar_priv *priv = host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400724 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300725 unsigned int handled = 0;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400726 struct ata_port *ap;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300727 u32 sataintstat;
728 unsigned long flags;
729
730 spin_lock_irqsave(&host->lock, flags);
731
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400732 sataintstat = ioread32(base + SATAINTSTAT_REG);
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400733 sataintstat &= SATA_RCAR_INT_MASK;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300734 if (!sataintstat)
735 goto done;
736 /* ack */
Tejun Heo5a0a6a42013-07-02 19:54:16 -0700737 iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300738
739 ap = host->ports[0];
740
741 if (sataintstat & SATAINTSTAT_ATA)
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400742 sata_rcar_ata_interrupt(ap);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300743
744 if (sataintstat & SATAINTSTAT_SERR)
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400745 sata_rcar_serr_interrupt(ap);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300746
Sergei Shtylyov52a2a102013-06-01 02:38:35 +0400747 handled = 1;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300748done:
749 spin_unlock_irqrestore(&host->lock, flags);
750
751 return IRQ_RETVAL(handled);
752}
753
754static void sata_rcar_setup_port(struct ata_host *host)
755{
756 struct ata_port *ap = host->ports[0];
757 struct ata_ioports *ioaddr = &ap->ioaddr;
758 struct sata_rcar_priv *priv = host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400759 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300760
761 ap->ops = &sata_rcar_port_ops;
762 ap->pio_mask = ATA_PIO4;
763 ap->udma_mask = ATA_UDMA6;
764 ap->flags |= ATA_FLAG_SATA;
765
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400766 ioaddr->cmd_addr = base + SDATA_REG;
767 ioaddr->ctl_addr = base + SSDEVCON_REG;
768 ioaddr->scr_addr = base + SCRSSTS_REG;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300769 ioaddr->altstatus_addr = ioaddr->ctl_addr;
770
771 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
772 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
773 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
774 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
775 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
776 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
777 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
778 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
779 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
780 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
781}
782
783static void sata_rcar_init_controller(struct ata_host *host)
784{
785 struct sata_rcar_priv *priv = host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400786 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300787 u32 val;
788
789 /* reset and setup phy */
Valentine Barshake67adb42013-11-08 16:09:29 +0400790 switch (priv->type) {
791 case RCAR_GEN1_SATA:
792 sata_rcar_gen1_phy_init(priv);
793 break;
794 case RCAR_GEN2_SATA:
795 sata_rcar_gen2_phy_init(priv);
796 break;
797 default:
798 dev_warn(host->dev, "SATA phy is not initialized\n");
799 break;
800 }
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300801
802 /* SATA-IP reset state */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400803 val = ioread32(base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300804 val |= ATAPI_CONTROL1_RESET;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400805 iowrite32(val, base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300806
807 /* ISM mode, PRD mode, DTEND flag at bit 0 */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400808 val = ioread32(base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300809 val |= ATAPI_CONTROL1_ISM;
810 val |= ATAPI_CONTROL1_DESE;
811 val |= ATAPI_CONTROL1_DTA32M;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400812 iowrite32(val, base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300813
814 /* Release the SATA-IP from the reset state */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400815 val = ioread32(base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300816 val &= ~ATAPI_CONTROL1_RESET;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400817 iowrite32(val, base + ATAPI_CONTROL1_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300818
819 /* ack and mask */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400820 iowrite32(0, base + SATAINTSTAT_REG);
821 iowrite32(0x7ff, base + SATAINTMASK_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300822 /* enable interrupts */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400823 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300824}
825
Valentine Barshake67adb42013-11-08 16:09:29 +0400826static struct of_device_id sata_rcar_match[] = {
827 {
828 /* Deprecated by "renesas,sata-r8a7779" */
829 .compatible = "renesas,rcar-sata",
830 .data = (void *)RCAR_GEN1_SATA,
831 },
832 {
833 .compatible = "renesas,sata-r8a7779",
834 .data = (void *)RCAR_GEN1_SATA,
835 },
836 {
837 .compatible = "renesas,sata-r8a7790",
838 .data = (void *)RCAR_GEN2_SATA
839 },
840 {
841 .compatible = "renesas,sata-r8a7791",
842 .data = (void *)RCAR_GEN2_SATA
843 },
844 { },
845};
846MODULE_DEVICE_TABLE(of, sata_rcar_match);
847
848static const struct platform_device_id sata_rcar_id_table[] = {
849 { "sata_rcar", RCAR_GEN1_SATA }, /* Deprecated by "sata-r8a7779" */
850 { "sata-r8a7779", RCAR_GEN1_SATA },
851 { "sata-r8a7790", RCAR_GEN2_SATA },
852 { "sata-r8a7791", RCAR_GEN2_SATA },
853 { },
854};
855MODULE_DEVICE_TABLE(platform, sata_rcar_id_table);
856
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300857static int sata_rcar_probe(struct platform_device *pdev)
858{
Valentine Barshake67adb42013-11-08 16:09:29 +0400859 const struct of_device_id *of_id;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300860 struct ata_host *host;
861 struct sata_rcar_priv *priv;
862 struct resource *mem;
863 int irq;
864 int ret = 0;
865
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300866 irq = platform_get_irq(pdev, 0);
867 if (irq <= 0)
868 return -EINVAL;
869
870 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
871 GFP_KERNEL);
872 if (!priv)
873 return -ENOMEM;
874
Valentine Barshake67adb42013-11-08 16:09:29 +0400875 of_id = of_match_device(sata_rcar_match, &pdev->dev);
876 if (of_id)
877 priv->type = (enum sata_rcar_type)of_id->data;
878 else
879 priv->type = platform_get_device_id(pdev)->driver_data;
880
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300881 priv->clk = devm_clk_get(&pdev->dev, NULL);
882 if (IS_ERR(priv->clk)) {
883 dev_err(&pdev->dev, "failed to get access to sata clock\n");
884 return PTR_ERR(priv->clk);
885 }
Laurent Pinchart329b4282013-10-28 23:49:21 +0100886 clk_prepare_enable(priv->clk);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300887
888 host = ata_host_alloc(&pdev->dev, 1);
889 if (!host) {
890 dev_err(&pdev->dev, "ata_host_alloc failed\n");
891 ret = -ENOMEM;
892 goto cleanup;
893 }
894
895 host->private_data = priv;
896
Julia Lawall4a9b7f92013-08-14 11:11:31 +0200897 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Sachin Kamat2de1d5e2013-04-04 14:56:36 +0530898 priv->base = devm_ioremap_resource(&pdev->dev, mem);
899 if (IS_ERR(priv->base)) {
900 ret = PTR_ERR(priv->base);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300901 goto cleanup;
902 }
903
904 /* setup port */
905 sata_rcar_setup_port(host);
906
907 /* initialize host controller */
908 sata_rcar_init_controller(host);
909
910 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
911 &sata_rcar_sht);
912 if (!ret)
913 return 0;
914
915cleanup:
Laurent Pinchart329b4282013-10-28 23:49:21 +0100916 clk_disable_unprepare(priv->clk);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300917
918 return ret;
919}
920
921static int sata_rcar_remove(struct platform_device *pdev)
922{
Jingoo Hand89995d2013-05-23 19:41:21 +0900923 struct ata_host *host = platform_get_drvdata(pdev);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300924 struct sata_rcar_priv *priv = host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400925 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300926
927 ata_host_detach(host);
928
929 /* disable interrupts */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400930 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300931 /* ack and mask */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400932 iowrite32(0, base + SATAINTSTAT_REG);
933 iowrite32(0x7ff, base + SATAINTMASK_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300934
Laurent Pinchart329b4282013-10-28 23:49:21 +0100935 clk_disable_unprepare(priv->clk);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300936
937 return 0;
938}
939
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +0200940#ifdef CONFIG_PM_SLEEP
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300941static int sata_rcar_suspend(struct device *dev)
942{
943 struct ata_host *host = dev_get_drvdata(dev);
944 struct sata_rcar_priv *priv = host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400945 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300946 int ret;
947
948 ret = ata_host_suspend(host, PMSG_SUSPEND);
949 if (!ret) {
950 /* disable interrupts */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400951 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300952 /* mask */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400953 iowrite32(0x7ff, base + SATAINTMASK_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300954
Laurent Pinchart329b4282013-10-28 23:49:21 +0100955 clk_disable_unprepare(priv->clk);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300956 }
957
958 return ret;
959}
960
961static int sata_rcar_resume(struct device *dev)
962{
963 struct ata_host *host = dev_get_drvdata(dev);
964 struct sata_rcar_priv *priv = host->private_data;
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400965 void __iomem *base = priv->base;
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300966
Laurent Pinchart329b4282013-10-28 23:49:21 +0100967 clk_prepare_enable(priv->clk);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300968
969 /* ack and mask */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400970 iowrite32(0, base + SATAINTSTAT_REG);
971 iowrite32(0x7ff, base + SATAINTMASK_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300972 /* enable interrupts */
Sergei Shtylyov1b20f6a2013-05-28 02:46:41 +0400973 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300974
975 ata_host_resume(host);
976
977 return 0;
978}
979
980static const struct dev_pm_ops sata_rcar_pm_ops = {
981 .suspend = sata_rcar_suspend,
982 .resume = sata_rcar_resume,
983};
984#endif
985
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300986static struct platform_driver sata_rcar_driver = {
987 .probe = sata_rcar_probe,
988 .remove = sata_rcar_remove,
Valentine Barshake67adb42013-11-08 16:09:29 +0400989 .id_table = sata_rcar_id_table,
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300990 .driver = {
991 .name = DRV_NAME,
992 .owner = THIS_MODULE,
993 .of_match_table = sata_rcar_match,
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +0200994#ifdef CONFIG_PM_SLEEP
Vladimir Barinov163cf81d2013-02-20 23:10:29 +0300995 .pm = &sata_rcar_pm_ops,
996#endif
997 },
998};
999
1000module_platform_driver(sata_rcar_driver);
1001
1002MODULE_LICENSE("GPL");
1003MODULE_AUTHOR("Vladimir Barinov");
1004MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");