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Mika Westerberg1f5a3712011-09-21 13:03:07 +02001/*
2 * Driver for Intel MSIC
3 *
4 * Copyright (C) 2011, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
Thierry Reding6c2db1c2013-01-21 11:09:09 +010012#include <linux/err.h>
Mika Westerberg1f5a3712011-09-21 13:03:07 +020013#include <linux/gpio.h>
Mika Westerberg5f6cb762011-10-21 11:56:26 +030014#include <linux/io.h>
Mika Westerberg1f5a3712011-09-21 13:03:07 +020015#include <linux/module.h>
16#include <linux/mfd/core.h>
17#include <linux/mfd/intel_msic.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20
21#include <asm/intel_scu_ipc.h>
22
23#define MSIC_VENDOR(id) ((id >> 6) & 3)
24#define MSIC_VERSION(id) (id & 0x3f)
25#define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7))
26#define MSIC_MINOR(id) (id & 7)
27
28/*
29 * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
Antonio Ospiteb39fc892014-06-04 14:03:46 +020030 * Since IRQ block starts from address 0x002 we need to subtract that from
Mika Westerberg1f5a3712011-09-21 13:03:07 +020031 * the actual IRQ status register address.
32 */
33#define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
34#define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)
35
36/*
37 * The SCU hardware has limitation of 16 bytes per read/write buffer on
38 * Medfield.
39 */
40#define SCU_IPC_RWBUF_LIMIT 16
41
42/**
43 * struct intel_msic - an MSIC MFD instance
44 * @pdev: pointer to the platform device
45 * @vendor: vendor ID
46 * @version: chip version
47 * @irq_base: base address of the mapped MSIC SRAM interrupt tree
48 */
49struct intel_msic {
50 struct platform_device *pdev;
51 unsigned vendor;
52 unsigned version;
53 void __iomem *irq_base;
54};
55
56static struct resource msic_touch_resources[] = {
57 {
58 .flags = IORESOURCE_IRQ,
59 },
60};
61
62static struct resource msic_adc_resources[] = {
63 {
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct resource msic_battery_resources[] = {
69 {
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct resource msic_gpio_resources[] = {
75 {
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static struct resource msic_audio_resources[] = {
81 {
82 .name = "IRQ",
83 .flags = IORESOURCE_IRQ,
84 },
85 /*
86 * We will pass IRQ_BASE to the driver now but this can be removed
87 * when/if the driver starts to use intel_msic_irq_read().
88 */
89 {
90 .name = "IRQ_BASE",
91 .flags = IORESOURCE_MEM,
92 .start = MSIC_IRQ_STATUS_ACCDET,
93 .end = MSIC_IRQ_STATUS_ACCDET,
94 },
95};
96
97static struct resource msic_hdmi_resources[] = {
98 {
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103static struct resource msic_thermal_resources[] = {
104 {
105 .flags = IORESOURCE_IRQ,
106 },
107};
108
109static struct resource msic_power_btn_resources[] = {
110 {
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static struct resource msic_ocd_resources[] = {
116 {
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121/*
122 * Devices that are part of the MSIC and are available via firmware
123 * populated SFI DEVS table.
124 */
125static struct mfd_cell msic_devs[] = {
126 [INTEL_MSIC_BLOCK_TOUCH] = {
127 .name = "msic_touch",
128 .num_resources = ARRAY_SIZE(msic_touch_resources),
129 .resources = msic_touch_resources,
130 },
131 [INTEL_MSIC_BLOCK_ADC] = {
132 .name = "msic_adc",
133 .num_resources = ARRAY_SIZE(msic_adc_resources),
134 .resources = msic_adc_resources,
135 },
136 [INTEL_MSIC_BLOCK_BATTERY] = {
137 .name = "msic_battery",
138 .num_resources = ARRAY_SIZE(msic_battery_resources),
139 .resources = msic_battery_resources,
140 },
141 [INTEL_MSIC_BLOCK_GPIO] = {
142 .name = "msic_gpio",
143 .num_resources = ARRAY_SIZE(msic_gpio_resources),
144 .resources = msic_gpio_resources,
145 },
146 [INTEL_MSIC_BLOCK_AUDIO] = {
147 .name = "msic_audio",
148 .num_resources = ARRAY_SIZE(msic_audio_resources),
149 .resources = msic_audio_resources,
150 },
151 [INTEL_MSIC_BLOCK_HDMI] = {
152 .name = "msic_hdmi",
153 .num_resources = ARRAY_SIZE(msic_hdmi_resources),
154 .resources = msic_hdmi_resources,
155 },
156 [INTEL_MSIC_BLOCK_THERMAL] = {
157 .name = "msic_thermal",
158 .num_resources = ARRAY_SIZE(msic_thermal_resources),
159 .resources = msic_thermal_resources,
160 },
161 [INTEL_MSIC_BLOCK_POWER_BTN] = {
162 .name = "msic_power_btn",
163 .num_resources = ARRAY_SIZE(msic_power_btn_resources),
164 .resources = msic_power_btn_resources,
165 },
166 [INTEL_MSIC_BLOCK_OCD] = {
167 .name = "msic_ocd",
168 .num_resources = ARRAY_SIZE(msic_ocd_resources),
169 .resources = msic_ocd_resources,
170 },
171};
172
173/*
174 * Other MSIC related devices which are not directly available via SFI DEVS
175 * table. These can be pseudo devices, regulators etc. which are needed for
176 * different purposes.
177 *
178 * These devices appear only after the MSIC driver itself is initialized so
179 * we can guarantee that the SCU IPC interface is ready.
180 */
Geert Uytterhoevencf3c7cf2013-11-18 14:32:58 +0100181static const struct mfd_cell msic_other_devs[] = {
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200182 /* Audio codec in the MSIC */
183 {
184 .id = -1,
185 .name = "sn95031",
186 },
187};
188
189/**
190 * intel_msic_reg_read - read a single MSIC register
191 * @reg: register to read
192 * @val: register value is placed here
193 *
194 * Read a single register from MSIC. Returns %0 on success and negative
195 * errno in case of failure.
196 *
197 * Function may sleep.
198 */
199int intel_msic_reg_read(unsigned short reg, u8 *val)
200{
201 return intel_scu_ipc_ioread8(reg, val);
202}
203EXPORT_SYMBOL_GPL(intel_msic_reg_read);
204
205/**
206 * intel_msic_reg_write - write a single MSIC register
207 * @reg: register to write
208 * @val: value to write to that register
209 *
210 * Write a single MSIC register. Returns 0 on success and negative
211 * errno in case of failure.
212 *
213 * Function may sleep.
214 */
215int intel_msic_reg_write(unsigned short reg, u8 val)
216{
217 return intel_scu_ipc_iowrite8(reg, val);
218}
219EXPORT_SYMBOL_GPL(intel_msic_reg_write);
220
221/**
222 * intel_msic_reg_update - update a single MSIC register
223 * @reg: register to update
224 * @val: value to write to the register
225 * @mask: specifies which of the bits are updated (%0 = don't update,
226 * %1 = update)
227 *
228 * Perform an update to a register @reg. @mask is used to specify which
229 * bits are updated. Returns %0 in case of success and negative errno in
230 * case of failure.
231 *
232 * Function may sleep.
233 */
234int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask)
235{
236 return intel_scu_ipc_update_register(reg, val, mask);
237}
238EXPORT_SYMBOL_GPL(intel_msic_reg_update);
239
240/**
241 * intel_msic_bulk_read - read an array of registers
242 * @reg: array of register addresses to read
243 * @buf: array where the read values are placed
244 * @count: number of registers to read
245 *
246 * Function reads @count registers from the MSIC using addresses passed in
247 * @reg. Read values are placed in @buf. Reads are performed atomically
248 * wrt. MSIC.
249 *
250 * Returns %0 in case of success and negative errno in case of failure.
251 *
252 * Function may sleep.
253 */
254int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count)
255{
256 if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
257 return -EINVAL;
258
259 return intel_scu_ipc_readv(reg, buf, count);
260}
261EXPORT_SYMBOL_GPL(intel_msic_bulk_read);
262
263/**
264 * intel_msic_bulk_write - write an array of values to the MSIC registers
265 * @reg: array of registers to write
266 * @buf: values to write to each register
267 * @count: number of registers to write
268 *
269 * Function writes @count registers in @buf to MSIC. Writes are performed
270 * atomically wrt MSIC. Returns %0 in case of success and negative errno in
271 * case of failure.
272 *
273 * Function may sleep.
274 */
275int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count)
276{
277 if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
278 return -EINVAL;
279
280 return intel_scu_ipc_writev(reg, buf, count);
281}
282EXPORT_SYMBOL_GPL(intel_msic_bulk_write);
283
284/**
285 * intel_msic_irq_read - read a register from an MSIC interrupt tree
286 * @msic: MSIC instance
287 * @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
288 * %INTEL_MSIC_RESETIRQ2)
289 * @val: value of the register is placed here
290 *
291 * This function can be used by an MSIC subdevice interrupt handler to read
292 * a register value from the MSIC interrupt tree. In this way subdevice
293 * drivers don't have to map in the interrupt tree themselves but can just
294 * call this function instead.
295 *
296 * Function doesn't sleep and is callable from interrupt context.
297 *
298 * Returns %-EINVAL if @reg is outside of the allowed register region.
299 */
300int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val)
301{
302 if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2))
303 return -EINVAL;
304
305 *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1));
306 return 0;
307}
308EXPORT_SYMBOL_GPL(intel_msic_irq_read);
309
Bill Pembertonf791be42012-11-19 13:23:04 -0500310static int intel_msic_init_devices(struct intel_msic *msic)
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200311{
312 struct platform_device *pdev = msic->pdev;
Jingoo Han334a41c2013-07-30 17:10:05 +0900313 struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200314 int ret, i;
315
316 if (pdata->gpio) {
317 struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO];
318
319 cell->platform_data = pdata->gpio;
320 cell->pdata_size = sizeof(*pdata->gpio);
321 }
322
323 if (pdata->ocd) {
324 unsigned gpio = pdata->ocd->gpio;
325
Jingoo Han54d34922013-02-20 18:28:49 +0900326 ret = devm_gpio_request_one(&pdev->dev, gpio,
327 GPIOF_IN, "ocd_gpio");
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200328 if (ret) {
329 dev_err(&pdev->dev, "failed to register OCD GPIO\n");
330 return ret;
331 }
332
333 ret = gpio_to_irq(gpio);
334 if (ret < 0) {
335 dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n");
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200336 return ret;
337 }
338
339 /* Update the IRQ number for the OCD */
340 pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret;
341 }
342
343 for (i = 0; i < ARRAY_SIZE(msic_devs); i++) {
344 if (!pdata->irq[i])
345 continue;
346
347 ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL,
Mark Brown0848c942012-09-11 15:16:36 +0800348 pdata->irq[i], NULL);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200349 if (ret)
350 goto fail;
351 }
352
353 ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs,
Mark Brown0848c942012-09-11 15:16:36 +0800354 ARRAY_SIZE(msic_other_devs), NULL, 0, NULL);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200355 if (ret)
356 goto fail;
357
358 return 0;
359
360fail:
361 mfd_remove_devices(&pdev->dev);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200362
363 return ret;
364}
365
Bill Pemberton4740f732012-11-19 13:26:01 -0500366static void intel_msic_remove_devices(struct intel_msic *msic)
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200367{
368 struct platform_device *pdev = msic->pdev;
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200369
370 mfd_remove_devices(&pdev->dev);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200371}
372
Bill Pembertonf791be42012-11-19 13:23:04 -0500373static int intel_msic_probe(struct platform_device *pdev)
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200374{
Jingoo Han334a41c2013-07-30 17:10:05 +0900375 struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200376 struct intel_msic *msic;
377 struct resource *res;
378 u8 id0, id1;
379 int ret;
380
381 if (!pdata) {
382 dev_err(&pdev->dev, "no platform data passed\n");
383 return -EINVAL;
384 }
385
386 /* First validate that we have an MSIC in place */
387 ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0);
388 if (ret) {
389 dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n");
390 return -ENXIO;
391 }
392
393 ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1);
394 if (ret) {
395 dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n");
396 return -ENXIO;
397 }
398
399 if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) {
400 dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1);
401 return -ENXIO;
402 }
403
Pasi Savanainen465c29d2012-04-12 12:40:37 +0300404 msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200405 if (!msic)
406 return -ENOMEM;
407
408 msic->vendor = MSIC_VENDOR(id0);
409 msic->version = MSIC_VERSION(id0);
410 msic->pdev = pdev;
411
412 /*
413 * Map in the MSIC interrupt tree area in SRAM. This is exposed to
414 * the clients via intel_msic_irq_read().
415 */
416 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding6c2db1c2013-01-21 11:09:09 +0100417 msic->irq_base = devm_ioremap_resource(&pdev->dev, res);
418 if (IS_ERR(msic->irq_base))
419 return PTR_ERR(msic->irq_base);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200420
421 platform_set_drvdata(pdev, msic);
422
423 ret = intel_msic_init_devices(msic);
424 if (ret) {
425 dev_err(&pdev->dev, "failed to initialize MSIC devices\n");
Pasi Savanainen465c29d2012-04-12 12:40:37 +0300426 return ret;
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200427 }
428
429 dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n",
430 MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version),
431 msic->vendor);
432
433 return 0;
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200434}
435
Bill Pemberton4740f732012-11-19 13:26:01 -0500436static int intel_msic_remove(struct platform_device *pdev)
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200437{
438 struct intel_msic *msic = platform_get_drvdata(pdev);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200439
440 intel_msic_remove_devices(msic);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200441
442 return 0;
443}
444
445static struct platform_driver intel_msic_driver = {
446 .probe = intel_msic_probe,
Bill Pemberton84449212012-11-19 13:20:24 -0500447 .remove = intel_msic_remove,
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200448 .driver = {
449 .name = "intel_msic",
450 .owner = THIS_MODULE,
451 },
452};
453
Mark Brown65349d62011-11-23 22:58:34 +0000454module_platform_driver(intel_msic_driver);
Mika Westerberg1f5a3712011-09-21 13:03:07 +0200455
456MODULE_DESCRIPTION("Driver for Intel MSIC");
457MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
458MODULE_LICENSE("GPL");