Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the Chelsio FCoE driver for Linux. |
| 3 | * |
| 4 | * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. |
| 5 | * |
| 6 | * This software is available to you under a choice of one of two |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU |
| 8 | * General Public License (GPL) Version 2, available from the file |
| 9 | * COPYING in the main directory of this source tree, or the |
| 10 | * OpenIB.org BSD license below: |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or |
| 13 | * without modification, are permitted provided that the following |
| 14 | * conditions are met: |
| 15 | * |
| 16 | * - Redistributions of source code must retain the above |
| 17 | * copyright notice, this list of conditions and the following |
| 18 | * disclaimer. |
| 19 | * |
| 20 | * - Redistributions in binary form must reproduce the above |
| 21 | * copyright notice, this list of conditions and the following |
| 22 | * disclaimer in the documentation and/or other materials |
| 23 | * provided with the distribution. |
| 24 | * |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 32 | * SOFTWARE. |
| 33 | */ |
| 34 | |
| 35 | #ifndef __CSIO_HW_H__ |
| 36 | #define __CSIO_HW_H__ |
| 37 | |
| 38 | #include <linux/kernel.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/device.h> |
| 41 | #include <linux/workqueue.h> |
| 42 | #include <linux/compiler.h> |
| 43 | #include <linux/cdev.h> |
| 44 | #include <linux/list.h> |
| 45 | #include <linux/mempool.h> |
| 46 | #include <linux/io.h> |
| 47 | #include <linux/spinlock_types.h> |
| 48 | #include <scsi/scsi_device.h> |
| 49 | #include <scsi/scsi_transport_fc.h> |
| 50 | |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 51 | #include "csio_hw_chip.h" |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 52 | #include "csio_wr.h" |
| 53 | #include "csio_mb.h" |
| 54 | #include "csio_scsi.h" |
| 55 | #include "csio_defs.h" |
| 56 | #include "t4_regs.h" |
| 57 | #include "t4_msg.h" |
| 58 | |
| 59 | /* |
| 60 | * An error value used by host. Should not clash with FW defined return values. |
| 61 | */ |
| 62 | #define FW_HOSTERROR 255 |
| 63 | |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 64 | #define CSIO_HW_NAME "Chelsio FCoE Adapter" |
| 65 | #define CSIO_MAX_PFN 8 |
| 66 | #define CSIO_MAX_PPORTS 4 |
| 67 | |
| 68 | #define CSIO_MAX_LUN 0xFFFF |
| 69 | #define CSIO_MAX_QUEUE 2048 |
| 70 | #define CSIO_MAX_CMD_PER_LUN 32 |
| 71 | #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024) |
| 72 | #define CSIO_MAX_SECTOR_SIZE 128 |
| 73 | |
| 74 | /* Interrupts */ |
| 75 | #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode |
| 76 | * (Forward intr iq + fw iq) */ |
| 77 | #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */ |
| 78 | #define CSIO_MAX_SCSI_CPU 128 |
| 79 | #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS) |
| 80 | #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS) |
| 81 | |
| 82 | /* Queues */ |
| 83 | enum { |
| 84 | CSIO_INTR_WRSIZE = 128, |
| 85 | CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE), |
| 86 | CSIO_FWEVT_WRSIZE = 128, |
| 87 | CSIO_FWEVT_IQLEN = 128, |
| 88 | CSIO_FWEVT_FLBUFS = 64, |
| 89 | CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN), |
| 90 | CSIO_HW_NIQ = 1, |
| 91 | CSIO_HW_NFLQ = 1, |
| 92 | CSIO_HW_NEQ = 1, |
| 93 | CSIO_HW_NINTXQ = 1, |
| 94 | }; |
| 95 | |
| 96 | struct csio_msix_entries { |
Alexander Gordeev | 6b73352 | 2014-08-18 08:01:50 +0200 | [diff] [blame] | 97 | unsigned short vector; /* Assigned MSI-X vector */ |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 98 | void *dev_id; /* Priv object associated w/ this msix*/ |
| 99 | char desc[24]; /* Description of this vector */ |
| 100 | }; |
| 101 | |
| 102 | struct csio_scsi_qset { |
| 103 | int iq_idx; /* Ingress index */ |
| 104 | int eq_idx; /* Egress index */ |
| 105 | uint32_t intr_idx; /* MSIX Vector index */ |
| 106 | }; |
| 107 | |
| 108 | struct csio_scsi_cpu_info { |
| 109 | int16_t max_cpus; |
| 110 | }; |
| 111 | |
| 112 | extern int csio_dbg_level; |
| 113 | extern int csio_force_master; |
| 114 | extern unsigned int csio_port_mask; |
| 115 | extern int csio_msi; |
| 116 | |
| 117 | #define CSIO_VENDOR_ID 0x1425 |
| 118 | #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00 |
| 119 | #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 120 | |
| 121 | #define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ |
| 122 | EDC1 | LE | TP | MA | PM_TX | PM_RX | \ |
| 123 | ULP_RX | CPL_SWITCH | SGE | \ |
| 124 | ULP_TX | SF) |
| 125 | |
| 126 | /* |
| 127 | * Hard parameters used to initialize the card in the absence of a |
| 128 | * configuration file. |
| 129 | */ |
| 130 | enum { |
| 131 | /* General */ |
| 132 | CSIO_SGE_DBFIFO_INT_THRESH = 10, |
| 133 | |
| 134 | CSIO_SGE_RX_DMA_OFFSET = 2, |
| 135 | |
| 136 | CSIO_SGE_FLBUF_SIZE1 = 65536, |
| 137 | CSIO_SGE_FLBUF_SIZE2 = 1536, |
| 138 | CSIO_SGE_FLBUF_SIZE3 = 9024, |
| 139 | CSIO_SGE_FLBUF_SIZE4 = 9216, |
| 140 | CSIO_SGE_FLBUF_SIZE5 = 2048, |
| 141 | CSIO_SGE_FLBUF_SIZE6 = 128, |
| 142 | CSIO_SGE_FLBUF_SIZE7 = 8192, |
| 143 | CSIO_SGE_FLBUF_SIZE8 = 16384, |
| 144 | |
| 145 | CSIO_SGE_TIMER_VAL_0 = 5, |
| 146 | CSIO_SGE_TIMER_VAL_1 = 10, |
| 147 | CSIO_SGE_TIMER_VAL_2 = 20, |
| 148 | CSIO_SGE_TIMER_VAL_3 = 50, |
| 149 | CSIO_SGE_TIMER_VAL_4 = 100, |
| 150 | CSIO_SGE_TIMER_VAL_5 = 200, |
| 151 | |
| 152 | CSIO_SGE_INT_CNT_VAL_0 = 1, |
| 153 | CSIO_SGE_INT_CNT_VAL_1 = 4, |
| 154 | CSIO_SGE_INT_CNT_VAL_2 = 8, |
| 155 | CSIO_SGE_INT_CNT_VAL_3 = 16, |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | /* Slowpath events */ |
| 159 | enum csio_evt { |
| 160 | CSIO_EVT_FW = 0, /* FW event */ |
| 161 | CSIO_EVT_MBX, /* MBX event */ |
| 162 | CSIO_EVT_SCN, /* State change notification */ |
| 163 | CSIO_EVT_DEV_LOSS, /* Device loss event */ |
| 164 | CSIO_EVT_MAX, /* Max supported event */ |
| 165 | }; |
| 166 | |
| 167 | #define CSIO_EVT_MSG_SIZE 512 |
| 168 | #define CSIO_EVTQ_SIZE 512 |
| 169 | |
| 170 | /* Event msg */ |
| 171 | struct csio_evt_msg { |
| 172 | struct list_head list; /* evt queue*/ |
| 173 | enum csio_evt type; |
| 174 | uint8_t data[CSIO_EVT_MSG_SIZE]; |
| 175 | }; |
| 176 | |
| 177 | enum { |
| 178 | EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ |
| 179 | SERNUM_LEN = 16, /* Serial # length */ |
| 180 | EC_LEN = 16, /* E/C length */ |
| 181 | ID_LEN = 16, /* ID length */ |
| 182 | TRACE_LEN = 112, /* length of trace data and mask */ |
| 183 | }; |
| 184 | |
| 185 | enum { |
| 186 | SF_PAGE_SIZE = 256, /* serial flash page size */ |
| 187 | SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ |
| 188 | SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */ |
| 189 | }; |
| 190 | |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 191 | /* serial flash and firmware constants */ |
| 192 | enum { |
| 193 | SF_ATTEMPTS = 10, /* max retries for SF operations */ |
| 194 | |
| 195 | /* flash command opcodes */ |
| 196 | SF_PROG_PAGE = 2, /* program page */ |
| 197 | SF_WR_DISABLE = 4, /* disable writes */ |
| 198 | SF_RD_STATUS = 5, /* read status register */ |
| 199 | SF_WR_ENABLE = 6, /* enable writes */ |
| 200 | SF_RD_DATA_FAST = 0xb, /* read flash */ |
| 201 | SF_RD_ID = 0x9f, /* read ID */ |
| 202 | SF_ERASE_SECTOR = 0xd8, /* erase sector */ |
| 203 | |
| 204 | FW_START_SEC = 8, /* first flash sector for FW */ |
| 205 | FW_END_SEC = 15, /* last flash sector for FW */ |
| 206 | FW_IMG_START = FW_START_SEC * SF_SEC_SIZE, |
| 207 | FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE, |
| 208 | |
| 209 | FLASH_CFG_MAX_SIZE = 0x10000 , /* max size of the flash config file*/ |
| 210 | FLASH_CFG_OFFSET = 0x1f0000, |
| 211 | FLASH_CFG_START_SEC = FLASH_CFG_OFFSET / SF_SEC_SIZE, |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | /* |
| 215 | * Flash layout. |
| 216 | */ |
| 217 | #define FLASH_START(start) ((start) * SF_SEC_SIZE) |
| 218 | #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) |
| 219 | |
| 220 | enum { |
| 221 | /* |
| 222 | * Location of firmware image in FLASH. |
| 223 | */ |
| 224 | FLASH_FW_START_SEC = 8, |
| 225 | FLASH_FW_NSECS = 8, |
| 226 | FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), |
| 227 | FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), |
| 228 | |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 229 | /* Location of Firmware Configuration File in FLASH. */ |
| 230 | FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | #undef FLASH_START |
| 234 | #undef FLASH_MAX_SIZE |
| 235 | |
| 236 | /* Management module */ |
| 237 | enum { |
| 238 | CSIO_MGMT_EQ_WRSIZE = 512, |
| 239 | CSIO_MGMT_IQ_WRSIZE = 128, |
| 240 | CSIO_MGMT_EQLEN = 64, |
| 241 | CSIO_MGMT_IQLEN = 64, |
| 242 | }; |
| 243 | |
| 244 | #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE) |
| 245 | #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE) |
| 246 | |
| 247 | /* mgmt module stats */ |
| 248 | struct csio_mgmtm_stats { |
| 249 | uint32_t n_abort_req; /* Total abort request */ |
| 250 | uint32_t n_abort_rsp; /* Total abort response */ |
| 251 | uint32_t n_close_req; /* Total close request */ |
| 252 | uint32_t n_close_rsp; /* Total close response */ |
| 253 | uint32_t n_err; /* Total Errors */ |
| 254 | uint32_t n_drop; /* Total request dropped */ |
| 255 | uint32_t n_active; /* Count of active_q */ |
| 256 | uint32_t n_cbfn; /* Count of cbfn_q */ |
| 257 | }; |
| 258 | |
| 259 | /* MGMT module */ |
| 260 | struct csio_mgmtm { |
| 261 | struct csio_hw *hw; /* Pointer to HW moduel */ |
| 262 | int eq_idx; /* Egress queue index */ |
| 263 | int iq_idx; /* Ingress queue index */ |
| 264 | int msi_vec; /* MSI vector */ |
| 265 | struct list_head active_q; /* Outstanding ELS/CT */ |
| 266 | struct list_head abort_q; /* Outstanding abort req */ |
| 267 | struct list_head cbfn_q; /* Completion queue */ |
| 268 | struct list_head mgmt_req_freelist; /* Free poll of reqs */ |
| 269 | /* ELSCT request freelist*/ |
| 270 | struct timer_list mgmt_timer; /* MGMT timer */ |
| 271 | struct csio_mgmtm_stats stats; /* ELS/CT stats */ |
| 272 | }; |
| 273 | |
| 274 | struct csio_adap_desc { |
| 275 | char model_no[16]; |
| 276 | char description[32]; |
| 277 | }; |
| 278 | |
| 279 | struct pci_params { |
| 280 | uint16_t vendor_id; |
| 281 | uint16_t device_id; |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 282 | int vpd_cap_addr; |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 283 | uint16_t speed; |
| 284 | uint8_t width; |
| 285 | }; |
| 286 | |
| 287 | /* User configurable hw parameters */ |
| 288 | struct csio_hw_params { |
| 289 | uint32_t sf_size; /* serial flash |
| 290 | * size in bytes |
| 291 | */ |
| 292 | uint32_t sf_nsec; /* # of flash sectors */ |
| 293 | struct pci_params pci; |
| 294 | uint32_t log_level; /* Module-level for |
| 295 | * debug log. |
| 296 | */ |
| 297 | }; |
| 298 | |
| 299 | struct csio_vpd { |
| 300 | uint32_t cclk; |
| 301 | uint8_t ec[EC_LEN + 1]; |
| 302 | uint8_t sn[SERNUM_LEN + 1]; |
| 303 | uint8_t id[ID_LEN + 1]; |
| 304 | }; |
| 305 | |
| 306 | struct csio_pport { |
| 307 | uint16_t pcap; |
| 308 | uint8_t portid; |
| 309 | uint8_t link_status; |
| 310 | uint16_t link_speed; |
| 311 | uint8_t mac[6]; |
| 312 | uint8_t mod_type; |
| 313 | uint8_t rsvd1; |
| 314 | uint8_t rsvd2; |
| 315 | uint8_t rsvd3; |
| 316 | }; |
| 317 | |
| 318 | /* fcoe resource information */ |
| 319 | struct csio_fcoe_res_info { |
| 320 | uint16_t e_d_tov; |
| 321 | uint16_t r_a_tov_seq; |
| 322 | uint16_t r_a_tov_els; |
| 323 | uint16_t r_r_tov; |
| 324 | uint32_t max_xchgs; |
| 325 | uint32_t max_ssns; |
| 326 | uint32_t used_xchgs; |
| 327 | uint32_t used_ssns; |
| 328 | uint32_t max_fcfs; |
| 329 | uint32_t max_vnps; |
| 330 | uint32_t used_fcfs; |
| 331 | uint32_t used_vnps; |
| 332 | }; |
| 333 | |
| 334 | /* HW State machine Events */ |
| 335 | enum csio_hw_ev { |
| 336 | CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */ |
| 337 | CSIO_HWE_INIT, /* Config done, start Init */ |
| 338 | CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */ |
| 339 | CSIO_HWE_FATAL, /* Fatal error during initialization */ |
| 340 | CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */ |
| 341 | CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */ |
| 342 | CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */ |
| 343 | CSIO_HWE_QUIESCED, /* HBA quiesced */ |
| 344 | CSIO_HWE_HBA_RESET, /* HBA reset requested */ |
| 345 | CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */ |
| 346 | CSIO_HWE_FW_DLOAD, /* FW download requested */ |
| 347 | CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */ |
| 348 | CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */ |
| 349 | CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */ |
| 350 | CSIO_HWE_MAX, /* Max HW event */ |
| 351 | }; |
| 352 | |
| 353 | /* hw stats */ |
| 354 | struct csio_hw_stats { |
| 355 | uint32_t n_evt_activeq; /* Number of event in active Q */ |
| 356 | uint32_t n_evt_freeq; /* Number of event in free Q */ |
| 357 | uint32_t n_evt_drop; /* Number of event droped */ |
| 358 | uint32_t n_evt_unexp; /* Number of unexpected events */ |
| 359 | uint32_t n_pcich_offline;/* Number of pci channel offline */ |
| 360 | uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */ |
| 361 | uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/ |
| 362 | uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/ |
| 363 | uint32_t n_cpl_unexp; /* Number of unexpected cpl */ |
| 364 | uint32_t n_mbint_unexp; /* Number of unexpected mbox */ |
| 365 | /* interrupt */ |
| 366 | uint32_t n_plint_unexp; /* Number of unexpected PL */ |
| 367 | /* interrupt */ |
| 368 | uint32_t n_plint_cnt; /* Number of PL interrupt */ |
| 369 | uint32_t n_int_stray; /* Number of stray interrupt */ |
| 370 | uint32_t n_err; /* Number of hw errors */ |
| 371 | uint32_t n_err_fatal; /* Number of fatal errors */ |
| 372 | uint32_t n_err_nomem; /* Number of memory alloc failure */ |
| 373 | uint32_t n_err_io; /* Number of IO failure */ |
| 374 | enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */ |
| 375 | uint64_t n_reset_start; /* Start time after the reset */ |
| 376 | uint32_t rsvd1; |
| 377 | }; |
| 378 | |
| 379 | /* Defines for hw->flags */ |
| 380 | #define CSIO_HWF_MASTER 0x00000001 /* This is the Master |
| 381 | * function for the |
| 382 | * card. |
| 383 | */ |
| 384 | #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt |
| 385 | * enable bit set? |
| 386 | */ |
| 387 | #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */ |
| 388 | #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been |
| 389 | * allocated memory. |
| 390 | */ |
| 391 | #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been |
| 392 | * allocated in FW. |
| 393 | */ |
| 394 | #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */ |
| 395 | #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device |
| 396 | * id cached */ |
| 397 | #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing |
| 398 | * FW events |
| 399 | */ |
| 400 | #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config |
| 401 | * params |
| 402 | */ |
| 403 | #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts |
| 404 | * enabled? |
| 405 | */ |
| 406 | |
| 407 | #define csio_is_hw_intr_enabled(__hw) \ |
| 408 | ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED) |
| 409 | #define csio_is_host_intr_enabled(__hw) \ |
| 410 | ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED) |
| 411 | #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER) |
| 412 | #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID) |
| 413 | #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED) |
| 414 | #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID) |
| 415 | #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED) |
| 416 | |
| 417 | /* Defines for intr_mode */ |
| 418 | enum csio_intr_mode { |
| 419 | CSIO_IM_NONE = 0, |
| 420 | CSIO_IM_INTX = 1, |
| 421 | CSIO_IM_MSI = 2, |
| 422 | CSIO_IM_MSIX = 3, |
| 423 | }; |
| 424 | |
| 425 | /* Master HW structure: One per function */ |
| 426 | struct csio_hw { |
| 427 | struct csio_sm sm; /* State machine: should |
| 428 | * be the 1st member. |
| 429 | */ |
| 430 | spinlock_t lock; /* Lock for hw */ |
| 431 | |
| 432 | struct csio_scsim scsim; /* SCSI module*/ |
| 433 | struct csio_wrm wrm; /* Work request module*/ |
| 434 | struct pci_dev *pdev; /* PCI device */ |
| 435 | |
| 436 | void __iomem *regstart; /* Virtual address of |
| 437 | * register map |
| 438 | */ |
| 439 | /* SCSI queue sets */ |
| 440 | uint32_t num_sqsets; /* Number of SCSI |
| 441 | * queue sets */ |
| 442 | uint32_t num_scsi_msix_cpus; /* Number of CPUs that |
| 443 | * will be used |
| 444 | * for ingress |
| 445 | * processing. |
| 446 | */ |
| 447 | |
| 448 | struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU]; |
| 449 | struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS]; |
| 450 | |
| 451 | uint32_t evtflag; /* Event flag */ |
| 452 | uint32_t flags; /* HW flags */ |
| 453 | |
| 454 | struct csio_mgmtm mgmtm; /* management module */ |
| 455 | struct csio_mbm mbm; /* Mailbox module */ |
| 456 | |
| 457 | /* Lnodes */ |
| 458 | uint32_t num_lns; /* Number of lnodes */ |
| 459 | struct csio_lnode *rln; /* Root lnode */ |
| 460 | struct list_head sln_head; /* Sibling node list |
| 461 | * list |
| 462 | */ |
| 463 | int intr_iq_idx; /* Forward interrupt |
| 464 | * queue. |
| 465 | */ |
| 466 | int fwevt_iq_idx; /* FW evt queue */ |
| 467 | struct work_struct evtq_work; /* Worker thread for |
| 468 | * HW events. |
| 469 | */ |
| 470 | struct list_head evt_free_q; /* freelist of evt |
| 471 | * elements |
| 472 | */ |
| 473 | struct list_head evt_active_q; /* active evt queue*/ |
| 474 | |
| 475 | /* board related info */ |
| 476 | char name[32]; |
| 477 | char hw_ver[16]; |
| 478 | char model_desc[32]; |
| 479 | char drv_version[32]; |
| 480 | char fwrev_str[32]; |
| 481 | uint32_t optrom_ver; |
| 482 | uint32_t fwrev; |
| 483 | uint32_t tp_vers; |
| 484 | char chip_ver; |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 485 | uint16_t chip_id; /* Tells T4/T5 chip */ |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 486 | uint32_t cfg_finiver; |
| 487 | uint32_t cfg_finicsum; |
| 488 | uint32_t cfg_cfcsum; |
| 489 | uint8_t cfg_csum_status; |
| 490 | uint8_t cfg_store; |
| 491 | enum csio_dev_state fw_state; |
| 492 | struct csio_vpd vpd; |
| 493 | |
| 494 | uint8_t pfn; /* Physical Function |
| 495 | * number |
| 496 | */ |
| 497 | uint32_t port_vec; /* Port vector */ |
| 498 | uint8_t num_pports; /* Number of physical |
| 499 | * ports. |
| 500 | */ |
| 501 | uint8_t rst_retries; /* Reset retries */ |
| 502 | uint8_t cur_evt; /* current s/m evt */ |
| 503 | uint8_t prev_evt; /* Previous s/m evt */ |
| 504 | uint32_t dev_num; /* device number */ |
| 505 | struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */ |
| 506 | struct csio_hw_params params; /* Hw parameters */ |
| 507 | |
| 508 | struct pci_pool *scsi_pci_pool; /* PCI pool for SCSI */ |
| 509 | mempool_t *mb_mempool; /* Mailbox memory pool*/ |
| 510 | mempool_t *rnode_mempool; /* rnode memory pool */ |
| 511 | |
| 512 | /* Interrupt */ |
| 513 | enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */ |
| 514 | uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt |
| 515 | * index |
| 516 | */ |
| 517 | uint32_t nondata_intr_idx; /* nondata MSIX/intr |
| 518 | * idx |
| 519 | */ |
| 520 | |
| 521 | uint8_t cfg_neq; /* FW configured no of |
| 522 | * egress queues |
| 523 | */ |
| 524 | uint8_t cfg_niq; /* FW configured no of |
| 525 | * iq queues. |
| 526 | */ |
| 527 | |
| 528 | struct csio_fcoe_res_info fres_info; /* Fcoe resource info */ |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 529 | struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific |
| 530 | * Operations |
| 531 | */ |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 532 | |
| 533 | /* MSIX vectors */ |
| 534 | struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS]; |
| 535 | |
| 536 | struct dentry *debugfs_root; /* Debug FS */ |
| 537 | struct csio_hw_stats stats; /* Hw statistics */ |
| 538 | }; |
| 539 | |
| 540 | /* Register access macros */ |
| 541 | #define csio_reg(_b, _r) ((_b) + (_r)) |
| 542 | |
| 543 | #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r))) |
| 544 | #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r))) |
| 545 | #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r))) |
| 546 | #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r))) |
| 547 | |
| 548 | #define csio_wr_reg8(_h, _v, _r) writeb((_v), \ |
| 549 | csio_reg((_h)->regstart, (_r))) |
| 550 | #define csio_wr_reg16(_h, _v, _r) writew((_v), \ |
| 551 | csio_reg((_h)->regstart, (_r))) |
| 552 | #define csio_wr_reg32(_h, _v, _r) writel((_v), \ |
| 553 | csio_reg((_h)->regstart, (_r))) |
| 554 | #define csio_wr_reg64(_h, _v, _r) writeq((_v), \ |
| 555 | csio_reg((_h)->regstart, (_r))) |
| 556 | |
| 557 | void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t); |
| 558 | |
| 559 | /* Core clocks <==> uSecs */ |
| 560 | static inline uint32_t |
| 561 | csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks) |
| 562 | { |
| 563 | /* add Core Clock / 2 to round ticks to nearest uS */ |
| 564 | return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk; |
| 565 | } |
| 566 | |
| 567 | static inline uint32_t |
| 568 | csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us) |
| 569 | { |
| 570 | return (us * hw->vpd.cclk) / 1000; |
| 571 | } |
| 572 | |
| 573 | /* Easy access macros */ |
| 574 | #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm)) |
| 575 | #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm)) |
| 576 | #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim)) |
| 577 | #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm)) |
| 578 | |
| 579 | #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number) |
| 580 | #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn)) |
| 581 | #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn)) |
| 582 | |
| 583 | #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i)) |
| 584 | #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx) |
| 585 | #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i)) |
| 586 | #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx) |
| 587 | |
| 588 | /* Printing/logging */ |
| 589 | #define CSIO_DEVID(__dev) ((__dev)->dev_num) |
| 590 | #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF) |
| 591 | #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF) |
| 592 | |
| 593 | #define csio_info(__hw, __fmt, ...) \ |
| 594 | dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) |
| 595 | |
| 596 | #define csio_fatal(__hw, __fmt, ...) \ |
| 597 | dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) |
| 598 | |
| 599 | #define csio_err(__hw, __fmt, ...) \ |
| 600 | dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) |
| 601 | |
| 602 | #define csio_warn(__hw, __fmt, ...) \ |
| 603 | dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) |
| 604 | |
| 605 | #ifdef __CSIO_DEBUG__ |
| 606 | #define csio_dbg(__hw, __fmt, ...) \ |
| 607 | csio_info((__hw), __fmt, ##__VA_ARGS__); |
| 608 | #else |
| 609 | #define csio_dbg(__hw, __fmt, ...) |
| 610 | #endif |
| 611 | |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 612 | int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int, |
| 613 | int, int, uint32_t *); |
| 614 | void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int, |
| 615 | unsigned int, unsigned int); |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 616 | int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *); |
| 617 | void csio_hw_intr_disable(struct csio_hw *); |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 618 | int csio_hw_slow_intr_handler(struct csio_hw *); |
| 619 | int csio_handle_intr_status(struct csio_hw *, unsigned int, |
| 620 | const struct intr_info *); |
| 621 | |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 622 | int csio_hw_start(struct csio_hw *); |
| 623 | int csio_hw_stop(struct csio_hw *); |
| 624 | int csio_hw_reset(struct csio_hw *); |
| 625 | int csio_is_hw_ready(struct csio_hw *); |
| 626 | int csio_is_hw_removing(struct csio_hw *); |
| 627 | |
| 628 | int csio_fwevtq_handler(struct csio_hw *); |
| 629 | void csio_evtq_worker(struct work_struct *); |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 630 | int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t); |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 631 | void csio_evtq_flush(struct csio_hw *hw); |
| 632 | |
| 633 | int csio_request_irqs(struct csio_hw *); |
| 634 | void csio_intr_enable(struct csio_hw *); |
| 635 | void csio_intr_disable(struct csio_hw *, bool); |
Arvind Bhushan | 7cc1638 | 2013-03-14 05:09:08 +0000 | [diff] [blame] | 636 | void csio_hw_fatal_err(struct csio_hw *); |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 637 | |
| 638 | struct csio_lnode *csio_lnode_alloc(struct csio_hw *); |
| 639 | int csio_config_queues(struct csio_hw *); |
| 640 | |
Naresh Kumar Inna | a3667aa | 2012-11-15 22:41:18 +0530 | [diff] [blame] | 641 | int csio_hw_init(struct csio_hw *); |
| 642 | void csio_hw_exit(struct csio_hw *); |
| 643 | #endif /* ifndef __CSIO_HW_H__ */ |