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Mike Rapoportc6c19332010-08-11 01:11:04 +02001#ifndef __LINUX_MFD_TPS6586X_H
2#define __LINUX_MFD_TPS6586X_H
3
Xin Xie500c5242011-08-09 18:47:50 +08004#define TPS6586X_SLEW_RATE_INSTANTLY 0x00
5#define TPS6586X_SLEW_RATE_110UV 0x01
6#define TPS6586X_SLEW_RATE_220UV 0x02
7#define TPS6586X_SLEW_RATE_440UV 0x03
8#define TPS6586X_SLEW_RATE_880UV 0x04
9#define TPS6586X_SLEW_RATE_1760UV 0x05
10#define TPS6586X_SLEW_RATE_3520UV 0x06
11#define TPS6586X_SLEW_RATE_7040UV 0x07
12
13#define TPS6586X_SLEW_RATE_SET 0x08
14#define TPS6586X_SLEW_RATE_MASK 0x07
15
Stefan Agnere0a3da82013-12-06 13:51:45 +010016/* VERSION CRC */
17#define TPS658621A 0x15
18#define TPS658621CD 0x2c
19#define TPS658623 0x1b
20#define TPS658643 0x03
21
Mike Rapoportc6c19332010-08-11 01:11:04 +020022enum {
Laxman Dewangan9394b802012-09-04 14:43:39 -060023 TPS6586X_ID_SYS,
Mike Rapoportc6c19332010-08-11 01:11:04 +020024 TPS6586X_ID_SM_0,
25 TPS6586X_ID_SM_1,
26 TPS6586X_ID_SM_2,
27 TPS6586X_ID_LDO_0,
28 TPS6586X_ID_LDO_1,
29 TPS6586X_ID_LDO_2,
30 TPS6586X_ID_LDO_3,
31 TPS6586X_ID_LDO_4,
32 TPS6586X_ID_LDO_5,
33 TPS6586X_ID_LDO_6,
34 TPS6586X_ID_LDO_7,
35 TPS6586X_ID_LDO_8,
36 TPS6586X_ID_LDO_9,
37 TPS6586X_ID_LDO_RTC,
Laxman Dewangan64e48162012-10-18 19:36:09 +053038 TPS6586X_ID_MAX_REGULATOR,
Mike Rapoportc6c19332010-08-11 01:11:04 +020039};
40
Gary Kingc26448c2010-09-20 00:18:27 +020041enum {
42 TPS6586X_INT_PLDO_0,
43 TPS6586X_INT_PLDO_1,
44 TPS6586X_INT_PLDO_2,
45 TPS6586X_INT_PLDO_3,
46 TPS6586X_INT_PLDO_4,
47 TPS6586X_INT_PLDO_5,
48 TPS6586X_INT_PLDO_6,
49 TPS6586X_INT_PLDO_7,
50 TPS6586X_INT_COMP_DET,
51 TPS6586X_INT_ADC,
52 TPS6586X_INT_PLDO_8,
53 TPS6586X_INT_PLDO_9,
54 TPS6586X_INT_PSM_0,
55 TPS6586X_INT_PSM_1,
56 TPS6586X_INT_PSM_2,
57 TPS6586X_INT_PSM_3,
58 TPS6586X_INT_RTC_ALM1,
59 TPS6586X_INT_ACUSB_OVP,
60 TPS6586X_INT_USB_DET,
61 TPS6586X_INT_AC_DET,
62 TPS6586X_INT_BAT_DET,
63 TPS6586X_INT_CHG_STAT,
64 TPS6586X_INT_CHG_TEMP,
65 TPS6586X_INT_PP,
66 TPS6586X_INT_RESUME,
67 TPS6586X_INT_LOW_SYS,
68 TPS6586X_INT_RTC_ALM2,
69};
70
Xin Xie500c5242011-08-09 18:47:50 +080071struct tps6586x_settings {
72 int slew_rate;
73};
74
Mike Rapoportc6c19332010-08-11 01:11:04 +020075struct tps6586x_subdev_info {
76 int id;
77 const char *name;
78 void *platform_data;
Thierry Reding62f6b082012-04-26 16:52:21 +020079 struct device_node *of_node;
Mike Rapoportc6c19332010-08-11 01:11:04 +020080};
81
82struct tps6586x_platform_data {
83 int num_subdevs;
84 struct tps6586x_subdev_info *subdevs;
85
86 int gpio_base;
Gary Kingc26448c2010-09-20 00:18:27 +020087 int irq_base;
Bill Huang004c15a2012-08-19 18:07:55 -070088 bool pm_off;
Laxman Dewangan64e48162012-10-18 19:36:09 +053089
90 struct regulator_init_data *reg_init_data[TPS6586X_ID_MAX_REGULATOR];
Mike Rapoportc6c19332010-08-11 01:11:04 +020091};
92
93/*
94 * NOTE: the functions below are not intended for use outside
95 * of the TPS6586X sub-device drivers
96 */
97extern int tps6586x_write(struct device *dev, int reg, uint8_t val);
98extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val);
99extern int tps6586x_read(struct device *dev, int reg, uint8_t *val);
100extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val);
101extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
102extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
103extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
104 uint8_t mask);
Laxman Dewangan605511a2012-11-13 19:18:05 +0530105extern int tps6586x_irq_get_virq(struct device *dev, int irq);
Stefan Agnere0a3da82013-12-06 13:51:45 +0100106extern int tps6586x_get_version(struct device *dev);
Mike Rapoportc6c19332010-08-11 01:11:04 +0200107
108#endif /*__LINUX_MFD_TPS6586X_H */