Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 29 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "i915_drm.h" |
| 34 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 35 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 40 | /** |
| 41 | * Interrupts that are always left unmasked. |
| 42 | * |
| 43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 44 | * we leave them always unmasked in IMR and then control enabling them through |
| 45 | * PIPESTAT alone. |
| 46 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 47 | #define I915_INTERRUPT_ENABLE_FIX \ |
| 48 | (I915_ASLE_INTERRUPT | \ |
| 49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
| 51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ |
| 52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ |
| 53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 54 | |
| 55 | /** Interrupts that we mask and unmask at runtime. */ |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 57 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 59 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 60 | |
| 61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 62 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 63 | |
| 64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 65 | DRM_I915_VBLANK_PIPE_B) |
| 66 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 67 | void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 69 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 70 | if ((dev_priv->gt_irq_mask & mask) != 0) { |
| 71 | dev_priv->gt_irq_mask &= ~mask; |
| 72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 73 | POSTING_READ(GTIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 74 | } |
| 75 | } |
| 76 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 77 | void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 79 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 80 | if ((dev_priv->gt_irq_mask & mask) != mask) { |
| 81 | dev_priv->gt_irq_mask |= mask; |
| 82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 83 | POSTING_READ(GTIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 84 | } |
| 85 | } |
| 86 | |
| 87 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 88 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 90 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 91 | if ((dev_priv->irq_mask & mask) != 0) { |
| 92 | dev_priv->irq_mask &= ~mask; |
| 93 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 94 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 95 | } |
| 96 | } |
| 97 | |
| 98 | static inline void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 100 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 101 | if ((dev_priv->irq_mask & mask) != mask) { |
| 102 | dev_priv->irq_mask |= mask; |
| 103 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 104 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 105 | } |
| 106 | } |
| 107 | |
| 108 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 110 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 111 | if ((dev_priv->irq_mask & mask) != 0) { |
| 112 | dev_priv->irq_mask &= ~mask; |
| 113 | I915_WRITE(IMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 114 | POSTING_READ(IMR); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 115 | } |
| 116 | } |
| 117 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 118 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 120 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 121 | if ((dev_priv->irq_mask & mask) != mask) { |
| 122 | dev_priv->irq_mask |= mask; |
| 123 | I915_WRITE(IMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 124 | POSTING_READ(IMR); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 125 | } |
| 126 | } |
| 127 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 128 | static inline u32 |
| 129 | i915_pipestat(int pipe) |
| 130 | { |
| 131 | if (pipe == 0) |
| 132 | return PIPEASTAT; |
| 133 | if (pipe == 1) |
| 134 | return PIPEBSTAT; |
Andrew Morton | 9c84ba4 | 2008-12-01 13:14:08 -0800 | [diff] [blame] | 135 | BUG(); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | void |
| 139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 140 | { |
| 141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
| 142 | u32 reg = i915_pipestat(pipe); |
| 143 | |
| 144 | dev_priv->pipestat[pipe] |= mask; |
| 145 | /* Enable the interrupt, clear any pending status */ |
| 146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 147 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 148 | } |
| 149 | } |
| 150 | |
| 151 | void |
| 152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 153 | { |
| 154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
| 155 | u32 reg = i915_pipestat(pipe); |
| 156 | |
| 157 | dev_priv->pipestat[pipe] &= ~mask; |
| 158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 159 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 160 | } |
| 161 | } |
| 162 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 163 | /** |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 164 | * intel_enable_asle - enable ASLE interrupt for OpRegion |
| 165 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 166 | void intel_enable_asle(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 167 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 168 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 169 | unsigned long irqflags; |
| 170 | |
| 171 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 172 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 173 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 174 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 175 | else { |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 176 | i915_enable_pipestat(dev_priv, 1, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 178 | if (INTEL_INFO(dev)->gen >= 4) |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 179 | i915_enable_pipestat(dev_priv, 0, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 180 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 181 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 182 | |
| 183 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 187 | * i915_pipe_enabled - check if a pipe is enabled |
| 188 | * @dev: DRM device |
| 189 | * @pipe: pipe to check |
| 190 | * |
| 191 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 192 | * Use this routine to make sure the PLL is running and the pipe is active |
| 193 | * before reading such registers if unsure. |
| 194 | */ |
| 195 | static int |
| 196 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 197 | { |
| 198 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 199 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 200 | } |
| 201 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 202 | /* Called from drm generic code, passed a 'crtc', which |
| 203 | * we use as a pipe index |
| 204 | */ |
| 205 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 206 | { |
| 207 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 208 | unsigned long high_frame; |
| 209 | unsigned long low_frame; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 210 | u32 high1, high2, low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 211 | |
| 212 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 213 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 214 | "pipe %d\n", pipe); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 215 | return 0; |
| 216 | } |
| 217 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 218 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 219 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 220 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 221 | /* |
| 222 | * High & low register fields aren't synchronized, so make sure |
| 223 | * we get a low value that's stable across two reads of the high |
| 224 | * register. |
| 225 | */ |
| 226 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 227 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 228 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; |
| 229 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 230 | } while (high1 != high2); |
| 231 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 232 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
| 233 | low >>= PIPE_FRAME_LOW_SHIFT; |
| 234 | return (high1 << 8) | low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 235 | } |
| 236 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 237 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
| 238 | { |
| 239 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 240 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
| 241 | |
| 242 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 243 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 244 | "pipe %d\n", pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | return I915_READ(reg); |
| 249 | } |
| 250 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 251 | /* |
| 252 | * Handle hotplug events outside the interrupt handler proper. |
| 253 | */ |
| 254 | static void i915_hotplug_work_func(struct work_struct *work) |
| 255 | { |
| 256 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 257 | hotplug_work); |
| 258 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 259 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 260 | struct intel_encoder *encoder; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 261 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 262 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 263 | if (encoder->hot_plug) |
| 264 | encoder->hot_plug(encoder); |
| 265 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 266 | /* Just fire off a uevent and let userspace tell us what to do */ |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 267 | drm_helper_hpd_irq_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 268 | } |
| 269 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 270 | static void i915_handle_rps_change(struct drm_device *dev) |
| 271 | { |
| 272 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 273 | u32 busy_up, busy_down, max_avg, min_avg; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 274 | u8 new_delay = dev_priv->cur_delay; |
| 275 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 276 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 277 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 278 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 279 | max_avg = I915_READ(RCBMAXAVG); |
| 280 | min_avg = I915_READ(RCBMINAVG); |
| 281 | |
| 282 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 283 | if (busy_up > max_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 284 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 285 | new_delay = dev_priv->cur_delay - 1; |
| 286 | if (new_delay < dev_priv->max_delay) |
| 287 | new_delay = dev_priv->max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 288 | } else if (busy_down < min_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 289 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 290 | new_delay = dev_priv->cur_delay + 1; |
| 291 | if (new_delay > dev_priv->min_delay) |
| 292 | new_delay = dev_priv->min_delay; |
| 293 | } |
| 294 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 295 | if (ironlake_set_drps(dev, new_delay)) |
| 296 | dev_priv->cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 297 | |
| 298 | return; |
| 299 | } |
| 300 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 301 | static void notify_ring(struct drm_device *dev, |
| 302 | struct intel_ring_buffer *ring) |
| 303 | { |
| 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 305 | u32 seqno = ring->get_seqno(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 306 | ring->irq_seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 307 | trace_i915_gem_request_complete(dev, seqno); |
| 308 | wake_up_all(&ring->irq_queue); |
| 309 | dev_priv->hangcheck_count = 0; |
| 310 | mod_timer(&dev_priv->hangcheck_timer, |
| 311 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 312 | } |
| 313 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 314 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 315 | { |
| 316 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 317 | int ret = IRQ_NONE; |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 318 | u32 de_iir, gt_iir, de_ier, pch_iir; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 319 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 320 | struct drm_i915_master_private *master_priv; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 321 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
| 322 | |
| 323 | if (IS_GEN6(dev)) |
| 324 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 325 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 326 | /* disable master interrupt before clearing iir */ |
| 327 | de_ier = I915_READ(DEIER); |
| 328 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 329 | POSTING_READ(DEIER); |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 330 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 331 | de_iir = I915_READ(DEIIR); |
| 332 | gt_iir = I915_READ(GTIIR); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 333 | pch_iir = I915_READ(SDEIIR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 334 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 335 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
| 336 | goto done; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 337 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 338 | if (HAS_PCH_CPT(dev)) |
| 339 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; |
| 340 | else |
| 341 | hotplug_mask = SDE_HOTPLUG_MASK; |
| 342 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 343 | ret = IRQ_HANDLED; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 344 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 345 | if (dev->primary->master) { |
| 346 | master_priv = dev->primary->master->driver_priv; |
| 347 | if (master_priv->sarea_priv) |
| 348 | master_priv->sarea_priv->last_dispatch = |
| 349 | READ_BREADCRUMB(dev_priv); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 350 | } |
| 351 | |
Chris Wilson | 88f23b8 | 2010-12-05 15:08:31 +0000 | [diff] [blame] | 352 | if (gt_iir & GT_USER_INTERRUPT) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 353 | notify_ring(dev, &dev_priv->ring[RCS]); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 354 | if (gt_iir & bsd_usr_interrupt) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 355 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 356 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
| 357 | notify_ring(dev, &dev_priv->ring[BCS]); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 358 | |
| 359 | if (de_iir & DE_GSE) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 360 | intel_opregion_gse_intr(dev); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 361 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 362 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 363 | intel_prepare_page_flip(dev, 0); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 364 | intel_finish_page_flip_plane(dev, 0); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 365 | } |
| 366 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 367 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 368 | intel_prepare_page_flip(dev, 1); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 369 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 370 | } |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 371 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 372 | if (de_iir & DE_PIPEA_VBLANK) |
| 373 | drm_handle_vblank(dev, 0); |
| 374 | |
| 375 | if (de_iir & DE_PIPEB_VBLANK) |
| 376 | drm_handle_vblank(dev, 1); |
| 377 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 378 | /* check event from PCH */ |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 379 | if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask)) |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 380 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 381 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 382 | if (de_iir & DE_PCU_EVENT) { |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 383 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 384 | i915_handle_rps_change(dev); |
| 385 | } |
| 386 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 387 | /* should clear PCH hotplug event before clear CPU irq */ |
| 388 | I915_WRITE(SDEIIR, pch_iir); |
| 389 | I915_WRITE(GTIIR, gt_iir); |
| 390 | I915_WRITE(DEIIR, de_iir); |
| 391 | |
| 392 | done: |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 393 | I915_WRITE(DEIER, de_ier); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 394 | POSTING_READ(DEIER); |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 395 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 396 | return ret; |
| 397 | } |
| 398 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 399 | /** |
| 400 | * i915_error_work_func - do process context error handling work |
| 401 | * @work: work struct |
| 402 | * |
| 403 | * Fire an error uevent so userspace can see that a hang or error |
| 404 | * was detected. |
| 405 | */ |
| 406 | static void i915_error_work_func(struct work_struct *work) |
| 407 | { |
| 408 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 409 | error_work); |
| 410 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 411 | char *error_event[] = { "ERROR=1", NULL }; |
| 412 | char *reset_event[] = { "RESET=1", NULL }; |
| 413 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 414 | |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 415 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 416 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 417 | if (atomic_read(&dev_priv->mm.wedged)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 418 | DRM_DEBUG_DRIVER("resetting chip\n"); |
| 419 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 420 | if (!i915_reset(dev, GRDOM_RENDER)) { |
| 421 | atomic_set(&dev_priv->mm.wedged, 0); |
| 422 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 423 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 424 | complete_all(&dev_priv->error_completion); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 425 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 426 | } |
| 427 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 428 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 429 | static struct drm_i915_error_object * |
| 430 | i915_error_object_create(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 431 | struct drm_i915_gem_object *src) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 432 | { |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 433 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 434 | struct drm_i915_error_object *dst; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 435 | int page, page_count; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 436 | u32 reloc_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 437 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 438 | if (src == NULL || src->pages == NULL) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 439 | return NULL; |
| 440 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 441 | page_count = src->base.size / PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 442 | |
| 443 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); |
| 444 | if (dst == NULL) |
| 445 | return NULL; |
| 446 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 447 | reloc_offset = src->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 448 | for (page = 0; page < page_count; page++) { |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 449 | unsigned long flags; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 450 | void __iomem *s; |
| 451 | void *d; |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 452 | |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 453 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 454 | if (d == NULL) |
| 455 | goto unwind; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 456 | |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 457 | local_irq_save(flags); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 458 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 459 | reloc_offset); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 460 | memcpy_fromio(d, s, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 461 | io_mapping_unmap_atomic(s); |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 462 | local_irq_restore(flags); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 463 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 464 | dst->pages[page] = d; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 465 | |
| 466 | reloc_offset += PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 467 | } |
| 468 | dst->page_count = page_count; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 469 | dst->gtt_offset = src->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 470 | |
| 471 | return dst; |
| 472 | |
| 473 | unwind: |
| 474 | while (page--) |
| 475 | kfree(dst->pages[page]); |
| 476 | kfree(dst); |
| 477 | return NULL; |
| 478 | } |
| 479 | |
| 480 | static void |
| 481 | i915_error_object_free(struct drm_i915_error_object *obj) |
| 482 | { |
| 483 | int page; |
| 484 | |
| 485 | if (obj == NULL) |
| 486 | return; |
| 487 | |
| 488 | for (page = 0; page < obj->page_count; page++) |
| 489 | kfree(obj->pages[page]); |
| 490 | |
| 491 | kfree(obj); |
| 492 | } |
| 493 | |
| 494 | static void |
| 495 | i915_error_state_free(struct drm_device *dev, |
| 496 | struct drm_i915_error_state *error) |
| 497 | { |
| 498 | i915_error_object_free(error->batchbuffer[0]); |
| 499 | i915_error_object_free(error->batchbuffer[1]); |
| 500 | i915_error_object_free(error->ringbuffer); |
| 501 | kfree(error->active_bo); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 502 | kfree(error->overlay); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 503 | kfree(error); |
| 504 | } |
| 505 | |
| 506 | static u32 |
| 507 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) |
| 508 | { |
| 509 | u32 cmd; |
| 510 | |
| 511 | if (IS_I830(dev) || IS_845G(dev)) |
| 512 | cmd = MI_BATCH_BUFFER; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 513 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 514 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | |
| 515 | MI_BATCH_NON_SECURE_I965); |
| 516 | else |
| 517 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); |
| 518 | |
| 519 | return ring[0] == cmd ? ring[1] : 0; |
| 520 | } |
| 521 | |
| 522 | static u32 |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 523 | i915_ringbuffer_last_batch(struct drm_device *dev, |
| 524 | struct intel_ring_buffer *ring) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 525 | { |
| 526 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 527 | u32 head, bbaddr; |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 528 | u32 *val; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 529 | |
| 530 | /* Locate the current position in the ringbuffer and walk back |
| 531 | * to find the most recently dispatched batch buffer. |
| 532 | */ |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 533 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 534 | |
Chris Wilson | ab5793a | 2010-11-22 13:24:13 +0000 | [diff] [blame] | 535 | val = (u32 *)(ring->virtual_start + head); |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 536 | while (--val >= (u32 *)ring->virtual_start) { |
| 537 | bbaddr = i915_get_bbaddr(dev, val); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 538 | if (bbaddr) |
Chris Wilson | ab5793a | 2010-11-22 13:24:13 +0000 | [diff] [blame] | 539 | return bbaddr; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 540 | } |
| 541 | |
Chris Wilson | ab5793a | 2010-11-22 13:24:13 +0000 | [diff] [blame] | 542 | val = (u32 *)(ring->virtual_start + ring->size); |
| 543 | while (--val >= (u32 *)ring->virtual_start) { |
| 544 | bbaddr = i915_get_bbaddr(dev, val); |
| 545 | if (bbaddr) |
| 546 | return bbaddr; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 547 | } |
| 548 | |
Chris Wilson | ab5793a | 2010-11-22 13:24:13 +0000 | [diff] [blame] | 549 | return 0; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 550 | } |
| 551 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 552 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
| 553 | int count, |
| 554 | struct list_head *head) |
| 555 | { |
| 556 | struct drm_i915_gem_object *obj; |
| 557 | int i = 0; |
| 558 | |
| 559 | list_for_each_entry(obj, head, mm_list) { |
| 560 | err->size = obj->base.size; |
| 561 | err->name = obj->base.name; |
| 562 | err->seqno = obj->last_rendering_seqno; |
| 563 | err->gtt_offset = obj->gtt_offset; |
| 564 | err->read_domains = obj->base.read_domains; |
| 565 | err->write_domain = obj->base.write_domain; |
| 566 | err->fence_reg = obj->fence_reg; |
| 567 | err->pinned = 0; |
| 568 | if (obj->pin_count > 0) |
| 569 | err->pinned = 1; |
| 570 | if (obj->user_pin_count > 0) |
| 571 | err->pinned = -1; |
| 572 | err->tiling = obj->tiling_mode; |
| 573 | err->dirty = obj->dirty; |
| 574 | err->purgeable = obj->madv != I915_MADV_WILLNEED; |
Chris Wilson | 3685092 | 2010-11-23 08:49:38 +0000 | [diff] [blame] | 575 | err->ring = obj->ring ? obj->ring->id : 0; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 576 | |
| 577 | if (++i == count) |
| 578 | break; |
| 579 | |
| 580 | err++; |
| 581 | } |
| 582 | |
| 583 | return i; |
| 584 | } |
| 585 | |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 586 | static void i915_gem_record_fences(struct drm_device *dev, |
| 587 | struct drm_i915_error_state *error) |
| 588 | { |
| 589 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 590 | int i; |
| 591 | |
| 592 | /* Fences */ |
| 593 | switch (INTEL_INFO(dev)->gen) { |
| 594 | case 6: |
| 595 | for (i = 0; i < 16; i++) |
| 596 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); |
| 597 | break; |
| 598 | case 5: |
| 599 | case 4: |
| 600 | for (i = 0; i < 16; i++) |
| 601 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); |
| 602 | break; |
| 603 | case 3: |
| 604 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 605 | for (i = 0; i < 8; i++) |
| 606 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); |
| 607 | case 2: |
| 608 | for (i = 0; i < 8; i++) |
| 609 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); |
| 610 | break; |
| 611 | |
| 612 | } |
| 613 | } |
| 614 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 615 | /** |
| 616 | * i915_capture_error_state - capture an error record for later analysis |
| 617 | * @dev: drm device |
| 618 | * |
| 619 | * Should be called when an error is detected (either a hang or an error |
| 620 | * interrupt) to capture error state from the time of the error. Fills |
| 621 | * out a structure which becomes available in debugfs for user level tools |
| 622 | * to pick up. |
| 623 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 624 | static void i915_capture_error_state(struct drm_device *dev) |
| 625 | { |
| 626 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 627 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 628 | struct drm_i915_error_state *error; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 629 | struct drm_i915_gem_object *batchbuffer[2]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 630 | unsigned long flags; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 631 | u32 bbaddr; |
| 632 | int count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 633 | |
| 634 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 635 | error = dev_priv->first_error; |
| 636 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 637 | if (error) |
| 638 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 639 | |
| 640 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 641 | if (!error) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 642 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
| 643 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 644 | } |
| 645 | |
Chris Wilson | 2fa772f | 2010-10-01 13:23:27 +0100 | [diff] [blame] | 646 | DRM_DEBUG_DRIVER("generating error event\n"); |
| 647 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 648 | error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 649 | error->eir = I915_READ(EIR); |
| 650 | error->pgtbl_er = I915_READ(PGTBL_ER); |
| 651 | error->pipeastat = I915_READ(PIPEASTAT); |
| 652 | error->pipebstat = I915_READ(PIPEBSTAT); |
| 653 | error->instpm = I915_READ(INSTPM); |
Chris Wilson | f406839 | 2010-10-27 20:36:41 +0100 | [diff] [blame] | 654 | error->error = 0; |
| 655 | if (INTEL_INFO(dev)->gen >= 6) { |
| 656 | error->error = I915_READ(ERROR_GEN6); |
Chris Wilson | add354d | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 657 | |
Chris Wilson | 1d8f38f | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 658 | error->bcs_acthd = I915_READ(BCS_ACTHD); |
| 659 | error->bcs_ipehr = I915_READ(BCS_IPEHR); |
| 660 | error->bcs_ipeir = I915_READ(BCS_IPEIR); |
| 661 | error->bcs_instdone = I915_READ(BCS_INSTDONE); |
| 662 | error->bcs_seqno = 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 663 | if (dev_priv->ring[BCS].get_seqno) |
| 664 | error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]); |
Chris Wilson | add354d | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 665 | |
| 666 | error->vcs_acthd = I915_READ(VCS_ACTHD); |
| 667 | error->vcs_ipehr = I915_READ(VCS_IPEHR); |
| 668 | error->vcs_ipeir = I915_READ(VCS_IPEIR); |
| 669 | error->vcs_instdone = I915_READ(VCS_INSTDONE); |
| 670 | error->vcs_seqno = 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 671 | if (dev_priv->ring[VCS].get_seqno) |
| 672 | error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]); |
Chris Wilson | f406839 | 2010-10-27 20:36:41 +0100 | [diff] [blame] | 673 | } |
| 674 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 675 | error->ipeir = I915_READ(IPEIR_I965); |
| 676 | error->ipehr = I915_READ(IPEHR_I965); |
| 677 | error->instdone = I915_READ(INSTDONE_I965); |
| 678 | error->instps = I915_READ(INSTPS); |
| 679 | error->instdone1 = I915_READ(INSTDONE1); |
| 680 | error->acthd = I915_READ(ACTHD_I965); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 681 | error->bbaddr = I915_READ64(BB_ADDR); |
Chris Wilson | f406839 | 2010-10-27 20:36:41 +0100 | [diff] [blame] | 682 | } else { |
| 683 | error->ipeir = I915_READ(IPEIR); |
| 684 | error->ipehr = I915_READ(IPEHR); |
| 685 | error->instdone = I915_READ(INSTDONE); |
| 686 | error->acthd = I915_READ(ACTHD); |
| 687 | error->bbaddr = 0; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 688 | } |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 689 | i915_gem_record_fences(dev, error); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 690 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 691 | bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->ring[RCS]); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 692 | |
| 693 | /* Grab the current batchbuffer, most likely to have crashed. */ |
| 694 | batchbuffer[0] = NULL; |
| 695 | batchbuffer[1] = NULL; |
| 696 | count = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 697 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 698 | if (batchbuffer[0] == NULL && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 699 | bbaddr >= obj->gtt_offset && |
| 700 | bbaddr < obj->gtt_offset + obj->base.size) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 701 | batchbuffer[0] = obj; |
| 702 | |
| 703 | if (batchbuffer[1] == NULL && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 704 | error->acthd >= obj->gtt_offset && |
| 705 | error->acthd < obj->gtt_offset + obj->base.size) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 706 | batchbuffer[1] = obj; |
| 707 | |
| 708 | count++; |
| 709 | } |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 710 | /* Scan the other lists for completeness for those bizarre errors. */ |
| 711 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 712 | list_for_each_entry(obj, &dev_priv->mm.flushing_list, mm_list) { |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 713 | if (batchbuffer[0] == NULL && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 714 | bbaddr >= obj->gtt_offset && |
| 715 | bbaddr < obj->gtt_offset + obj->base.size) |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 716 | batchbuffer[0] = obj; |
| 717 | |
| 718 | if (batchbuffer[1] == NULL && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 719 | error->acthd >= obj->gtt_offset && |
| 720 | error->acthd < obj->gtt_offset + obj->base.size) |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 721 | batchbuffer[1] = obj; |
| 722 | |
| 723 | if (batchbuffer[0] && batchbuffer[1]) |
| 724 | break; |
| 725 | } |
| 726 | } |
| 727 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 728 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) { |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 729 | if (batchbuffer[0] == NULL && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 730 | bbaddr >= obj->gtt_offset && |
| 731 | bbaddr < obj->gtt_offset + obj->base.size) |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 732 | batchbuffer[0] = obj; |
| 733 | |
| 734 | if (batchbuffer[1] == NULL && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 735 | error->acthd >= obj->gtt_offset && |
| 736 | error->acthd < obj->gtt_offset + obj->base.size) |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 737 | batchbuffer[1] = obj; |
| 738 | |
| 739 | if (batchbuffer[0] && batchbuffer[1]) |
| 740 | break; |
| 741 | } |
| 742 | } |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 743 | |
| 744 | /* We need to copy these to an anonymous buffer as the simplest |
Andrea Gelmini | 139d363 | 2010-10-15 17:14:33 +0200 | [diff] [blame] | 745 | * method to avoid being overwritten by userspace. |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 746 | */ |
| 747 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 748 | if (batchbuffer[1] != batchbuffer[0]) |
| 749 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); |
| 750 | else |
| 751 | error->batchbuffer[1] = NULL; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 752 | |
| 753 | /* Record the ringbuffer */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 754 | error->ringbuffer = i915_error_object_create(dev, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 755 | dev_priv->ring[RCS].obj); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 756 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 757 | /* Record buffers on the active and pinned lists. */ |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 758 | error->active_bo = NULL; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 759 | error->pinned_bo = NULL; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 760 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 761 | error->active_bo_count = count; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 762 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 763 | count++; |
| 764 | error->pinned_bo_count = count - error->active_bo_count; |
| 765 | |
| 766 | if (count) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 767 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, |
| 768 | GFP_ATOMIC); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 769 | if (error->active_bo) |
| 770 | error->pinned_bo = |
| 771 | error->active_bo + error->active_bo_count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 772 | } |
| 773 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 774 | if (error->active_bo) |
| 775 | error->active_bo_count = |
| 776 | capture_bo_list(error->active_bo, |
| 777 | error->active_bo_count, |
| 778 | &dev_priv->mm.active_list); |
| 779 | |
| 780 | if (error->pinned_bo) |
| 781 | error->pinned_bo_count = |
| 782 | capture_bo_list(error->pinned_bo, |
| 783 | error->pinned_bo_count, |
| 784 | &dev_priv->mm.pinned_list); |
| 785 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 786 | do_gettimeofday(&error->time); |
| 787 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 788 | error->overlay = intel_overlay_capture_error_state(dev); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 789 | error->display = intel_display_capture_error_state(dev); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 790 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 791 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 792 | if (dev_priv->first_error == NULL) { |
| 793 | dev_priv->first_error = error; |
| 794 | error = NULL; |
| 795 | } |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 796 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 797 | |
| 798 | if (error) |
| 799 | i915_error_state_free(dev, error); |
| 800 | } |
| 801 | |
| 802 | void i915_destroy_error_state(struct drm_device *dev) |
| 803 | { |
| 804 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 805 | struct drm_i915_error_state *error; |
| 806 | |
| 807 | spin_lock(&dev_priv->error_lock); |
| 808 | error = dev_priv->first_error; |
| 809 | dev_priv->first_error = NULL; |
| 810 | spin_unlock(&dev_priv->error_lock); |
| 811 | |
| 812 | if (error) |
| 813 | i915_error_state_free(dev, error); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 814 | } |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 815 | #else |
| 816 | #define i915_capture_error_state(x) |
| 817 | #endif |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 818 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 819 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 820 | { |
| 821 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 822 | u32 eir = I915_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 823 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 824 | if (!eir) |
| 825 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 826 | |
| 827 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", |
| 828 | eir); |
| 829 | |
| 830 | if (IS_G4X(dev)) { |
| 831 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 832 | u32 ipeir = I915_READ(IPEIR_I965); |
| 833 | |
| 834 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 835 | I915_READ(IPEIR_I965)); |
| 836 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 837 | I915_READ(IPEHR_I965)); |
| 838 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 839 | I915_READ(INSTDONE_I965)); |
| 840 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 841 | I915_READ(INSTPS)); |
| 842 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 843 | I915_READ(INSTDONE1)); |
| 844 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 845 | I915_READ(ACTHD_I965)); |
| 846 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 847 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 848 | } |
| 849 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 850 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 851 | printk(KERN_ERR "page table error\n"); |
| 852 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 853 | pgtbl_err); |
| 854 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 855 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 856 | } |
| 857 | } |
| 858 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 859 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 860 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 861 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 862 | printk(KERN_ERR "page table error\n"); |
| 863 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 864 | pgtbl_err); |
| 865 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 866 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 867 | } |
| 868 | } |
| 869 | |
| 870 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 871 | u32 pipea_stats = I915_READ(PIPEASTAT); |
| 872 | u32 pipeb_stats = I915_READ(PIPEBSTAT); |
| 873 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 874 | printk(KERN_ERR "memory refresh error\n"); |
| 875 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", |
| 876 | pipea_stats); |
| 877 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", |
| 878 | pipeb_stats); |
| 879 | /* pipestat has already been acked */ |
| 880 | } |
| 881 | if (eir & I915_ERROR_INSTRUCTION) { |
| 882 | printk(KERN_ERR "instruction error\n"); |
| 883 | printk(KERN_ERR " INSTPM: 0x%08x\n", |
| 884 | I915_READ(INSTPM)); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 885 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 886 | u32 ipeir = I915_READ(IPEIR); |
| 887 | |
| 888 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 889 | I915_READ(IPEIR)); |
| 890 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 891 | I915_READ(IPEHR)); |
| 892 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 893 | I915_READ(INSTDONE)); |
| 894 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 895 | I915_READ(ACTHD)); |
| 896 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 897 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 898 | } else { |
| 899 | u32 ipeir = I915_READ(IPEIR_I965); |
| 900 | |
| 901 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 902 | I915_READ(IPEIR_I965)); |
| 903 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 904 | I915_READ(IPEHR_I965)); |
| 905 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 906 | I915_READ(INSTDONE_I965)); |
| 907 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 908 | I915_READ(INSTPS)); |
| 909 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 910 | I915_READ(INSTDONE1)); |
| 911 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 912 | I915_READ(ACTHD_I965)); |
| 913 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 914 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 915 | } |
| 916 | } |
| 917 | |
| 918 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 919 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 920 | eir = I915_READ(EIR); |
| 921 | if (eir) { |
| 922 | /* |
| 923 | * some errors might have become stuck, |
| 924 | * mask them. |
| 925 | */ |
| 926 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 927 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 928 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 929 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 930 | } |
| 931 | |
| 932 | /** |
| 933 | * i915_handle_error - handle an error interrupt |
| 934 | * @dev: drm device |
| 935 | * |
| 936 | * Do some basic checking of regsiter state at error interrupt time and |
| 937 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 938 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 939 | * so userspace knows something bad happened (should trigger collection |
| 940 | * of a ring dump etc.). |
| 941 | */ |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 942 | void i915_handle_error(struct drm_device *dev, bool wedged) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 943 | { |
| 944 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 945 | |
| 946 | i915_capture_error_state(dev); |
| 947 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 948 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 949 | if (wedged) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 950 | INIT_COMPLETION(dev_priv->error_completion); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 951 | atomic_set(&dev_priv->mm.wedged, 1); |
| 952 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 953 | /* |
| 954 | * Wakeup waiting processes so they don't hang |
| 955 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 956 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 957 | if (HAS_BSD(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 958 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 959 | if (HAS_BLT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 960 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 961 | } |
| 962 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 963 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 964 | } |
| 965 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 966 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
| 967 | { |
| 968 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 969 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 971 | struct drm_i915_gem_object *obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 972 | struct intel_unpin_work *work; |
| 973 | unsigned long flags; |
| 974 | bool stall_detected; |
| 975 | |
| 976 | /* Ignore early vblank irqs */ |
| 977 | if (intel_crtc == NULL) |
| 978 | return; |
| 979 | |
| 980 | spin_lock_irqsave(&dev->event_lock, flags); |
| 981 | work = intel_crtc->unpin_work; |
| 982 | |
| 983 | if (work == NULL || work->pending || !work->enable_stall_check) { |
| 984 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 985 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 986 | return; |
| 987 | } |
| 988 | |
| 989 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 990 | obj = work->pending_flip_obj; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 991 | if (INTEL_INFO(dev)->gen >= 4) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 992 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 993 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 994 | } else { |
| 995 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 996 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 997 | crtc->y * crtc->fb->pitch + |
| 998 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 999 | } |
| 1000 | |
| 1001 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1002 | |
| 1003 | if (stall_detected) { |
| 1004 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 1005 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 1006 | } |
| 1007 | } |
| 1008 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1009 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 1010 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1011 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1013 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1014 | u32 iir, new_iir; |
| 1015 | u32 pipea_stats, pipeb_stats; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1016 | u32 vblank_status; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1017 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1018 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1019 | int irq_received; |
| 1020 | int ret = IRQ_NONE; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1021 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 1022 | atomic_inc(&dev_priv->irq_received); |
| 1023 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1024 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1025 | return ironlake_irq_handler(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1026 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1027 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1028 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1029 | if (INTEL_INFO(dev)->gen >= 4) |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 1030 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
Jesse Barnes | e25e660 | 2010-06-30 13:15:19 -0700 | [diff] [blame] | 1031 | else |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 1032 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1033 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1034 | for (;;) { |
| 1035 | irq_received = iir != 0; |
| 1036 | |
| 1037 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 1038 | * have been cleared after the pipestat interrupt was received. |
| 1039 | * It doesn't set the bit in iir again, but it still produces |
| 1040 | * interrupts (for non-MSI). |
| 1041 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1042 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1043 | pipea_stats = I915_READ(PIPEASTAT); |
| 1044 | pipeb_stats = I915_READ(PIPEBSTAT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1045 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1046 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1047 | i915_handle_error(dev, false); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1048 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1049 | /* |
| 1050 | * Clear the PIPE(A|B)STAT regs before the IIR |
| 1051 | */ |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1052 | if (pipea_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1053 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1054 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1055 | I915_WRITE(PIPEASTAT, pipea_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1056 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1057 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1058 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1059 | if (pipeb_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1060 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1061 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1062 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1063 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1064 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1065 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1066 | |
| 1067 | if (!irq_received) |
| 1068 | break; |
| 1069 | |
| 1070 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1072 | /* Consume port. Then clear IIR or we'll miss events */ |
| 1073 | if ((I915_HAS_HOTPLUG(dev)) && |
| 1074 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 1075 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 1076 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1077 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1078 | hotplug_status); |
| 1079 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1080 | queue_work(dev_priv->wq, |
| 1081 | &dev_priv->hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1082 | |
| 1083 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1084 | I915_READ(PORT_HOTPLUG_STAT); |
| 1085 | } |
| 1086 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1087 | I915_WRITE(IIR, iir); |
| 1088 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1089 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1090 | if (dev->primary->master) { |
| 1091 | master_priv = dev->primary->master->driver_priv; |
| 1092 | if (master_priv->sarea_priv) |
| 1093 | master_priv->sarea_priv->last_dispatch = |
| 1094 | READ_BREADCRUMB(dev_priv); |
| 1095 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1096 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1097 | if (iir & I915_USER_INTERRUPT) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1098 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 1099 | if (iir & I915_BSD_USER_INTERRUPT) |
| 1100 | notify_ring(dev, &dev_priv->ring[VCS]); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1101 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1102 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1103 | intel_prepare_page_flip(dev, 0); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1104 | if (dev_priv->flip_pending_is_done) |
| 1105 | intel_finish_page_flip_plane(dev, 0); |
| 1106 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1107 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1108 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
Jesse Barnes | 70565d0 | 2010-07-01 04:45:43 -0700 | [diff] [blame] | 1109 | intel_prepare_page_flip(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1110 | if (dev_priv->flip_pending_is_done) |
| 1111 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1112 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1113 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1114 | if (pipea_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1115 | vblank++; |
| 1116 | drm_handle_vblank(dev, 0); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1117 | if (!dev_priv->flip_pending_is_done) { |
| 1118 | i915_pageflip_stall_check(dev, 0); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1119 | intel_finish_page_flip(dev, 0); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1120 | } |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1121 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1122 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1123 | if (pipeb_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1124 | vblank++; |
| 1125 | drm_handle_vblank(dev, 1); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1126 | if (!dev_priv->flip_pending_is_done) { |
| 1127 | i915_pageflip_stall_check(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1128 | intel_finish_page_flip(dev, 1); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1129 | } |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1130 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1131 | |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 1132 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
| 1133 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1134 | (iir & I915_ASLE_INTERRUPT)) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1135 | intel_opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1136 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1137 | /* With MSI, interrupts are only generated when iir |
| 1138 | * transitions from zero to nonzero. If another bit got |
| 1139 | * set while we were handling the existing iir bits, then |
| 1140 | * we would never get another interrupt. |
| 1141 | * |
| 1142 | * This is fine on non-MSI as well, as if we hit this path |
| 1143 | * we avoid exiting the interrupt handler only to generate |
| 1144 | * another one. |
| 1145 | * |
| 1146 | * Note that for MSI this could cause a stray interrupt report |
| 1147 | * if an interrupt landed in the time between writing IIR and |
| 1148 | * the posting read. This should be rare enough to never |
| 1149 | * trigger the 99% of 100,000 interrupts test for disabling |
| 1150 | * stray interrupts. |
| 1151 | */ |
| 1152 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1153 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1154 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1155 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | } |
| 1157 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1158 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | { |
| 1160 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1161 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | |
| 1163 | i915_kernel_lost_context(dev); |
| 1164 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1165 | DRM_DEBUG_DRIVER("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1167 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1168 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1169 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1170 | if (master_priv->sarea_priv) |
| 1171 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1172 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1173 | if (BEGIN_LP_RING(4) == 0) { |
| 1174 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1175 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1176 | OUT_RING(dev_priv->counter); |
| 1177 | OUT_RING(MI_USER_INTERRUPT); |
| 1178 | ADVANCE_LP_RING(); |
| 1179 | } |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1180 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1181 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1182 | } |
| 1183 | |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1184 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
| 1185 | { |
| 1186 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1187 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1188 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame^] | 1189 | if (dev_priv->trace_irq_seqno == 0 && |
| 1190 | ring->irq_get(ring)) |
| 1191 | dev_priv->trace_irq_seqno = seqno; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1192 | } |
| 1193 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1194 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1195 | { |
| 1196 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1197 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1198 | int ret = 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1199 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1201 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1202 | READ_BREADCRUMB(dev_priv)); |
| 1203 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1204 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1205 | if (master_priv->sarea_priv) |
| 1206 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1207 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1208 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1209 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1210 | if (master_priv->sarea_priv) |
| 1211 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1212 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame^] | 1213 | ret = -ENODEV; |
| 1214 | if (ring->irq_get(ring)) { |
| 1215 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, |
| 1216 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
| 1217 | ring->irq_put(ring); |
| 1218 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1219 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1220 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1221 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1222 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 1223 | } |
| 1224 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1225 | return ret; |
| 1226 | } |
| 1227 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1228 | /* Needs the lock as it touches the ring. |
| 1229 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1230 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 1231 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1232 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1233 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1234 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | int result; |
| 1236 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1237 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1238 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1239 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1240 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 1241 | |
| 1242 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 1243 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1244 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1245 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1246 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1247 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1248 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1249 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1250 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1251 | } |
| 1252 | |
| 1253 | return 0; |
| 1254 | } |
| 1255 | |
| 1256 | /* Doesn't need the hardware lock. |
| 1257 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1258 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 1259 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1260 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1262 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1263 | |
| 1264 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1265 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1266 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1267 | } |
| 1268 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1269 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1270 | } |
| 1271 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1272 | /* Called from drm generic code, passed 'crtc' which |
| 1273 | * we use as a pipe index |
| 1274 | */ |
| 1275 | int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1276 | { |
| 1277 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1278 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1279 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1280 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1281 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1282 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1283 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1284 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1285 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 1286 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1287 | else if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1288 | i915_enable_pipestat(dev_priv, pipe, |
| 1289 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1290 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1291 | i915_enable_pipestat(dev_priv, pipe, |
| 1292 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1293 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1294 | return 0; |
| 1295 | } |
| 1296 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1297 | /* Called from drm generic code, passed 'crtc' which |
| 1298 | * we use as a pipe index |
| 1299 | */ |
| 1300 | void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1301 | { |
| 1302 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1303 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1304 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1305 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1306 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1307 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 1308 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
| 1309 | else |
| 1310 | i915_disable_pipestat(dev_priv, pipe, |
| 1311 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 1312 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1313 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1314 | } |
| 1315 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1316 | void i915_enable_interrupt (struct drm_device *dev) |
| 1317 | { |
| 1318 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 1319 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1320 | if (!HAS_PCH_SPLIT(dev)) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1321 | intel_opregion_enable_asle(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1322 | dev_priv->irq_enabled = 1; |
| 1323 | } |
| 1324 | |
| 1325 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1326 | /* Set the vblank monitor pipe |
| 1327 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1328 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 1329 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1330 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1331 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1332 | |
| 1333 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1334 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1335 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1336 | } |
| 1337 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 1338 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1339 | } |
| 1340 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1341 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 1342 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1343 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1344 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1345 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1346 | |
| 1347 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1348 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1349 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1350 | } |
| 1351 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1352 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1353 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1354 | return 0; |
| 1355 | } |
| 1356 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1357 | /** |
| 1358 | * Schedule buffer swap at given vertical blank. |
| 1359 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1360 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 1361 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1362 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1363 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 1364 | * removed. The model was that the client requested a delayed flip/swap |
| 1365 | * from the kernel, then waited for vblank before continuing to perform |
| 1366 | * rendering. The problem was that the kernel might wake the client |
| 1367 | * up before it dispatched the vblank swap (since the lock has to be |
| 1368 | * held while touching the ringbuffer), in which case the client would |
| 1369 | * clear and start the next frame before the swap occurred, and |
| 1370 | * flicker would occur in addition to likely missing the vblank. |
| 1371 | * |
| 1372 | * In the absence of this ioctl, userland falls back to a correct path |
| 1373 | * of waiting for a vblank, then dispatching the swap on its own. |
| 1374 | * Context switching to userland and back is plenty fast enough for |
| 1375 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1376 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1377 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1378 | } |
| 1379 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1380 | static u32 |
| 1381 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1382 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1383 | return list_entry(ring->request_list.prev, |
| 1384 | struct drm_i915_gem_request, list)->seqno; |
| 1385 | } |
| 1386 | |
| 1387 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) |
| 1388 | { |
| 1389 | if (list_empty(&ring->request_list) || |
| 1390 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { |
| 1391 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1392 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1393 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
| 1394 | ring->name, |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1395 | ring->waiting_seqno, |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1396 | ring->get_seqno(ring)); |
| 1397 | wake_up_all(&ring->irq_queue); |
| 1398 | *err = true; |
| 1399 | } |
| 1400 | return true; |
| 1401 | } |
| 1402 | return false; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1403 | } |
| 1404 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1405 | static bool kick_ring(struct intel_ring_buffer *ring) |
| 1406 | { |
| 1407 | struct drm_device *dev = ring->dev; |
| 1408 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1409 | u32 tmp = I915_READ_CTL(ring); |
| 1410 | if (tmp & RING_WAIT) { |
| 1411 | DRM_ERROR("Kicking stuck wait on %s\n", |
| 1412 | ring->name); |
| 1413 | I915_WRITE_CTL(ring, tmp); |
| 1414 | return true; |
| 1415 | } |
| 1416 | if (IS_GEN6(dev) && |
| 1417 | (tmp & RING_WAIT_SEMAPHORE)) { |
| 1418 | DRM_ERROR("Kicking stuck semaphore on %s\n", |
| 1419 | ring->name); |
| 1420 | I915_WRITE_CTL(ring, tmp); |
| 1421 | return true; |
| 1422 | } |
| 1423 | return false; |
| 1424 | } |
| 1425 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1426 | /** |
| 1427 | * This is called when the chip hasn't reported back with completed |
| 1428 | * batchbuffers in a long time. The first time this is called we simply record |
| 1429 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 1430 | * again, we assume the chip is wedged and try to fix it. |
| 1431 | */ |
| 1432 | void i915_hangcheck_elapsed(unsigned long data) |
| 1433 | { |
| 1434 | struct drm_device *dev = (struct drm_device *)data; |
| 1435 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1436 | uint32_t acthd, instdone, instdone1; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1437 | bool err = false; |
| 1438 | |
| 1439 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1440 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
| 1441 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && |
| 1442 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1443 | dev_priv->hangcheck_count = 0; |
| 1444 | if (err) |
| 1445 | goto repeat; |
| 1446 | return; |
| 1447 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 1448 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1449 | if (INTEL_INFO(dev)->gen < 4) { |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1450 | acthd = I915_READ(ACTHD); |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1451 | instdone = I915_READ(INSTDONE); |
| 1452 | instdone1 = 0; |
| 1453 | } else { |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1454 | acthd = I915_READ(ACTHD_I965); |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1455 | instdone = I915_READ(INSTDONE_I965); |
| 1456 | instdone1 = I915_READ(INSTDONE1); |
| 1457 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1458 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1459 | if (dev_priv->last_acthd == acthd && |
| 1460 | dev_priv->last_instdone == instdone && |
| 1461 | dev_priv->last_instdone1 == instdone1) { |
| 1462 | if (dev_priv->hangcheck_count++ > 1) { |
| 1463 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
Chris Wilson | 8c80b59 | 2010-08-08 20:38:12 +0100 | [diff] [blame] | 1464 | |
| 1465 | if (!IS_GEN2(dev)) { |
| 1466 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 1467 | * If so we can simply poke the RB_WAIT bit |
| 1468 | * and break the hang. This should work on |
| 1469 | * all but the second generation chipsets. |
| 1470 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1471 | |
| 1472 | if (kick_ring(&dev_priv->ring[RCS])) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1473 | goto repeat; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1474 | |
| 1475 | if (HAS_BSD(dev) && |
| 1476 | kick_ring(&dev_priv->ring[VCS])) |
| 1477 | goto repeat; |
| 1478 | |
| 1479 | if (HAS_BLT(dev) && |
| 1480 | kick_ring(&dev_priv->ring[BCS])) |
| 1481 | goto repeat; |
Chris Wilson | 8c80b59 | 2010-08-08 20:38:12 +0100 | [diff] [blame] | 1482 | } |
| 1483 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1484 | i915_handle_error(dev, true); |
| 1485 | return; |
| 1486 | } |
| 1487 | } else { |
| 1488 | dev_priv->hangcheck_count = 0; |
| 1489 | |
| 1490 | dev_priv->last_acthd = acthd; |
| 1491 | dev_priv->last_instdone = instdone; |
| 1492 | dev_priv->last_instdone1 = instdone1; |
| 1493 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1494 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1495 | repeat: |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1496 | /* Reset timer case chip hangs without another request being added */ |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1497 | mod_timer(&dev_priv->hangcheck_timer, |
| 1498 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1499 | } |
| 1500 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1501 | /* drm_dma.h hooks |
| 1502 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1503 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1504 | { |
| 1505 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1506 | |
| 1507 | I915_WRITE(HWSTAM, 0xeffe); |
| 1508 | |
| 1509 | /* XXX hotplug from PCH */ |
| 1510 | |
| 1511 | I915_WRITE(DEIMR, 0xffffffff); |
| 1512 | I915_WRITE(DEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1513 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1514 | |
| 1515 | /* and GT */ |
| 1516 | I915_WRITE(GTIMR, 0xffffffff); |
| 1517 | I915_WRITE(GTIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1518 | POSTING_READ(GTIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1519 | |
| 1520 | /* south display irq */ |
| 1521 | I915_WRITE(SDEIMR, 0xffffffff); |
| 1522 | I915_WRITE(SDEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1523 | POSTING_READ(SDEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1524 | } |
| 1525 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1526 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1527 | { |
| 1528 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1529 | /* enable kind of interrupts always enabled */ |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 1530 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 1531 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1532 | u32 render_irqs; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1533 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1534 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1535 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1536 | |
| 1537 | /* should always can generate irq */ |
| 1538 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1539 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
| 1540 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1541 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1542 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1543 | dev_priv->gt_irq_mask = ~0; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1544 | |
| 1545 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1546 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1547 | if (IS_GEN6(dev)) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1548 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_USER_INTERRUPT); |
| 1549 | I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1550 | I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1551 | } |
| 1552 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1553 | if (IS_GEN6(dev)) |
| 1554 | render_irqs = |
| 1555 | GT_USER_INTERRUPT | |
| 1556 | GT_GEN6_BSD_USER_INTERRUPT | |
| 1557 | GT_BLT_USER_INTERRUPT; |
| 1558 | else |
| 1559 | render_irqs = |
Chris Wilson | 88f23b8 | 2010-12-05 15:08:31 +0000 | [diff] [blame] | 1560 | GT_USER_INTERRUPT | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1561 | GT_BSD_USER_INTERRUPT; |
| 1562 | I915_WRITE(GTIER, render_irqs); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1563 | POSTING_READ(GTIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1564 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1565 | if (HAS_PCH_CPT(dev)) { |
| 1566 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | |
| 1567 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; |
| 1568 | } else { |
| 1569 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
| 1570 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; |
| 1571 | } |
| 1572 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1573 | dev_priv->pch_irq_mask = ~hotplug_mask; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1574 | |
| 1575 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1576 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
| 1577 | I915_WRITE(SDEIER, hotplug_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1578 | POSTING_READ(SDEIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1579 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1580 | if (IS_IRONLAKE_M(dev)) { |
| 1581 | /* Clear & enable PCU event interrupts */ |
| 1582 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 1583 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); |
| 1584 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
| 1585 | } |
| 1586 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1587 | return 0; |
| 1588 | } |
| 1589 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1590 | void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1591 | { |
| 1592 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1593 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1594 | atomic_set(&dev_priv->irq_received, 0); |
| 1595 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1596 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1597 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1598 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1599 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1600 | ironlake_irq_preinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1601 | return; |
| 1602 | } |
| 1603 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1604 | if (I915_HAS_HOTPLUG(dev)) { |
| 1605 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1606 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1607 | } |
| 1608 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1609 | I915_WRITE(HWSTAM, 0xeffe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1610 | I915_WRITE(PIPEASTAT, 0); |
| 1611 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1612 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1613 | I915_WRITE(IER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1614 | POSTING_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1615 | } |
| 1616 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1617 | /* |
| 1618 | * Must be called after intel_modeset_init or hotplug interrupts won't be |
| 1619 | * enabled correctly. |
| 1620 | */ |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1621 | int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1622 | { |
| 1623 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1624 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1625 | u32 error_mask; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1626 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1627 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1628 | if (HAS_BSD(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1629 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1630 | if (HAS_BLT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1631 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1632 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1633 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1634 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1635 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1636 | return ironlake_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1637 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1638 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1639 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1640 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1641 | dev_priv->pipestat[0] = 0; |
| 1642 | dev_priv->pipestat[1] = 0; |
| 1643 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1644 | if (I915_HAS_HOTPLUG(dev)) { |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 1645 | /* Enable in IER... */ |
| 1646 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 1647 | /* and unmask in IMR */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1648 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 1649 | } |
| 1650 | |
| 1651 | /* |
| 1652 | * Enable some error detection, note the instruction error mask |
| 1653 | * bit is reserved, so we leave it masked. |
| 1654 | */ |
| 1655 | if (IS_G4X(dev)) { |
| 1656 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 1657 | GM45_ERROR_MEM_PRIV | |
| 1658 | GM45_ERROR_CP_PRIV | |
| 1659 | I915_ERROR_MEMORY_REFRESH); |
| 1660 | } else { |
| 1661 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 1662 | I915_ERROR_MEMORY_REFRESH); |
| 1663 | } |
| 1664 | I915_WRITE(EMR, error_mask); |
| 1665 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1666 | I915_WRITE(IMR, dev_priv->irq_mask); |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 1667 | I915_WRITE(IER, enable_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1668 | POSTING_READ(IER); |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 1669 | |
| 1670 | if (I915_HAS_HOTPLUG(dev)) { |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1671 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 1672 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1673 | /* Note HDMI and DP share bits */ |
| 1674 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 1675 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 1676 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 1677 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 1678 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 1679 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 1680 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 1681 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 1682 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 1683 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
Andy Lutomirski | 2d1c975 | 2010-06-12 05:21:18 -0400 | [diff] [blame] | 1684 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1685 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
Andy Lutomirski | 2d1c975 | 2010-06-12 05:21:18 -0400 | [diff] [blame] | 1686 | |
| 1687 | /* Programming the CRT detection parameters tends |
| 1688 | to generate a spurious hotplug event about three |
| 1689 | seconds later. So just do it once. |
| 1690 | */ |
| 1691 | if (IS_G4X(dev)) |
| 1692 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
| 1693 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
| 1694 | } |
| 1695 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1696 | /* Ignore TV since it's buggy */ |
| 1697 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1698 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1699 | } |
| 1700 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1701 | intel_opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1702 | |
| 1703 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1704 | } |
| 1705 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1706 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1707 | { |
| 1708 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1709 | I915_WRITE(HWSTAM, 0xffffffff); |
| 1710 | |
| 1711 | I915_WRITE(DEIMR, 0xffffffff); |
| 1712 | I915_WRITE(DEIER, 0x0); |
| 1713 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1714 | |
| 1715 | I915_WRITE(GTIMR, 0xffffffff); |
| 1716 | I915_WRITE(GTIER, 0x0); |
| 1717 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1718 | } |
| 1719 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1720 | void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1721 | { |
| 1722 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1723 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1724 | if (!dev_priv) |
| 1725 | return; |
| 1726 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1727 | dev_priv->vblank_pipe = 0; |
| 1728 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1729 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1730 | ironlake_irq_uninstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1731 | return; |
| 1732 | } |
| 1733 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1734 | if (I915_HAS_HOTPLUG(dev)) { |
| 1735 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1736 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1737 | } |
| 1738 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1739 | I915_WRITE(HWSTAM, 0xffffffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1740 | I915_WRITE(PIPEASTAT, 0); |
| 1741 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1742 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1743 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1744 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1745 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1746 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1747 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1748 | } |