| Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 1 | config IRQCHIP |
| 2 | def_bool y |
| 3 | depends on OF_IRQ |
| 4 | |
| Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 5 | config ARM_GIC |
| 6 | bool |
| 7 | select IRQ_DOMAIN |
| 8 | select MULTI_IRQ_HANDLER |
| 9 | |
| 10 | config GIC_NON_BANKED |
| 11 | bool |
| 12 | |
| Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 13 | config ARM_NVIC |
| 14 | bool |
| 15 | select IRQ_DOMAIN |
| 16 | select GENERIC_IRQ_CHIP |
| 17 | |
| Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 18 | config ARM_VIC |
| 19 | bool |
| 20 | select IRQ_DOMAIN |
| 21 | select MULTI_IRQ_HANDLER |
| 22 | |
| 23 | config ARM_VIC_NR |
| 24 | int |
| 25 | default 4 if ARCH_S5PV210 |
| 26 | default 3 if ARCH_S5PC100 |
| 27 | default 2 |
| 28 | depends on ARM_VIC |
| 29 | help |
| 30 | The maximum number of VICs available in the system, for |
| 31 | power management. |
| 32 | |
| Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 33 | config BRCMSTB_L2_IRQ |
| 34 | bool |
| 35 | depends on ARM |
| 36 | select GENERIC_IRQ_CHIP |
| 37 | select IRQ_DOMAIN |
| 38 | |
| Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 39 | config DW_APB_ICTL |
| 40 | bool |
| 41 | select IRQ_DOMAIN |
| 42 | |
| James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 43 | config IMGPDC_IRQ |
| 44 | bool |
| 45 | select GENERIC_IRQ_CHIP |
| 46 | select IRQ_DOMAIN |
| 47 | |
| Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 48 | config CLPS711X_IRQCHIP |
| 49 | bool |
| 50 | depends on ARCH_CLPS711X |
| 51 | select IRQ_DOMAIN |
| 52 | select MULTI_IRQ_HANDLER |
| 53 | select SPARSE_IRQ |
| 54 | default y |
| 55 | |
| Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 56 | config ORION_IRQCHIP |
| 57 | bool |
| 58 | select IRQ_DOMAIN |
| 59 | select MULTI_IRQ_HANDLER |
| 60 | |
| Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 61 | config RENESAS_INTC_IRQPIN |
| 62 | bool |
| 63 | select IRQ_DOMAIN |
| 64 | |
| Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 65 | config RENESAS_IRQC |
| 66 | bool |
| 67 | select IRQ_DOMAIN |
| 68 | |
| Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 69 | config TB10X_IRQC |
| 70 | bool |
| 71 | select IRQ_DOMAIN |
| 72 | select GENERIC_IRQ_CHIP |
| 73 | |
| Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 74 | config VERSATILE_FPGA_IRQ |
| 75 | bool |
| 76 | select IRQ_DOMAIN |
| 77 | |
| 78 | config VERSATILE_FPGA_IRQ_NR |
| 79 | int |
| 80 | default 4 |
| 81 | depends on VERSATILE_FPGA_IRQ |
| Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 82 | |
| 83 | config XTENSA_MX |
| 84 | bool |
| 85 | select IRQ_DOMAIN |
| Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 86 | |
| 87 | config IRQ_CROSSBAR |
| 88 | bool |
| 89 | help |
| 90 | Support for a CROSSBAR ip that preceeds the main interrupt controller. |
| 91 | The primary irqchip invokes the crossbar's callback which inturn allocates |
| 92 | a free irq and configures the IP. Thus the peripheral interrupts are |
| 93 | routed to one of the free irqchip interrupt lines. |