Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Christian König. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Christian König |
| 25 | * Rafał Miłecki |
| 26 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 27 | #include <linux/hdmi.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/radeon_drm.h> |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | #include "radeon_asic.h" |
| 32 | #include "evergreend.h" |
| 33 | #include "atom.h" |
| 34 | |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 35 | extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 36 | extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); |
| 37 | extern void dce6_afmt_select_pin(struct drm_encoder *encoder); |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame^] | 38 | extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
| 39 | struct drm_display_mode *mode); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 40 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 41 | /* |
| 42 | * update the N and CTS parameters for a given pixel clock rate |
| 43 | */ |
| 44 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| 45 | { |
| 46 | struct drm_device *dev = encoder->dev; |
| 47 | struct radeon_device *rdev = dev->dev_private; |
| 48 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 49 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 50 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 51 | uint32_t offset = dig->afmt->offset; |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 52 | |
| 53 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
| 54 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
| 55 | |
| 56 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
| 57 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
| 58 | |
| 59 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
| 60 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
| 61 | } |
| 62 | |
Alex Deucher | 712fd8a | 2013-10-10 17:54:51 -0400 | [diff] [blame] | 63 | static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
| 64 | struct drm_display_mode *mode) |
| 65 | { |
| 66 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 67 | struct drm_connector *connector; |
| 68 | struct radeon_connector *radeon_connector = NULL; |
| 69 | u32 tmp = 0; |
| 70 | |
| 71 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 72 | if (connector->encoder == encoder) { |
| 73 | radeon_connector = to_radeon_connector(connector); |
| 74 | break; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | if (!radeon_connector) { |
| 79 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 84 | if (connector->latency_present[1]) |
| 85 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
| 86 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
| 87 | else |
| 88 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
| 89 | } else { |
| 90 | if (connector->latency_present[0]) |
| 91 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
| 92 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
| 93 | else |
| 94 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
| 95 | } |
| 96 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
| 97 | } |
| 98 | |
Alex Deucher | ba7def4 | 2013-08-15 09:34:07 -0400 | [diff] [blame] | 99 | static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
| 100 | { |
| 101 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 102 | struct drm_connector *connector; |
| 103 | struct radeon_connector *radeon_connector = NULL; |
| 104 | u32 tmp; |
| 105 | u8 *sadb; |
| 106 | int sad_count; |
| 107 | |
| 108 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
Alex Deucher | 8a992ee | 2013-10-10 17:58:27 -0400 | [diff] [blame] | 109 | if (connector->encoder == encoder) { |
Alex Deucher | ba7def4 | 2013-08-15 09:34:07 -0400 | [diff] [blame] | 110 | radeon_connector = to_radeon_connector(connector); |
Alex Deucher | 8a992ee | 2013-10-10 17:58:27 -0400 | [diff] [blame] | 111 | break; |
| 112 | } |
Alex Deucher | ba7def4 | 2013-08-15 09:34:07 -0400 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | if (!radeon_connector) { |
| 116 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 117 | return; |
| 118 | } |
| 119 | |
| 120 | sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); |
| 121 | if (sad_count < 0) { |
| 122 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | /* program the speaker allocation */ |
| 127 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
| 128 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
| 129 | /* set HDMI mode */ |
| 130 | tmp |= HDMI_CONNECTION; |
| 131 | if (sad_count) |
| 132 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
| 133 | else |
| 134 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
| 135 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
| 136 | |
| 137 | kfree(sadb); |
| 138 | } |
| 139 | |
Rafał Miłecki | 46892ca | 2013-04-19 19:01:26 +0200 | [diff] [blame] | 140 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
| 141 | { |
| 142 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 143 | struct drm_connector *connector; |
| 144 | struct radeon_connector *radeon_connector = NULL; |
| 145 | struct cea_sad *sads; |
| 146 | int i, sad_count; |
| 147 | |
| 148 | static const u16 eld_reg_to_type[][2] = { |
| 149 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
| 150 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
| 151 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
| 152 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
| 153 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
| 154 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
| 155 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
| 156 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
| 157 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
| 158 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
| 159 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
| 160 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
| 161 | }; |
| 162 | |
| 163 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
Alex Deucher | 8a992ee | 2013-10-10 17:58:27 -0400 | [diff] [blame] | 164 | if (connector->encoder == encoder) { |
Rafał Miłecki | 46892ca | 2013-04-19 19:01:26 +0200 | [diff] [blame] | 165 | radeon_connector = to_radeon_connector(connector); |
Alex Deucher | 8a992ee | 2013-10-10 17:58:27 -0400 | [diff] [blame] | 166 | break; |
| 167 | } |
Rafał Miłecki | 46892ca | 2013-04-19 19:01:26 +0200 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | if (!radeon_connector) { |
| 171 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); |
| 176 | if (sad_count < 0) { |
| 177 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 178 | return; |
| 179 | } |
| 180 | BUG_ON(!sads); |
| 181 | |
| 182 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
| 183 | u32 value = 0; |
| 184 | int j; |
| 185 | |
| 186 | for (j = 0; j < sad_count; j++) { |
| 187 | struct cea_sad *sad = &sads[j]; |
| 188 | |
| 189 | if (sad->format == eld_reg_to_type[i][1]) { |
| 190 | value = MAX_CHANNELS(sad->channels) | |
| 191 | DESCRIPTOR_BYTE_2(sad->byte2) | |
| 192 | SUPPORTED_FREQUENCIES(sad->freq); |
| 193 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
| 194 | value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); |
| 195 | break; |
| 196 | } |
| 197 | } |
| 198 | WREG32(eld_reg_to_type[i][0], value); |
| 199 | } |
| 200 | |
| 201 | kfree(sads); |
| 202 | } |
| 203 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 204 | /* |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 205 | * build a HDMI Video Info Frame |
| 206 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 207 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
| 208 | void *buffer, size_t size) |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 209 | { |
| 210 | struct drm_device *dev = encoder->dev; |
| 211 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 212 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 213 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 214 | uint32_t offset = dig->afmt->offset; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 215 | uint8_t *frame = buffer + 3; |
Alex Deucher | f100380 | 2013-06-07 10:41:03 -0400 | [diff] [blame] | 216 | uint8_t *header = buffer; |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 217 | |
| 218 | WREG32(AFMT_AVI_INFO0 + offset, |
| 219 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
| 220 | WREG32(AFMT_AVI_INFO1 + offset, |
| 221 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
| 222 | WREG32(AFMT_AVI_INFO2 + offset, |
| 223 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
| 224 | WREG32(AFMT_AVI_INFO3 + offset, |
Alex Deucher | f100380 | 2013-06-07 10:41:03 -0400 | [diff] [blame] | 225 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 226 | } |
| 227 | |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 228 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
| 229 | { |
| 230 | struct drm_device *dev = encoder->dev; |
| 231 | struct radeon_device *rdev = dev->dev_private; |
| 232 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 233 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 234 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
Alex Deucher | 731da21 | 2013-05-13 11:35:26 -0400 | [diff] [blame] | 235 | u32 base_rate = 24000; |
Alex Deucher | 1518dd8 | 2013-07-30 17:31:07 -0400 | [diff] [blame] | 236 | u32 max_ratio = clock / base_rate; |
| 237 | u32 dto_phase; |
| 238 | u32 dto_modulo = clock; |
| 239 | u32 wallclock_ratio; |
| 240 | u32 dto_cntl; |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 241 | |
| 242 | if (!dig || !dig->afmt) |
| 243 | return; |
| 244 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 245 | if (ASIC_IS_DCE6(rdev)) { |
Alex Deucher | 1518dd8 | 2013-07-30 17:31:07 -0400 | [diff] [blame] | 246 | dto_phase = 24 * 1000; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 247 | } else { |
| 248 | if (max_ratio >= 8) { |
| 249 | dto_phase = 192 * 1000; |
| 250 | wallclock_ratio = 3; |
| 251 | } else if (max_ratio >= 4) { |
| 252 | dto_phase = 96 * 1000; |
| 253 | wallclock_ratio = 2; |
| 254 | } else if (max_ratio >= 2) { |
| 255 | dto_phase = 48 * 1000; |
| 256 | wallclock_ratio = 1; |
| 257 | } else { |
| 258 | dto_phase = 24 * 1000; |
| 259 | wallclock_ratio = 0; |
| 260 | } |
| 261 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
| 262 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
| 263 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
Alex Deucher | 1518dd8 | 2013-07-30 17:31:07 -0400 | [diff] [blame] | 264 | } |
Alex Deucher | 1518dd8 | 2013-07-30 17:31:07 -0400 | [diff] [blame] | 265 | |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 266 | /* XXX two dtos; generally use dto0 for hdmi */ |
| 267 | /* Express [24MHz / target pixel clock] as an exact rational |
| 268 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 269 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 270 | */ |
Alex Deucher | 7d61d83 | 2013-07-26 13:26:05 -0400 | [diff] [blame] | 271 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
Alex Deucher | 1518dd8 | 2013-07-30 17:31:07 -0400 | [diff] [blame] | 272 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
| 273 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 277 | /* |
| 278 | * update the info frames with the data from the current display mode |
| 279 | */ |
| 280 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
| 281 | { |
| 282 | struct drm_device *dev = encoder->dev; |
| 283 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 284 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 285 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 286 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
| 287 | struct hdmi_avi_infoframe frame; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 288 | uint32_t offset; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 289 | ssize_t err; |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 290 | |
Alex Deucher | c2b4cac | 2013-07-08 18:16:56 -0400 | [diff] [blame] | 291 | if (!dig || !dig->afmt) |
| 292 | return; |
| 293 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 294 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 295 | if (!dig->afmt->enabled) |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 296 | return; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 297 | offset = dig->afmt->offset; |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 298 | |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 299 | evergreen_audio_set_dto(encoder, mode->clock); |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 300 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 301 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
| 302 | HDMI_NULL_SEND); /* send null packets when required */ |
| 303 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 304 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 305 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 306 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
| 307 | HDMI_NULL_SEND | /* send null packets when required */ |
| 308 | HDMI_GC_SEND | /* send general control packets */ |
| 309 | HDMI_GC_CONT); /* send general control packets every frame */ |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 310 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 311 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 312 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 313 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
| 314 | |
| 315 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
| 316 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
| 317 | |
| 318 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 319 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
| 320 | |
| 321 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 322 | |
Rafał Miłecki | 91a4401 | 2013-04-18 09:26:08 -0400 | [diff] [blame] | 323 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
| 324 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
| 325 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
| 326 | |
| 327 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
| 328 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
| 329 | |
| 330 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ |
| 331 | |
| 332 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
| 333 | HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ |
| 334 | HDMI_ACR_SOURCE); /* select SW CTS value */ |
| 335 | |
| 336 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
| 337 | |
Rafał Miłecki | f93e3fc | 2013-04-14 01:26:24 +0200 | [diff] [blame] | 338 | WREG32(AFMT_60958_0 + offset, |
| 339 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
| 340 | |
| 341 | WREG32(AFMT_60958_1 + offset, |
| 342 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
| 343 | |
| 344 | WREG32(AFMT_60958_2 + offset, |
| 345 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
| 346 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
| 347 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
| 348 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
| 349 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
| 350 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
| 351 | |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 352 | if (ASIC_IS_DCE6(rdev)) { |
| 353 | dce6_afmt_write_speaker_allocation(encoder); |
| 354 | } else { |
Alex Deucher | ba7def4 | 2013-08-15 09:34:07 -0400 | [diff] [blame] | 355 | dce4_afmt_write_speaker_allocation(encoder); |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 356 | } |
Rafał Miłecki | f93e3fc | 2013-04-14 01:26:24 +0200 | [diff] [blame] | 357 | |
| 358 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
| 359 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
| 360 | |
| 361 | /* fglrx sets 0x40 in 0x5f80 here */ |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 362 | |
| 363 | if (ASIC_IS_DCE6(rdev)) { |
| 364 | dce6_afmt_select_pin(encoder); |
| 365 | dce6_afmt_write_sad_regs(encoder); |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame^] | 366 | dce6_afmt_write_latency_fields(encoder, mode); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 367 | } else { |
| 368 | evergreen_hdmi_write_sad_regs(encoder); |
Alex Deucher | 712fd8a | 2013-10-10 17:54:51 -0400 | [diff] [blame] | 369 | dce4_afmt_write_latency_fields(encoder, mode); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 370 | } |
Rafał Miłecki | f93e3fc | 2013-04-14 01:26:24 +0200 | [diff] [blame] | 371 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 372 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
| 373 | if (err < 0) { |
| 374 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
| 375 | return; |
| 376 | } |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 377 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 378 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 379 | if (err < 0) { |
| 380 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
| 381 | return; |
| 382 | } |
| 383 | |
| 384 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 385 | |
Rafał Miłecki | d3418ea | 2013-04-18 09:23:12 -0400 | [diff] [blame] | 386 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
| 387 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
| 388 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
| 389 | |
| 390 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
| 391 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
| 392 | ~HDMI_AVI_INFO_LINE_MASK); |
| 393 | |
| 394 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
| 395 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ |
| 396 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 397 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
| 398 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
| 399 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
| 400 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
| 401 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 402 | } |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 403 | |
| 404 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
| 405 | { |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 406 | struct drm_device *dev = encoder->dev; |
| 407 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 408 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 409 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 410 | |
Alex Deucher | c2b4cac | 2013-07-08 18:16:56 -0400 | [diff] [blame] | 411 | if (!dig || !dig->afmt) |
| 412 | return; |
| 413 | |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 414 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 415 | if (enable && dig->afmt->enabled) |
| 416 | return; |
| 417 | if (!enable && !dig->afmt->enabled) |
| 418 | return; |
| 419 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 420 | if (enable) { |
| 421 | if (ASIC_IS_DCE6(rdev)) |
| 422 | dig->afmt->pin = dce6_audio_get_pin(rdev); |
| 423 | else |
| 424 | dig->afmt->pin = r600_audio_get_pin(rdev); |
| 425 | } else { |
| 426 | dig->afmt->pin = NULL; |
| 427 | } |
| 428 | |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 429 | dig->afmt->enabled = enable; |
| 430 | |
| 431 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
| 432 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
| 433 | } |