| Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h |
| 2 | * |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com/ |
| 5 | * |
| 6 | * S5PV310 - Clock register definitions |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_REGS_CLOCK_H |
| 14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ |
| 15 | |
| 16 | #include <mach/map.h> |
| 17 | |
| 18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) |
| 19 | |
| 20 | #define S5P_INFORM0 S5P_CLKREG(0x800) |
| 21 | |
| 22 | #define S5P_EPLL_CON0 S5P_CLKREG(0x1C110) |
| 23 | #define S5P_EPLL_CON1 S5P_CLKREG(0x1C114) |
| 24 | #define S5P_VPLL_CON0 S5P_CLKREG(0x1C120) |
| 25 | #define S5P_VPLL_CON1 S5P_CLKREG(0x1C124) |
| 26 | |
| 27 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210) |
| 28 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214) |
| 29 | |
| 30 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250) |
| 31 | |
| 32 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510) |
| 33 | |
| 34 | #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550) |
| 35 | #define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554) |
| 36 | #define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558) |
| 37 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C) |
| 38 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560) |
| 39 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564) |
| 40 | |
| 41 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950) |
| 42 | |
| 43 | #define S5P_CLKSRC_CORE S5P_CLKREG(0x20200) |
| 44 | |
| 45 | #define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500) |
| 46 | |
| 47 | #define S5P_APLL_LOCK S5P_CLKREG(0x24000) |
| 48 | #define S5P_MPLL_LOCK S5P_CLKREG(0x24004) |
| 49 | #define S5P_APLL_CON0 S5P_CLKREG(0x24100) |
| 50 | #define S5P_APLL_CON1 S5P_CLKREG(0x24104) |
| 51 | #define S5P_MPLL_CON0 S5P_CLKREG(0x24108) |
| 52 | #define S5P_MPLL_CON1 S5P_CLKREG(0x2410C) |
| 53 | |
| 54 | #define S5P_CLKSRC_CPU S5P_CLKREG(0x24200) |
| 55 | #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400) |
| 56 | |
| 57 | #define S5P_CLKDIV_CPU S5P_CLKREG(0x24500) |
| 58 | #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600) |
| 59 | |
| 60 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800) |
| 61 | |
| 62 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |