Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 29 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "i915_drm.h" |
| 34 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 35 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 40 | /** |
| 41 | * Interrupts that are always left unmasked. |
| 42 | * |
| 43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 44 | * we leave them always unmasked in IMR and then control enabling them through |
| 45 | * PIPESTAT alone. |
| 46 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 47 | #define I915_INTERRUPT_ENABLE_FIX \ |
| 48 | (I915_ASLE_INTERRUPT | \ |
| 49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
| 51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ |
| 52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ |
| 53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 54 | |
| 55 | /** Interrupts that we mask and unmask at runtime. */ |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 57 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 59 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 60 | |
| 61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 62 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 63 | |
| 64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 65 | DRM_I915_VBLANK_PIPE_B) |
| 66 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 67 | void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 69 | { |
| 70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { |
| 71 | dev_priv->gt_irq_mask_reg &= ~mask; |
| 72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 73 | (void) I915_READ(GTIMR); |
| 74 | } |
| 75 | } |
| 76 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 77 | void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 79 | { |
| 80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { |
| 81 | dev_priv->gt_irq_mask_reg |= mask; |
| 82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 83 | (void) I915_READ(GTIMR); |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 88 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 90 | { |
| 91 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 92 | dev_priv->irq_mask_reg &= ~mask; |
| 93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 94 | (void) I915_READ(DEIMR); |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | static inline void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 100 | { |
| 101 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 102 | dev_priv->irq_mask_reg |= mask; |
| 103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 104 | (void) I915_READ(DEIMR); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 110 | { |
| 111 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 112 | dev_priv->irq_mask_reg &= ~mask; |
| 113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 114 | (void) I915_READ(IMR); |
| 115 | } |
| 116 | } |
| 117 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 118 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 120 | { |
| 121 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 122 | dev_priv->irq_mask_reg |= mask; |
| 123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 124 | (void) I915_READ(IMR); |
| 125 | } |
| 126 | } |
| 127 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 128 | static inline u32 |
| 129 | i915_pipestat(int pipe) |
| 130 | { |
| 131 | if (pipe == 0) |
| 132 | return PIPEASTAT; |
| 133 | if (pipe == 1) |
| 134 | return PIPEBSTAT; |
Andrew Morton | 9c84ba4 | 2008-12-01 13:14:08 -0800 | [diff] [blame] | 135 | BUG(); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | void |
| 139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 140 | { |
| 141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
| 142 | u32 reg = i915_pipestat(pipe); |
| 143 | |
| 144 | dev_priv->pipestat[pipe] |= mask; |
| 145 | /* Enable the interrupt, clear any pending status */ |
| 146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
| 147 | (void) I915_READ(reg); |
| 148 | } |
| 149 | } |
| 150 | |
| 151 | void |
| 152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 153 | { |
| 154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
| 155 | u32 reg = i915_pipestat(pipe); |
| 156 | |
| 157 | dev_priv->pipestat[pipe] &= ~mask; |
| 158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
| 159 | (void) I915_READ(reg); |
| 160 | } |
| 161 | } |
| 162 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 163 | /** |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 164 | * intel_enable_asle - enable ASLE interrupt for OpRegion |
| 165 | */ |
| 166 | void intel_enable_asle (struct drm_device *dev) |
| 167 | { |
| 168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 169 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 170 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 172 | else { |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 173 | i915_enable_pipestat(dev_priv, 1, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 175 | if (INTEL_INFO(dev)->gen >= 4) |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 176 | i915_enable_pipestat(dev_priv, 0, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 178 | } |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 182 | * i915_pipe_enabled - check if a pipe is enabled |
| 183 | * @dev: DRM device |
| 184 | * @pipe: pipe to check |
| 185 | * |
| 186 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 187 | * Use this routine to make sure the PLL is running and the pipe is active |
| 188 | * before reading such registers if unsure. |
| 189 | */ |
| 190 | static int |
| 191 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 192 | { |
| 193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 194 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 195 | } |
| 196 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 197 | /* Called from drm generic code, passed a 'crtc', which |
| 198 | * we use as a pipe index |
| 199 | */ |
| 200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 201 | { |
| 202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 203 | unsigned long high_frame; |
| 204 | unsigned long low_frame; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 205 | u32 high1, high2, low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 206 | |
| 207 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 208 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 209 | "pipe %d\n", pipe); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 210 | return 0; |
| 211 | } |
| 212 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 213 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 214 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 215 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 216 | /* |
| 217 | * High & low register fields aren't synchronized, so make sure |
| 218 | * we get a low value that's stable across two reads of the high |
| 219 | * register. |
| 220 | */ |
| 221 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 222 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 223 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; |
| 224 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 225 | } while (high1 != high2); |
| 226 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 227 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
| 228 | low >>= PIPE_FRAME_LOW_SHIFT; |
| 229 | return (high1 << 8) | low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 230 | } |
| 231 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 232 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
| 233 | { |
| 234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 235 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
| 236 | |
| 237 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 238 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 239 | "pipe %d\n", pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 240 | return 0; |
| 241 | } |
| 242 | |
| 243 | return I915_READ(reg); |
| 244 | } |
| 245 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 246 | /* |
| 247 | * Handle hotplug events outside the interrupt handler proper. |
| 248 | */ |
| 249 | static void i915_hotplug_work_func(struct work_struct *work) |
| 250 | { |
| 251 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 252 | hotplug_work); |
| 253 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 254 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 255 | struct intel_encoder *encoder; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 256 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 257 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 258 | if (encoder->hot_plug) |
| 259 | encoder->hot_plug(encoder); |
| 260 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 261 | /* Just fire off a uevent and let userspace tell us what to do */ |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 262 | drm_helper_hpd_irq_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 263 | } |
| 264 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 265 | static void i915_handle_rps_change(struct drm_device *dev) |
| 266 | { |
| 267 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 268 | u32 busy_up, busy_down, max_avg, min_avg; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 269 | u8 new_delay = dev_priv->cur_delay; |
| 270 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 271 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 272 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 273 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 274 | max_avg = I915_READ(RCBMAXAVG); |
| 275 | min_avg = I915_READ(RCBMINAVG); |
| 276 | |
| 277 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 278 | if (busy_up > max_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 279 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 280 | new_delay = dev_priv->cur_delay - 1; |
| 281 | if (new_delay < dev_priv->max_delay) |
| 282 | new_delay = dev_priv->max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 283 | } else if (busy_down < min_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 284 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 285 | new_delay = dev_priv->cur_delay + 1; |
| 286 | if (new_delay > dev_priv->min_delay) |
| 287 | new_delay = dev_priv->min_delay; |
| 288 | } |
| 289 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 290 | if (ironlake_set_drps(dev, new_delay)) |
| 291 | dev_priv->cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 292 | |
| 293 | return; |
| 294 | } |
| 295 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 296 | static void notify_ring(struct drm_device *dev, |
| 297 | struct intel_ring_buffer *ring) |
| 298 | { |
| 299 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 300 | u32 seqno = ring->get_seqno(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame^] | 301 | ring->irq_seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 302 | trace_i915_gem_request_complete(dev, seqno); |
| 303 | wake_up_all(&ring->irq_queue); |
| 304 | dev_priv->hangcheck_count = 0; |
| 305 | mod_timer(&dev_priv->hangcheck_timer, |
| 306 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 307 | } |
| 308 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 309 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 310 | { |
| 311 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 312 | int ret = IRQ_NONE; |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 313 | u32 de_iir, gt_iir, de_ier, pch_iir; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 314 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 315 | struct drm_i915_master_private *master_priv; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 316 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
| 317 | |
| 318 | if (IS_GEN6(dev)) |
| 319 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 320 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 321 | /* disable master interrupt before clearing iir */ |
| 322 | de_ier = I915_READ(DEIER); |
| 323 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
| 324 | (void)I915_READ(DEIER); |
| 325 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 326 | de_iir = I915_READ(DEIIR); |
| 327 | gt_iir = I915_READ(GTIIR); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 328 | pch_iir = I915_READ(SDEIIR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 329 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 330 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
| 331 | goto done; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 332 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 333 | if (HAS_PCH_CPT(dev)) |
| 334 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; |
| 335 | else |
| 336 | hotplug_mask = SDE_HOTPLUG_MASK; |
| 337 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 338 | ret = IRQ_HANDLED; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 339 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 340 | if (dev->primary->master) { |
| 341 | master_priv = dev->primary->master->driver_priv; |
| 342 | if (master_priv->sarea_priv) |
| 343 | master_priv->sarea_priv->last_dispatch = |
| 344 | READ_BREADCRUMB(dev_priv); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 345 | } |
| 346 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 347 | if (gt_iir & GT_PIPE_NOTIFY) |
| 348 | notify_ring(dev, &dev_priv->render_ring); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 349 | if (gt_iir & bsd_usr_interrupt) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 350 | notify_ring(dev, &dev_priv->bsd_ring); |
| 351 | if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT) |
| 352 | notify_ring(dev, &dev_priv->blt_ring); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 353 | |
| 354 | if (de_iir & DE_GSE) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 355 | intel_opregion_gse_intr(dev); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 356 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 357 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 358 | intel_prepare_page_flip(dev, 0); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 359 | intel_finish_page_flip_plane(dev, 0); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 360 | } |
| 361 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 362 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 363 | intel_prepare_page_flip(dev, 1); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 364 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 365 | } |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 366 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 367 | if (de_iir & DE_PIPEA_VBLANK) |
| 368 | drm_handle_vblank(dev, 0); |
| 369 | |
| 370 | if (de_iir & DE_PIPEB_VBLANK) |
| 371 | drm_handle_vblank(dev, 1); |
| 372 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 373 | /* check event from PCH */ |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 374 | if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask)) |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 375 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 376 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 377 | if (de_iir & DE_PCU_EVENT) { |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 378 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 379 | i915_handle_rps_change(dev); |
| 380 | } |
| 381 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 382 | /* should clear PCH hotplug event before clear CPU irq */ |
| 383 | I915_WRITE(SDEIIR, pch_iir); |
| 384 | I915_WRITE(GTIIR, gt_iir); |
| 385 | I915_WRITE(DEIIR, de_iir); |
| 386 | |
| 387 | done: |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 388 | I915_WRITE(DEIER, de_ier); |
| 389 | (void)I915_READ(DEIER); |
| 390 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 391 | return ret; |
| 392 | } |
| 393 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 394 | /** |
| 395 | * i915_error_work_func - do process context error handling work |
| 396 | * @work: work struct |
| 397 | * |
| 398 | * Fire an error uevent so userspace can see that a hang or error |
| 399 | * was detected. |
| 400 | */ |
| 401 | static void i915_error_work_func(struct work_struct *work) |
| 402 | { |
| 403 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 404 | error_work); |
| 405 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 406 | char *error_event[] = { "ERROR=1", NULL }; |
| 407 | char *reset_event[] = { "RESET=1", NULL }; |
| 408 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 409 | |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 410 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 411 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 412 | if (atomic_read(&dev_priv->mm.wedged)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 413 | DRM_DEBUG_DRIVER("resetting chip\n"); |
| 414 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 415 | if (!i915_reset(dev, GRDOM_RENDER)) { |
| 416 | atomic_set(&dev_priv->mm.wedged, 0); |
| 417 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 418 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 419 | complete_all(&dev_priv->error_completion); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 420 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 421 | } |
| 422 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 423 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 424 | static struct drm_i915_error_object * |
| 425 | i915_error_object_create(struct drm_device *dev, |
| 426 | struct drm_gem_object *src) |
| 427 | { |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 428 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 429 | struct drm_i915_error_object *dst; |
| 430 | struct drm_i915_gem_object *src_priv; |
| 431 | int page, page_count; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 432 | u32 reloc_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 433 | |
| 434 | if (src == NULL) |
| 435 | return NULL; |
| 436 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 437 | src_priv = to_intel_bo(src); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 438 | if (src_priv->pages == NULL) |
| 439 | return NULL; |
| 440 | |
| 441 | page_count = src->size / PAGE_SIZE; |
| 442 | |
| 443 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); |
| 444 | if (dst == NULL) |
| 445 | return NULL; |
| 446 | |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 447 | reloc_offset = src_priv->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 448 | for (page = 0; page < page_count; page++) { |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 449 | unsigned long flags; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 450 | void __iomem *s; |
| 451 | void *d; |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 452 | |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 453 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 454 | if (d == NULL) |
| 455 | goto unwind; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 456 | |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 457 | local_irq_save(flags); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 458 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 459 | reloc_offset); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 460 | memcpy_fromio(d, s, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 461 | io_mapping_unmap_atomic(s); |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 462 | local_irq_restore(flags); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 463 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 464 | dst->pages[page] = d; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 465 | |
| 466 | reloc_offset += PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 467 | } |
| 468 | dst->page_count = page_count; |
| 469 | dst->gtt_offset = src_priv->gtt_offset; |
| 470 | |
| 471 | return dst; |
| 472 | |
| 473 | unwind: |
| 474 | while (page--) |
| 475 | kfree(dst->pages[page]); |
| 476 | kfree(dst); |
| 477 | return NULL; |
| 478 | } |
| 479 | |
| 480 | static void |
| 481 | i915_error_object_free(struct drm_i915_error_object *obj) |
| 482 | { |
| 483 | int page; |
| 484 | |
| 485 | if (obj == NULL) |
| 486 | return; |
| 487 | |
| 488 | for (page = 0; page < obj->page_count; page++) |
| 489 | kfree(obj->pages[page]); |
| 490 | |
| 491 | kfree(obj); |
| 492 | } |
| 493 | |
| 494 | static void |
| 495 | i915_error_state_free(struct drm_device *dev, |
| 496 | struct drm_i915_error_state *error) |
| 497 | { |
| 498 | i915_error_object_free(error->batchbuffer[0]); |
| 499 | i915_error_object_free(error->batchbuffer[1]); |
| 500 | i915_error_object_free(error->ringbuffer); |
| 501 | kfree(error->active_bo); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 502 | kfree(error->overlay); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 503 | kfree(error); |
| 504 | } |
| 505 | |
| 506 | static u32 |
| 507 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) |
| 508 | { |
| 509 | u32 cmd; |
| 510 | |
| 511 | if (IS_I830(dev) || IS_845G(dev)) |
| 512 | cmd = MI_BATCH_BUFFER; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 513 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 514 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | |
| 515 | MI_BATCH_NON_SECURE_I965); |
| 516 | else |
| 517 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); |
| 518 | |
| 519 | return ring[0] == cmd ? ring[1] : 0; |
| 520 | } |
| 521 | |
| 522 | static u32 |
| 523 | i915_ringbuffer_last_batch(struct drm_device *dev) |
| 524 | { |
| 525 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 526 | u32 head, bbaddr; |
| 527 | u32 *ring; |
| 528 | |
| 529 | /* Locate the current position in the ringbuffer and walk back |
| 530 | * to find the most recently dispatched batch buffer. |
| 531 | */ |
| 532 | bbaddr = 0; |
| 533 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
Eric Anholt | d3301d8 | 2010-05-21 13:55:54 -0700 | [diff] [blame] | 534 | ring = (u32 *)(dev_priv->render_ring.virtual_start + head); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 535 | |
Eric Anholt | d3301d8 | 2010-05-21 13:55:54 -0700 | [diff] [blame] | 536 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 537 | bbaddr = i915_get_bbaddr(dev, ring); |
| 538 | if (bbaddr) |
| 539 | break; |
| 540 | } |
| 541 | |
| 542 | if (bbaddr == 0) { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 543 | ring = (u32 *)(dev_priv->render_ring.virtual_start |
| 544 | + dev_priv->render_ring.size); |
Eric Anholt | d3301d8 | 2010-05-21 13:55:54 -0700 | [diff] [blame] | 545 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 546 | bbaddr = i915_get_bbaddr(dev, ring); |
| 547 | if (bbaddr) |
| 548 | break; |
| 549 | } |
| 550 | } |
| 551 | |
| 552 | return bbaddr; |
| 553 | } |
| 554 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 555 | /** |
| 556 | * i915_capture_error_state - capture an error record for later analysis |
| 557 | * @dev: drm device |
| 558 | * |
| 559 | * Should be called when an error is detected (either a hang or an error |
| 560 | * interrupt) to capture error state from the time of the error. Fills |
| 561 | * out a structure which becomes available in debugfs for user level tools |
| 562 | * to pick up. |
| 563 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 564 | static void i915_capture_error_state(struct drm_device *dev) |
| 565 | { |
| 566 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 567 | struct drm_i915_gem_object *obj_priv; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 568 | struct drm_i915_error_state *error; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 569 | struct drm_gem_object *batchbuffer[2]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 570 | unsigned long flags; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 571 | u32 bbaddr; |
| 572 | int count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 573 | |
| 574 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 575 | error = dev_priv->first_error; |
| 576 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 577 | if (error) |
| 578 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 579 | |
| 580 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 581 | if (!error) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 582 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
| 583 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 584 | } |
| 585 | |
Chris Wilson | 2fa772f | 2010-10-01 13:23:27 +0100 | [diff] [blame] | 586 | DRM_DEBUG_DRIVER("generating error event\n"); |
| 587 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 588 | error->seqno = |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 589 | dev_priv->render_ring.get_seqno(&dev_priv->render_ring); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 590 | error->eir = I915_READ(EIR); |
| 591 | error->pgtbl_er = I915_READ(PGTBL_ER); |
| 592 | error->pipeastat = I915_READ(PIPEASTAT); |
| 593 | error->pipebstat = I915_READ(PIPEBSTAT); |
| 594 | error->instpm = I915_READ(INSTPM); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 595 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 596 | error->ipeir = I915_READ(IPEIR); |
| 597 | error->ipehr = I915_READ(IPEHR); |
| 598 | error->instdone = I915_READ(INSTDONE); |
| 599 | error->acthd = I915_READ(ACTHD); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 600 | error->bbaddr = 0; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 601 | } else { |
| 602 | error->ipeir = I915_READ(IPEIR_I965); |
| 603 | error->ipehr = I915_READ(IPEHR_I965); |
| 604 | error->instdone = I915_READ(INSTDONE_I965); |
| 605 | error->instps = I915_READ(INSTPS); |
| 606 | error->instdone1 = I915_READ(INSTDONE1); |
| 607 | error->acthd = I915_READ(ACTHD_I965); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 608 | error->bbaddr = I915_READ64(BB_ADDR); |
| 609 | } |
| 610 | |
| 611 | bbaddr = i915_ringbuffer_last_batch(dev); |
| 612 | |
| 613 | /* Grab the current batchbuffer, most likely to have crashed. */ |
| 614 | batchbuffer[0] = NULL; |
| 615 | batchbuffer[1] = NULL; |
| 616 | count = 0; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 617 | list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 618 | struct drm_gem_object *obj = &obj_priv->base; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 619 | |
| 620 | if (batchbuffer[0] == NULL && |
| 621 | bbaddr >= obj_priv->gtt_offset && |
| 622 | bbaddr < obj_priv->gtt_offset + obj->size) |
| 623 | batchbuffer[0] = obj; |
| 624 | |
| 625 | if (batchbuffer[1] == NULL && |
| 626 | error->acthd >= obj_priv->gtt_offset && |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 627 | error->acthd < obj_priv->gtt_offset + obj->size) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 628 | batchbuffer[1] = obj; |
| 629 | |
| 630 | count++; |
| 631 | } |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 632 | /* Scan the other lists for completeness for those bizarre errors. */ |
| 633 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 634 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) { |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 635 | struct drm_gem_object *obj = &obj_priv->base; |
| 636 | |
| 637 | if (batchbuffer[0] == NULL && |
| 638 | bbaddr >= obj_priv->gtt_offset && |
| 639 | bbaddr < obj_priv->gtt_offset + obj->size) |
| 640 | batchbuffer[0] = obj; |
| 641 | |
| 642 | if (batchbuffer[1] == NULL && |
| 643 | error->acthd >= obj_priv->gtt_offset && |
| 644 | error->acthd < obj_priv->gtt_offset + obj->size) |
| 645 | batchbuffer[1] = obj; |
| 646 | |
| 647 | if (batchbuffer[0] && batchbuffer[1]) |
| 648 | break; |
| 649 | } |
| 650 | } |
| 651 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 652 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) { |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 653 | struct drm_gem_object *obj = &obj_priv->base; |
| 654 | |
| 655 | if (batchbuffer[0] == NULL && |
| 656 | bbaddr >= obj_priv->gtt_offset && |
| 657 | bbaddr < obj_priv->gtt_offset + obj->size) |
| 658 | batchbuffer[0] = obj; |
| 659 | |
| 660 | if (batchbuffer[1] == NULL && |
| 661 | error->acthd >= obj_priv->gtt_offset && |
| 662 | error->acthd < obj_priv->gtt_offset + obj->size) |
| 663 | batchbuffer[1] = obj; |
| 664 | |
| 665 | if (batchbuffer[0] && batchbuffer[1]) |
| 666 | break; |
| 667 | } |
| 668 | } |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 669 | |
| 670 | /* We need to copy these to an anonymous buffer as the simplest |
Andrea Gelmini | 139d363 | 2010-10-15 17:14:33 +0200 | [diff] [blame] | 671 | * method to avoid being overwritten by userspace. |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 672 | */ |
| 673 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 674 | if (batchbuffer[1] != batchbuffer[0]) |
| 675 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); |
| 676 | else |
| 677 | error->batchbuffer[1] = NULL; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 678 | |
| 679 | /* Record the ringbuffer */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 680 | error->ringbuffer = i915_error_object_create(dev, |
| 681 | dev_priv->render_ring.gem_object); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 682 | |
| 683 | /* Record buffers on the active list. */ |
| 684 | error->active_bo = NULL; |
| 685 | error->active_bo_count = 0; |
| 686 | |
| 687 | if (count) |
| 688 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, |
| 689 | GFP_ATOMIC); |
| 690 | |
| 691 | if (error->active_bo) { |
| 692 | int i = 0; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 693 | list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 694 | struct drm_gem_object *obj = &obj_priv->base; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 695 | |
| 696 | error->active_bo[i].size = obj->size; |
| 697 | error->active_bo[i].name = obj->name; |
| 698 | error->active_bo[i].seqno = obj_priv->last_rendering_seqno; |
| 699 | error->active_bo[i].gtt_offset = obj_priv->gtt_offset; |
| 700 | error->active_bo[i].read_domains = obj->read_domains; |
| 701 | error->active_bo[i].write_domain = obj->write_domain; |
| 702 | error->active_bo[i].fence_reg = obj_priv->fence_reg; |
| 703 | error->active_bo[i].pinned = 0; |
| 704 | if (obj_priv->pin_count > 0) |
| 705 | error->active_bo[i].pinned = 1; |
| 706 | if (obj_priv->user_pin_count > 0) |
| 707 | error->active_bo[i].pinned = -1; |
| 708 | error->active_bo[i].tiling = obj_priv->tiling_mode; |
| 709 | error->active_bo[i].dirty = obj_priv->dirty; |
| 710 | error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED; |
| 711 | |
| 712 | if (++i == count) |
| 713 | break; |
| 714 | } |
| 715 | error->active_bo_count = i; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 716 | } |
| 717 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 718 | do_gettimeofday(&error->time); |
| 719 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 720 | error->overlay = intel_overlay_capture_error_state(dev); |
| 721 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 722 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 723 | if (dev_priv->first_error == NULL) { |
| 724 | dev_priv->first_error = error; |
| 725 | error = NULL; |
| 726 | } |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 727 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 728 | |
| 729 | if (error) |
| 730 | i915_error_state_free(dev, error); |
| 731 | } |
| 732 | |
| 733 | void i915_destroy_error_state(struct drm_device *dev) |
| 734 | { |
| 735 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 736 | struct drm_i915_error_state *error; |
| 737 | |
| 738 | spin_lock(&dev_priv->error_lock); |
| 739 | error = dev_priv->first_error; |
| 740 | dev_priv->first_error = NULL; |
| 741 | spin_unlock(&dev_priv->error_lock); |
| 742 | |
| 743 | if (error) |
| 744 | i915_error_state_free(dev, error); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 745 | } |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 746 | #else |
| 747 | #define i915_capture_error_state(x) |
| 748 | #endif |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 749 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 750 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 751 | { |
| 752 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 753 | u32 eir = I915_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 754 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 755 | if (!eir) |
| 756 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 757 | |
| 758 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", |
| 759 | eir); |
| 760 | |
| 761 | if (IS_G4X(dev)) { |
| 762 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 763 | u32 ipeir = I915_READ(IPEIR_I965); |
| 764 | |
| 765 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 766 | I915_READ(IPEIR_I965)); |
| 767 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 768 | I915_READ(IPEHR_I965)); |
| 769 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 770 | I915_READ(INSTDONE_I965)); |
| 771 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 772 | I915_READ(INSTPS)); |
| 773 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 774 | I915_READ(INSTDONE1)); |
| 775 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 776 | I915_READ(ACTHD_I965)); |
| 777 | I915_WRITE(IPEIR_I965, ipeir); |
| 778 | (void)I915_READ(IPEIR_I965); |
| 779 | } |
| 780 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 781 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 782 | printk(KERN_ERR "page table error\n"); |
| 783 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 784 | pgtbl_err); |
| 785 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 786 | (void)I915_READ(PGTBL_ER); |
| 787 | } |
| 788 | } |
| 789 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 790 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 791 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 792 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 793 | printk(KERN_ERR "page table error\n"); |
| 794 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 795 | pgtbl_err); |
| 796 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 797 | (void)I915_READ(PGTBL_ER); |
| 798 | } |
| 799 | } |
| 800 | |
| 801 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 802 | u32 pipea_stats = I915_READ(PIPEASTAT); |
| 803 | u32 pipeb_stats = I915_READ(PIPEBSTAT); |
| 804 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 805 | printk(KERN_ERR "memory refresh error\n"); |
| 806 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", |
| 807 | pipea_stats); |
| 808 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", |
| 809 | pipeb_stats); |
| 810 | /* pipestat has already been acked */ |
| 811 | } |
| 812 | if (eir & I915_ERROR_INSTRUCTION) { |
| 813 | printk(KERN_ERR "instruction error\n"); |
| 814 | printk(KERN_ERR " INSTPM: 0x%08x\n", |
| 815 | I915_READ(INSTPM)); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 816 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 817 | u32 ipeir = I915_READ(IPEIR); |
| 818 | |
| 819 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 820 | I915_READ(IPEIR)); |
| 821 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 822 | I915_READ(IPEHR)); |
| 823 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 824 | I915_READ(INSTDONE)); |
| 825 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 826 | I915_READ(ACTHD)); |
| 827 | I915_WRITE(IPEIR, ipeir); |
| 828 | (void)I915_READ(IPEIR); |
| 829 | } else { |
| 830 | u32 ipeir = I915_READ(IPEIR_I965); |
| 831 | |
| 832 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 833 | I915_READ(IPEIR_I965)); |
| 834 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 835 | I915_READ(IPEHR_I965)); |
| 836 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 837 | I915_READ(INSTDONE_I965)); |
| 838 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 839 | I915_READ(INSTPS)); |
| 840 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 841 | I915_READ(INSTDONE1)); |
| 842 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 843 | I915_READ(ACTHD_I965)); |
| 844 | I915_WRITE(IPEIR_I965, ipeir); |
| 845 | (void)I915_READ(IPEIR_I965); |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | I915_WRITE(EIR, eir); |
| 850 | (void)I915_READ(EIR); |
| 851 | eir = I915_READ(EIR); |
| 852 | if (eir) { |
| 853 | /* |
| 854 | * some errors might have become stuck, |
| 855 | * mask them. |
| 856 | */ |
| 857 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 858 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 859 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 860 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 861 | } |
| 862 | |
| 863 | /** |
| 864 | * i915_handle_error - handle an error interrupt |
| 865 | * @dev: drm device |
| 866 | * |
| 867 | * Do some basic checking of regsiter state at error interrupt time and |
| 868 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 869 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 870 | * so userspace knows something bad happened (should trigger collection |
| 871 | * of a ring dump etc.). |
| 872 | */ |
| 873 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
| 874 | { |
| 875 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 876 | |
| 877 | i915_capture_error_state(dev); |
| 878 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 879 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 880 | if (wedged) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 881 | INIT_COMPLETION(dev_priv->error_completion); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 882 | atomic_set(&dev_priv->mm.wedged, 1); |
| 883 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 884 | /* |
| 885 | * Wakeup waiting processes so they don't hang |
| 886 | */ |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 887 | wake_up_all(&dev_priv->render_ring.irq_queue); |
| 888 | if (HAS_BSD(dev)) |
| 889 | wake_up_all(&dev_priv->bsd_ring.irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 890 | if (HAS_BLT(dev)) |
| 891 | wake_up_all(&dev_priv->blt_ring.irq_queue); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 892 | } |
| 893 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 894 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 895 | } |
| 896 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 897 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
| 898 | { |
| 899 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 900 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 902 | struct drm_i915_gem_object *obj_priv; |
| 903 | struct intel_unpin_work *work; |
| 904 | unsigned long flags; |
| 905 | bool stall_detected; |
| 906 | |
| 907 | /* Ignore early vblank irqs */ |
| 908 | if (intel_crtc == NULL) |
| 909 | return; |
| 910 | |
| 911 | spin_lock_irqsave(&dev->event_lock, flags); |
| 912 | work = intel_crtc->unpin_work; |
| 913 | |
| 914 | if (work == NULL || work->pending || !work->enable_stall_check) { |
| 915 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 916 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 917 | return; |
| 918 | } |
| 919 | |
| 920 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
| 921 | obj_priv = to_intel_bo(work->pending_flip_obj); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 922 | if (INTEL_INFO(dev)->gen >= 4) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 923 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
| 924 | stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset; |
| 925 | } else { |
| 926 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; |
| 927 | stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset + |
| 928 | crtc->y * crtc->fb->pitch + |
| 929 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 930 | } |
| 931 | |
| 932 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 933 | |
| 934 | if (stall_detected) { |
| 935 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 936 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 937 | } |
| 938 | } |
| 939 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 940 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 941 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 942 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 943 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 944 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 945 | u32 iir, new_iir; |
| 946 | u32 pipea_stats, pipeb_stats; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 947 | u32 vblank_status; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 948 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 949 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 950 | int irq_received; |
| 951 | int ret = IRQ_NONE; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 952 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 953 | atomic_inc(&dev_priv->irq_received); |
| 954 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 955 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 956 | return ironlake_irq_handler(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 957 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 958 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 959 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 960 | if (INTEL_INFO(dev)->gen >= 4) |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 961 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
Jesse Barnes | e25e660 | 2010-06-30 13:15:19 -0700 | [diff] [blame] | 962 | else |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 963 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 965 | for (;;) { |
| 966 | irq_received = iir != 0; |
| 967 | |
| 968 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 969 | * have been cleared after the pipestat interrupt was received. |
| 970 | * It doesn't set the bit in iir again, but it still produces |
| 971 | * interrupts (for non-MSI). |
| 972 | */ |
| 973 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
| 974 | pipea_stats = I915_READ(PIPEASTAT); |
| 975 | pipeb_stats = I915_READ(PIPEBSTAT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 976 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 977 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 978 | i915_handle_error(dev, false); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 979 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 980 | /* |
| 981 | * Clear the PIPE(A|B)STAT regs before the IIR |
| 982 | */ |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 983 | if (pipea_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 984 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 985 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 986 | I915_WRITE(PIPEASTAT, pipea_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 987 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 988 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 989 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 990 | if (pipeb_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 991 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 992 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 993 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 994 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 995 | } |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 996 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
| 997 | |
| 998 | if (!irq_received) |
| 999 | break; |
| 1000 | |
| 1001 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1003 | /* Consume port. Then clear IIR or we'll miss events */ |
| 1004 | if ((I915_HAS_HOTPLUG(dev)) && |
| 1005 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 1006 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 1007 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1008 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1009 | hotplug_status); |
| 1010 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1011 | queue_work(dev_priv->wq, |
| 1012 | &dev_priv->hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1013 | |
| 1014 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1015 | I915_READ(PORT_HOTPLUG_STAT); |
| 1016 | } |
| 1017 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1018 | I915_WRITE(IIR, iir); |
| 1019 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1020 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1021 | if (dev->primary->master) { |
| 1022 | master_priv = dev->primary->master->driver_priv; |
| 1023 | if (master_priv->sarea_priv) |
| 1024 | master_priv->sarea_priv->last_dispatch = |
| 1025 | READ_BREADCRUMB(dev_priv); |
| 1026 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1027 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1028 | if (iir & I915_USER_INTERRUPT) |
| 1029 | notify_ring(dev, &dev_priv->render_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1030 | if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1031 | notify_ring(dev, &dev_priv->bsd_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1032 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1033 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1034 | intel_prepare_page_flip(dev, 0); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1035 | if (dev_priv->flip_pending_is_done) |
| 1036 | intel_finish_page_flip_plane(dev, 0); |
| 1037 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1038 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1039 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
Jesse Barnes | 70565d0 | 2010-07-01 04:45:43 -0700 | [diff] [blame] | 1040 | intel_prepare_page_flip(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1041 | if (dev_priv->flip_pending_is_done) |
| 1042 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1043 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1044 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1045 | if (pipea_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1046 | vblank++; |
| 1047 | drm_handle_vblank(dev, 0); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1048 | if (!dev_priv->flip_pending_is_done) { |
| 1049 | i915_pageflip_stall_check(dev, 0); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1050 | intel_finish_page_flip(dev, 0); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1051 | } |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1052 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1053 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1054 | if (pipeb_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1055 | vblank++; |
| 1056 | drm_handle_vblank(dev, 1); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1057 | if (!dev_priv->flip_pending_is_done) { |
| 1058 | i915_pageflip_stall_check(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1059 | intel_finish_page_flip(dev, 1); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1060 | } |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1061 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1062 | |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 1063 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
| 1064 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1065 | (iir & I915_ASLE_INTERRUPT)) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1066 | intel_opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1067 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1068 | /* With MSI, interrupts are only generated when iir |
| 1069 | * transitions from zero to nonzero. If another bit got |
| 1070 | * set while we were handling the existing iir bits, then |
| 1071 | * we would never get another interrupt. |
| 1072 | * |
| 1073 | * This is fine on non-MSI as well, as if we hit this path |
| 1074 | * we avoid exiting the interrupt handler only to generate |
| 1075 | * another one. |
| 1076 | * |
| 1077 | * Note that for MSI this could cause a stray interrupt report |
| 1078 | * if an interrupt landed in the time between writing IIR and |
| 1079 | * the posting read. This should be rare enough to never |
| 1080 | * trigger the 99% of 100,000 interrupts test for disabling |
| 1081 | * stray interrupts. |
| 1082 | */ |
| 1083 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1084 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1085 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1086 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1087 | } |
| 1088 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1089 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | { |
| 1091 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1092 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | |
| 1094 | i915_kernel_lost_context(dev); |
| 1095 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1096 | DRM_DEBUG_DRIVER("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1097 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1098 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1099 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1100 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1101 | if (master_priv->sarea_priv) |
| 1102 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1103 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1104 | if (BEGIN_LP_RING(4) == 0) { |
| 1105 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1106 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1107 | OUT_RING(dev_priv->counter); |
| 1108 | OUT_RING(MI_USER_INTERRUPT); |
| 1109 | ADVANCE_LP_RING(); |
| 1110 | } |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1111 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1112 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1113 | } |
| 1114 | |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1115 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
| 1116 | { |
| 1117 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1118 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1119 | |
| 1120 | if (dev_priv->trace_irq_seqno == 0) |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1121 | render_ring->user_irq_get(render_ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1122 | |
| 1123 | dev_priv->trace_irq_seqno = seqno; |
| 1124 | } |
| 1125 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1126 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1127 | { |
| 1128 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1129 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1130 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1131 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1132 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1133 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | READ_BREADCRUMB(dev_priv)); |
| 1135 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1136 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1137 | if (master_priv->sarea_priv) |
| 1138 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1139 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1140 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1142 | if (master_priv->sarea_priv) |
| 1143 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1144 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1145 | render_ring->user_irq_get(render_ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1146 | DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1147 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1148 | render_ring->user_irq_put(render_ring); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1150 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1151 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1152 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 1153 | } |
| 1154 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1155 | return ret; |
| 1156 | } |
| 1157 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1158 | /* Needs the lock as it touches the ring. |
| 1159 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1160 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 1161 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1163 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1164 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1165 | int result; |
| 1166 | |
Eric Anholt | d3301d8 | 2010-05-21 13:55:54 -0700 | [diff] [blame] | 1167 | if (!dev_priv || !dev_priv->render_ring.virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1168 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1169 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1170 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 1171 | |
| 1172 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 1173 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1174 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1175 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1176 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1177 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1178 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1180 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | return 0; |
| 1184 | } |
| 1185 | |
| 1186 | /* Doesn't need the hardware lock. |
| 1187 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1188 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 1189 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1190 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1191 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1192 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1193 | |
| 1194 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1195 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1196 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1197 | } |
| 1198 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1199 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1202 | /* Called from drm generic code, passed 'crtc' which |
| 1203 | * we use as a pipe index |
| 1204 | */ |
| 1205 | int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1206 | { |
| 1207 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1208 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1209 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1210 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1211 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1212 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1213 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1214 | if (HAS_PCH_SPLIT(dev)) |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 1215 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
| 1216 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1217 | else if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1218 | i915_enable_pipestat(dev_priv, pipe, |
| 1219 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1220 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1221 | i915_enable_pipestat(dev_priv, pipe, |
| 1222 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1223 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1224 | return 0; |
| 1225 | } |
| 1226 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1227 | /* Called from drm generic code, passed 'crtc' which |
| 1228 | * we use as a pipe index |
| 1229 | */ |
| 1230 | void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1231 | { |
| 1232 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1233 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1234 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1235 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1236 | if (HAS_PCH_SPLIT(dev)) |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 1237 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
| 1238 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
| 1239 | else |
| 1240 | i915_disable_pipestat(dev_priv, pipe, |
| 1241 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 1242 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1243 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1244 | } |
| 1245 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1246 | void i915_enable_interrupt (struct drm_device *dev) |
| 1247 | { |
| 1248 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 1249 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1250 | if (!HAS_PCH_SPLIT(dev)) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1251 | intel_opregion_enable_asle(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1252 | dev_priv->irq_enabled = 1; |
| 1253 | } |
| 1254 | |
| 1255 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1256 | /* Set the vblank monitor pipe |
| 1257 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1258 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 1259 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1260 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1261 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1262 | |
| 1263 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1264 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1265 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1266 | } |
| 1267 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 1268 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1269 | } |
| 1270 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1271 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 1272 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1273 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1274 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1275 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1276 | |
| 1277 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1278 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1279 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1280 | } |
| 1281 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1282 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1283 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1284 | return 0; |
| 1285 | } |
| 1286 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1287 | /** |
| 1288 | * Schedule buffer swap at given vertical blank. |
| 1289 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1290 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 1291 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1292 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1293 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 1294 | * removed. The model was that the client requested a delayed flip/swap |
| 1295 | * from the kernel, then waited for vblank before continuing to perform |
| 1296 | * rendering. The problem was that the kernel might wake the client |
| 1297 | * up before it dispatched the vblank swap (since the lock has to be |
| 1298 | * held while touching the ringbuffer), in which case the client would |
| 1299 | * clear and start the next frame before the swap occurred, and |
| 1300 | * flicker would occur in addition to likely missing the vblank. |
| 1301 | * |
| 1302 | * In the absence of this ioctl, userland falls back to a correct path |
| 1303 | * of waiting for a vblank, then dispatching the swap on its own. |
| 1304 | * Context switching to userland and back is plenty fast enough for |
| 1305 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1306 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1307 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1308 | } |
| 1309 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1310 | static u32 |
| 1311 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1312 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1313 | return list_entry(ring->request_list.prev, |
| 1314 | struct drm_i915_gem_request, list)->seqno; |
| 1315 | } |
| 1316 | |
| 1317 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) |
| 1318 | { |
| 1319 | if (list_empty(&ring->request_list) || |
| 1320 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { |
| 1321 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame^] | 1322 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1323 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
| 1324 | ring->name, |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame^] | 1325 | ring->waiting_seqno, |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1326 | ring->get_seqno(ring)); |
| 1327 | wake_up_all(&ring->irq_queue); |
| 1328 | *err = true; |
| 1329 | } |
| 1330 | return true; |
| 1331 | } |
| 1332 | return false; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1333 | } |
| 1334 | |
| 1335 | /** |
| 1336 | * This is called when the chip hasn't reported back with completed |
| 1337 | * batchbuffers in a long time. The first time this is called we simply record |
| 1338 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 1339 | * again, we assume the chip is wedged and try to fix it. |
| 1340 | */ |
| 1341 | void i915_hangcheck_elapsed(unsigned long data) |
| 1342 | { |
| 1343 | struct drm_device *dev = (struct drm_device *)data; |
| 1344 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1345 | uint32_t acthd, instdone, instdone1; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1346 | bool err = false; |
| 1347 | |
| 1348 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
| 1349 | if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) && |
| 1350 | i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) && |
| 1351 | i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) { |
| 1352 | dev_priv->hangcheck_count = 0; |
| 1353 | if (err) |
| 1354 | goto repeat; |
| 1355 | return; |
| 1356 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 1357 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1358 | if (INTEL_INFO(dev)->gen < 4) { |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1359 | acthd = I915_READ(ACTHD); |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1360 | instdone = I915_READ(INSTDONE); |
| 1361 | instdone1 = 0; |
| 1362 | } else { |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1363 | acthd = I915_READ(ACTHD_I965); |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1364 | instdone = I915_READ(INSTDONE_I965); |
| 1365 | instdone1 = I915_READ(INSTDONE1); |
| 1366 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1367 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1368 | if (dev_priv->last_acthd == acthd && |
| 1369 | dev_priv->last_instdone == instdone && |
| 1370 | dev_priv->last_instdone1 == instdone1) { |
| 1371 | if (dev_priv->hangcheck_count++ > 1) { |
| 1372 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
Chris Wilson | 8c80b59 | 2010-08-08 20:38:12 +0100 | [diff] [blame] | 1373 | |
| 1374 | if (!IS_GEN2(dev)) { |
| 1375 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 1376 | * If so we can simply poke the RB_WAIT bit |
| 1377 | * and break the hang. This should work on |
| 1378 | * all but the second generation chipsets. |
| 1379 | */ |
| 1380 | u32 tmp = I915_READ(PRB0_CTL); |
| 1381 | if (tmp & RING_WAIT) { |
| 1382 | I915_WRITE(PRB0_CTL, tmp); |
| 1383 | POSTING_READ(PRB0_CTL); |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1384 | goto repeat; |
Chris Wilson | 8c80b59 | 2010-08-08 20:38:12 +0100 | [diff] [blame] | 1385 | } |
| 1386 | } |
| 1387 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1388 | i915_handle_error(dev, true); |
| 1389 | return; |
| 1390 | } |
| 1391 | } else { |
| 1392 | dev_priv->hangcheck_count = 0; |
| 1393 | |
| 1394 | dev_priv->last_acthd = acthd; |
| 1395 | dev_priv->last_instdone = instdone; |
| 1396 | dev_priv->last_instdone1 = instdone1; |
| 1397 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1398 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1399 | repeat: |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1400 | /* Reset timer case chip hangs without another request being added */ |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1401 | mod_timer(&dev_priv->hangcheck_timer, |
| 1402 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1403 | } |
| 1404 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1405 | /* drm_dma.h hooks |
| 1406 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1407 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1408 | { |
| 1409 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1410 | |
| 1411 | I915_WRITE(HWSTAM, 0xeffe); |
| 1412 | |
| 1413 | /* XXX hotplug from PCH */ |
| 1414 | |
| 1415 | I915_WRITE(DEIMR, 0xffffffff); |
| 1416 | I915_WRITE(DEIER, 0x0); |
| 1417 | (void) I915_READ(DEIER); |
| 1418 | |
| 1419 | /* and GT */ |
| 1420 | I915_WRITE(GTIMR, 0xffffffff); |
| 1421 | I915_WRITE(GTIER, 0x0); |
| 1422 | (void) I915_READ(GTIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1423 | |
| 1424 | /* south display irq */ |
| 1425 | I915_WRITE(SDEIMR, 0xffffffff); |
| 1426 | I915_WRITE(SDEIER, 0x0); |
| 1427 | (void) I915_READ(SDEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1428 | } |
| 1429 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1430 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1431 | { |
| 1432 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1433 | /* enable kind of interrupts always enabled */ |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 1434 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 1435 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1436 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1437 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1438 | |
| 1439 | dev_priv->irq_mask_reg = ~display_mask; |
Li Peng | 643ced9 | 2010-01-28 01:05:09 +0800 | [diff] [blame] | 1440 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1441 | |
| 1442 | /* should always can generate irq */ |
| 1443 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1444 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 1445 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); |
| 1446 | (void) I915_READ(DEIER); |
| 1447 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1448 | if (IS_GEN6(dev)) { |
| 1449 | render_mask = |
| 1450 | GT_PIPE_NOTIFY | |
| 1451 | GT_GEN6_BSD_USER_INTERRUPT | |
| 1452 | GT_BLT_USER_INTERRUPT; |
| 1453 | } |
Zhenyu Wang | 3fdef02 | 2010-08-19 09:46:15 +0800 | [diff] [blame] | 1454 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1455 | dev_priv->gt_irq_mask_reg = ~render_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1456 | dev_priv->gt_irq_enable_reg = render_mask; |
| 1457 | |
| 1458 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1459 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1460 | if (IS_GEN6(dev)) { |
Zhenyu Wang | 3fdef02 | 2010-08-19 09:46:15 +0800 | [diff] [blame] | 1461 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1462 | I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1463 | I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1464 | } |
| 1465 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1466 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
| 1467 | (void) I915_READ(GTIER); |
| 1468 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1469 | if (HAS_PCH_CPT(dev)) { |
| 1470 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | |
| 1471 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; |
| 1472 | } else { |
| 1473 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
| 1474 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; |
| 1475 | } |
| 1476 | |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1477 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
| 1478 | dev_priv->pch_irq_enable_reg = hotplug_mask; |
| 1479 | |
| 1480 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 1481 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); |
| 1482 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); |
| 1483 | (void) I915_READ(SDEIER); |
| 1484 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1485 | if (IS_IRONLAKE_M(dev)) { |
| 1486 | /* Clear & enable PCU event interrupts */ |
| 1487 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 1488 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); |
| 1489 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
| 1490 | } |
| 1491 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1492 | return 0; |
| 1493 | } |
| 1494 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1495 | void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1496 | { |
| 1497 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1498 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1499 | atomic_set(&dev_priv->irq_received, 0); |
| 1500 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1501 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1502 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1503 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1504 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1505 | ironlake_irq_preinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1506 | return; |
| 1507 | } |
| 1508 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1509 | if (I915_HAS_HOTPLUG(dev)) { |
| 1510 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1511 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1512 | } |
| 1513 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1514 | I915_WRITE(HWSTAM, 0xeffe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1515 | I915_WRITE(PIPEASTAT, 0); |
| 1516 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1517 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1518 | I915_WRITE(IER, 0x0); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1519 | (void) I915_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1520 | } |
| 1521 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1522 | /* |
| 1523 | * Must be called after intel_modeset_init or hotplug interrupts won't be |
| 1524 | * enabled correctly. |
| 1525 | */ |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1526 | int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1527 | { |
| 1528 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1529 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1530 | u32 error_mask; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1531 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1532 | DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1533 | if (HAS_BSD(dev)) |
| 1534 | DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1535 | if (HAS_BLT(dev)) |
| 1536 | DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1537 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1538 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1539 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1540 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1541 | return ironlake_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1542 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1543 | /* Unmask the interrupts that we always want on. */ |
| 1544 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1545 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1546 | dev_priv->pipestat[0] = 0; |
| 1547 | dev_priv->pipestat[1] = 0; |
| 1548 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1549 | if (I915_HAS_HOTPLUG(dev)) { |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 1550 | /* Enable in IER... */ |
| 1551 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 1552 | /* and unmask in IMR */ |
| 1553 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 1554 | } |
| 1555 | |
| 1556 | /* |
| 1557 | * Enable some error detection, note the instruction error mask |
| 1558 | * bit is reserved, so we leave it masked. |
| 1559 | */ |
| 1560 | if (IS_G4X(dev)) { |
| 1561 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 1562 | GM45_ERROR_MEM_PRIV | |
| 1563 | GM45_ERROR_CP_PRIV | |
| 1564 | I915_ERROR_MEMORY_REFRESH); |
| 1565 | } else { |
| 1566 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 1567 | I915_ERROR_MEMORY_REFRESH); |
| 1568 | } |
| 1569 | I915_WRITE(EMR, error_mask); |
| 1570 | |
| 1571 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 1572 | I915_WRITE(IER, enable_mask); |
| 1573 | (void) I915_READ(IER); |
| 1574 | |
| 1575 | if (I915_HAS_HOTPLUG(dev)) { |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1576 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 1577 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1578 | /* Note HDMI and DP share bits */ |
| 1579 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 1580 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 1581 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 1582 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 1583 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 1584 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 1585 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 1586 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 1587 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 1588 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
Andy Lutomirski | 2d1c975 | 2010-06-12 05:21:18 -0400 | [diff] [blame] | 1589 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1590 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
Andy Lutomirski | 2d1c975 | 2010-06-12 05:21:18 -0400 | [diff] [blame] | 1591 | |
| 1592 | /* Programming the CRT detection parameters tends |
| 1593 | to generate a spurious hotplug event about three |
| 1594 | seconds later. So just do it once. |
| 1595 | */ |
| 1596 | if (IS_G4X(dev)) |
| 1597 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
| 1598 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
| 1599 | } |
| 1600 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1601 | /* Ignore TV since it's buggy */ |
| 1602 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1603 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1604 | } |
| 1605 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1606 | intel_opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1607 | |
| 1608 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1609 | } |
| 1610 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1611 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1612 | { |
| 1613 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1614 | I915_WRITE(HWSTAM, 0xffffffff); |
| 1615 | |
| 1616 | I915_WRITE(DEIMR, 0xffffffff); |
| 1617 | I915_WRITE(DEIER, 0x0); |
| 1618 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1619 | |
| 1620 | I915_WRITE(GTIMR, 0xffffffff); |
| 1621 | I915_WRITE(GTIER, 0x0); |
| 1622 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1623 | } |
| 1624 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1625 | void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1626 | { |
| 1627 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1628 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1629 | if (!dev_priv) |
| 1630 | return; |
| 1631 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1632 | dev_priv->vblank_pipe = 0; |
| 1633 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1634 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1635 | ironlake_irq_uninstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1636 | return; |
| 1637 | } |
| 1638 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1639 | if (I915_HAS_HOTPLUG(dev)) { |
| 1640 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1641 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1642 | } |
| 1643 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1644 | I915_WRITE(HWSTAM, 0xffffffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1645 | I915_WRITE(PIPEASTAT, 0); |
| 1646 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1647 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1648 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1649 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1650 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1651 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1652 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1653 | } |