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Stephen Boyd8ff1f4c2015-11-30 17:31:39 -08001/*
Rajendra Nayake512fb22016-04-18 11:40:43 +05302 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -08003 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_ALPHA_PLL_H__
15#define __QCOM_CLK_ALPHA_PLL_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
Rajendra Nayake512fb22016-04-18 11:40:43 +053019#include "clk-pll.h"
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080020
21struct pll_vco {
22 unsigned long min_freq;
23 unsigned long max_freq;
24 u32 val;
25};
26
Deepak Katragadda2b803212016-06-29 16:35:22 -070027enum pll_type {
28 ALPHA_PLL,
29 FABIA_PLL,
30};
31
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080032/**
33 * struct clk_alpha_pll - phase locked loop (PLL)
34 * @offset: base address of registers
Deepak Katragadda2b803212016-06-29 16:35:22 -070035 * @inited: flag that's set when the PLL is initialized
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080036 * @vco_table: array of VCO settings
37 * @clkr: regmap clock handle
Deepak Katragadda2b803212016-06-29 16:35:22 -070038 * @is_fabia: Set if the PLL type is FABIA
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080039 */
40struct clk_alpha_pll {
41 u32 offset;
Deepak Katragadda2b803212016-06-29 16:35:22 -070042 struct pll_config *config;
43 bool inited;
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080044
45 const struct pll_vco *vco_table;
46 size_t num_vco;
47
48 struct clk_regmap clkr;
Rajendra Nayake512fb22016-04-18 11:40:43 +053049 u32 config_ctl_val;
50#define PLLOUT_MAIN BIT(0)
51#define PLLOUT_AUX BIT(1)
52#define PLLOUT_AUX2 BIT(2)
53#define PLLOUT_EARLY BIT(3)
54 u32 pllout_flags;
Deepak Katragadda2b803212016-06-29 16:35:22 -070055 enum pll_type type;
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080056};
57
58/**
59 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
60 * @offset: base address of registers
61 * @width: width of post-divider
Deepak Katragadda2b803212016-06-29 16:35:22 -070062 * @post_div_shift: shift to differentiate between odd and even post-divider
Deepak Katragadda582d6022016-11-09 16:17:45 -080063 * @post_div_table: table with PLL odd and even post-divider settings
64 * @num_post_div: Number of PLL post-divider settings
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080065 * @clkr: regmap clock handle
66 */
67struct clk_alpha_pll_postdiv {
68 u32 offset;
69 u8 width;
Deepak Katragadda2b803212016-06-29 16:35:22 -070070 int post_div_shift;
Deepak Katragadda582d6022016-11-09 16:17:45 -080071 const struct clk_div_table *post_div_table;
72 size_t num_post_div;
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080073 struct clk_regmap clkr;
74};
75
76extern const struct clk_ops clk_alpha_pll_ops;
Rajendra Nayake512fb22016-04-18 11:40:43 +053077extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080078extern const struct clk_ops clk_alpha_pll_postdiv_ops;
Deepak Katragadda2b803212016-06-29 16:35:22 -070079extern const struct clk_ops clk_fabia_pll_ops;
80extern const struct clk_ops clk_fabia_fixed_pll_ops;
Deepak Katragadda582d6022016-11-09 16:17:45 -080081extern const struct clk_ops clk_generic_pll_postdiv_ops;
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080082
Rajendra Nayake512fb22016-04-18 11:40:43 +053083void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
84 const struct pll_config *config);
Deepak Katragadda2b803212016-06-29 16:35:22 -070085void clk_fabia_pll_configure(struct clk_alpha_pll *pll,
86 struct regmap *regmap, const struct pll_config *config);
Rajendra Nayake512fb22016-04-18 11:40:43 +053087
Stephen Boyd8ff1f4c2015-11-30 17:31:39 -080088#endif