blob: 91c266b9f6cf22f996faf66f4095d19e1b3f1650 [file] [log] [blame]
Doug Thompsoncfe40fd2009-05-04 19:25:34 +02001/*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 *
10 * Originally Written by Thayne Harbaugh
11 *
12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
13 * - K8 CPU Revision D and greater support
14 *
15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
16 * - Module largely rewritten, with new (and hopefully correct)
17 * code for dealing with node and chip select interleaving,
18 * various code cleanup, and bug fixes
19 * - Added support for memory hoisting using DRAM hole address
20 * register
21 *
22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
23 * -K8 Rev (1207) revision support added, required Revision
24 * specific mini-driver code to support Rev F as well as
25 * prior revisions
26 *
27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
28 * -Family 10h revision support added. New PCI Device IDs,
29 * indicating new changes. Actual registers modified
30 * were slight, less than the Rev E to Rev F transition
31 * but changing the PCI Device ID was the proper thing to
32 * do, as it provides for almost automactic family
33 * detection. The mods to Rev F required more family
34 * information detection.
35 *
36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
37 * - misc fixes and code cleanups
38 *
39 * This module is based on the following documents
40 * (available from http://www.amd.com/):
41 *
42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
43 * Opteron Processors
44 * AMD publication #: 26094
45 *` Revision: 3.26
46 *
47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
48 * Processors
49 * AMD publication #: 32559
50 * Revision: 3.00
51 * Issue Date: May 2006
52 *
53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
54 * Processors
55 * AMD publication #: 31116
56 * Revision: 3.00
57 * Issue Date: September 07, 2007
58 *
59 * Sections in the first 2 documents are no longer in sync with each other.
60 * The Family 10h BKDG was totally re-written from scratch with a new
61 * presentation model.
62 * Therefore, comments that refer to a Document section might be off.
63 */
64
65#include <linux/module.h>
66#include <linux/ctype.h>
67#include <linux/init.h>
68#include <linux/pci.h>
69#include <linux/pci_ids.h>
70#include <linux/slab.h>
71#include <linux/mmzone.h>
72#include <linux/edac.h>
Doug Thompsonf9431992009-04-27 19:46:08 +020073#include <asm/msr.h>
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020074#include "edac_core.h"
Borislav Petkov47ca08a2010-09-27 15:30:39 +020075#include "mce_amd.h"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020076
Borislav Petkov24f9a7f2010-10-07 18:29:15 +020077#define amd64_debug(fmt, arg...) \
78 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020079
Borislav Petkov24f9a7f2010-10-07 18:29:15 +020080#define amd64_info(fmt, arg...) \
81 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
82
83#define amd64_notice(fmt, arg...) \
84 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
85
86#define amd64_warn(fmt, arg...) \
87 edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
88
89#define amd64_err(fmt, arg...) \
90 edac_printk(KERN_ERR, "amd64", fmt, ##arg)
91
92#define amd64_mc_warn(mci, fmt, arg...) \
93 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
94
95#define amd64_mc_err(mci, fmt, arg...) \
96 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020097
98/*
99 * Throughout the comments in this code, the following terms are used:
100 *
101 * SysAddr, DramAddr, and InputAddr
102 *
103 * These terms come directly from the amd64 documentation
104 * (AMD publication #26094). They are defined as follows:
105 *
106 * SysAddr:
107 * This is a physical address generated by a CPU core or a device
108 * doing DMA. If generated by a CPU core, a SysAddr is the result of
109 * a virtual to physical address translation by the CPU core's address
110 * translation mechanism (MMU).
111 *
112 * DramAddr:
113 * A DramAddr is derived from a SysAddr by subtracting an offset that
114 * depends on which node the SysAddr maps to and whether the SysAddr
115 * is within a range affected by memory hoisting. The DRAM Base
116 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
117 * determine which node a SysAddr maps to.
118 *
119 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
120 * is within the range of addresses specified by this register, then
121 * a value x from the DHAR is subtracted from the SysAddr to produce a
122 * DramAddr. Here, x represents the base address for the node that
123 * the SysAddr maps to plus an offset due to memory hoisting. See
124 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
125 * sys_addr_to_dram_addr() below for more information.
126 *
127 * If the SysAddr is not affected by the DHAR then a value y is
128 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
129 * base address for the node that the SysAddr maps to. See section
130 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
131 * information.
132 *
133 * InputAddr:
134 * A DramAddr is translated to an InputAddr before being passed to the
135 * memory controller for the node that the DramAddr is associated
136 * with. The memory controller then maps the InputAddr to a csrow.
137 * If node interleaving is not in use, then the InputAddr has the same
138 * value as the DramAddr. Otherwise, the InputAddr is produced by
139 * discarding the bits used for node interleaving from the DramAddr.
140 * See section 3.4.4 for more information.
141 *
142 * The memory controller for a given node uses its DRAM CS Base and
143 * DRAM CS Mask registers to map an InputAddr to a csrow. See
144 * sections 3.5.4 and 3.5.5 for more information.
145 */
146
Borislav Petkov24f9a7f2010-10-07 18:29:15 +0200147#define EDAC_AMD64_VERSION "v3.3.0"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200148#define EDAC_MOD_STR "amd64_edac"
149
150/* Extended Model from CPUID, for CPU Revision numbers */
Borislav Petkov1433eb92009-10-21 13:44:36 +0200151#define K8_REV_D 1
152#define K8_REV_E 2
153#define K8_REV_F 4
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200154
155/* Hardware limit on ChipSelect rows per MC and processors per system */
Borislav Petkov9d858bb2009-09-21 14:35:51 +0200156#define MAX_CS_COUNT 8
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200157#define DRAM_REG_COUNT 8
158
Borislav Petkovf6d6ae92009-11-03 15:29:26 +0100159#define ON true
160#define OFF false
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200161
162/*
163 * PCI-defined configuration space registers
164 */
165
166
167/*
168 * Function 1 - Address Map
169 */
170#define K8_DRAM_BASE_LOW 0x40
171#define K8_DRAM_LIMIT_LOW 0x44
172#define K8_DHAR 0xf0
173
174#define DHAR_VALID BIT(0)
175#define F10_DRAM_MEM_HOIST_VALID BIT(1)
176
177#define DHAR_BASE_MASK 0xff000000
178#define dhar_base(dhar) (dhar & DHAR_BASE_MASK)
179
180#define K8_DHAR_OFFSET_MASK 0x0000ff00
181#define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16)
182
183#define F10_DHAR_OFFSET_MASK 0x0000ff80
184 /* NOTE: Extra mask bit vs K8 */
185#define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16)
186
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200187#define DCT_CFG_SEL 0x10C
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200188
189/* F10 High BASE/LIMIT registers */
190#define F10_DRAM_BASE_HIGH 0x140
191#define F10_DRAM_LIMIT_HIGH 0x144
192
193
194/*
195 * Function 2 - DRAM controller
196 */
197#define K8_DCSB0 0x40
198#define F10_DCSB1 0x140
199
200#define K8_DCSB_CS_ENABLE BIT(0)
201#define K8_DCSB_NPT_SPARE BIT(1)
202#define K8_DCSB_NPT_TESTFAIL BIT(2)
203
204/*
205 * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
206 * the address
207 */
208#define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL)
209#define REV_E_DCS_SHIFT 4
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200210
211#define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL)
212#define REV_F_F1Xh_DCS_SHIFT 8
213
214/*
215 * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
216 * to form the address
217 */
218#define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL)
219#define REV_F_DCS_SHIFT 8
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200220
221/* DRAM CS Mask Registers */
222#define K8_DCSM0 0x60
223#define F10_DCSM1 0x160
224
225/* REV E: select [29:21] and [15:9] from DCSM */
226#define REV_E_DCSM_MASK_BITS 0x3FE0FE00
227
228/* unused bits [24:20] and [12:0] */
229#define REV_E_DCS_NOTUSED_BITS 0x01F01FFF
230
231/* REV F and later: select [28:19] and [13:5] from DCSM */
232#define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0
233
234/* unused bits [26:22] and [12:0] */
235#define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF
236
237#define DBAM0 0x80
238#define DBAM1 0x180
239
240/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
241#define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)
242
243#define DBAM_MAX_VALUE 11
244
245
246#define F10_DCLR_0 0x90
247#define F10_DCLR_1 0x190
248#define REVE_WIDTH_128 BIT(16)
249#define F10_WIDTH_128 BIT(11)
250
251
252#define F10_DCHR_0 0x94
253#define F10_DCHR_1 0x194
254
255#define F10_DCHR_FOUR_RANK_DIMM BIT(18)
Borislav Petkov1433eb92009-10-21 13:44:36 +0200256#define DDR3_MODE BIT(8)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200257#define F10_DCHR_MblMode BIT(6)
258
259
260#define F10_DCTL_SEL_LOW 0x110
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200261#define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800)
262#define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3)
263#define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0))
264#define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2))
265#define dct_ganging_enabled(pvt) (pvt->dct_sel_low & BIT(4))
266#define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5))
267#define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8))
268#define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10))
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200269
270#define F10_DCTL_SEL_HIGH 0x114
271
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200272/*
273 * Function 3 - Misc Control
274 */
275#define K8_NBCTL 0x40
276
277/* Correctable ECC error reporting enable */
278#define K8_NBCTL_CECCEn BIT(0)
279
280/* UnCorrectable ECC error reporting enable */
281#define K8_NBCTL_UECCEn BIT(1)
282
283#define K8_NBCFG 0x44
284#define K8_NBCFG_CHIPKILL BIT(23)
285#define K8_NBCFG_ECC_ENABLE BIT(22)
286
287#define K8_NBSL 0x48
288
289
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200290/* Family F10h: Normalized Extended Error Codes */
291#define F10_NBSL_EXT_ERR_RES 0x0
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200292#define F10_NBSL_EXT_ERR_ECC 0x8
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200293
294/* Next two are overloaded values */
295#define F10_NBSL_EXT_ERR_LINK_PROTO 0xB
296#define F10_NBSL_EXT_ERR_L3_PROTO 0xB
297
298#define F10_NBSL_EXT_ERR_NB_ARRAY 0xC
299#define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD
300#define F10_NBSL_EXT_ERR_LINK_RETRY 0xE
301
302/* Next two are overloaded values */
303#define F10_NBSL_EXT_ERR_GART_WALK 0xF
304#define F10_NBSL_EXT_ERR_DEV_WALK 0xF
305
306/* 0x10 to 0x1B: Reserved */
307#define F10_NBSL_EXT_ERR_L3_DATA 0x1C
308#define F10_NBSL_EXT_ERR_L3_TAG 0x1D
309#define F10_NBSL_EXT_ERR_L3_LRU 0x1E
310
311/* K8: Normalized Extended Error Codes */
312#define K8_NBSL_EXT_ERR_ECC 0x0
313#define K8_NBSL_EXT_ERR_CRC 0x1
314#define K8_NBSL_EXT_ERR_SYNC 0x2
315#define K8_NBSL_EXT_ERR_MST 0x3
316#define K8_NBSL_EXT_ERR_TGT 0x4
317#define K8_NBSL_EXT_ERR_GART 0x5
318#define K8_NBSL_EXT_ERR_RMW 0x6
319#define K8_NBSL_EXT_ERR_WDT 0x7
320#define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8
321#define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD
322
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200323/*
324 * The following are for BUS type errors AFTER values have been normalized by
325 * shifting right
326 */
327#define K8_NBSL_PP_SRC 0x0
328#define K8_NBSL_PP_RES 0x1
329#define K8_NBSL_PP_OBS 0x2
330#define K8_NBSL_PP_GENERIC 0x3
331
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200332#define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200333
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200334#define K8_NBEAL 0x50
335#define K8_NBEAH 0x54
336#define K8_SCRCTRL 0x58
337
338#define F10_NB_CFG_LOW 0x88
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200339
340#define F10_ONLINE_SPARE 0xB0
341#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
342#define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3))
343#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
344#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
345
346#define F10_NB_ARRAY_ADDR 0xB8
347
348#define F10_NB_ARRAY_DRAM_ECC 0x80000000
349
350/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
351#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
352
353#define F10_NB_ARRAY_DATA 0xBC
354
355#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
356 (BIT(((word) & 0xF) + 20) | \
Borislav Petkov94baaee2009-09-24 11:05:30 +0200357 BIT(17) | bits)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200358
359#define SET_NB_DRAM_INJECTION_READ(word, bits) \
360 (BIT(((word) & 0xF) + 20) | \
Borislav Petkov94baaee2009-09-24 11:05:30 +0200361 BIT(16) | bits)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200362
363#define K8_NBCAP 0xE8
364#define K8_NBCAP_CORES (BIT(12)|BIT(13))
365#define K8_NBCAP_CHIPKILL BIT(4)
366#define K8_NBCAP_SECDED BIT(3)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200367#define K8_NBCAP_DCT_DUAL BIT(0)
368
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100369#define EXT_NB_MCA_CFG 0x180
370
Borislav Petkovf6d6ae92009-11-03 15:29:26 +0100371/* MSRs */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200372#define K8_MSR_MCGCTL_NBE BIT(4)
373
374#define K8_MSR_MC4CTL 0x0410
375#define K8_MSR_MC4STAT 0x0411
376#define K8_MSR_MC4ADDR 0x0412
377
378/* AMD sets the first MC device at device ID 0x18. */
Borislav Petkov37da0452009-06-10 17:36:57 +0200379static inline int get_node_id(struct pci_dev *pdev)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200380{
381 return PCI_SLOT(pdev->devfn) - 0x18;
382}
383
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200384enum amd_families {
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200385 K8_CPUS = 0,
386 F10_CPUS,
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200387 F15_CPUS,
388 NUM_FAMILIES,
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200389};
390
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200391/* Error injection control structure */
392struct error_injection {
393 u32 section;
394 u32 word;
395 u32 bit_map;
396};
397
398struct amd64_pvt {
Borislav Petkovb8cfa022010-10-01 19:35:38 +0200399 struct low_ops *ops;
400
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200401 /* pci_device handles which we utilize */
Borislav Petkov8d5b5d92010-10-01 20:11:07 +0200402 struct pci_dev *F1, *F2, *F3;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200403
404 int mc_node_id; /* MC index of this MC node */
405 int ext_model; /* extended model value of this node */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200406 int channel_count;
407
408 /* Raw registers */
409 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
410 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
411 u32 dchr0; /* DRAM Configuration High DCT0 reg */
412 u32 dchr1; /* DRAM Configuration High DCT1 reg */
413 u32 nbcap; /* North Bridge Capabilities */
414 u32 nbcfg; /* F10 North Bridge Configuration */
415 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
416 u32 dhar; /* DRAM Hoist reg */
417 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
418 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
419
420 /* DRAM CS Base Address Registers F2x[1,0][5C:40] */
Borislav Petkov9d858bb2009-09-21 14:35:51 +0200421 u32 dcsb0[MAX_CS_COUNT];
422 u32 dcsb1[MAX_CS_COUNT];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200423
424 /* DRAM CS Mask Registers F2x[1,0][6C:60] */
Borislav Petkov9d858bb2009-09-21 14:35:51 +0200425 u32 dcsm0[MAX_CS_COUNT];
426 u32 dcsm1[MAX_CS_COUNT];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200427
428 /*
429 * Decoded parts of DRAM BASE and LIMIT Registers
430 * F1x[78,70,68,60,58,50,48,40]
431 */
432 u64 dram_base[DRAM_REG_COUNT];
433 u64 dram_limit[DRAM_REG_COUNT];
434 u8 dram_IntlvSel[DRAM_REG_COUNT];
435 u8 dram_IntlvEn[DRAM_REG_COUNT];
436 u8 dram_DstNode[DRAM_REG_COUNT];
437 u8 dram_rw_en[DRAM_REG_COUNT];
438
439 /*
440 * The following fields are set at (load) run time, after CPU revision
441 * has been determined, since the dct_base and dct_mask registers vary
442 * based on revision
443 */
444 u32 dcsb_base; /* DCSB base bits */
445 u32 dcsm_mask; /* DCSM mask bits */
Borislav Petkov9d858bb2009-09-21 14:35:51 +0200446 u32 cs_count; /* num chip selects (== num DCSB registers) */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200447 u32 num_dcsm; /* Number of DCSM registers */
448 u32 dcs_mask_notused; /* DCSM notused mask bits */
449 u32 dcs_shift; /* DCSB and DCSM shift value */
450
451 u64 top_mem; /* top of memory below 4GB */
452 u64 top_mem2; /* top of memory above 4GB */
453
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200454 u32 dct_sel_low; /* DRAM Controller Select Low Reg */
455 u32 dct_sel_hi; /* DRAM Controller Select High Reg */
456 u32 online_spare; /* On-Line spare Reg */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200457
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100458 /* x4 or x8 syndromes in use */
459 u8 syn_type;
460
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200461 /* temp storage for when input is received from sysfs */
Borislav Petkovef44cc42009-07-23 14:45:48 +0200462 struct err_regs ctl_error_info;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200463
464 /* place to store error injection parameters prior to issue */
465 struct error_injection injection;
466
Borislav Petkov395ae782010-10-01 18:38:19 +0200467 /* DCT per-family scrubrate setting */
468 u32 min_scrubrate;
469
Borislav Petkov0092b202010-10-01 19:20:05 +0200470 /* family name this instance is running on */
471 const char *ctl_name;
472
Borislav Petkovae7bb7c2010-10-14 16:01:30 +0200473};
474
475/*
476 * per-node ECC settings descriptor
477 */
478struct ecc_settings {
479 u32 old_nbctl;
480 bool nbctl_valid;
481
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200482 struct flags {
Borislav Petkovd95cf4d2010-02-24 14:49:47 +0100483 unsigned long nb_mce_enable:1;
484 unsigned long nb_ecc_prev:1;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200485 } flags;
486};
487
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200488extern const char *tt_msgs[4];
489extern const char *ll_msgs[4];
490extern const char *rrrr_msgs[16];
491extern const char *to_msgs[2];
492extern const char *pp_msgs[4];
493extern const char *ii_msgs[4];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200494extern const char *htlink_msgs[8];
495
Doug Thompson7d6034d2009-04-27 20:01:01 +0200496#ifdef CONFIG_EDAC_DEBUG
Borislav Petkov9cdeb402010-09-02 18:33:24 +0200497#define NUM_DBG_ATTRS 5
Doug Thompson7d6034d2009-04-27 20:01:01 +0200498#else
499#define NUM_DBG_ATTRS 0
500#endif
501
502#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
503#define NUM_INJ_ATTRS 5
504#else
505#define NUM_INJ_ATTRS 0
506#endif
507
508extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
509 amd64_inj_attrs[NUM_INJ_ATTRS];
510
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200511/*
512 * Each of the PCI Device IDs types have their own set of hardware accessor
513 * functions and per device encoding/decoding logic.
514 */
515struct low_ops {
Borislav Petkov1433eb92009-10-21 13:44:36 +0200516 int (*early_channel_count) (struct amd64_pvt *pvt);
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200517
Borislav Petkov1433eb92009-10-21 13:44:36 +0200518 u64 (*get_error_address) (struct mem_ctl_info *mci,
519 struct err_regs *info);
520 void (*read_dram_base_limit) (struct amd64_pvt *pvt, int dram);
521 void (*read_dram_ctl_register) (struct amd64_pvt *pvt);
522 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
523 struct err_regs *info, u64 SystemAddr);
524 int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200525 int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
526 u32 *val, const char *func);
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200527};
528
529struct amd64_family_type {
530 const char *ctl_name;
Borislav Petkov8d5b5d92010-10-01 20:11:07 +0200531 u16 f1_id, f3_id;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200532 struct low_ops ops;
533};
534
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200535int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
536 u32 val, const char *func);
Borislav Petkov6ba5dcd2009-10-13 19:26:55 +0200537
538#define amd64_read_pci_cfg(pdev, offset, val) \
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200539 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
540
541#define amd64_write_pci_cfg(pdev, offset, val) \
542 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
543
544#define amd64_read_dct_pci_cfg(pvt, offset, val) \
545 pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
Borislav Petkov6ba5dcd2009-10-13 19:26:55 +0200546
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200547/*
548 * For future CPU versions, verify the following as new 'slow' rates appear and
549 * modify the necessary skip values for the supported CPU.
550 */
551#define K8_MIN_SCRUB_RATE_BITS 0x0
552#define F10_MIN_SCRUB_RATE_BITS 0x5
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200553
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200554int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
555 u64 *hole_offset, u64 *hole_size);