Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | #include "drmP.h" |
| 2 | #include "drm_mode.h" |
| 3 | #include "nouveau_reg.h" |
| 4 | #include "nouveau_drv.h" |
| 5 | #include "nouveau_crtc.h" |
| 6 | #include "nouveau_hw.h" |
| 7 | |
| 8 | static void |
| 9 | nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) |
| 10 | { |
| 11 | nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); |
| 12 | } |
| 13 | |
| 14 | static void |
| 15 | nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) |
| 16 | { |
| 17 | nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); |
| 18 | } |
| 19 | |
| 20 | static void |
| 21 | nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) |
| 22 | { |
Maarten Maathuis | b334f2b | 2010-05-09 14:49:52 +0200 | [diff] [blame^] | 23 | nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 24 | NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, |
| 25 | NV_PRAMDAC_CU_START_POS, |
| 26 | XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | |
| 27 | XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); |
| 28 | } |
| 29 | |
| 30 | static void |
| 31 | crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) |
| 32 | { |
| 33 | NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, |
| 34 | crtcstate->CRTC[index]); |
| 35 | } |
| 36 | |
| 37 | static void |
| 38 | nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) |
| 39 | { |
| 40 | struct drm_device *dev = nv_crtc->base.dev; |
| 41 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 42 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; |
| 43 | struct drm_crtc *crtc = &nv_crtc->base; |
| 44 | |
| 45 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = |
| 46 | MASK(NV_CIO_CRE_HCUR_ASI) | |
| 47 | XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); |
| 48 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = |
| 49 | XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); |
| 50 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
| 51 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= |
| 52 | MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); |
| 53 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; |
| 54 | |
| 55 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); |
| 56 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); |
| 57 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); |
| 58 | if (dev_priv->card_type == NV_40) |
| 59 | nv_fix_nv40_hw_cursor(dev, nv_crtc->index); |
| 60 | } |
| 61 | |
| 62 | int |
| 63 | nv04_cursor_init(struct nouveau_crtc *crtc) |
| 64 | { |
| 65 | crtc->cursor.set_offset = nv04_cursor_set_offset; |
| 66 | crtc->cursor.set_pos = nv04_cursor_set_pos; |
| 67 | crtc->cursor.hide = nv04_cursor_hide; |
| 68 | crtc->cursor.show = nv04_cursor_show; |
| 69 | return 0; |
| 70 | } |
| 71 | |