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Dave Jiangc0d12172007-07-19 01:49:46 -07001/*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -07006 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
Dave Jiangc0d12172007-07-19 01:49:46 -07007 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12#ifndef _LINUX_EDAC_H_
13#define _LINUX_EDAC_H_
14
Arun Sharma600634972011-07-26 16:09:06 -070015#include <linux/atomic.h>
Paul Gortmaker313162d2012-01-30 11:46:54 -050016#include <linux/kobject.h>
17#include <linux/completion.h>
18#include <linux/workqueue.h>
19
20struct device;
Dave Jiangc0d12172007-07-19 01:49:46 -070021
22#define EDAC_OPSTATE_INVAL -1
23#define EDAC_OPSTATE_POLL 0
24#define EDAC_OPSTATE_NMI 1
25#define EDAC_OPSTATE_INT 2
26
27extern int edac_op_state;
Dave Jiang66ee2f92007-07-19 01:49:54 -070028extern int edac_err_assert;
Dave Jiangc0d12172007-07-19 01:49:46 -070029extern atomic_t edac_handlers;
Kay Sieversfe5ff8b2011-12-14 15:21:07 -080030extern struct bus_type edac_subsys;
Dave Jiangc0d12172007-07-19 01:49:46 -070031
32extern int edac_handler_set(void);
33extern void edac_atomic_assert_error(void);
Kay Sieversfe5ff8b2011-12-14 15:21:07 -080034extern struct bus_type *edac_get_sysfs_subsys(void);
35extern void edac_put_sysfs_subsys(void);
Dave Jiangc0d12172007-07-19 01:49:46 -070036
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -070037static inline void opstate_init(void)
38{
39 switch (edac_op_state) {
40 case EDAC_OPSTATE_POLL:
41 case EDAC_OPSTATE_NMI:
42 break;
43 default:
44 edac_op_state = EDAC_OPSTATE_POLL;
45 }
46 return;
47}
48
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -030049#define EDAC_MC_LABEL_LEN 31
50#define MC_PROC_NAME_MAX_LEN 7
51
52/* memory devices */
53enum dev_type {
54 DEV_UNKNOWN = 0,
55 DEV_X1,
56 DEV_X2,
57 DEV_X4,
58 DEV_X8,
59 DEV_X16,
60 DEV_X32, /* Do these parts exist? */
61 DEV_X64 /* Do these parts exist? */
62};
63
64#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
65#define DEV_FLAG_X1 BIT(DEV_X1)
66#define DEV_FLAG_X2 BIT(DEV_X2)
67#define DEV_FLAG_X4 BIT(DEV_X4)
68#define DEV_FLAG_X8 BIT(DEV_X8)
69#define DEV_FLAG_X16 BIT(DEV_X16)
70#define DEV_FLAG_X32 BIT(DEV_X32)
71#define DEV_FLAG_X64 BIT(DEV_X64)
72
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -030073/**
Mauro Carvalho Chehab982216a2012-04-16 13:04:46 -030074 * enum hw_event_mc_err_type - type of the detected error
75 *
76 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
77 * corrected error was detected
78 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
79 * can't be corrected by ECC, but it is not
80 * fatal (maybe it is on an unused memory area,
81 * or the memory controller could recover from
82 * it for example, by re-trying the operation).
83 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
84 * be recovered.
85 */
86enum hw_event_mc_err_type {
87 HW_EVENT_ERR_CORRECTED,
88 HW_EVENT_ERR_UNCORRECTED,
89 HW_EVENT_ERR_FATAL,
90};
91
92/**
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -030093 * enum mem_type - memory types. For a more detailed reference, please see
94 * http://en.wikipedia.org/wiki/DRAM
95 *
96 * @MEM_EMPTY Empty csrow
97 * @MEM_RESERVED: Reserved csrow type
98 * @MEM_UNKNOWN: Unknown csrow type
99 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
100 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
101 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
102 * @MEM_SDR: SDR - Single data rate SDRAM
103 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
104 * They use 3 pins for chip select: Pins 0 and 2 are
105 * for rank 0; pins 1 and 3 are for rank 1, if the memory
106 * is dual-rank.
107 * @MEM_RDR: Registered SDR SDRAM
108 * @MEM_DDR: Double data rate SDRAM
109 * http://en.wikipedia.org/wiki/DDR_SDRAM
110 * @MEM_RDDR: Registered Double data rate SDRAM
111 * This is a variant of the DDR memories.
112 * A registered memory has a buffer inside it, hiding
113 * part of the memory details to the memory controller.
114 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
115 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
116 * Those memories are labed as "PC2-" instead of "PC" to
117 * differenciate from DDR.
118 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
119 * and JESD206.
120 * Those memories are accessed per DIMM slot, and not by
121 * a chip select signal.
122 * @MEM_RDDR2: Registered DDR2 RAM
123 * This is a variant of the DDR2 memories.
124 * @MEM_XDR: Rambus XDR
125 * It is an evolution of the original RAMBUS memories,
126 * created to compete with DDR2. Weren't used on any
127 * x86 arch, but cell_edac PPC memory controller uses it.
128 * @MEM_DDR3: DDR3 RAM
129 * @MEM_RDDR3: Registered DDR3 RAM
130 * This is a variant of the DDR3 memories.
131 */
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300132enum mem_type {
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300133 MEM_EMPTY = 0,
134 MEM_RESERVED,
135 MEM_UNKNOWN,
136 MEM_FPM,
137 MEM_EDO,
138 MEM_BEDO,
139 MEM_SDR,
140 MEM_RDR,
141 MEM_DDR,
142 MEM_RDDR,
143 MEM_RMBS,
144 MEM_DDR2,
145 MEM_FB_DDR2,
146 MEM_RDDR2,
147 MEM_XDR,
148 MEM_DDR3,
149 MEM_RDDR3,
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300150};
151
152#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
153#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
154#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
155#define MEM_FLAG_FPM BIT(MEM_FPM)
156#define MEM_FLAG_EDO BIT(MEM_EDO)
157#define MEM_FLAG_BEDO BIT(MEM_BEDO)
158#define MEM_FLAG_SDR BIT(MEM_SDR)
159#define MEM_FLAG_RDR BIT(MEM_RDR)
160#define MEM_FLAG_DDR BIT(MEM_DDR)
161#define MEM_FLAG_RDDR BIT(MEM_RDDR)
162#define MEM_FLAG_RMBS BIT(MEM_RMBS)
163#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
164#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
165#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
166#define MEM_FLAG_XDR BIT(MEM_XDR)
167#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
168#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
169
170/* chipset Error Detection and Correction capabilities and mode */
171enum edac_type {
172 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
173 EDAC_NONE, /* Doesn't support ECC */
174 EDAC_RESERVED, /* Reserved ECC type */
175 EDAC_PARITY, /* Detects parity errors */
176 EDAC_EC, /* Error Checking - no correction */
177 EDAC_SECDED, /* Single bit error correction, Double detection */
178 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
179 EDAC_S4ECD4ED, /* Chipkill x4 devices */
180 EDAC_S8ECD8ED, /* Chipkill x8 devices */
181 EDAC_S16ECD16ED, /* Chipkill x16 devices */
182};
183
184#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
185#define EDAC_FLAG_NONE BIT(EDAC_NONE)
186#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
187#define EDAC_FLAG_EC BIT(EDAC_EC)
188#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
189#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
190#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
191#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
192#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
193
194/* scrubbing capabilities */
195enum scrub_type {
196 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
197 SCRUB_NONE, /* No scrubber */
198 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
199 SCRUB_SW_SRC, /* Software scrub only errors */
200 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
201 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
202 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
203 SCRUB_HW_SRC, /* Hardware scrub only errors */
204 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
205 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
206};
207
208#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
209#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
210#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
211#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
212#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
213#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
214#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
215#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
216
217/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
218
219/* EDAC internal operation states */
220#define OP_ALLOC 0x100
221#define OP_RUNNING_POLL 0x201
222#define OP_RUNNING_INTERRUPT 0x202
223#define OP_RUNNING_POLL_INTR 0x203
224#define OP_OFFLINE 0x300
225
226/*
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300227 * Concepts used at the EDAC subsystem
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300228 *
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300229 * There are several things to be aware of that aren't at all obvious:
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300230 *
231 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
232 *
233 * These are some of the many terms that are thrown about that don't always
234 * mean what people think they mean (Inconceivable!). In the interest of
235 * creating a common ground for discussion, terms and their definitions
236 * will be established.
237 *
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300238 * Memory devices: The individual DRAM chips on a memory stick. These
239 * devices commonly output 4 and 8 bits each (x4, x8).
240 * Grouping several of these in parallel provides the
241 * number of bits that the memory controller expects:
242 * typically 72 bits, in order to provide 64 bits +
243 * 8 bits of ECC data.
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300244 *
245 * Memory Stick: A printed circuit board that aggregates multiple
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300246 * memory devices in parallel. In general, this is the
247 * Field Replaceable Unit (FRU) which gets replaced, in
248 * the case of excessive errors. Most often it is also
249 * called DIMM (Dual Inline Memory Module).
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300250 *
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300251 * Memory Socket: A physical connector on the motherboard that accepts
252 * a single memory stick. Also called as "slot" on several
253 * datasheets.
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300254 *
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300255 * Channel: A memory controller channel, responsible to communicate
256 * with a group of DIMMs. Each channel has its own
257 * independent control (command) and data bus, and can
258 * be used independently or grouped with other channels.
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300259 *
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300260 * Branch: It is typically the highest hierarchy on a
261 * Fully-Buffered DIMM memory controller.
262 * Typically, it contains two channels.
263 * Two channels at the same branch can be used in single
264 * mode or in lockstep mode.
265 * When lockstep is enabled, the cacheline is doubled,
266 * but it generally brings some performance penalty.
267 * Also, it is generally not possible to point to just one
268 * memory stick when an error occurs, as the error
269 * correction code is calculated using two DIMMs instead
270 * of one. Due to that, it is capable of correcting more
271 * errors than on single mode.
272 *
273 * Single-channel: The data accessed by the memory controller is contained
274 * into one dimm only. E. g. if the data is 64 bits-wide,
275 * the data flows to the CPU using one 64 bits parallel
276 * access.
277 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
278 * FB-DIMM and RAMBUS use a different concept for channel,
279 * so this concept doesn't apply there.
280 *
281 * Double-channel: The data size accessed by the memory controller is
282 * interlaced into two dimms, accessed at the same time.
283 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
284 * the data flows to the CPU using a 128 bits parallel
285 * access.
286 *
287 * Chip-select row: This is the name of the DRAM signal used to select the
288 * DRAM ranks to be accessed. Common chip-select rows for
289 * single channel are 64 bits, for dual channel 128 bits.
290 * It may not be visible by the memory controller, as some
291 * DIMM types have a memory buffer that can hide direct
292 * access to it from the Memory Controller.
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300293 *
294 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
295 * Motherboards commonly drive two chip-select pins to
296 * a memory stick. A single-ranked stick, will occupy
297 * only one of those rows. The other will be unused.
298 *
299 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
300 * access different sets of memory devices. The two
301 * rows cannot be accessed concurrently.
302 *
303 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
304 * A double-sided stick has two chip-select rows which
Mauro Carvalho Chehab01a6e282012-02-03 13:17:48 -0300305 * access different sets of memory devices. The two
306 * rows cannot be accessed concurrently. "Double-sided"
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300307 * is irrespective of the memory devices being mounted
308 * on both sides of the memory stick.
309 *
310 * Socket set: All of the memory sticks that are required for
311 * a single memory access or all of the memory sticks
312 * spanned by a chip-select row. A single socket set
313 * has two chip-select rows and if double-sided sticks
314 * are used these will occupy those chip-select rows.
315 *
316 * Bank: This term is avoided because it is unclear when
317 * needing to distinguish between chip-select rows and
318 * socket sets.
319 *
320 * Controller pages:
321 *
322 * Physical pages:
323 *
324 * Virtual pages:
325 *
326 *
327 * STRUCTURE ORGANIZATION AND CHOICES
328 *
329 *
330 *
331 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
332 */
333
Mauro Carvalho Chehab982216a2012-04-16 13:04:46 -0300334/**
335 * enum edac_mc_layer - memory controller hierarchy layer
336 *
337 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
338 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
339 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
340 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
341 *
342 * This enum is used by the drivers to tell edac_mc_sysfs what name should
343 * be used when describing a memory stick location.
344 */
345enum edac_mc_layer_type {
346 EDAC_MC_LAYER_BRANCH,
347 EDAC_MC_LAYER_CHANNEL,
348 EDAC_MC_LAYER_SLOT,
349 EDAC_MC_LAYER_CHIP_SELECT,
350};
351
352/**
353 * struct edac_mc_layer - describes the memory controller hierarchy
354 * @layer: layer type
355 * @size: number of components per layer. For example,
356 * if the channel layer has two channels, size = 2
357 * @is_virt_csrow: This layer is part of the "csrow" when old API
358 * compatibility mode is enabled. Otherwise, it is
359 * a channel
360 */
361struct edac_mc_layer {
362 enum edac_mc_layer_type type;
363 unsigned size;
364 bool is_virt_csrow;
365};
366
367/*
368 * Maximum number of layers used by the memory controller to uniquely
369 * identify a single memory stick.
370 * NOTE: Changing this constant requires not only to change the constant
371 * below, but also to change the existing code at the core, as there are
372 * some code there that are optimized for 3 layers.
373 */
374#define EDAC_MAX_LAYERS 3
375
376/**
377 * EDAC_DIMM_PTR - Macro responsible to find a pointer inside a pointer array
378 * for the element given by [layer0,layer1,layer2] position
379 *
380 * @layers: a struct edac_mc_layer array, describing how many elements
381 * were allocated for each layer
382 * @var: name of the var where we want to get the pointer
383 * (like mci->dimms)
384 * @n_layers: Number of layers at the @layers array
385 * @layer0: layer0 position
386 * @layer1: layer1 position. Unused if n_layers < 2
387 * @layer2: layer2 position. Unused if n_layers < 3
388 *
389 * For 1 layer, this macro returns &var[layer0]
390 * For 2 layers, this macro is similar to allocate a bi-dimensional array
391 * and to return "&var[layer0][layer1]"
392 * For 3 layers, this macro is similar to allocate a tri-dimensional array
393 * and to return "&var[layer0][layer1][layer2]"
394 *
395 * A loop could be used here to make it more generic, but, as we only have
396 * 3 layers, this is a little faster.
397 * By design, layers can never be 0 or more than 3. If that ever happens,
398 * a NULL is returned, causing an OOPS during the memory allocation routine,
399 * with would point to the developer that he's doing something wrong.
400 */
401#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
402 typeof(var) __p; \
403 if ((nlayers) == 1) \
404 __p = &var[layer0]; \
405 else if ((nlayers) == 2) \
406 __p = &var[(layer1) + ((layers[1]).size * (layer0))]; \
407 else if ((nlayers) == 3) \
408 __p = &var[(layer2) + ((layers[2]).size * ((layer1) + \
409 ((layers[1]).size * (layer0))))]; \
410 else \
411 __p = NULL; \
412 __p; \
413})
414
415
416/* FIXME: add the proper per-location error counts */
Mauro Carvalho Chehaba7d7d2e2012-01-27 14:12:32 -0300417struct dimm_info {
418 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300419
420 /* Memory location data */
421 unsigned location[EDAC_MAX_LAYERS];
422
423 struct mem_ctl_info *mci; /* the parent */
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300424
425 u32 grain; /* granularity of reported error in bytes */
426 enum dev_type dtype; /* memory device type */
427 enum mem_type mtype; /* memory dimm type */
428 enum edac_type edac_mode; /* EDAC mode for this dimm */
429
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300430 u32 nr_pages; /* number of pages on this dimm */
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300431
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300432 unsigned csrow, cschannel; /* Points to the old API data */
Mauro Carvalho Chehaba7d7d2e2012-01-27 14:12:32 -0300433};
434
Mauro Carvalho Chehaba4b4be32012-01-27 10:26:13 -0300435/**
436 * struct rank_info - contains the information for one DIMM rank
437 *
438 * @chan_idx: channel number where the rank is (typically, 0 or 1)
439 * @ce_count: number of correctable errors for this rank
Mauro Carvalho Chehaba4b4be32012-01-27 10:26:13 -0300440 * @csrow: A pointer to the chip select row structure (the parent
441 * structure). The location of the rank is given by
442 * the (csrow->csrow_idx, chan_idx) vector.
Mauro Carvalho Chehaba7d7d2e2012-01-27 14:12:32 -0300443 * @dimm: A pointer to the DIMM structure, where the DIMM label
444 * information is stored.
445 *
446 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
447 * This is a bad assumption, but it makes this patch easier. Later
448 * patches in this series will fix this issue.
Mauro Carvalho Chehaba4b4be32012-01-27 10:26:13 -0300449 */
450struct rank_info {
451 int chan_idx;
Mauro Carvalho Chehaba7d7d2e2012-01-27 14:12:32 -0300452 struct csrow_info *csrow;
453 struct dimm_info *dimm;
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300454
455 u32 ce_count; /* Correctable Errors for this csrow */
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300456};
457
458struct csrow_info {
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300459 /* Used only by edac_mc_find_csrow_by_page() */
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300460 unsigned long first_page; /* first page number in csrow */
461 unsigned long last_page; /* last page number in csrow */
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300462 unsigned long page_mask; /* used for interleaving -
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300463 * 0UL for non intlv */
464
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300465 int csrow_idx; /* the chip-select row */
466
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300467 u32 ue_count; /* Uncorrectable Errors for this csrow */
468 u32 ce_count; /* Correctable Errors for this csrow */
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300469
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300470 struct mem_ctl_info *mci; /* the parent */
471
472 struct kobject kobj; /* sysfs kobject for this csrow */
473
474 /* channel information for this csrow */
475 u32 nr_channels;
Mauro Carvalho Chehaba4b4be32012-01-27 10:26:13 -0300476 struct rank_info *channels;
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300477};
478
479struct mcidev_sysfs_group {
480 const char *name; /* group name */
481 const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
482};
483
484struct mcidev_sysfs_group_kobj {
485 struct list_head list; /* list for all instances within a mc */
486
487 struct kobject kobj; /* kobj for the group */
488
489 const struct mcidev_sysfs_group *grp; /* group description table */
490 struct mem_ctl_info *mci; /* the parent */
491};
492
493/* mcidev_sysfs_attribute structure
494 * used for driver sysfs attributes and in mem_ctl_info
495 * sysfs top level entries
496 */
497struct mcidev_sysfs_attribute {
498 /* It should use either attr or grp */
499 struct attribute attr;
500 const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
501
502 /* Ops for show/store values at the attribute - not used on group */
503 ssize_t (*show)(struct mem_ctl_info *,char *);
504 ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
505};
506
507/* MEMORY controller information structure
508 */
509struct mem_ctl_info {
510 struct list_head link; /* for global list of mem_ctl_info structs */
511
512 struct module *owner; /* Module owner of this control struct */
513
514 unsigned long mtype_cap; /* memory types supported by mc */
515 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
516 unsigned long edac_cap; /* configuration capabilities - this is
517 * closely related to edac_ctl_cap. The
518 * difference is that the controller may be
519 * capable of s4ecd4ed which would be listed
520 * in edac_ctl_cap, but if channels aren't
521 * capable of s4ecd4ed then the edac_cap would
522 * not have that capability.
523 */
524 unsigned long scrub_cap; /* chipset scrub capabilities */
525 enum scrub_type scrub_mode; /* current scrub mode */
526
527 /* Translates sdram memory scrub rate given in bytes/sec to the
528 internal representation and configures whatever else needs
529 to be configured.
530 */
531 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
532
533 /* Get the current sdram memory scrub rate from the internal
534 representation and converts it to the closest matching
535 bandwidth in bytes/sec.
536 */
537 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
538
539
540 /* pointer to edac checking routine */
541 void (*edac_check) (struct mem_ctl_info * mci);
542
543 /*
544 * Remaps memory pages: controller pages to physical pages.
545 * For most MC's, this will be NULL.
546 */
547 /* FIXME - why not send the phys page to begin with? */
548 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
549 unsigned long page);
550 int mc_idx;
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300551 struct csrow_info *csrows;
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300552 unsigned nr_csrows, num_cschannel;
553
554 /* Memory Controller hierarchy */
555 unsigned n_layers;
556 struct edac_mc_layer *layers;
557 bool mem_is_per_rank;
Mauro Carvalho Chehaba7d7d2e2012-01-27 14:12:32 -0300558
559 /*
560 * DIMM info. Will eventually remove the entire csrows_info some day
561 */
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300562 unsigned tot_dimms;
Mauro Carvalho Chehaba7d7d2e2012-01-27 14:12:32 -0300563 struct dimm_info *dimms;
564
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300565 /*
566 * FIXME - what about controllers on other busses? - IDs must be
567 * unique. dev pointer should be sufficiently unique, but
568 * BUS:SLOT.FUNC numbers may not be unique.
569 */
570 struct device *dev;
571 const char *mod_name;
572 const char *mod_ver;
573 const char *ctl_name;
574 const char *dev_name;
575 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
576 void *pvt_info;
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300577 unsigned long start_time; /* mci load start time (in jiffies) */
578
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300579 /*
580 * drivers shouldn't access those fields directly, as the core
581 * already handles that.
582 */
583 u32 ce_noinfo_count, ue_noinfo_count;
Mauro Carvalho Chehab5926ff52012-02-09 11:05:20 -0300584 u32 ue_mc, ce_mc;
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300585 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
586
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300587 struct completion complete;
588
589 /* edac sysfs device control */
590 struct kobject edac_mci_kobj;
591
592 /* list for all grp instances within a mc */
593 struct list_head grp_kobj_list;
594
595 /* Additional top controller level attributes, but specified
596 * by the low level driver.
597 *
598 * Set by the low level driver to provide attributes at the
Mauro Carvalho Chehab4275be62012-04-18 15:20:50 -0300599 * controller level.
Mauro Carvalho Chehabddeb3542011-03-04 15:11:29 -0300600 * An array of structures, NULL terminated
601 *
602 * If attributes are desired, then set to array of attributes
603 * If no attributes are desired, leave NULL
604 */
605 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
606
607 /* work struct for this MC */
608 struct delayed_work work;
609
610 /* the internal state of this controller instance */
611 int op_state;
612};
613
Dave Jiangc0d12172007-07-19 01:49:46 -0700614#endif