blob: 508838ee31e023f2ac1038236299b7ea7eb4e38b [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080028#include <linux/kernel.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include "drmP.h"
30#include "intel_drv.h"
31#include "i915_drm.h"
32#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070033#include "intel_dp.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034
35#include "drm_crtc_helper.h"
36
37bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080038static void intel_update_watermarks(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080039
40typedef struct {
41 /* given values */
42 int n;
43 int m1, m2;
44 int p1, p2;
45 /* derived values */
46 int dot;
47 int vco;
48 int m;
49 int p;
50} intel_clock_t;
51
52typedef struct {
53 int min, max;
54} intel_range_t;
55
56typedef struct {
57 int dot_limit;
58 int p2_slow, p2_fast;
59} intel_p2_t;
60
61#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080062typedef struct intel_limit intel_limit_t;
63struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080064 intel_range_t dot, vco, n, m, m1, m2, p, p1;
65 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080066 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
67 int, int, intel_clock_t *);
68};
Jesse Barnes79e53942008-11-07 14:24:08 -080069
70#define I8XX_DOT_MIN 25000
71#define I8XX_DOT_MAX 350000
72#define I8XX_VCO_MIN 930000
73#define I8XX_VCO_MAX 1400000
74#define I8XX_N_MIN 3
75#define I8XX_N_MAX 16
76#define I8XX_M_MIN 96
77#define I8XX_M_MAX 140
78#define I8XX_M1_MIN 18
79#define I8XX_M1_MAX 26
80#define I8XX_M2_MIN 6
81#define I8XX_M2_MAX 16
82#define I8XX_P_MIN 4
83#define I8XX_P_MAX 128
84#define I8XX_P1_MIN 2
85#define I8XX_P1_MAX 33
86#define I8XX_P1_LVDS_MIN 1
87#define I8XX_P1_LVDS_MAX 6
88#define I8XX_P2_SLOW 4
89#define I8XX_P2_FAST 2
90#define I8XX_P2_LVDS_SLOW 14
91#define I8XX_P2_LVDS_FAST 14 /* No fast option */
92#define I8XX_P2_SLOW_LIMIT 165000
93
94#define I9XX_DOT_MIN 20000
95#define I9XX_DOT_MAX 400000
96#define I9XX_VCO_MIN 1400000
97#define I9XX_VCO_MAX 2800000
Shaohua Li21778322009-02-23 15:19:16 +080098#define IGD_VCO_MIN 1700000
99#define IGD_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500100#define I9XX_N_MIN 1
101#define I9XX_N_MAX 6
Shaohua Li21778322009-02-23 15:19:16 +0800102/* IGD's Ncounter is a ring counter */
103#define IGD_N_MIN 3
104#define IGD_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800105#define I9XX_M_MIN 70
106#define I9XX_M_MAX 120
Shaohua Li21778322009-02-23 15:19:16 +0800107#define IGD_M_MIN 2
108#define IGD_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800109#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500110#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800111#define I9XX_M2_MIN 5
112#define I9XX_M2_MAX 9
Shaohua Li21778322009-02-23 15:19:16 +0800113/* IGD M1 is reserved, and must be 0 */
114#define IGD_M1_MIN 0
115#define IGD_M1_MAX 0
116#define IGD_M2_MIN 0
117#define IGD_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800118#define I9XX_P_SDVO_DAC_MIN 5
119#define I9XX_P_SDVO_DAC_MAX 80
120#define I9XX_P_LVDS_MIN 7
121#define I9XX_P_LVDS_MAX 98
Shaohua Li21778322009-02-23 15:19:16 +0800122#define IGD_P_LVDS_MIN 7
123#define IGD_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800124#define I9XX_P1_MIN 1
125#define I9XX_P1_MAX 8
126#define I9XX_P2_SDVO_DAC_SLOW 10
127#define I9XX_P2_SDVO_DAC_FAST 5
128#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
129#define I9XX_P2_LVDS_SLOW 14
130#define I9XX_P2_LVDS_FAST 7
131#define I9XX_P2_LVDS_SLOW_LIMIT 112000
132
Ma Ling044c7c42009-03-18 20:13:23 +0800133/*The parameter is for SDVO on G4x platform*/
134#define G4X_DOT_SDVO_MIN 25000
135#define G4X_DOT_SDVO_MAX 270000
136#define G4X_VCO_MIN 1750000
137#define G4X_VCO_MAX 3500000
138#define G4X_N_SDVO_MIN 1
139#define G4X_N_SDVO_MAX 4
140#define G4X_M_SDVO_MIN 104
141#define G4X_M_SDVO_MAX 138
142#define G4X_M1_SDVO_MIN 17
143#define G4X_M1_SDVO_MAX 23
144#define G4X_M2_SDVO_MIN 5
145#define G4X_M2_SDVO_MAX 11
146#define G4X_P_SDVO_MIN 10
147#define G4X_P_SDVO_MAX 30
148#define G4X_P1_SDVO_MIN 1
149#define G4X_P1_SDVO_MAX 3
150#define G4X_P2_SDVO_SLOW 10
151#define G4X_P2_SDVO_FAST 10
152#define G4X_P2_SDVO_LIMIT 270000
153
154/*The parameter is for HDMI_DAC on G4x platform*/
155#define G4X_DOT_HDMI_DAC_MIN 22000
156#define G4X_DOT_HDMI_DAC_MAX 400000
157#define G4X_N_HDMI_DAC_MIN 1
158#define G4X_N_HDMI_DAC_MAX 4
159#define G4X_M_HDMI_DAC_MIN 104
160#define G4X_M_HDMI_DAC_MAX 138
161#define G4X_M1_HDMI_DAC_MIN 16
162#define G4X_M1_HDMI_DAC_MAX 23
163#define G4X_M2_HDMI_DAC_MIN 5
164#define G4X_M2_HDMI_DAC_MAX 11
165#define G4X_P_HDMI_DAC_MIN 5
166#define G4X_P_HDMI_DAC_MAX 80
167#define G4X_P1_HDMI_DAC_MIN 1
168#define G4X_P1_HDMI_DAC_MAX 8
169#define G4X_P2_HDMI_DAC_SLOW 10
170#define G4X_P2_HDMI_DAC_FAST 5
171#define G4X_P2_HDMI_DAC_LIMIT 165000
172
173/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
174#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
175#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
176#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
177#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
178#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
179#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
180#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
181#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
182#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
183#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
184#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
185#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
186#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
187#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
188#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
189#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
190#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
191
192/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
193#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
194#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
195#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
196#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
197#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
198#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
199#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
200#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
201#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
202#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
203#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
204#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
205#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
206#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
207#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
208#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
209#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
210
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700211/*The parameter is for DISPLAY PORT on G4x platform*/
212#define G4X_DOT_DISPLAY_PORT_MIN 161670
213#define G4X_DOT_DISPLAY_PORT_MAX 227000
214#define G4X_N_DISPLAY_PORT_MIN 1
215#define G4X_N_DISPLAY_PORT_MAX 2
216#define G4X_M_DISPLAY_PORT_MIN 97
217#define G4X_M_DISPLAY_PORT_MAX 108
218#define G4X_M1_DISPLAY_PORT_MIN 0x10
219#define G4X_M1_DISPLAY_PORT_MAX 0x12
220#define G4X_M2_DISPLAY_PORT_MIN 0x05
221#define G4X_M2_DISPLAY_PORT_MAX 0x06
222#define G4X_P_DISPLAY_PORT_MIN 10
223#define G4X_P_DISPLAY_PORT_MAX 20
224#define G4X_P1_DISPLAY_PORT_MIN 1
225#define G4X_P1_DISPLAY_PORT_MAX 2
226#define G4X_P2_DISPLAY_PORT_SLOW 10
227#define G4X_P2_DISPLAY_PORT_FAST 10
228#define G4X_P2_DISPLAY_PORT_LIMIT 0
229
Zhenyu Wang2c072452009-06-05 15:38:42 +0800230/* IGDNG */
231/* as we calculate clock using (register_value + 2) for
232 N/M1/M2, so here the range value for them is (actual_value-2).
233 */
234#define IGDNG_DOT_MIN 25000
235#define IGDNG_DOT_MAX 350000
236#define IGDNG_VCO_MIN 1760000
237#define IGDNG_VCO_MAX 3510000
238#define IGDNG_N_MIN 1
239#define IGDNG_N_MAX 5
240#define IGDNG_M_MIN 79
241#define IGDNG_M_MAX 118
242#define IGDNG_M1_MIN 12
243#define IGDNG_M1_MAX 23
244#define IGDNG_M2_MIN 5
245#define IGDNG_M2_MAX 9
246#define IGDNG_P_SDVO_DAC_MIN 5
247#define IGDNG_P_SDVO_DAC_MAX 80
248#define IGDNG_P_LVDS_MIN 28
249#define IGDNG_P_LVDS_MAX 112
250#define IGDNG_P1_MIN 1
251#define IGDNG_P1_MAX 8
252#define IGDNG_P2_SDVO_DAC_SLOW 10
253#define IGDNG_P2_SDVO_DAC_FAST 5
254#define IGDNG_P2_LVDS_SLOW 14 /* single channel */
255#define IGDNG_P2_LVDS_FAST 7 /* double channel */
256#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
257
Ma Lingd4906092009-03-18 20:13:27 +0800258static bool
259intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
260 int target, int refclk, intel_clock_t *best_clock);
261static bool
262intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
263 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800264static bool
265intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
266 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800267
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700268static bool
269intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271
Keith Packarde4b36692009-06-05 19:22:17 -0700272static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800273 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
274 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
275 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
276 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
277 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
278 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
279 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
280 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
281 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
282 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800283 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700284};
285
286static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800287 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
288 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
289 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
290 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
291 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
292 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
293 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
294 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
295 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
296 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800297 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700298};
299
300static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800301 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
302 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
303 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
304 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
305 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
306 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
307 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
308 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
309 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
310 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800311 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700312};
313
314static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800315 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
316 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
317 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
318 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
319 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
320 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
321 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
322 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
323 /* The single-channel range is 25-112Mhz, and dual-channel
324 * is 80-224Mhz. Prefer single channel as much as possible.
325 */
326 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
327 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800328 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700329};
330
Ma Ling044c7c42009-03-18 20:13:23 +0800331 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700332static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800333 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
334 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
335 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
336 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
337 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
338 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
339 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
340 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
341 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
342 .p2_slow = G4X_P2_SDVO_SLOW,
343 .p2_fast = G4X_P2_SDVO_FAST
344 },
Ma Lingd4906092009-03-18 20:13:27 +0800345 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700346};
347
348static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800349 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
350 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
351 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
352 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
353 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
354 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
355 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
356 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
357 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
358 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
359 .p2_fast = G4X_P2_HDMI_DAC_FAST
360 },
Ma Lingd4906092009-03-18 20:13:27 +0800361 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700362};
363
364static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800365 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
366 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
367 .vco = { .min = G4X_VCO_MIN,
368 .max = G4X_VCO_MAX },
369 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
370 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
371 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
372 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
373 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
374 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
375 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
376 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
377 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
378 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
379 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
380 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
381 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
382 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
383 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
384 },
Ma Lingd4906092009-03-18 20:13:27 +0800385 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700386};
387
388static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800389 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
390 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
391 .vco = { .min = G4X_VCO_MIN,
392 .max = G4X_VCO_MAX },
393 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
394 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
395 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
396 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
397 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
398 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
399 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
400 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
401 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
402 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
403 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
404 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
405 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
406 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
407 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
408 },
Ma Lingd4906092009-03-18 20:13:27 +0800409 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700410};
411
412static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700413 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
414 .max = G4X_DOT_DISPLAY_PORT_MAX },
415 .vco = { .min = G4X_VCO_MIN,
416 .max = G4X_VCO_MAX},
417 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
418 .max = G4X_N_DISPLAY_PORT_MAX },
419 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
420 .max = G4X_M_DISPLAY_PORT_MAX },
421 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
422 .max = G4X_M1_DISPLAY_PORT_MAX },
423 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
424 .max = G4X_M2_DISPLAY_PORT_MAX },
425 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
426 .max = G4X_P_DISPLAY_PORT_MAX },
427 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
428 .max = G4X_P1_DISPLAY_PORT_MAX},
429 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
430 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
431 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
432 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700433};
434
435static const intel_limit_t intel_limits_igd_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800436 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
437 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
438 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
439 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
440 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
441 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
442 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
443 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
444 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
445 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800446 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700447};
448
449static const intel_limit_t intel_limits_igd_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800450 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
451 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
452 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
453 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
454 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
455 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
456 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
457 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
458 /* IGD only supports single-channel mode. */
459 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
460 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800461 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700462};
463
464static const intel_limit_t intel_limits_igdng_sdvo = {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800465 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
466 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
467 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
468 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
469 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
470 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
471 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
472 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
473 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
474 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
475 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
476 .find_pll = intel_igdng_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700477};
478
479static const intel_limit_t intel_limits_igdng_lvds = {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800480 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
481 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
482 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
483 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
484 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
485 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
486 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
487 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
488 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
489 .p2_slow = IGDNG_P2_LVDS_SLOW,
490 .p2_fast = IGDNG_P2_LVDS_FAST },
491 .find_pll = intel_igdng_find_best_PLL,
Jesse Barnes79e53942008-11-07 14:24:08 -0800492};
493
Zhenyu Wang2c072452009-06-05 15:38:42 +0800494static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
495{
496 const intel_limit_t *limit;
497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700498 limit = &intel_limits_igdng_lvds;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800499 else
Keith Packarde4b36692009-06-05 19:22:17 -0700500 limit = &intel_limits_igdng_sdvo;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800501
502 return limit;
503}
504
Ma Ling044c7c42009-03-18 20:13:23 +0800505static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
506{
507 struct drm_device *dev = crtc->dev;
508 struct drm_i915_private *dev_priv = dev->dev_private;
509 const intel_limit_t *limit;
510
511 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
512 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
513 LVDS_CLKB_POWER_UP)
514 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700515 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800516 else
517 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700518 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700521 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700523 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700524 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700525 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800526 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700527 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800528
529 return limit;
530}
531
Jesse Barnes79e53942008-11-07 14:24:08 -0800532static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
Zhenyu Wang2c072452009-06-05 15:38:42 +0800537 if (IS_IGDNG(dev))
538 limit = intel_igdng_limit(crtc);
539 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800540 limit = intel_g4x_limit(crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800541 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700543 limit = &intel_limits_i9xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800544 else
Keith Packarde4b36692009-06-05 19:22:17 -0700545 limit = &intel_limits_i9xx_sdvo;
Shaohua Li21778322009-02-23 15:19:16 +0800546 } else if (IS_IGD(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700548 limit = &intel_limits_igd_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800549 else
Keith Packarde4b36692009-06-05 19:22:17 -0700550 limit = &intel_limits_igd_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800551 } else {
552 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700553 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800554 else
Keith Packarde4b36692009-06-05 19:22:17 -0700555 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800556 }
557 return limit;
558}
559
Shaohua Li21778322009-02-23 15:19:16 +0800560/* m1 is reserved as 0 in IGD, n is a ring counter */
561static void igd_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800562{
Shaohua Li21778322009-02-23 15:19:16 +0800563 clock->m = clock->m2 + 2;
564 clock->p = clock->p1 * clock->p2;
565 clock->vco = refclk * clock->m / clock->n;
566 clock->dot = clock->vco / clock->p;
567}
568
569static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
570{
571 if (IS_IGD(dev)) {
572 igd_clock(refclk, clock);
573 return;
574 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800575 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
576 clock->p = clock->p1 * clock->p2;
577 clock->vco = refclk * clock->m / (clock->n + 2);
578 clock->dot = clock->vco / clock->p;
579}
580
Jesse Barnes79e53942008-11-07 14:24:08 -0800581/**
582 * Returns whether any output on the specified pipe is of the specified type
583 */
584bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
585{
586 struct drm_device *dev = crtc->dev;
587 struct drm_mode_config *mode_config = &dev->mode_config;
588 struct drm_connector *l_entry;
589
590 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
591 if (l_entry->encoder &&
592 l_entry->encoder->crtc == crtc) {
593 struct intel_output *intel_output = to_intel_output(l_entry);
594 if (intel_output->type == type)
595 return true;
596 }
597 }
598 return false;
599}
600
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800601#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800602/**
603 * Returns whether the given set of divisors are valid for a given refclk with
604 * the given connectors.
605 */
606
607static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
608{
609 const intel_limit_t *limit = intel_limit (crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800610 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800611
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid ("p1 out of range\n");
614 if (clock->p < limit->p.min || limit->p.max < clock->p)
615 INTELPllInvalid ("p out of range\n");
616 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
617 INTELPllInvalid ("m2 out of range\n");
618 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
619 INTELPllInvalid ("m1 out of range\n");
Shaohua Li21778322009-02-23 15:19:16 +0800620 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800621 INTELPllInvalid ("m1 <= m2\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid ("m out of range\n");
624 if (clock->n < limit->n.min || limit->n.max < clock->n)
625 INTELPllInvalid ("n out of range\n");
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid ("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid ("dot out of range\n");
633
634 return true;
635}
636
Ma Lingd4906092009-03-18 20:13:27 +0800637static bool
638intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
639 int target, int refclk, intel_clock_t *best_clock)
640
Jesse Barnes79e53942008-11-07 14:24:08 -0800641{
642 struct drm_device *dev = crtc->dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645 int err = target;
646
647 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
648 (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
649 /*
650 * For LVDS, if the panel is on, just rely on its current
651 * settings for dual-channel. We haven't figured out how to
652 * reliably set up different single/dual channel state, if we
653 * even can.
654 */
655 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
656 LVDS_CLKB_POWER_UP)
657 clock.p2 = limit->p2.p2_fast;
658 else
659 clock.p2 = limit->p2.p2_slow;
660 } else {
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
663 else
664 clock.p2 = limit->p2.p2_fast;
665 }
666
667 memset (best_clock, 0, sizeof (*best_clock));
668
669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Shaohua Li21778322009-02-23 15:19:16 +0800670 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in IGD */
672 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
673 break;
Jesse Barnes79e53942008-11-07 14:24:08 -0800674 for (clock.n = limit->n.min; clock.n <= limit->n.max;
675 clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
Shaohua Li21778322009-02-23 15:19:16 +0800680 intel_clock(dev, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800681
682 if (!intel_PLL_is_valid(crtc, &clock))
683 continue;
684
685 this_err = abs(clock.dot - target);
686 if (this_err < err) {
687 *best_clock = clock;
688 err = this_err;
689 }
690 }
691 }
692 }
693 }
694
695 return (err != target);
696}
697
Ma Lingd4906092009-03-18 20:13:27 +0800698static bool
699intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
700 int target, int refclk, intel_clock_t *best_clock)
701{
702 struct drm_device *dev = crtc->dev;
703 struct drm_i915_private *dev_priv = dev->dev_private;
704 intel_clock_t clock;
705 int max_n;
706 bool found;
707 /* approximately equals target * 0.00488 */
708 int err_most = (target >> 8) + (target >> 10);
709 found = false;
710
711 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
712 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
713 LVDS_CLKB_POWER_UP)
714 clock.p2 = limit->p2.p2_fast;
715 else
716 clock.p2 = limit->p2.p2_slow;
717 } else {
718 if (target < limit->p2.dot_limit)
719 clock.p2 = limit->p2.p2_slow;
720 else
721 clock.p2 = limit->p2.p2_fast;
722 }
723
724 memset(best_clock, 0, sizeof(*best_clock));
725 max_n = limit->n.max;
726 /* based on hardware requriment prefer smaller n to precision */
727 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
728 /* based on hardware requirment prefere larger m1,m2, p1 */
729 for (clock.m1 = limit->m1.max;
730 clock.m1 >= limit->m1.min; clock.m1--) {
731 for (clock.m2 = limit->m2.max;
732 clock.m2 >= limit->m2.min; clock.m2--) {
733 for (clock.p1 = limit->p1.max;
734 clock.p1 >= limit->p1.min; clock.p1--) {
735 int this_err;
736
Shaohua Li21778322009-02-23 15:19:16 +0800737 intel_clock(dev, refclk, &clock);
Ma Lingd4906092009-03-18 20:13:27 +0800738 if (!intel_PLL_is_valid(crtc, &clock))
739 continue;
740 this_err = abs(clock.dot - target) ;
741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800751 return found;
752}
Ma Lingd4906092009-03-18 20:13:27 +0800753
Zhenyu Wang2c072452009-06-05 15:38:42 +0800754static bool
755intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *best_clock)
757{
758 struct drm_device *dev = crtc->dev;
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 intel_clock_t clock;
761 int max_n;
762 bool found;
763 int err_most = 47;
764 found = false;
765
766 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
767 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
768 LVDS_CLKB_POWER_UP)
769 clock.p2 = limit->p2.p2_fast;
770 else
771 clock.p2 = limit->p2.p2_slow;
772 } else {
773 if (target < limit->p2.dot_limit)
774 clock.p2 = limit->p2.p2_slow;
775 else
776 clock.p2 = limit->p2.p2_fast;
777 }
778
779 memset(best_clock, 0, sizeof(*best_clock));
780 max_n = limit->n.max;
781 /* based on hardware requriment prefer smaller n to precision */
782 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
783 /* based on hardware requirment prefere larger m1,m2, p1 */
784 for (clock.m1 = limit->m1.max;
785 clock.m1 >= limit->m1.min; clock.m1--) {
786 for (clock.m2 = limit->m2.max;
787 clock.m2 >= limit->m2.min; clock.m2--) {
788 for (clock.p1 = limit->p1.max;
789 clock.p1 >= limit->p1.min; clock.p1--) {
790 int this_err;
791
792 intel_clock(dev, refclk, &clock);
793 if (!intel_PLL_is_valid(crtc, &clock))
794 continue;
795 this_err = abs((10000 - (target*10000/clock.dot)));
796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 /* found on first matching */
802 goto out;
803 }
804 }
805 }
806 }
807 }
808out:
Ma Lingd4906092009-03-18 20:13:27 +0800809 return found;
810}
811
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700812/* DisplayPort has only two frequencies, 162MHz and 270MHz */
813static bool
814intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
815 int target, int refclk, intel_clock_t *best_clock)
816{
817 intel_clock_t clock;
818 if (target < 200000) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700819 clock.p1 = 2;
820 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700821 clock.n = 2;
822 clock.m1 = 23;
823 clock.m2 = 8;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700824 } else {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700825 clock.p1 = 1;
826 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700827 clock.n = 1;
828 clock.m1 = 14;
829 clock.m2 = 2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700830 }
Keith Packardb3d25492009-06-24 23:09:15 -0700831 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
832 clock.p = (clock.p1 * clock.p2);
833 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700834 memcpy(best_clock, &clock, sizeof(intel_clock_t));
835 return true;
836}
837
Jesse Barnes79e53942008-11-07 14:24:08 -0800838void
839intel_wait_for_vblank(struct drm_device *dev)
840{
841 /* Wait for 20ms, i.e. one cycle at 50hz. */
Arjan van de Ven580982d2009-03-23 13:36:25 -0700842 mdelay(20);
Jesse Barnes79e53942008-11-07 14:24:08 -0800843}
844
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000845static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500846intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
847 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -0800848{
849 struct drm_device *dev = crtc->dev;
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 struct drm_i915_master_private *master_priv;
852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
853 struct intel_framebuffer *intel_fb;
854 struct drm_i915_gem_object *obj_priv;
855 struct drm_gem_object *obj;
856 int pipe = intel_crtc->pipe;
857 unsigned long Start, Offset;
858 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
859 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
860 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
Jesse Barnesf5448472009-04-14 14:17:47 -0700861 int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
Jesse Barnes79e53942008-11-07 14:24:08 -0800862 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500863 u32 dspcntr, alignment;
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000864 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -0800865
866 /* no fb bound */
867 if (!crtc->fb) {
868 DRM_DEBUG("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000869 return 0;
870 }
871
872 switch (pipe) {
873 case 0:
874 case 1:
875 break;
876 default:
877 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
878 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -0800879 }
880
881 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -0800882 obj = intel_fb->obj;
883 obj_priv = obj->driver_private;
884
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500885 switch (obj_priv->tiling_mode) {
886 case I915_TILING_NONE:
887 alignment = 64 * 1024;
888 break;
889 case I915_TILING_X:
Chris Wilson2ebed172009-02-11 14:26:30 +0000890 /* pin() will align the object as required by fence */
891 alignment = 0;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500892 break;
893 case I915_TILING_Y:
894 /* FIXME: Is this true? */
895 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000896 return -EINVAL;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500897 default:
898 BUG();
899 }
900
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000901 mutex_lock(&dev->struct_mutex);
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100902 ret = i915_gem_object_pin(obj, alignment);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000903 if (ret != 0) {
904 mutex_unlock(&dev->struct_mutex);
905 return ret;
906 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500907
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100908 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000909 if (ret != 0) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100910 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000911 mutex_unlock(&dev->struct_mutex);
912 return ret;
913 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800914
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100915 /* Pre-i965 needs to install a fence for tiled scan-out */
916 if (!IS_I965G(dev) &&
917 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
918 obj_priv->tiling_mode != I915_TILING_NONE) {
919 ret = i915_gem_object_get_fence_reg(obj);
920 if (ret != 0) {
921 i915_gem_object_unpin(obj);
922 mutex_unlock(&dev->struct_mutex);
923 return ret;
924 }
925 }
926
Jesse Barnes79e53942008-11-07 14:24:08 -0800927 dspcntr = I915_READ(dspcntr_reg);
Jesse Barnes712531b2009-01-09 13:56:14 -0800928 /* Mask out pixel format bits in case we change it */
929 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Jesse Barnes79e53942008-11-07 14:24:08 -0800930 switch (crtc->fb->bits_per_pixel) {
931 case 8:
932 dspcntr |= DISPPLANE_8BPP;
933 break;
934 case 16:
935 if (crtc->fb->depth == 15)
936 dspcntr |= DISPPLANE_15_16BPP;
937 else
938 dspcntr |= DISPPLANE_16BPP;
939 break;
940 case 24:
941 case 32:
942 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
943 break;
944 default:
945 DRM_ERROR("Unknown color depth\n");
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100946 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000947 mutex_unlock(&dev->struct_mutex);
948 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -0800949 }
Jesse Barnesf5448472009-04-14 14:17:47 -0700950 if (IS_I965G(dev)) {
951 if (obj_priv->tiling_mode != I915_TILING_NONE)
952 dspcntr |= DISPPLANE_TILED;
953 else
954 dspcntr &= ~DISPPLANE_TILED;
955 }
956
Jesse Barnes79e53942008-11-07 14:24:08 -0800957 I915_WRITE(dspcntr_reg, dspcntr);
958
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000959 Start = obj_priv->gtt_offset;
960 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
961
Jesse Barnes79e53942008-11-07 14:24:08 -0800962 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000963 I915_WRITE(dspstride, crtc->fb->pitch);
Jesse Barnes79e53942008-11-07 14:24:08 -0800964 if (IS_I965G(dev)) {
965 I915_WRITE(dspbase, Offset);
966 I915_READ(dspbase);
967 I915_WRITE(dspsurf, Start);
968 I915_READ(dspsurf);
Jesse Barnesf5448472009-04-14 14:17:47 -0700969 I915_WRITE(dsptileoff, (y << 16) | x);
Jesse Barnes79e53942008-11-07 14:24:08 -0800970 } else {
971 I915_WRITE(dspbase, Start + Offset);
972 I915_READ(dspbase);
973 }
974
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500975 intel_wait_for_vblank(dev);
976
977 if (old_fb) {
978 intel_fb = to_intel_framebuffer(old_fb);
979 i915_gem_object_unpin(intel_fb->obj);
980 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000981 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -0800982
983 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000984 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800985
986 master_priv = dev->primary->master->driver_priv;
987 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000988 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800989
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000990 if (pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800991 master_priv->sarea_priv->pipeB_x = x;
992 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000993 } else {
994 master_priv->sarea_priv->pipeA_x = x;
995 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -0800996 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000997
998 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800999}
1000
Zhenyu Wang2c072452009-06-05 15:38:42 +08001001static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08001002{
1003 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006 int pipe = intel_crtc->pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08001007 int plane = intel_crtc->plane;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001008 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1009 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1010 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1011 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1012 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1013 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1014 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1015 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1016 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1017 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1018 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1019 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1020 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1021 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1022 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1023 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1024 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1025 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1026 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1027 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1028 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1029 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1030 u32 temp;
1031 int tries = 5, j;
1032
1033 /* XXX: When our outputs are all unaware of DPMS modes other than off
1034 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1035 */
1036 switch (mode) {
1037 case DRM_MODE_DPMS_ON:
1038 case DRM_MODE_DPMS_STANDBY:
1039 case DRM_MODE_DPMS_SUSPEND:
1040 DRM_DEBUG("crtc %d dpms on\n", pipe);
1041 /* enable PCH DPLL */
1042 temp = I915_READ(pch_dpll_reg);
1043 if ((temp & DPLL_VCO_ENABLE) == 0) {
1044 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1045 I915_READ(pch_dpll_reg);
1046 }
1047
1048 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1049 temp = I915_READ(fdi_rx_reg);
1050 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1051 FDI_SEL_PCDCLK |
1052 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1053 I915_READ(fdi_rx_reg);
1054 udelay(200);
1055
1056 /* Enable CPU FDI TX PLL, always on for IGDNG */
1057 temp = I915_READ(fdi_tx_reg);
1058 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1059 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1060 I915_READ(fdi_tx_reg);
1061 udelay(100);
1062 }
1063
1064 /* Enable CPU pipe */
1065 temp = I915_READ(pipeconf_reg);
1066 if ((temp & PIPEACONF_ENABLE) == 0) {
1067 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1068 I915_READ(pipeconf_reg);
1069 udelay(100);
1070 }
1071
1072 /* configure and enable CPU plane */
1073 temp = I915_READ(dspcntr_reg);
1074 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1075 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1076 /* Flush the plane changes */
1077 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1078 }
1079
1080 /* enable CPU FDI TX and PCH FDI RX */
1081 temp = I915_READ(fdi_tx_reg);
1082 temp |= FDI_TX_ENABLE;
1083 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1084 temp &= ~FDI_LINK_TRAIN_NONE;
1085 temp |= FDI_LINK_TRAIN_PATTERN_1;
1086 I915_WRITE(fdi_tx_reg, temp);
1087 I915_READ(fdi_tx_reg);
1088
1089 temp = I915_READ(fdi_rx_reg);
1090 temp &= ~FDI_LINK_TRAIN_NONE;
1091 temp |= FDI_LINK_TRAIN_PATTERN_1;
1092 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1093 I915_READ(fdi_rx_reg);
1094
1095 udelay(150);
1096
1097 /* Train FDI. */
1098 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1099 for train result */
1100 temp = I915_READ(fdi_rx_imr_reg);
1101 temp &= ~FDI_RX_SYMBOL_LOCK;
1102 temp &= ~FDI_RX_BIT_LOCK;
1103 I915_WRITE(fdi_rx_imr_reg, temp);
1104 I915_READ(fdi_rx_imr_reg);
1105 udelay(150);
1106
1107 temp = I915_READ(fdi_rx_iir_reg);
1108 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1109
1110 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1111 for (j = 0; j < tries; j++) {
1112 temp = I915_READ(fdi_rx_iir_reg);
1113 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1114 if (temp & FDI_RX_BIT_LOCK)
1115 break;
1116 udelay(200);
1117 }
1118 if (j != tries)
1119 I915_WRITE(fdi_rx_iir_reg,
1120 temp | FDI_RX_BIT_LOCK);
1121 else
1122 DRM_DEBUG("train 1 fail\n");
1123 } else {
1124 I915_WRITE(fdi_rx_iir_reg,
1125 temp | FDI_RX_BIT_LOCK);
1126 DRM_DEBUG("train 1 ok 2!\n");
1127 }
1128 temp = I915_READ(fdi_tx_reg);
1129 temp &= ~FDI_LINK_TRAIN_NONE;
1130 temp |= FDI_LINK_TRAIN_PATTERN_2;
1131 I915_WRITE(fdi_tx_reg, temp);
1132
1133 temp = I915_READ(fdi_rx_reg);
1134 temp &= ~FDI_LINK_TRAIN_NONE;
1135 temp |= FDI_LINK_TRAIN_PATTERN_2;
1136 I915_WRITE(fdi_rx_reg, temp);
1137
1138 udelay(150);
1139
1140 temp = I915_READ(fdi_rx_iir_reg);
1141 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1142
1143 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1144 for (j = 0; j < tries; j++) {
1145 temp = I915_READ(fdi_rx_iir_reg);
1146 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1147 if (temp & FDI_RX_SYMBOL_LOCK)
1148 break;
1149 udelay(200);
1150 }
1151 if (j != tries) {
1152 I915_WRITE(fdi_rx_iir_reg,
1153 temp | FDI_RX_SYMBOL_LOCK);
1154 DRM_DEBUG("train 2 ok 1!\n");
1155 } else
1156 DRM_DEBUG("train 2 fail\n");
1157 } else {
1158 I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1159 DRM_DEBUG("train 2 ok 2!\n");
1160 }
1161 DRM_DEBUG("train done\n");
1162
1163 /* set transcoder timing */
1164 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1165 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1166 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1167
1168 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1169 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1170 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1171
1172 /* enable PCH transcoder */
1173 temp = I915_READ(transconf_reg);
1174 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1175 I915_READ(transconf_reg);
1176
1177 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1178 ;
1179
1180 /* enable normal */
1181
1182 temp = I915_READ(fdi_tx_reg);
1183 temp &= ~FDI_LINK_TRAIN_NONE;
1184 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1185 FDI_TX_ENHANCE_FRAME_ENABLE);
1186 I915_READ(fdi_tx_reg);
1187
1188 temp = I915_READ(fdi_rx_reg);
1189 temp &= ~FDI_LINK_TRAIN_NONE;
1190 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1191 FDI_RX_ENHANCE_FRAME_ENABLE);
1192 I915_READ(fdi_rx_reg);
1193
1194 /* wait one idle pattern time */
1195 udelay(100);
1196
1197 intel_crtc_load_lut(crtc);
1198
1199 break;
1200 case DRM_MODE_DPMS_OFF:
1201 DRM_DEBUG("crtc %d dpms off\n", pipe);
1202
1203 /* Disable the VGA plane that we never use */
1204 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1205
1206 /* Disable display plane */
1207 temp = I915_READ(dspcntr_reg);
1208 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1209 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1210 /* Flush the plane changes */
1211 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1212 I915_READ(dspbase_reg);
1213 }
1214
1215 /* disable cpu pipe, disable after all planes disabled */
1216 temp = I915_READ(pipeconf_reg);
1217 if ((temp & PIPEACONF_ENABLE) != 0) {
1218 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1219 I915_READ(pipeconf_reg);
1220 /* wait for cpu pipe off, pipe state */
1221 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1222 ;
1223 } else
1224 DRM_DEBUG("crtc %d is disabled\n", pipe);
1225
1226 /* IGDNG-A : disable cpu panel fitter ? */
1227 temp = I915_READ(pf_ctl_reg);
1228 if ((temp & PF_ENABLE) != 0) {
1229 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1230 I915_READ(pf_ctl_reg);
1231 }
1232
1233 /* disable CPU FDI tx and PCH FDI rx */
1234 temp = I915_READ(fdi_tx_reg);
1235 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1236 I915_READ(fdi_tx_reg);
1237
1238 temp = I915_READ(fdi_rx_reg);
1239 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1240 I915_READ(fdi_rx_reg);
1241
1242 /* still set train pattern 1 */
1243 temp = I915_READ(fdi_tx_reg);
1244 temp &= ~FDI_LINK_TRAIN_NONE;
1245 temp |= FDI_LINK_TRAIN_PATTERN_1;
1246 I915_WRITE(fdi_tx_reg, temp);
1247
1248 temp = I915_READ(fdi_rx_reg);
1249 temp &= ~FDI_LINK_TRAIN_NONE;
1250 temp |= FDI_LINK_TRAIN_PATTERN_1;
1251 I915_WRITE(fdi_rx_reg, temp);
1252
1253 /* disable PCH transcoder */
1254 temp = I915_READ(transconf_reg);
1255 if ((temp & TRANS_ENABLE) != 0) {
1256 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1257 I915_READ(transconf_reg);
1258 /* wait for PCH transcoder off, transcoder state */
1259 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1260 ;
1261 }
1262
1263 /* disable PCH DPLL */
1264 temp = I915_READ(pch_dpll_reg);
1265 if ((temp & DPLL_VCO_ENABLE) != 0) {
1266 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1267 I915_READ(pch_dpll_reg);
1268 }
1269
1270 temp = I915_READ(fdi_rx_reg);
1271 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1272 temp &= ~FDI_SEL_PCDCLK;
1273 temp &= ~FDI_RX_PLL_ENABLE;
1274 I915_WRITE(fdi_rx_reg, temp);
1275 I915_READ(fdi_rx_reg);
1276 }
1277
1278 /* Wait for the clocks to turn off. */
1279 udelay(150);
1280 break;
1281 }
1282}
1283
1284static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1285{
1286 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08001287 struct drm_i915_private *dev_priv = dev->dev_private;
1288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1289 int pipe = intel_crtc->pipe;
1290 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1291 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1292 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1293 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1294 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08001295
1296 /* XXX: When our outputs are all unaware of DPMS modes other than off
1297 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1298 */
1299 switch (mode) {
1300 case DRM_MODE_DPMS_ON:
1301 case DRM_MODE_DPMS_STANDBY:
1302 case DRM_MODE_DPMS_SUSPEND:
1303 /* Enable the DPLL */
1304 temp = I915_READ(dpll_reg);
1305 if ((temp & DPLL_VCO_ENABLE) == 0) {
1306 I915_WRITE(dpll_reg, temp);
1307 I915_READ(dpll_reg);
1308 /* Wait for the clocks to stabilize. */
1309 udelay(150);
1310 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1311 I915_READ(dpll_reg);
1312 /* Wait for the clocks to stabilize. */
1313 udelay(150);
1314 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1315 I915_READ(dpll_reg);
1316 /* Wait for the clocks to stabilize. */
1317 udelay(150);
1318 }
1319
1320 /* Enable the pipe */
1321 temp = I915_READ(pipeconf_reg);
1322 if ((temp & PIPEACONF_ENABLE) == 0)
1323 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1324
1325 /* Enable the plane */
1326 temp = I915_READ(dspcntr_reg);
1327 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1328 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1329 /* Flush the plane changes */
1330 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1331 }
1332
1333 intel_crtc_load_lut(crtc);
1334
1335 /* Give the overlay scaler a chance to enable if it's on this pipe */
1336 //intel_crtc_dpms_video(crtc, true); TODO
Shaohua Li7662c8b2009-06-26 11:23:55 +08001337 intel_update_watermarks(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001338 break;
1339 case DRM_MODE_DPMS_OFF:
Shaohua Li7662c8b2009-06-26 11:23:55 +08001340 intel_update_watermarks(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001341 /* Give the overlay scaler a chance to disable if it's on this pipe */
1342 //intel_crtc_dpms_video(crtc, FALSE); TODO
1343
1344 /* Disable the VGA plane that we never use */
1345 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1346
1347 /* Disable display plane */
1348 temp = I915_READ(dspcntr_reg);
1349 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1350 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1351 /* Flush the plane changes */
1352 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1353 I915_READ(dspbase_reg);
1354 }
1355
1356 if (!IS_I9XX(dev)) {
1357 /* Wait for vblank for the disable to take effect */
1358 intel_wait_for_vblank(dev);
1359 }
1360
1361 /* Next, disable display pipes */
1362 temp = I915_READ(pipeconf_reg);
1363 if ((temp & PIPEACONF_ENABLE) != 0) {
1364 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1365 I915_READ(pipeconf_reg);
1366 }
1367
1368 /* Wait for vblank for the disable to take effect. */
1369 intel_wait_for_vblank(dev);
1370
1371 temp = I915_READ(dpll_reg);
1372 if ((temp & DPLL_VCO_ENABLE) != 0) {
1373 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1374 I915_READ(dpll_reg);
1375 }
1376
1377 /* Wait for the clocks to turn off. */
1378 udelay(150);
1379 break;
1380 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001381}
1382
1383/**
1384 * Sets the power management mode of the pipe and plane.
1385 *
1386 * This code should probably grow support for turning the cursor off and back
1387 * on appropriately at the same time as we're turning the pipe off/on.
1388 */
1389static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1390{
1391 struct drm_device *dev = crtc->dev;
1392 struct drm_i915_master_private *master_priv;
1393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1394 int pipe = intel_crtc->pipe;
1395 bool enabled;
1396
1397 if (IS_IGDNG(dev))
1398 igdng_crtc_dpms(crtc, mode);
1399 else
1400 i9xx_crtc_dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08001401
1402 if (!dev->primary->master)
1403 return;
1404
1405 master_priv = dev->primary->master->driver_priv;
1406 if (!master_priv->sarea_priv)
1407 return;
1408
1409 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1410
1411 switch (pipe) {
1412 case 0:
1413 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1414 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1415 break;
1416 case 1:
1417 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1418 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1419 break;
1420 default:
1421 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1422 break;
1423 }
1424
1425 intel_crtc->dpms_mode = mode;
1426}
1427
1428static void intel_crtc_prepare (struct drm_crtc *crtc)
1429{
1430 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1431 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1432}
1433
1434static void intel_crtc_commit (struct drm_crtc *crtc)
1435{
1436 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1437 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1438}
1439
1440void intel_encoder_prepare (struct drm_encoder *encoder)
1441{
1442 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1443 /* lvds has its own version of prepare see intel_lvds_prepare */
1444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1445}
1446
1447void intel_encoder_commit (struct drm_encoder *encoder)
1448{
1449 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1450 /* lvds has its own version of commit see intel_lvds_commit */
1451 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1452}
1453
1454static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1455 struct drm_display_mode *mode,
1456 struct drm_display_mode *adjusted_mode)
1457{
Zhenyu Wang2c072452009-06-05 15:38:42 +08001458 struct drm_device *dev = crtc->dev;
1459 if (IS_IGDNG(dev)) {
1460 /* FDI link clock is fixed at 2.7G */
1461 if (mode->clock * 3 > 27000 * 4)
1462 return MODE_CLOCK_HIGH;
1463 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001464 return true;
1465}
1466
1467
1468/** Returns the core display clock speed for i830 - i945 */
1469static int intel_get_core_clock_speed(struct drm_device *dev)
1470{
1471
1472 /* Core clock values taken from the published datasheets.
1473 * The 830 may go up to 166 Mhz, which we should check.
1474 */
1475 if (IS_I945G(dev))
1476 return 400000;
1477 else if (IS_I915G(dev))
1478 return 333000;
Shaohua Li21778322009-02-23 15:19:16 +08001479 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08001480 return 200000;
1481 else if (IS_I915GM(dev)) {
1482 u16 gcfgc = 0;
1483
1484 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1485
1486 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1487 return 133000;
1488 else {
1489 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1490 case GC_DISPLAY_CLOCK_333_MHZ:
1491 return 333000;
1492 default:
1493 case GC_DISPLAY_CLOCK_190_200_MHZ:
1494 return 190000;
1495 }
1496 }
1497 } else if (IS_I865G(dev))
1498 return 266000;
1499 else if (IS_I855(dev)) {
1500 u16 hpllcc = 0;
1501 /* Assume that the hardware is in the high speed state. This
1502 * should be the default.
1503 */
1504 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1505 case GC_CLOCK_133_200:
1506 case GC_CLOCK_100_200:
1507 return 200000;
1508 case GC_CLOCK_166_250:
1509 return 250000;
1510 case GC_CLOCK_100_133:
1511 return 133000;
1512 }
1513 } else /* 852, 830 */
1514 return 133000;
1515
1516 return 0; /* Silence gcc warning */
1517}
1518
Jesse Barnes79e53942008-11-07 14:24:08 -08001519/**
1520 * Return the pipe currently connected to the panel fitter,
1521 * or -1 if the panel fitter is not present or not in use
1522 */
1523static int intel_panel_fitter_pipe (struct drm_device *dev)
1524{
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526 u32 pfit_control;
1527
1528 /* i830 doesn't have a panel fitter */
1529 if (IS_I830(dev))
1530 return -1;
1531
1532 pfit_control = I915_READ(PFIT_CONTROL);
1533
1534 /* See if the panel fitter is in use */
1535 if ((pfit_control & PFIT_ENABLE) == 0)
1536 return -1;
1537
1538 /* 965 can place panel fitter on either pipe */
1539 if (IS_I965G(dev))
1540 return (pfit_control >> 29) & 0x3;
1541
1542 /* older chips can only use pipe 1 */
1543 return 1;
1544}
1545
Zhenyu Wang2c072452009-06-05 15:38:42 +08001546struct fdi_m_n {
1547 u32 tu;
1548 u32 gmch_m;
1549 u32 gmch_n;
1550 u32 link_m;
1551 u32 link_n;
1552};
1553
1554static void
1555fdi_reduce_ratio(u32 *num, u32 *den)
1556{
1557 while (*num > 0xffffff || *den > 0xffffff) {
1558 *num >>= 1;
1559 *den >>= 1;
1560 }
1561}
1562
1563#define DATA_N 0x800000
1564#define LINK_N 0x80000
1565
1566static void
1567igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1568 int pixel_clock, int link_clock,
1569 struct fdi_m_n *m_n)
1570{
1571 u64 temp;
1572
1573 m_n->tu = 64; /* default size */
1574
1575 temp = (u64) DATA_N * pixel_clock;
1576 temp = div_u64(temp, link_clock);
Andy Whitcroft956dba32009-07-01 15:20:59 +01001577 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001578 m_n->gmch_n = DATA_N;
1579 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1580
1581 temp = (u64) LINK_N * pixel_clock;
1582 m_n->link_m = div_u64(temp, link_clock);
1583 m_n->link_n = LINK_N;
1584 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1585}
1586
1587
Shaohua Li7662c8b2009-06-26 11:23:55 +08001588struct intel_watermark_params {
1589 unsigned long fifo_size;
1590 unsigned long max_wm;
1591 unsigned long default_wm;
1592 unsigned long guard_size;
1593 unsigned long cacheline_size;
1594};
1595
1596/* IGD has different values for various configs */
1597static struct intel_watermark_params igd_display_wm = {
1598 IGD_DISPLAY_FIFO,
1599 IGD_MAX_WM,
1600 IGD_DFT_WM,
1601 IGD_GUARD_WM,
1602 IGD_FIFO_LINE_SIZE
1603};
1604static struct intel_watermark_params igd_display_hplloff_wm = {
1605 IGD_DISPLAY_FIFO,
1606 IGD_MAX_WM,
1607 IGD_DFT_HPLLOFF_WM,
1608 IGD_GUARD_WM,
1609 IGD_FIFO_LINE_SIZE
1610};
1611static struct intel_watermark_params igd_cursor_wm = {
1612 IGD_CURSOR_FIFO,
1613 IGD_CURSOR_MAX_WM,
1614 IGD_CURSOR_DFT_WM,
1615 IGD_CURSOR_GUARD_WM,
1616 IGD_FIFO_LINE_SIZE,
1617};
1618static struct intel_watermark_params igd_cursor_hplloff_wm = {
1619 IGD_CURSOR_FIFO,
1620 IGD_CURSOR_MAX_WM,
1621 IGD_CURSOR_DFT_WM,
1622 IGD_CURSOR_GUARD_WM,
1623 IGD_FIFO_LINE_SIZE
1624};
1625static struct intel_watermark_params i945_wm_info = {
1626 I915_FIFO_LINE_SIZE,
1627 I915_MAX_WM,
1628 1,
1629 0,
1630 IGD_FIFO_LINE_SIZE
1631};
1632static struct intel_watermark_params i915_wm_info = {
1633 I945_FIFO_SIZE,
1634 I915_MAX_WM,
1635 1,
1636 0,
1637 I915_FIFO_LINE_SIZE
1638};
1639static struct intel_watermark_params i855_wm_info = {
1640 I855GM_FIFO_SIZE,
1641 I915_MAX_WM,
1642 1,
1643 0,
1644 I830_FIFO_LINE_SIZE
1645};
1646static struct intel_watermark_params i830_wm_info = {
1647 I830_FIFO_SIZE,
1648 I915_MAX_WM,
1649 1,
1650 0,
1651 I830_FIFO_LINE_SIZE
1652};
1653
1654static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1655 struct intel_watermark_params *wm,
1656 int pixel_size,
1657 unsigned long latency_ns)
1658{
1659 unsigned long bytes_required, wm_size;
1660
1661 bytes_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1662 bytes_required /= wm->cacheline_size;
1663 wm_size = wm->fifo_size - bytes_required - wm->guard_size;
1664
1665 if (wm_size > wm->max_wm)
1666 wm_size = wm->max_wm;
1667 if (wm_size == 0)
1668 wm_size = wm->default_wm;
1669 return wm_size;
1670}
1671
1672struct cxsr_latency {
1673 int is_desktop;
1674 unsigned long fsb_freq;
1675 unsigned long mem_freq;
1676 unsigned long display_sr;
1677 unsigned long display_hpll_disable;
1678 unsigned long cursor_sr;
1679 unsigned long cursor_hpll_disable;
1680};
1681
1682static struct cxsr_latency cxsr_latency_table[] = {
1683 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1684 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1685 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1686
1687 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1688 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1689 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1690
1691 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1692 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1693 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1694
1695 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1696 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1697 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1698
1699 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1700 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1701 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1702
1703 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1704 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1705 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1706};
1707
1708static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1709 int mem)
1710{
1711 int i;
1712 struct cxsr_latency *latency;
1713
1714 if (fsb == 0 || mem == 0)
1715 return NULL;
1716
1717 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1718 latency = &cxsr_latency_table[i];
1719 if (is_desktop == latency->is_desktop &&
1720 fsb == latency->fsb_freq && mem == latency->mem_freq)
1721 break;
1722 }
1723 if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1724 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1725 return NULL;
1726 }
1727 return latency;
1728}
1729
1730static void igd_disable_cxsr(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 u32 reg;
1734
1735 /* deactivate cxsr */
1736 reg = I915_READ(DSPFW3);
1737 reg &= ~(IGD_SELF_REFRESH_EN);
1738 I915_WRITE(DSPFW3, reg);
1739 DRM_INFO("Big FIFO is disabled\n");
1740}
1741
1742static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1743 int pixel_size)
1744{
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 u32 reg;
1747 unsigned long wm;
1748 struct cxsr_latency *latency;
1749
1750 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
1751 dev_priv->mem_freq);
1752 if (!latency) {
1753 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1754 igd_disable_cxsr(dev);
1755 return;
1756 }
1757
1758 /* Display SR */
1759 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
1760 latency->display_sr);
1761 reg = I915_READ(DSPFW1);
1762 reg &= 0x7fffff;
1763 reg |= wm << 23;
1764 I915_WRITE(DSPFW1, reg);
1765 DRM_DEBUG("DSPFW1 register is %x\n", reg);
1766
1767 /* cursor SR */
1768 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
1769 latency->cursor_sr);
1770 reg = I915_READ(DSPFW3);
1771 reg &= ~(0x3f << 24);
1772 reg |= (wm & 0x3f) << 24;
1773 I915_WRITE(DSPFW3, reg);
1774
1775 /* Display HPLL off SR */
1776 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
1777 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
1778 reg = I915_READ(DSPFW3);
1779 reg &= 0xfffffe00;
1780 reg |= wm & 0x1ff;
1781 I915_WRITE(DSPFW3, reg);
1782
1783 /* cursor HPLL off SR */
1784 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
1785 latency->cursor_hpll_disable);
1786 reg = I915_READ(DSPFW3);
1787 reg &= ~(0x3f << 16);
1788 reg |= (wm & 0x3f) << 16;
1789 I915_WRITE(DSPFW3, reg);
1790 DRM_DEBUG("DSPFW3 register is %x\n", reg);
1791
1792 /* activate cxsr */
1793 reg = I915_READ(DSPFW3);
1794 reg |= IGD_SELF_REFRESH_EN;
1795 I915_WRITE(DSPFW3, reg);
1796
1797 DRM_INFO("Big FIFO is enabled\n");
1798
1799 return;
1800}
1801
1802const static int latency_ns = 5000; /* default for non-igd platforms */
1803
1804
1805static void i965_update_wm(struct drm_device *dev)
1806{
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1808
1809 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
1810
1811 /* 965 has limitations... */
1812 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
1813 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1814}
1815
1816static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1817 int planeb_clock, int sr_hdisplay, int pixel_size)
1818{
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
1821 uint32_t fwater_hi = I915_READ(FW_BLC2) & LM_FIFO_WATERMARK;
1822 int bsize, asize, cwm, bwm = 1, awm = 1, srwm = 1;
1823 uint32_t dsparb = I915_READ(DSPARB);
1824 int planea_entries, planeb_entries;
1825 struct intel_watermark_params *wm_params;
1826 unsigned long line_time_us;
1827 int sr_clock, sr_entries = 0;
1828
1829 if (IS_I965GM(dev) || IS_I945GM(dev))
1830 wm_params = &i945_wm_info;
1831 else if (IS_I9XX(dev))
1832 wm_params = &i915_wm_info;
1833 else
1834 wm_params = &i855_wm_info;
1835
1836 planea_entries = intel_calculate_wm(planea_clock, wm_params,
1837 pixel_size, latency_ns);
1838 planeb_entries = intel_calculate_wm(planeb_clock, wm_params,
1839 pixel_size, latency_ns);
1840
1841 DRM_DEBUG("FIFO entries - A: %d, B: %d\n", planea_entries,
1842 planeb_entries);
1843
1844 if (IS_I9XX(dev)) {
1845 asize = dsparb & 0x7f;
1846 bsize = (dsparb >> DSPARB_CSTART_SHIFT) & 0x7f;
1847 } else {
1848 asize = dsparb & 0x1ff;
1849 bsize = (dsparb >> DSPARB_BEND_SHIFT) & 0x1ff;
1850 }
1851 DRM_DEBUG("FIFO size - A: %d, B: %d\n", asize, bsize);
1852
1853 /* Two extra entries for padding */
1854 awm = asize - (planea_entries + 2);
1855 bwm = bsize - (planeb_entries + 2);
1856
1857 /* Sanity check against potentially bad FIFO allocations */
1858 if (awm <= 0) {
1859 /* pipe is on but has too few FIFO entries */
1860 if (planea_entries != 0)
1861 DRM_DEBUG("plane A needs more FIFO entries\n");
1862 awm = 1;
1863 }
1864 if (bwm <= 0) {
1865 if (planeb_entries != 0)
1866 DRM_DEBUG("plane B needs more FIFO entries\n");
1867 bwm = 1;
1868 }
1869
1870 /*
1871 * Overlay gets an aggressive default since video jitter is bad.
1872 */
1873 cwm = 2;
1874
1875 /* Calc sr entries for one pipe configs */
1876 if (!planea_clock || !planeb_clock) {
1877 sr_clock = planea_clock ? planea_clock : planeb_clock;
1878 line_time_us = (sr_hdisplay * 1000) / sr_clock;
1879 sr_entries = (((latency_ns / line_time_us) + 1) * pixel_size *
1880 sr_hdisplay) / 1000;
1881 sr_entries = roundup(sr_entries / wm_params->cacheline_size, 1);
1882 if (sr_entries < wm_params->fifo_size)
1883 srwm = wm_params->fifo_size - sr_entries;
1884 }
1885
1886 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1887 awm, bwm, cwm, srwm);
1888
1889 fwater_lo = fwater_lo | ((bwm & 0x3f) << 16) | (awm & 0x3f);
1890 fwater_hi = fwater_hi | (cwm & 0x1f);
1891
1892 I915_WRITE(FW_BLC, fwater_lo);
1893 I915_WRITE(FW_BLC2, fwater_hi);
1894 if (IS_I9XX(dev))
1895 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
1896}
1897
1898static void i830_update_wm(struct drm_device *dev, int planea_clock,
1899 int pixel_size)
1900{
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902 uint32_t dsparb = I915_READ(DSPARB);
1903 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
1904 unsigned int asize, awm;
1905 int planea_entries;
1906
1907 planea_entries = intel_calculate_wm(planea_clock, &i830_wm_info,
1908 pixel_size, latency_ns);
1909
1910 asize = dsparb & 0x7f;
1911
1912 awm = asize - planea_entries;
1913
1914 fwater_lo = fwater_lo | awm;
1915
1916 I915_WRITE(FW_BLC, fwater_lo);
1917}
1918
1919/**
1920 * intel_update_watermarks - update FIFO watermark values based on current modes
1921 *
1922 * Calculate watermark values for the various WM regs based on current mode
1923 * and plane configuration.
1924 *
1925 * There are several cases to deal with here:
1926 * - normal (i.e. non-self-refresh)
1927 * - self-refresh (SR) mode
1928 * - lines are large relative to FIFO size (buffer can hold up to 2)
1929 * - lines are small relative to FIFO size (buffer can hold more than 2
1930 * lines), so need to account for TLB latency
1931 *
1932 * The normal calculation is:
1933 * watermark = dotclock * bytes per pixel * latency
1934 * where latency is platform & configuration dependent (we assume pessimal
1935 * values here).
1936 *
1937 * The SR calculation is:
1938 * watermark = (trunc(latency/line time)+1) * surface width *
1939 * bytes per pixel
1940 * where
1941 * line time = htotal / dotclock
1942 * and latency is assumed to be high, as above.
1943 *
1944 * The final value programmed to the register should always be rounded up,
1945 * and include an extra 2 entries to account for clock crossings.
1946 *
1947 * We don't use the sprite, so we can ignore that. And on Crestline we have
1948 * to set the non-SR watermarks to 8.
1949 */
1950static void intel_update_watermarks(struct drm_device *dev)
1951{
1952 struct drm_crtc *crtc;
1953 struct intel_crtc *intel_crtc;
1954 int sr_hdisplay = 0;
1955 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
1956 int enabled = 0, pixel_size = 0;
1957
1958 if (DSPARB_HWCONTROL(dev))
1959 return;
1960
1961 /* Get the clock config from both planes */
1962 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1963 intel_crtc = to_intel_crtc(crtc);
1964 if (crtc->enabled) {
1965 enabled++;
1966 if (intel_crtc->plane == 0) {
1967 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
1968 intel_crtc->pipe, crtc->mode.clock);
1969 planea_clock = crtc->mode.clock;
1970 } else {
1971 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
1972 intel_crtc->pipe, crtc->mode.clock);
1973 planeb_clock = crtc->mode.clock;
1974 }
1975 sr_hdisplay = crtc->mode.hdisplay;
1976 sr_clock = crtc->mode.clock;
1977 if (crtc->fb)
1978 pixel_size = crtc->fb->bits_per_pixel / 8;
1979 else
1980 pixel_size = 4; /* by default */
1981 }
1982 }
1983
1984 if (enabled <= 0)
1985 return;
1986
1987 /* Single pipe configs can enable self refresh */
1988 if (enabled == 1 && IS_IGD(dev))
1989 igd_enable_cxsr(dev, sr_clock, pixel_size);
1990 else if (IS_IGD(dev))
1991 igd_disable_cxsr(dev);
1992
1993 if (IS_I965G(dev))
1994 i965_update_wm(dev);
1995 else if (IS_I9XX(dev) || IS_MOBILE(dev))
1996 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
1997 pixel_size);
1998 else
1999 i830_update_wm(dev, planea_clock, pixel_size);
2000}
2001
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002002static int intel_crtc_mode_set(struct drm_crtc *crtc,
2003 struct drm_display_mode *mode,
2004 struct drm_display_mode *adjusted_mode,
2005 int x, int y,
2006 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002007{
2008 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2011 int pipe = intel_crtc->pipe;
2012 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2013 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2014 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2015 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2016 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2017 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2018 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2019 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2020 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2021 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2022 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2023 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2024 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2025 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002026 int refclk, num_outputs = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002027 intel_clock_t clock;
2028 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2029 bool ok, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002030 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08002031 struct drm_mode_config *mode_config = &dev->mode_config;
2032 struct drm_connector *connector;
Ma Lingd4906092009-03-18 20:13:27 +08002033 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002034 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002035 struct fdi_m_n m_n = {0};
2036 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2037 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2038 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2039 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2040 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2041 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2042 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang541998a2009-06-05 15:38:44 +08002043 int lvds_reg = LVDS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002044 u32 temp;
2045 int sdvo_pixel_multiply;
Jesse Barnes79e53942008-11-07 14:24:08 -08002046
2047 drm_vblank_pre_modeset(dev, pipe);
2048
2049 list_for_each_entry(connector, &mode_config->connector_list, head) {
2050 struct intel_output *intel_output = to_intel_output(connector);
2051
2052 if (!connector->encoder || connector->encoder->crtc != crtc)
2053 continue;
2054
2055 switch (intel_output->type) {
2056 case INTEL_OUTPUT_LVDS:
2057 is_lvds = true;
2058 break;
2059 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08002060 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08002061 is_sdvo = true;
Jesse Barnese2f0ba92009-02-02 15:11:52 -08002062 if (intel_output->needs_tv_clock)
2063 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08002064 break;
2065 case INTEL_OUTPUT_DVO:
2066 is_dvo = true;
2067 break;
2068 case INTEL_OUTPUT_TVOUT:
2069 is_tv = true;
2070 break;
2071 case INTEL_OUTPUT_ANALOG:
2072 is_crt = true;
2073 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002074 case INTEL_OUTPUT_DISPLAYPORT:
2075 is_dp = true;
2076 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08002077 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002078
2079 num_outputs++;
Jesse Barnes79e53942008-11-07 14:24:08 -08002080 }
2081
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002082 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2083 refclk = dev_priv->lvds_ssc_freq * 1000;
2084 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2085 } else if (IS_I9XX(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002086 refclk = 96000;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002087 if (IS_IGDNG(dev))
2088 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08002089 } else {
2090 refclk = 48000;
2091 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002092
Jesse Barnes79e53942008-11-07 14:24:08 -08002093
Ma Lingd4906092009-03-18 20:13:27 +08002094 /*
2095 * Returns a set of divisors for the desired target clock with the given
2096 * refclk, or FALSE. The returned values represent the clock equation:
2097 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2098 */
2099 limit = intel_limit(crtc);
2100 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002101 if (!ok) {
2102 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01002103 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002104 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002105 }
2106
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08002107 /* SDVO TV has fixed PLL values depend on its clock range,
2108 this mirrors vbios setting. */
2109 if (is_sdvo && is_tv) {
2110 if (adjusted_mode->clock >= 100000
2111 && adjusted_mode->clock < 140500) {
2112 clock.p1 = 2;
2113 clock.p2 = 10;
2114 clock.n = 3;
2115 clock.m1 = 16;
2116 clock.m2 = 8;
2117 } else if (adjusted_mode->clock >= 140500
2118 && adjusted_mode->clock <= 200000) {
2119 clock.p1 = 1;
2120 clock.p2 = 10;
2121 clock.n = 6;
2122 clock.m1 = 12;
2123 clock.m2 = 8;
2124 }
2125 }
2126
Zhenyu Wang2c072452009-06-05 15:38:42 +08002127 /* FDI link */
2128 if (IS_IGDNG(dev))
2129 igdng_compute_m_n(3, 4, /* lane num 4 */
2130 adjusted_mode->clock,
2131 270000, /* lane clock */
2132 &m_n);
2133
Shaohua Li21778322009-02-23 15:19:16 +08002134 if (IS_IGD(dev))
2135 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2136 else
2137 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08002138
Zhenyu Wang2c072452009-06-05 15:38:42 +08002139 if (!IS_IGDNG(dev))
2140 dpll = DPLL_VGA_MODE_DIS;
2141
Jesse Barnes79e53942008-11-07 14:24:08 -08002142 if (IS_I9XX(dev)) {
2143 if (is_lvds)
2144 dpll |= DPLLB_MODE_LVDS;
2145 else
2146 dpll |= DPLLB_MODE_DAC_SERIAL;
2147 if (is_sdvo) {
2148 dpll |= DPLL_DVO_HIGH_SPEED;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002149 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2150 if (IS_I945G(dev) || IS_I945GM(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002151 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002152 else if (IS_IGDNG(dev))
2153 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002154 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002155 if (is_dp)
2156 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08002157
2158 /* compute bitmask from p1 value */
Shaohua Li21778322009-02-23 15:19:16 +08002159 if (IS_IGD(dev))
2160 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002161 else {
Shaohua Li21778322009-02-23 15:19:16 +08002162 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002163 /* also FPA1 */
2164 if (IS_IGDNG(dev))
2165 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2166 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002167 switch (clock.p2) {
2168 case 5:
2169 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2170 break;
2171 case 7:
2172 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2173 break;
2174 case 10:
2175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2176 break;
2177 case 14:
2178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2179 break;
2180 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002181 if (IS_I965G(dev) && !IS_IGDNG(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002182 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2183 } else {
2184 if (is_lvds) {
2185 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2186 } else {
2187 if (clock.p1 == 2)
2188 dpll |= PLL_P1_DIVIDE_BY_TWO;
2189 else
2190 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2191 if (clock.p2 == 4)
2192 dpll |= PLL_P2_DIVIDE_BY_4;
2193 }
2194 }
2195
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002196 if (is_sdvo && is_tv)
2197 dpll |= PLL_REF_INPUT_TVCLKINBC;
2198 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08002199 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002200 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08002201 dpll |= 3;
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002202 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2203 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08002204 else
2205 dpll |= PLL_REF_INPUT_DREFCLK;
2206
2207 /* setup pipeconf */
2208 pipeconf = I915_READ(pipeconf_reg);
2209
2210 /* Set up the display plane register */
2211 dspcntr = DISPPLANE_GAMMA_ENABLE;
2212
Zhenyu Wang2c072452009-06-05 15:38:42 +08002213 /* IGDNG's plane is forced to pipe, bit 24 is to
2214 enable color space conversion */
2215 if (!IS_IGDNG(dev)) {
2216 if (pipe == 0)
2217 dspcntr |= DISPPLANE_SEL_PIPE_A;
2218 else
2219 dspcntr |= DISPPLANE_SEL_PIPE_B;
2220 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002221
2222 if (pipe == 0 && !IS_I965G(dev)) {
2223 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2224 * core speed.
2225 *
2226 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2227 * pipe == 0 check?
2228 */
2229 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2230 pipeconf |= PIPEACONF_DOUBLE_WIDE;
2231 else
2232 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2233 }
2234
2235 dspcntr |= DISPLAY_PLANE_ENABLE;
2236 pipeconf |= PIPEACONF_ENABLE;
2237 dpll |= DPLL_VCO_ENABLE;
2238
2239
2240 /* Disable the panel fitter if it was on our pipe */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002241 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08002242 I915_WRITE(PFIT_CONTROL, 0);
2243
2244 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2245 drm_mode_debug_printmodeline(mode);
2246
Zhenyu Wang2c072452009-06-05 15:38:42 +08002247 /* assign to IGDNG registers */
2248 if (IS_IGDNG(dev)) {
2249 fp_reg = pch_fp_reg;
2250 dpll_reg = pch_dpll_reg;
2251 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002252
2253 if (dpll & DPLL_VCO_ENABLE) {
2254 I915_WRITE(fp_reg, fp);
2255 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2256 I915_READ(dpll_reg);
2257 udelay(150);
2258 }
2259
Zhenyu Wang2c072452009-06-05 15:38:42 +08002260 if (IS_IGDNG(dev)) {
2261 /* enable PCH clock reference source */
2262 /* XXX need to change the setting for other outputs */
2263 u32 temp;
2264 temp = I915_READ(PCH_DREF_CONTROL);
2265 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2266 temp |= DREF_NONSPREAD_CK505_ENABLE;
2267 temp &= ~DREF_SSC_SOURCE_MASK;
2268 temp |= DREF_SSC_SOURCE_ENABLE;
2269 temp &= ~DREF_SSC1_ENABLE;
2270 /* if no eDP, disable source output to CPU */
2271 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2272 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2273 I915_WRITE(PCH_DREF_CONTROL, temp);
2274 }
2275
Jesse Barnes79e53942008-11-07 14:24:08 -08002276 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2277 * This is an exception to the general rule that mode_set doesn't turn
2278 * things on.
2279 */
2280 if (is_lvds) {
Zhenyu Wang541998a2009-06-05 15:38:44 +08002281 u32 lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08002282
Zhenyu Wang541998a2009-06-05 15:38:44 +08002283 if (IS_IGDNG(dev))
2284 lvds_reg = PCH_LVDS;
2285
2286 lvds = I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08002287 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2288 /* Set the B0-B3 data pairs corresponding to whether we're going to
2289 * set the DPLLs for dual-channel mode or not.
2290 */
2291 if (clock.p2 == 7)
2292 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2293 else
2294 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2295
2296 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2297 * appropriately here, but we need to look more thoroughly into how
2298 * panels behave in the two modes.
2299 */
2300
Zhenyu Wang541998a2009-06-05 15:38:44 +08002301 I915_WRITE(lvds_reg, lvds);
2302 I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08002303 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002304 if (is_dp)
2305 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002306
2307 I915_WRITE(fp_reg, fp);
2308 I915_WRITE(dpll_reg, dpll);
2309 I915_READ(dpll_reg);
2310 /* Wait for the clocks to stabilize. */
2311 udelay(150);
2312
Zhenyu Wang2c072452009-06-05 15:38:42 +08002313 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2314 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08002315 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2316 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2317 } else {
2318 /* write it again -- the BIOS does, after all */
2319 I915_WRITE(dpll_reg, dpll);
2320 }
2321 I915_READ(dpll_reg);
2322 /* Wait for the clocks to stabilize. */
2323 udelay(150);
2324
2325 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2326 ((adjusted_mode->crtc_htotal - 1) << 16));
2327 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2328 ((adjusted_mode->crtc_hblank_end - 1) << 16));
2329 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2330 ((adjusted_mode->crtc_hsync_end - 1) << 16));
2331 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2332 ((adjusted_mode->crtc_vtotal - 1) << 16));
2333 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2334 ((adjusted_mode->crtc_vblank_end - 1) << 16));
2335 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2336 ((adjusted_mode->crtc_vsync_end - 1) << 16));
2337 /* pipesrc and dspsize control the size that is scaled from, which should
2338 * always be the user's requested size.
2339 */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002340 if (!IS_IGDNG(dev)) {
2341 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2342 (mode->hdisplay - 1));
2343 I915_WRITE(dsppos_reg, 0);
2344 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002345 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08002346
2347 if (IS_IGDNG(dev)) {
2348 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2349 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2350 I915_WRITE(link_m1_reg, m_n.link_m);
2351 I915_WRITE(link_n1_reg, m_n.link_n);
2352
2353 /* enable FDI RX PLL too */
2354 temp = I915_READ(fdi_rx_reg);
2355 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2356 udelay(200);
2357 }
2358
Jesse Barnes79e53942008-11-07 14:24:08 -08002359 I915_WRITE(pipeconf_reg, pipeconf);
2360 I915_READ(pipeconf_reg);
2361
2362 intel_wait_for_vblank(dev);
2363
2364 I915_WRITE(dspcntr_reg, dspcntr);
2365
2366 /* Flush the plane changes */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002367 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002368
2369 intel_update_watermarks(dev);
2370
Jesse Barnes79e53942008-11-07 14:24:08 -08002371 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002372
Chris Wilson1f803ee2009-06-06 09:45:59 +01002373 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002374}
2375
2376/** Loads the palette/gamma unit for the CRTC with the prepared values */
2377void intel_crtc_load_lut(struct drm_crtc *crtc)
2378{
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2383 int i;
2384
2385 /* The clocks have to be on to load the palette. */
2386 if (!crtc->enabled)
2387 return;
2388
Zhenyu Wang2c072452009-06-05 15:38:42 +08002389 /* use legacy palette for IGDNG */
2390 if (IS_IGDNG(dev))
2391 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2392 LGC_PALETTE_B;
2393
Jesse Barnes79e53942008-11-07 14:24:08 -08002394 for (i = 0; i < 256; i++) {
2395 I915_WRITE(palreg + 4 * i,
2396 (intel_crtc->lut_r[i] << 16) |
2397 (intel_crtc->lut_g[i] << 8) |
2398 intel_crtc->lut_b[i]);
2399 }
2400}
2401
2402static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2403 struct drm_file *file_priv,
2404 uint32_t handle,
2405 uint32_t width, uint32_t height)
2406{
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 struct drm_gem_object *bo;
2411 struct drm_i915_gem_object *obj_priv;
2412 int pipe = intel_crtc->pipe;
2413 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2414 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
Jesse Barnes14b60392009-05-20 16:47:08 -04002415 uint32_t temp = I915_READ(control);
Jesse Barnes79e53942008-11-07 14:24:08 -08002416 size_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002417 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002418
2419 DRM_DEBUG("\n");
2420
2421 /* if we want to turn off the cursor ignore width and height */
2422 if (!handle) {
2423 DRM_DEBUG("cursor off\n");
Jesse Barnes14b60392009-05-20 16:47:08 -04002424 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2425 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2426 temp |= CURSOR_MODE_DISABLE;
2427 } else {
2428 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2429 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002430 addr = 0;
2431 bo = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10002432 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002433 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08002434 }
2435
2436 /* Currently we only support 64x64 cursors */
2437 if (width != 64 || height != 64) {
2438 DRM_ERROR("we currently only support 64x64 cursors\n");
2439 return -EINVAL;
2440 }
2441
2442 bo = drm_gem_object_lookup(dev, file_priv, handle);
2443 if (!bo)
2444 return -ENOENT;
2445
2446 obj_priv = bo->driver_private;
2447
2448 if (bo->size < width * height * 4) {
2449 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10002450 ret = -ENOMEM;
2451 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08002452 }
2453
Dave Airlie71acb5e2008-12-30 20:31:46 +10002454 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002455 mutex_lock(&dev->struct_mutex);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002456 if (!dev_priv->cursor_needs_physical) {
2457 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2458 if (ret) {
2459 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002460 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10002461 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002462 addr = obj_priv->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10002463 } else {
2464 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2465 if (ret) {
2466 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002467 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10002468 }
2469 addr = obj_priv->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002470 }
2471
Jesse Barnes14b60392009-05-20 16:47:08 -04002472 if (!IS_I9XX(dev))
2473 I915_WRITE(CURSIZE, (height << 12) | width);
2474
2475 /* Hooray for CUR*CNTR differences */
2476 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2477 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2478 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2479 temp |= (pipe << 28); /* Connect to correct pipe */
2480 } else {
2481 temp &= ~(CURSOR_FORMAT_MASK);
2482 temp |= CURSOR_ENABLE;
2483 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2484 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002485
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002486 finish:
Jesse Barnes79e53942008-11-07 14:24:08 -08002487 I915_WRITE(control, temp);
2488 I915_WRITE(base, addr);
2489
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002490 if (intel_crtc->cursor_bo) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10002491 if (dev_priv->cursor_needs_physical) {
2492 if (intel_crtc->cursor_bo != bo)
2493 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2494 } else
2495 i915_gem_object_unpin(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002496 drm_gem_object_unreference(intel_crtc->cursor_bo);
2497 }
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002498 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002499
2500 intel_crtc->cursor_addr = addr;
2501 intel_crtc->cursor_bo = bo;
2502
Jesse Barnes79e53942008-11-07 14:24:08 -08002503 return 0;
Dave Airlie34b8686e2009-01-15 14:03:07 +10002504fail:
2505 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002506fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10002507 drm_gem_object_unreference(bo);
2508 mutex_unlock(&dev->struct_mutex);
2509 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002510}
2511
2512static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2513{
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 int pipe = intel_crtc->pipe;
2518 uint32_t temp = 0;
2519 uint32_t adder;
2520
2521 if (x < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07002522 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002523 x = -x;
2524 }
2525 if (y < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07002526 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002527 y = -y;
2528 }
2529
Keith Packard2245fda2009-05-30 20:42:29 -07002530 temp |= x << CURSOR_X_SHIFT;
2531 temp |= y << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002532
2533 adder = intel_crtc->cursor_addr;
2534 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2535 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2536
2537 return 0;
2538}
2539
2540/** Sets the color ramps on behalf of RandR */
2541void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2542 u16 blue, int regno)
2543{
2544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545
2546 intel_crtc->lut_r[regno] = red >> 8;
2547 intel_crtc->lut_g[regno] = green >> 8;
2548 intel_crtc->lut_b[regno] = blue >> 8;
2549}
2550
2551static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2552 u16 *blue, uint32_t size)
2553{
2554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2555 int i;
2556
2557 if (size != 256)
2558 return;
2559
2560 for (i = 0; i < 256; i++) {
2561 intel_crtc->lut_r[i] = red[i] >> 8;
2562 intel_crtc->lut_g[i] = green[i] >> 8;
2563 intel_crtc->lut_b[i] = blue[i] >> 8;
2564 }
2565
2566 intel_crtc_load_lut(crtc);
2567}
2568
2569/**
2570 * Get a pipe with a simple mode set on it for doing load-based monitor
2571 * detection.
2572 *
2573 * It will be up to the load-detect code to adjust the pipe as appropriate for
2574 * its requirements. The pipe will be connected to no other outputs.
2575 *
2576 * Currently this code will only succeed if there is a pipe with no outputs
2577 * configured for it. In the future, it could choose to temporarily disable
2578 * some outputs to free up a pipe for its use.
2579 *
2580 * \return crtc, or NULL if no pipes are available.
2581 */
2582
2583/* VESA 640x480x72Hz mode to set on the pipe */
2584static struct drm_display_mode load_detect_mode = {
2585 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2586 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2587};
2588
2589struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2590 struct drm_display_mode *mode,
2591 int *dpms_mode)
2592{
2593 struct intel_crtc *intel_crtc;
2594 struct drm_crtc *possible_crtc;
2595 struct drm_crtc *supported_crtc =NULL;
2596 struct drm_encoder *encoder = &intel_output->enc;
2597 struct drm_crtc *crtc = NULL;
2598 struct drm_device *dev = encoder->dev;
2599 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2600 struct drm_crtc_helper_funcs *crtc_funcs;
2601 int i = -1;
2602
2603 /*
2604 * Algorithm gets a little messy:
2605 * - if the connector already has an assigned crtc, use it (but make
2606 * sure it's on first)
2607 * - try to find the first unused crtc that can drive this connector,
2608 * and use that if we find one
2609 * - if there are no unused crtcs available, try to use the first
2610 * one we found that supports the connector
2611 */
2612
2613 /* See if we already have a CRTC for this connector */
2614 if (encoder->crtc) {
2615 crtc = encoder->crtc;
2616 /* Make sure the crtc and connector are running */
2617 intel_crtc = to_intel_crtc(crtc);
2618 *dpms_mode = intel_crtc->dpms_mode;
2619 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2620 crtc_funcs = crtc->helper_private;
2621 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2622 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2623 }
2624 return crtc;
2625 }
2626
2627 /* Find an unused one (if possible) */
2628 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2629 i++;
2630 if (!(encoder->possible_crtcs & (1 << i)))
2631 continue;
2632 if (!possible_crtc->enabled) {
2633 crtc = possible_crtc;
2634 break;
2635 }
2636 if (!supported_crtc)
2637 supported_crtc = possible_crtc;
2638 }
2639
2640 /*
2641 * If we didn't find an unused CRTC, don't use any.
2642 */
2643 if (!crtc) {
2644 return NULL;
2645 }
2646
2647 encoder->crtc = crtc;
Keith Packard03d60692009-06-05 18:19:56 -07002648 intel_output->base.encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08002649 intel_output->load_detect_temp = true;
2650
2651 intel_crtc = to_intel_crtc(crtc);
2652 *dpms_mode = intel_crtc->dpms_mode;
2653
2654 if (!crtc->enabled) {
2655 if (!mode)
2656 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002657 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08002658 } else {
2659 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2660 crtc_funcs = crtc->helper_private;
2661 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2662 }
2663
2664 /* Add this connector to the crtc */
2665 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2666 encoder_funcs->commit(encoder);
2667 }
2668 /* let the connector get through one full cycle before testing */
2669 intel_wait_for_vblank(dev);
2670
2671 return crtc;
2672}
2673
2674void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2675{
2676 struct drm_encoder *encoder = &intel_output->enc;
2677 struct drm_device *dev = encoder->dev;
2678 struct drm_crtc *crtc = encoder->crtc;
2679 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2680 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2681
2682 if (intel_output->load_detect_temp) {
2683 encoder->crtc = NULL;
Keith Packard03d60692009-06-05 18:19:56 -07002684 intel_output->base.encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002685 intel_output->load_detect_temp = false;
2686 crtc->enabled = drm_helper_crtc_in_use(crtc);
2687 drm_helper_disable_unused_functions(dev);
2688 }
2689
2690 /* Switch crtc and output back off if necessary */
2691 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2692 if (encoder->crtc == crtc)
2693 encoder_funcs->dpms(encoder, dpms_mode);
2694 crtc_funcs->dpms(crtc, dpms_mode);
2695 }
2696}
2697
2698/* Returns the clock of the currently programmed mode of the given pipe. */
2699static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2700{
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 int pipe = intel_crtc->pipe;
2704 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2705 u32 fp;
2706 intel_clock_t clock;
2707
2708 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2709 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2710 else
2711 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2712
2713 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08002714 if (IS_IGD(dev)) {
2715 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2716 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2717 } else {
2718 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2719 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2720 }
2721
Jesse Barnes79e53942008-11-07 14:24:08 -08002722 if (IS_I9XX(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08002723 if (IS_IGD(dev))
2724 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2725 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2726 else
2727 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08002728 DPLL_FPA01_P1_POST_DIV_SHIFT);
2729
2730 switch (dpll & DPLL_MODE_MASK) {
2731 case DPLLB_MODE_DAC_SERIAL:
2732 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2733 5 : 10;
2734 break;
2735 case DPLLB_MODE_LVDS:
2736 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2737 7 : 14;
2738 break;
2739 default:
2740 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2741 "mode\n", (int)(dpll & DPLL_MODE_MASK));
2742 return 0;
2743 }
2744
2745 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08002746 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002747 } else {
2748 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2749
2750 if (is_lvds) {
2751 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2752 DPLL_FPA01_P1_POST_DIV_SHIFT);
2753 clock.p2 = 14;
2754
2755 if ((dpll & PLL_REF_INPUT_MASK) ==
2756 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2757 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08002758 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002759 } else
Shaohua Li21778322009-02-23 15:19:16 +08002760 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002761 } else {
2762 if (dpll & PLL_P1_DIVIDE_BY_TWO)
2763 clock.p1 = 2;
2764 else {
2765 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2766 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2767 }
2768 if (dpll & PLL_P2_DIVIDE_BY_4)
2769 clock.p2 = 4;
2770 else
2771 clock.p2 = 2;
2772
Shaohua Li21778322009-02-23 15:19:16 +08002773 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002774 }
2775 }
2776
2777 /* XXX: It would be nice to validate the clocks, but we can't reuse
2778 * i830PllIsValid() because it relies on the xf86_config connector
2779 * configuration being accurate, which it isn't necessarily.
2780 */
2781
2782 return clock.dot;
2783}
2784
2785/** Returns the currently programmed mode of the given pipe. */
2786struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2787 struct drm_crtc *crtc)
2788{
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2791 int pipe = intel_crtc->pipe;
2792 struct drm_display_mode *mode;
2793 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2794 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2795 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2796 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2797
2798 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2799 if (!mode)
2800 return NULL;
2801
2802 mode->clock = intel_crtc_clock_get(dev, crtc);
2803 mode->hdisplay = (htot & 0xffff) + 1;
2804 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2805 mode->hsync_start = (hsync & 0xffff) + 1;
2806 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2807 mode->vdisplay = (vtot & 0xffff) + 1;
2808 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2809 mode->vsync_start = (vsync & 0xffff) + 1;
2810 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2811
2812 drm_mode_set_name(mode);
2813 drm_mode_set_crtcinfo(mode, 0);
2814
2815 return mode;
2816}
2817
2818static void intel_crtc_destroy(struct drm_crtc *crtc)
2819{
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821
Dave Airlie7ff14552009-04-22 18:52:14 +10002822 if (intel_crtc->mode_set.mode)
2823 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002824 drm_crtc_cleanup(crtc);
2825 kfree(intel_crtc);
2826}
2827
2828static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2829 .dpms = intel_crtc_dpms,
2830 .mode_fixup = intel_crtc_mode_fixup,
2831 .mode_set = intel_crtc_mode_set,
2832 .mode_set_base = intel_pipe_set_base,
2833 .prepare = intel_crtc_prepare,
2834 .commit = intel_crtc_commit,
2835};
2836
2837static const struct drm_crtc_funcs intel_crtc_funcs = {
2838 .cursor_set = intel_crtc_cursor_set,
2839 .cursor_move = intel_crtc_cursor_move,
2840 .gamma_set = intel_crtc_gamma_set,
2841 .set_config = drm_crtc_helper_set_config,
2842 .destroy = intel_crtc_destroy,
2843};
2844
2845
Hannes Ederb358d0a2008-12-18 21:18:47 +01002846static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08002847{
2848 struct intel_crtc *intel_crtc;
2849 int i;
2850
2851 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2852 if (intel_crtc == NULL)
2853 return;
2854
2855 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2856
2857 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2858 intel_crtc->pipe = pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002859 intel_crtc->plane = pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08002860 for (i = 0; i < 256; i++) {
2861 intel_crtc->lut_r[i] = i;
2862 intel_crtc->lut_g[i] = i;
2863 intel_crtc->lut_b[i] = i;
2864 }
2865
2866 intel_crtc->cursor_addr = 0;
2867 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2868 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2869
2870 intel_crtc->mode_set.crtc = &intel_crtc->base;
2871 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2872 intel_crtc->mode_set.num_connectors = 0;
2873
2874 if (i915_fbpercrtc) {
2875
2876
2877
2878 }
2879}
2880
Carl Worth08d7b3d2009-04-29 14:43:54 -07002881int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv)
2883{
2884 drm_i915_private_t *dev_priv = dev->dev_private;
2885 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2886 struct drm_crtc *crtc = NULL;
2887 int pipe = -1;
2888
2889 if (!dev_priv) {
2890 DRM_ERROR("called with no initialization\n");
2891 return -EINVAL;
2892 }
2893
2894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2896 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2897 pipe = intel_crtc->pipe;
2898 break;
2899 }
2900 }
2901
2902 if (pipe == -1) {
2903 DRM_ERROR("no such CRTC id\n");
2904 return -EINVAL;
2905 }
2906
2907 pipe_from_crtc_id->pipe = pipe;
2908
2909 return 0;
2910}
2911
Jesse Barnes79e53942008-11-07 14:24:08 -08002912struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2913{
2914 struct drm_crtc *crtc = NULL;
2915
2916 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918 if (intel_crtc->pipe == pipe)
2919 break;
2920 }
2921 return crtc;
2922}
2923
Hannes Ederb358d0a2008-12-18 21:18:47 +01002924static int intel_connector_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08002925{
2926 int index_mask = 0;
2927 struct drm_connector *connector;
2928 int entry = 0;
2929
2930 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2931 struct intel_output *intel_output = to_intel_output(connector);
2932 if (type_mask & (1 << intel_output->type))
2933 index_mask |= (1 << entry);
2934 entry++;
2935 }
2936 return index_mask;
2937}
2938
2939
2940static void intel_setup_outputs(struct drm_device *dev)
2941{
Eric Anholt725e30a2009-01-22 13:01:02 -08002942 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002943 struct drm_connector *connector;
2944
2945 intel_crt_init(dev);
2946
2947 /* Set up integrated LVDS */
Zhenyu Wang541998a2009-06-05 15:38:44 +08002948 if (IS_MOBILE(dev) && !IS_I830(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002949 intel_lvds_init(dev);
2950
Zhenyu Wang2c072452009-06-05 15:38:42 +08002951 if (IS_IGDNG(dev)) {
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08002952 int found;
2953
2954 if (I915_READ(HDMIB) & PORT_DETECTED) {
2955 /* check SDVOB */
2956 /* found = intel_sdvo_init(dev, HDMIB); */
2957 found = 0;
2958 if (!found)
2959 intel_hdmi_init(dev, HDMIB);
2960 }
2961
2962 if (I915_READ(HDMIC) & PORT_DETECTED)
2963 intel_hdmi_init(dev, HDMIC);
2964
2965 if (I915_READ(HDMID) & PORT_DETECTED)
2966 intel_hdmi_init(dev, HDMID);
2967
Zhenyu Wang2c072452009-06-05 15:38:42 +08002968 } else if (IS_I9XX(dev)) {
Eric Anholt7d573822009-01-02 13:33:00 -08002969 int found;
Kristian Høgsberg13520b02009-03-13 15:42:14 -04002970 u32 reg;
Eric Anholt7d573822009-01-02 13:33:00 -08002971
Eric Anholt725e30a2009-01-22 13:01:02 -08002972 if (I915_READ(SDVOB) & SDVO_DETECTED) {
2973 found = intel_sdvo_init(dev, SDVOB);
2974 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2975 intel_hdmi_init(dev, SDVOB);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002976 if (!found && SUPPORTS_INTEGRATED_DP(dev))
2977 intel_dp_init(dev, DP_B);
Eric Anholt725e30a2009-01-22 13:01:02 -08002978 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04002979
2980 /* Before G4X SDVOC doesn't have its own detect register */
2981 if (IS_G4X(dev))
2982 reg = SDVOC;
2983 else
2984 reg = SDVOB;
2985
2986 if (I915_READ(reg) & SDVO_DETECTED) {
Eric Anholt725e30a2009-01-22 13:01:02 -08002987 found = intel_sdvo_init(dev, SDVOC);
2988 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2989 intel_hdmi_init(dev, SDVOC);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002990 if (!found && SUPPORTS_INTEGRATED_DP(dev))
2991 intel_dp_init(dev, DP_C);
Eric Anholt725e30a2009-01-22 13:01:02 -08002992 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002993 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
2994 intel_dp_init(dev, DP_D);
Jesse Barnes79e53942008-11-07 14:24:08 -08002995 } else
2996 intel_dvo_init(dev);
2997
Zhenyu Wang2c072452009-06-05 15:38:42 +08002998 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002999 intel_tv_init(dev);
3000
3001 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3002 struct intel_output *intel_output = to_intel_output(connector);
3003 struct drm_encoder *encoder = &intel_output->enc;
3004 int crtc_mask = 0, clone_mask = 0;
3005
3006 /* valid crtcs */
3007 switch(intel_output->type) {
Eric Anholt7d573822009-01-02 13:33:00 -08003008 case INTEL_OUTPUT_HDMI:
3009 crtc_mask = ((1 << 0)|
3010 (1 << 1));
3011 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3012 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003013 case INTEL_OUTPUT_DVO:
3014 case INTEL_OUTPUT_SDVO:
3015 crtc_mask = ((1 << 0)|
3016 (1 << 1));
3017 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3018 (1 << INTEL_OUTPUT_DVO) |
3019 (1 << INTEL_OUTPUT_SDVO));
3020 break;
3021 case INTEL_OUTPUT_ANALOG:
3022 crtc_mask = ((1 << 0)|
3023 (1 << 1));
3024 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3025 (1 << INTEL_OUTPUT_DVO) |
3026 (1 << INTEL_OUTPUT_SDVO));
3027 break;
3028 case INTEL_OUTPUT_LVDS:
3029 crtc_mask = (1 << 1);
3030 clone_mask = (1 << INTEL_OUTPUT_LVDS);
3031 break;
3032 case INTEL_OUTPUT_TVOUT:
3033 crtc_mask = ((1 << 0) |
3034 (1 << 1));
3035 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3036 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003037 case INTEL_OUTPUT_DISPLAYPORT:
3038 crtc_mask = ((1 << 0) |
3039 (1 << 1));
3040 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3041 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003042 }
3043 encoder->possible_crtcs = crtc_mask;
3044 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3045 }
3046}
3047
3048static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3049{
3050 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3051 struct drm_device *dev = fb->dev;
3052
3053 if (fb->fbdev)
3054 intelfb_remove(dev, fb);
3055
3056 drm_framebuffer_cleanup(fb);
3057 mutex_lock(&dev->struct_mutex);
3058 drm_gem_object_unreference(intel_fb->obj);
3059 mutex_unlock(&dev->struct_mutex);
3060
3061 kfree(intel_fb);
3062}
3063
3064static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3065 struct drm_file *file_priv,
3066 unsigned int *handle)
3067{
3068 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3069 struct drm_gem_object *object = intel_fb->obj;
3070
3071 return drm_gem_handle_create(file_priv, object, handle);
3072}
3073
3074static const struct drm_framebuffer_funcs intel_fb_funcs = {
3075 .destroy = intel_user_framebuffer_destroy,
3076 .create_handle = intel_user_framebuffer_create_handle,
3077};
3078
3079int intel_framebuffer_create(struct drm_device *dev,
3080 struct drm_mode_fb_cmd *mode_cmd,
3081 struct drm_framebuffer **fb,
3082 struct drm_gem_object *obj)
3083{
3084 struct intel_framebuffer *intel_fb;
3085 int ret;
3086
3087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3088 if (!intel_fb)
3089 return -ENOMEM;
3090
3091 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3092 if (ret) {
3093 DRM_ERROR("framebuffer init failed %d\n", ret);
3094 return ret;
3095 }
3096
3097 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3098
3099 intel_fb->obj = obj;
3100
3101 *fb = &intel_fb->base;
3102
3103 return 0;
3104}
3105
3106
3107static struct drm_framebuffer *
3108intel_user_framebuffer_create(struct drm_device *dev,
3109 struct drm_file *filp,
3110 struct drm_mode_fb_cmd *mode_cmd)
3111{
3112 struct drm_gem_object *obj;
3113 struct drm_framebuffer *fb;
3114 int ret;
3115
3116 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3117 if (!obj)
3118 return NULL;
3119
3120 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3121 if (ret) {
Jesse Barnes496818f2009-02-11 13:28:14 -08003122 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08003123 drm_gem_object_unreference(obj);
Jesse Barnes496818f2009-02-11 13:28:14 -08003124 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08003125 return NULL;
3126 }
3127
3128 return fb;
3129}
3130
Jesse Barnes79e53942008-11-07 14:24:08 -08003131static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08003132 .fb_create = intel_user_framebuffer_create,
3133 .fb_changed = intelfb_probe,
3134};
3135
3136void intel_modeset_init(struct drm_device *dev)
3137{
3138 int num_pipe;
3139 int i;
3140
3141 drm_mode_config_init(dev);
3142
3143 dev->mode_config.min_width = 0;
3144 dev->mode_config.min_height = 0;
3145
3146 dev->mode_config.funcs = (void *)&intel_mode_funcs;
3147
3148 if (IS_I965G(dev)) {
3149 dev->mode_config.max_width = 8192;
3150 dev->mode_config.max_height = 8192;
3151 } else {
3152 dev->mode_config.max_width = 2048;
3153 dev->mode_config.max_height = 2048;
3154 }
3155
3156 /* set memory base */
3157 if (IS_I9XX(dev))
3158 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3159 else
3160 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3161
3162 if (IS_MOBILE(dev) || IS_I9XX(dev))
3163 num_pipe = 2;
3164 else
3165 num_pipe = 1;
3166 DRM_DEBUG("%d display pipe%s available.\n",
3167 num_pipe, num_pipe > 1 ? "s" : "");
3168
3169 for (i = 0; i < num_pipe; i++) {
3170 intel_crtc_init(dev, i);
3171 }
3172
3173 intel_setup_outputs(dev);
3174}
3175
3176void intel_modeset_cleanup(struct drm_device *dev)
3177{
3178 drm_mode_config_cleanup(dev);
3179}
3180
3181
3182/* current intel driver doesn't take advantage of encoders
3183 always give back the encoder for the connector
3184*/
3185struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3186{
3187 struct intel_output *intel_output = to_intel_output(connector);
3188
3189 return &intel_output->enc;
3190}