Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 2 | * Copyright © 2008-2015 Intel Corporation |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Yu Zhang | eb82289 | 2015-02-10 19:05:49 +0800 | [diff] [blame] | 32 | #include "i915_vgpu.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 33 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 34 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 35 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 36 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 39 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 40 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 41 | #define RQ_BUG_ON(expr) |
| 42 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 45 | static void |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 46 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
| 47 | static void |
| 48 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 49 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 50 | struct drm_i915_gem_object *obj); |
| 51 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 52 | struct drm_i915_fence_reg *fence, |
| 53 | bool enable); |
| 54 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 55 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 56 | enum i915_cache_level level) |
| 57 | { |
| 58 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 59 | } |
| 60 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 61 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 62 | { |
| 63 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 64 | return true; |
| 65 | |
| 66 | return obj->pin_display; |
| 67 | } |
| 68 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 69 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 70 | { |
| 71 | if (obj->tiling_mode) |
| 72 | i915_gem_release_mmap(obj); |
| 73 | |
| 74 | /* As we do not have an associated fence register, we will force |
| 75 | * a tiling change if we ever need to acquire one. |
| 76 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 77 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 78 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 79 | } |
| 80 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 81 | /* some bookkeeping */ |
| 82 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 83 | size_t size) |
| 84 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 85 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 86 | dev_priv->mm.object_count++; |
| 87 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 88 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 92 | size_t size) |
| 93 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 94 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 95 | dev_priv->mm.object_count--; |
| 96 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 97 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 98 | } |
| 99 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 100 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 101 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 102 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 103 | int ret; |
| 104 | |
Daniel Vetter | 7abb690 | 2013-05-24 21:29:32 +0200 | [diff] [blame] | 105 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 106 | i915_terminally_wedged(error)) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 107 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 108 | return 0; |
| 109 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 110 | /* |
| 111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 112 | * userspace. If it takes that long something really bad is going on and |
| 113 | * we should simply try to bail out and fail as gracefully as possible. |
| 114 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 116 | EXIT_COND, |
| 117 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 118 | if (ret == 0) { |
| 119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 120 | return -EIO; |
| 121 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 122 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 123 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 124 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 125 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 126 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 127 | } |
| 128 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 129 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 130 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 131 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 132 | int ret; |
| 133 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 134 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 135 | if (ret) |
| 136 | return ret; |
| 137 | |
| 138 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 139 | if (ret) |
| 140 | return ret; |
| 141 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 142 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 143 | return 0; |
| 144 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 145 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 146 | int |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 148 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 149 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 150 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 151 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 152 | struct drm_i915_gem_object *obj; |
| 153 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 154 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 155 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 156 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 157 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 158 | if (i915_gem_obj_is_pinned(obj)) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 159 | pinned += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 160 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 161 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 162 | args->aper_size = dev_priv->gtt.base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 163 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 164 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 165 | return 0; |
| 166 | } |
| 167 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 168 | static int |
| 169 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 170 | { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 171 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 172 | char *vaddr = obj->phys_handle->vaddr; |
| 173 | struct sg_table *st; |
| 174 | struct scatterlist *sg; |
| 175 | int i; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 176 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 177 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
| 178 | return -EINVAL; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 179 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 180 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 181 | struct page *page; |
| 182 | char *src; |
| 183 | |
| 184 | page = shmem_read_mapping_page(mapping, i); |
| 185 | if (IS_ERR(page)) |
| 186 | return PTR_ERR(page); |
| 187 | |
| 188 | src = kmap_atomic(page); |
| 189 | memcpy(vaddr, src, PAGE_SIZE); |
| 190 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 191 | kunmap_atomic(src); |
| 192 | |
| 193 | page_cache_release(page); |
| 194 | vaddr += PAGE_SIZE; |
| 195 | } |
| 196 | |
| 197 | i915_gem_chipset_flush(obj->base.dev); |
| 198 | |
| 199 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 200 | if (st == NULL) |
| 201 | return -ENOMEM; |
| 202 | |
| 203 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { |
| 204 | kfree(st); |
| 205 | return -ENOMEM; |
| 206 | } |
| 207 | |
| 208 | sg = st->sgl; |
| 209 | sg->offset = 0; |
| 210 | sg->length = obj->base.size; |
| 211 | |
| 212 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
| 213 | sg_dma_len(sg) = obj->base.size; |
| 214 | |
| 215 | obj->pages = st; |
| 216 | obj->has_dma_mapping = true; |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static void |
| 221 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) |
| 222 | { |
| 223 | int ret; |
| 224 | |
| 225 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 226 | |
| 227 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 228 | if (ret) { |
| 229 | /* In the event of a disaster, abandon all caches and |
| 230 | * hope for the best. |
| 231 | */ |
| 232 | WARN_ON(ret != -EIO); |
| 233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 234 | } |
| 235 | |
| 236 | if (obj->madv == I915_MADV_DONTNEED) |
| 237 | obj->dirty = 0; |
| 238 | |
| 239 | if (obj->dirty) { |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 240 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 241 | char *vaddr = obj->phys_handle->vaddr; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 242 | int i; |
| 243 | |
| 244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 245 | struct page *page; |
| 246 | char *dst; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 247 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 248 | page = shmem_read_mapping_page(mapping, i); |
| 249 | if (IS_ERR(page)) |
| 250 | continue; |
| 251 | |
| 252 | dst = kmap_atomic(page); |
| 253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 254 | memcpy(dst, vaddr, PAGE_SIZE); |
| 255 | kunmap_atomic(dst); |
| 256 | |
| 257 | set_page_dirty(page); |
| 258 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 259 | mark_page_accessed(page); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 260 | page_cache_release(page); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 261 | vaddr += PAGE_SIZE; |
| 262 | } |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 263 | obj->dirty = 0; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 264 | } |
| 265 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 266 | sg_free_table(obj->pages); |
| 267 | kfree(obj->pages); |
| 268 | |
| 269 | obj->has_dma_mapping = false; |
| 270 | } |
| 271 | |
| 272 | static void |
| 273 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) |
| 274 | { |
| 275 | drm_pci_free(obj->base.dev, obj->phys_handle); |
| 276 | } |
| 277 | |
| 278 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { |
| 279 | .get_pages = i915_gem_object_get_pages_phys, |
| 280 | .put_pages = i915_gem_object_put_pages_phys, |
| 281 | .release = i915_gem_object_release_phys, |
| 282 | }; |
| 283 | |
| 284 | static int |
| 285 | drop_pages(struct drm_i915_gem_object *obj) |
| 286 | { |
| 287 | struct i915_vma *vma, *next; |
| 288 | int ret; |
| 289 | |
| 290 | drm_gem_object_reference(&obj->base); |
| 291 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) |
| 292 | if (i915_vma_unbind(vma)) |
| 293 | break; |
| 294 | |
| 295 | ret = i915_gem_object_put_pages(obj); |
| 296 | drm_gem_object_unreference(&obj->base); |
| 297 | |
| 298 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | int |
| 302 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 303 | int align) |
| 304 | { |
| 305 | drm_dma_handle_t *phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 306 | int ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 307 | |
| 308 | if (obj->phys_handle) { |
| 309 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 310 | return -EBUSY; |
| 311 | |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | if (obj->madv != I915_MADV_WILLNEED) |
| 316 | return -EFAULT; |
| 317 | |
| 318 | if (obj->base.filp == NULL) |
| 319 | return -EINVAL; |
| 320 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 321 | ret = drop_pages(obj); |
| 322 | if (ret) |
| 323 | return ret; |
| 324 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 325 | /* create a new object */ |
| 326 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 327 | if (!phys) |
| 328 | return -ENOMEM; |
| 329 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 330 | obj->phys_handle = phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 331 | obj->ops = &i915_gem_phys_ops; |
| 332 | |
| 333 | return i915_gem_object_get_pages(obj); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static int |
| 337 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 338 | struct drm_i915_gem_pwrite *args, |
| 339 | struct drm_file *file_priv) |
| 340 | { |
| 341 | struct drm_device *dev = obj->base.dev; |
| 342 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 343 | char __user *user_data = to_user_ptr(args->data_ptr); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 344 | int ret = 0; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 345 | |
| 346 | /* We manually control the domain here and pretend that it |
| 347 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. |
| 348 | */ |
| 349 | ret = i915_gem_object_wait_rendering(obj, false); |
| 350 | if (ret) |
| 351 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 352 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 353 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 354 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 355 | unsigned long unwritten; |
| 356 | |
| 357 | /* The physical object once assigned is fixed for the lifetime |
| 358 | * of the obj, so we can safely drop the lock and continue |
| 359 | * to access vaddr. |
| 360 | */ |
| 361 | mutex_unlock(&dev->struct_mutex); |
| 362 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 363 | mutex_lock(&dev->struct_mutex); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 364 | if (unwritten) { |
| 365 | ret = -EFAULT; |
| 366 | goto out; |
| 367 | } |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 368 | } |
| 369 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 370 | drm_clflush_virt_range(vaddr, args->size); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 371 | i915_gem_chipset_flush(dev); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 372 | |
| 373 | out: |
| 374 | intel_fb_obj_flush(obj, false); |
| 375 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 376 | } |
| 377 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 378 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 379 | { |
| 380 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 381 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 385 | { |
| 386 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 387 | kmem_cache_free(dev_priv->objects, obj); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 388 | } |
| 389 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 390 | static int |
| 391 | i915_gem_create(struct drm_file *file, |
| 392 | struct drm_device *dev, |
| 393 | uint64_t size, |
| 394 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 395 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 396 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 397 | int ret; |
| 398 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 399 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 400 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 401 | if (size == 0) |
| 402 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 403 | |
| 404 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 405 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 406 | if (obj == NULL) |
| 407 | return -ENOMEM; |
| 408 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 409 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 410 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 411 | drm_gem_object_unreference_unlocked(&obj->base); |
| 412 | if (ret) |
| 413 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 414 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 415 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 416 | return 0; |
| 417 | } |
| 418 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 419 | int |
| 420 | i915_gem_dumb_create(struct drm_file *file, |
| 421 | struct drm_device *dev, |
| 422 | struct drm_mode_create_dumb *args) |
| 423 | { |
| 424 | /* have to work out size/pitch and return them */ |
Paulo Zanoni | de45eaf | 2013-10-18 18:48:24 -0300 | [diff] [blame] | 425 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 426 | args->size = args->pitch * args->height; |
| 427 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 428 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 429 | } |
| 430 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 431 | /** |
| 432 | * Creates a new mm object and returns a handle to it. |
| 433 | */ |
| 434 | int |
| 435 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 436 | struct drm_file *file) |
| 437 | { |
| 438 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 439 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 440 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 441 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 442 | } |
| 443 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 444 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 445 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 446 | const char *gpu_vaddr, int gpu_offset, |
| 447 | int length) |
| 448 | { |
| 449 | int ret, cpu_offset = 0; |
| 450 | |
| 451 | while (length > 0) { |
| 452 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 453 | int this_length = min(cacheline_end - gpu_offset, length); |
| 454 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 455 | |
| 456 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 457 | gpu_vaddr + swizzled_gpu_offset, |
| 458 | this_length); |
| 459 | if (ret) |
| 460 | return ret + length; |
| 461 | |
| 462 | cpu_offset += this_length; |
| 463 | gpu_offset += this_length; |
| 464 | length -= this_length; |
| 465 | } |
| 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 471 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 472 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 473 | int length) |
| 474 | { |
| 475 | int ret, cpu_offset = 0; |
| 476 | |
| 477 | while (length > 0) { |
| 478 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 479 | int this_length = min(cacheline_end - gpu_offset, length); |
| 480 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 481 | |
| 482 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 483 | cpu_vaddr + cpu_offset, |
| 484 | this_length); |
| 485 | if (ret) |
| 486 | return ret + length; |
| 487 | |
| 488 | cpu_offset += this_length; |
| 489 | gpu_offset += this_length; |
| 490 | length -= this_length; |
| 491 | } |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 496 | /* |
| 497 | * Pins the specified object's pages and synchronizes the object with |
| 498 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 499 | * flush the object from the CPU cache. |
| 500 | */ |
| 501 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 502 | int *needs_clflush) |
| 503 | { |
| 504 | int ret; |
| 505 | |
| 506 | *needs_clflush = 0; |
| 507 | |
| 508 | if (!obj->base.filp) |
| 509 | return -EINVAL; |
| 510 | |
| 511 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 512 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 513 | * read domain and manually flush cachelines (if required). This |
| 514 | * optimizes for the case when the gpu will dirty the data |
| 515 | * anyway again before the next pread happens. */ |
| 516 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 517 | obj->cache_level); |
| 518 | ret = i915_gem_object_wait_rendering(obj, true); |
| 519 | if (ret) |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | ret = i915_gem_object_get_pages(obj); |
| 524 | if (ret) |
| 525 | return ret; |
| 526 | |
| 527 | i915_gem_object_pin_pages(obj); |
| 528 | |
| 529 | return ret; |
| 530 | } |
| 531 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 532 | /* Per-page copy function for the shmem pread fastpath. |
| 533 | * Flushes invalid cachelines before reading the target if |
| 534 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 535 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 536 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 537 | char __user *user_data, |
| 538 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 539 | { |
| 540 | char *vaddr; |
| 541 | int ret; |
| 542 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 543 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 544 | return -EINVAL; |
| 545 | |
| 546 | vaddr = kmap_atomic(page); |
| 547 | if (needs_clflush) |
| 548 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 549 | page_length); |
| 550 | ret = __copy_to_user_inatomic(user_data, |
| 551 | vaddr + shmem_page_offset, |
| 552 | page_length); |
| 553 | kunmap_atomic(vaddr); |
| 554 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 555 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 556 | } |
| 557 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 558 | static void |
| 559 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 560 | bool swizzled) |
| 561 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 562 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 563 | unsigned long start = (unsigned long) addr; |
| 564 | unsigned long end = (unsigned long) addr + length; |
| 565 | |
| 566 | /* For swizzling simply ensure that we always flush both |
| 567 | * channels. Lame, but simple and it works. Swizzled |
| 568 | * pwrite/pread is far from a hotpath - current userspace |
| 569 | * doesn't use it at all. */ |
| 570 | start = round_down(start, 128); |
| 571 | end = round_up(end, 128); |
| 572 | |
| 573 | drm_clflush_virt_range((void *)start, end - start); |
| 574 | } else { |
| 575 | drm_clflush_virt_range(addr, length); |
| 576 | } |
| 577 | |
| 578 | } |
| 579 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 580 | /* Only difference to the fast-path function is that this can handle bit17 |
| 581 | * and uses non-atomic copy and kmap functions. */ |
| 582 | static int |
| 583 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 584 | char __user *user_data, |
| 585 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 586 | { |
| 587 | char *vaddr; |
| 588 | int ret; |
| 589 | |
| 590 | vaddr = kmap(page); |
| 591 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 592 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 593 | page_length, |
| 594 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 595 | |
| 596 | if (page_do_bit17_swizzling) |
| 597 | ret = __copy_to_user_swizzled(user_data, |
| 598 | vaddr, shmem_page_offset, |
| 599 | page_length); |
| 600 | else |
| 601 | ret = __copy_to_user(user_data, |
| 602 | vaddr + shmem_page_offset, |
| 603 | page_length); |
| 604 | kunmap(page); |
| 605 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 606 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 607 | } |
| 608 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 609 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 610 | i915_gem_shmem_pread(struct drm_device *dev, |
| 611 | struct drm_i915_gem_object *obj, |
| 612 | struct drm_i915_gem_pread *args, |
| 613 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 614 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 615 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 616 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 617 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 618 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 619 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 620 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 621 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 622 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 623 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 624 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 625 | remain = args->size; |
| 626 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 627 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 628 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 629 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 630 | if (ret) |
| 631 | return ret; |
| 632 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 633 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 634 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 635 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 636 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 637 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 638 | |
| 639 | if (remain <= 0) |
| 640 | break; |
| 641 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 642 | /* Operation in this page |
| 643 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 644 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 645 | * page_length = bytes to copy for this page |
| 646 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 647 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 648 | page_length = remain; |
| 649 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 650 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 651 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 652 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 653 | (page_to_phys(page) & (1 << 17)) != 0; |
| 654 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 655 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 656 | user_data, page_do_bit17_swizzling, |
| 657 | needs_clflush); |
| 658 | if (ret == 0) |
| 659 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 660 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 661 | mutex_unlock(&dev->struct_mutex); |
| 662 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 663 | if (likely(!i915.prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 664 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 665 | /* Userspace is tricking us, but we've already clobbered |
| 666 | * its pages with the prefault and promised to write the |
| 667 | * data up to the first fault. Hence ignore any errors |
| 668 | * and just continue. */ |
| 669 | (void)ret; |
| 670 | prefaulted = 1; |
| 671 | } |
| 672 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 673 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 674 | user_data, page_do_bit17_swizzling, |
| 675 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 676 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 677 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 678 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 679 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 680 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 681 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 682 | next_page: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 683 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 684 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 685 | offset += page_length; |
| 686 | } |
| 687 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 688 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 689 | i915_gem_object_unpin_pages(obj); |
| 690 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 691 | return ret; |
| 692 | } |
| 693 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 694 | /** |
| 695 | * Reads data from the object referenced by handle. |
| 696 | * |
| 697 | * On error, the contents of *data are undefined. |
| 698 | */ |
| 699 | int |
| 700 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 701 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 702 | { |
| 703 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 704 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 705 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 706 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 707 | if (args->size == 0) |
| 708 | return 0; |
| 709 | |
| 710 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 711 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 712 | args->size)) |
| 713 | return -EFAULT; |
| 714 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 715 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 716 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 717 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 718 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 719 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 720 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 721 | ret = -ENOENT; |
| 722 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 723 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 724 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 725 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 726 | if (args->offset > obj->base.size || |
| 727 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 728 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 729 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 730 | } |
| 731 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 732 | /* prime objects have no backing filp to GEM pread/pwrite |
| 733 | * pages from. |
| 734 | */ |
| 735 | if (!obj->base.filp) { |
| 736 | ret = -EINVAL; |
| 737 | goto out; |
| 738 | } |
| 739 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 740 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 741 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 742 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 743 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 744 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 745 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 746 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 747 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 748 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 749 | } |
| 750 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 751 | /* This is the fast write path which cannot handle |
| 752 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 753 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 754 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 755 | static inline int |
| 756 | fast_user_write(struct io_mapping *mapping, |
| 757 | loff_t page_base, int page_offset, |
| 758 | char __user *user_data, |
| 759 | int length) |
| 760 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 761 | void __iomem *vaddr_atomic; |
| 762 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 763 | unsigned long unwritten; |
| 764 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 765 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 766 | /* We can use the cpu mem copy function because this is X86. */ |
| 767 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 768 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 769 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 770 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 771 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 772 | } |
| 773 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 774 | /** |
| 775 | * This is the fast pwrite path, where we copy the data directly from the |
| 776 | * user into the GTT, uncached. |
| 777 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 778 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 779 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 780 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 781 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 782 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 783 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 784 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 785 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 786 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 787 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 788 | int page_offset, page_length, ret; |
| 789 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 790 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 791 | if (ret) |
| 792 | goto out; |
| 793 | |
| 794 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 795 | if (ret) |
| 796 | goto out_unpin; |
| 797 | |
| 798 | ret = i915_gem_object_put_fence(obj); |
| 799 | if (ret) |
| 800 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 801 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 802 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 803 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 804 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 805 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 806 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 807 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 808 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 809 | while (remain > 0) { |
| 810 | /* Operation in this page |
| 811 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 812 | * page_base = page offset within aperture |
| 813 | * page_offset = offset within page |
| 814 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 815 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 816 | page_base = offset & PAGE_MASK; |
| 817 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 818 | page_length = remain; |
| 819 | if ((page_offset + remain) > PAGE_SIZE) |
| 820 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 821 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 822 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 823 | * source page isn't available. Return the error and we'll |
| 824 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 825 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 826 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 827 | page_offset, user_data, page_length)) { |
| 828 | ret = -EFAULT; |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 829 | goto out_flush; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 830 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 831 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 832 | remain -= page_length; |
| 833 | user_data += page_length; |
| 834 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 835 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 836 | |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 837 | out_flush: |
| 838 | intel_fb_obj_flush(obj, false); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 839 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 840 | i915_gem_object_ggtt_unpin(obj); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 841 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 842 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 843 | } |
| 844 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 845 | /* Per-page copy function for the shmem pwrite fastpath. |
| 846 | * Flushes invalid cachelines before writing to the target if |
| 847 | * needs_clflush_before is set and flushes out any written cachelines after |
| 848 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 849 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 850 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 851 | char __user *user_data, |
| 852 | bool page_do_bit17_swizzling, |
| 853 | bool needs_clflush_before, |
| 854 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 855 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 856 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 857 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 858 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 859 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 860 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 861 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 862 | vaddr = kmap_atomic(page); |
| 863 | if (needs_clflush_before) |
| 864 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 865 | page_length); |
Chris Wilson | c2831a9 | 2014-03-07 08:30:37 +0000 | [diff] [blame] | 866 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 867 | user_data, page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 868 | if (needs_clflush_after) |
| 869 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 870 | page_length); |
| 871 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 872 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 873 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 874 | } |
| 875 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 876 | /* Only difference to the fast-path function is that this can handle bit17 |
| 877 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 878 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 879 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 880 | char __user *user_data, |
| 881 | bool page_do_bit17_swizzling, |
| 882 | bool needs_clflush_before, |
| 883 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 884 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 885 | char *vaddr; |
| 886 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 887 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 888 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 889 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 890 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 891 | page_length, |
| 892 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 893 | if (page_do_bit17_swizzling) |
| 894 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 895 | user_data, |
| 896 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 897 | else |
| 898 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 899 | user_data, |
| 900 | page_length); |
| 901 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 902 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 903 | page_length, |
| 904 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 905 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 906 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 907 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 908 | } |
| 909 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 910 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 911 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 912 | struct drm_i915_gem_object *obj, |
| 913 | struct drm_i915_gem_pwrite *args, |
| 914 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 915 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 916 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 917 | loff_t offset; |
| 918 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 919 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 920 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 921 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 922 | int needs_clflush_after = 0; |
| 923 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 924 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 925 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 926 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 927 | remain = args->size; |
| 928 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 929 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 930 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 931 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 932 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 933 | * write domain and manually flush cachelines (if required). This |
| 934 | * optimizes for the case when the gpu will use the data |
| 935 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 936 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 937 | ret = i915_gem_object_wait_rendering(obj, false); |
| 938 | if (ret) |
| 939 | return ret; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 940 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 941 | /* Same trick applies to invalidate partially written cachelines read |
| 942 | * before writing. */ |
| 943 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 944 | needs_clflush_before = |
| 945 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 946 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 947 | ret = i915_gem_object_get_pages(obj); |
| 948 | if (ret) |
| 949 | return ret; |
| 950 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 951 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 952 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 953 | i915_gem_object_pin_pages(obj); |
| 954 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 955 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 956 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 957 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 958 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 959 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 960 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 961 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 962 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 963 | if (remain <= 0) |
| 964 | break; |
| 965 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 966 | /* Operation in this page |
| 967 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 968 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 969 | * page_length = bytes to copy for this page |
| 970 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 971 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 972 | |
| 973 | page_length = remain; |
| 974 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 975 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 976 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 977 | /* If we don't overwrite a cacheline completely we need to be |
| 978 | * careful to have up-to-date data by first clflushing. Don't |
| 979 | * overcomplicate things and flush the entire patch. */ |
| 980 | partial_cacheline_write = needs_clflush_before && |
| 981 | ((shmem_page_offset | page_length) |
| 982 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 983 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 984 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 985 | (page_to_phys(page) & (1 << 17)) != 0; |
| 986 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 987 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 988 | user_data, page_do_bit17_swizzling, |
| 989 | partial_cacheline_write, |
| 990 | needs_clflush_after); |
| 991 | if (ret == 0) |
| 992 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 993 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 994 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 995 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 996 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 997 | user_data, page_do_bit17_swizzling, |
| 998 | partial_cacheline_write, |
| 999 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1000 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1001 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1002 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1003 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1004 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1005 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 1006 | next_page: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1007 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1008 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1009 | offset += page_length; |
| 1010 | } |
| 1011 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1012 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1013 | i915_gem_object_unpin_pages(obj); |
| 1014 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1015 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 1016 | /* |
| 1017 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 1018 | * cachelines in-line while writing and the object moved |
| 1019 | * out of the cpu write domain while we've dropped the lock. |
| 1020 | */ |
| 1021 | if (!needs_clflush_after && |
| 1022 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 1023 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 1024 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1025 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1026 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1027 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1028 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1029 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1030 | |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 1031 | intel_fb_obj_flush(obj, false); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1032 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1033 | } |
| 1034 | |
| 1035 | /** |
| 1036 | * Writes data to the object referenced by handle. |
| 1037 | * |
| 1038 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1039 | */ |
| 1040 | int |
| 1041 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1042 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1043 | { |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1044 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1045 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1046 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1047 | int ret; |
| 1048 | |
| 1049 | if (args->size == 0) |
| 1050 | return 0; |
| 1051 | |
| 1052 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 1053 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1054 | args->size)) |
| 1055 | return -EFAULT; |
| 1056 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1057 | if (likely(!i915.prefault_disable)) { |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1058 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1059 | args->size); |
| 1060 | if (ret) |
| 1061 | return -EFAULT; |
| 1062 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1063 | |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1064 | intel_runtime_pm_get(dev_priv); |
| 1065 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1066 | ret = i915_mutex_lock_interruptible(dev); |
| 1067 | if (ret) |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1068 | goto put_rpm; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1069 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1070 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1071 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1072 | ret = -ENOENT; |
| 1073 | goto unlock; |
| 1074 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1075 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1076 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1077 | if (args->offset > obj->base.size || |
| 1078 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1079 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1080 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1081 | } |
| 1082 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1083 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1084 | * pages from. |
| 1085 | */ |
| 1086 | if (!obj->base.filp) { |
| 1087 | ret = -EINVAL; |
| 1088 | goto out; |
| 1089 | } |
| 1090 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1091 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1092 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1093 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1094 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1095 | * it would end up going through the fenced access, and we'll get |
| 1096 | * different detiling behavior between reading and writing. |
| 1097 | * pread/pwrite currently are reading and writing from the CPU |
| 1098 | * perspective, requiring manual detiling by the client. |
| 1099 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1100 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1101 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1102 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1103 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1104 | /* Note that the gtt paths might fail with non-page-backed user |
| 1105 | * pointers (e.g. gtt mappings when moving data between |
| 1106 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1107 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1108 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 1109 | if (ret == -EFAULT || ret == -ENOSPC) { |
| 1110 | if (obj->phys_handle) |
| 1111 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1112 | else |
| 1113 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1114 | } |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 1115 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1116 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1117 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1118 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1119 | mutex_unlock(&dev->struct_mutex); |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1120 | put_rpm: |
| 1121 | intel_runtime_pm_put(dev_priv); |
| 1122 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1123 | return ret; |
| 1124 | } |
| 1125 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1126 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1127 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1128 | bool interruptible) |
| 1129 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1130 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1131 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1132 | * -EIO unconditionally for these. */ |
| 1133 | if (!interruptible) |
| 1134 | return -EIO; |
| 1135 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1136 | /* Recovery complete, but the reset failed ... */ |
| 1137 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1138 | return -EIO; |
| 1139 | |
McAulay, Alistair | 6689c16 | 2014-08-15 18:51:35 +0100 | [diff] [blame] | 1140 | /* |
| 1141 | * Check if GPU Reset is in progress - we need intel_ring_begin |
| 1142 | * to work properly to reinit the hw state while the gpu is |
| 1143 | * still marked as reset-in-progress. Handle this with a flag. |
| 1144 | */ |
| 1145 | if (!error->reload_in_reset) |
| 1146 | return -EAGAIN; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | /* |
John Harrison | b6660d5 | 2014-11-24 18:49:30 +0000 | [diff] [blame] | 1153 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1154 | */ |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 1155 | int |
John Harrison | b6660d5 | 2014-11-24 18:49:30 +0000 | [diff] [blame] | 1156 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1157 | { |
John Harrison | b6660d5 | 2014-11-24 18:49:30 +0000 | [diff] [blame] | 1158 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1159 | |
John Harrison | b6660d5 | 2014-11-24 18:49:30 +0000 | [diff] [blame] | 1160 | if (req == req->ring->outstanding_lazy_request) |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 1161 | i915_add_request(req->ring); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1162 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 1163 | return 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1164 | } |
| 1165 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1166 | static void fake_irq(unsigned long data) |
| 1167 | { |
| 1168 | wake_up_process((struct task_struct *)data); |
| 1169 | } |
| 1170 | |
| 1171 | static bool missed_irq(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1172 | struct intel_engine_cs *ring) |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1173 | { |
| 1174 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
| 1175 | } |
| 1176 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1177 | static int __i915_spin_request(struct drm_i915_gem_request *req) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1178 | { |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1179 | unsigned long timeout; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1180 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1181 | if (i915_gem_request_get_ring(req)->irq_refcount) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1182 | return -EBUSY; |
| 1183 | |
| 1184 | timeout = jiffies + 1; |
| 1185 | while (!need_resched()) { |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1186 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1187 | return 0; |
| 1188 | |
| 1189 | if (time_after_eq(jiffies, timeout)) |
| 1190 | break; |
| 1191 | |
| 1192 | cpu_relax_lowlatency(); |
| 1193 | } |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1194 | if (i915_gem_request_completed(req, false)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1195 | return 0; |
| 1196 | |
| 1197 | return -EAGAIN; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1198 | } |
| 1199 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1200 | /** |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1201 | * __i915_wait_request - wait until execution of request has finished |
| 1202 | * @req: duh! |
| 1203 | * @reset_counter: reset sequence associated with the given request |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1204 | * @interruptible: do an interruptible wait (normally yes) |
| 1205 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1206 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1207 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1208 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1209 | * locks are involved, it is sufficient to read the reset_counter before |
| 1210 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1211 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1212 | * inserted. |
| 1213 | * |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1214 | * Returns 0 if the request was found within the alloted time. Else returns the |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1215 | * errno with remaining time filled in timeout argument. |
| 1216 | */ |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1217 | int __i915_wait_request(struct drm_i915_gem_request *req, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1218 | unsigned reset_counter, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1219 | bool interruptible, |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1220 | s64 *timeout, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1221 | struct intel_rps_client *rps) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1222 | { |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1223 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1224 | struct drm_device *dev = ring->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1225 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1226 | const bool irq_test_in_progress = |
| 1227 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1228 | DEFINE_WAIT(wait); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1229 | unsigned long timeout_expire; |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1230 | s64 before, now; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1231 | int ret; |
| 1232 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 1233 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1234 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1235 | if (list_empty(&req->list)) |
| 1236 | return 0; |
| 1237 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 1238 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1239 | return 0; |
| 1240 | |
Daniel Vetter | 7bd0e22 | 2014-12-04 11:12:54 +0100 | [diff] [blame] | 1241 | timeout_expire = timeout ? |
| 1242 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1243 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1244 | if (INTEL_INFO(dev_priv)->gen >= 6) |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 1245 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1246 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1247 | /* Record current time in case interrupted by signal, or wedged */ |
John Harrison | 74328ee | 2014-11-24 18:49:38 +0000 | [diff] [blame] | 1248 | trace_i915_gem_request_wait_begin(req); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1249 | before = ktime_get_raw_ns(); |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1250 | |
| 1251 | /* Optimistic spin for the next jiffie before touching IRQs */ |
| 1252 | ret = __i915_spin_request(req); |
| 1253 | if (ret == 0) |
| 1254 | goto out; |
| 1255 | |
| 1256 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { |
| 1257 | ret = -ENODEV; |
| 1258 | goto out; |
| 1259 | } |
| 1260 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1261 | for (;;) { |
| 1262 | struct timer_list timer; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1263 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1264 | prepare_to_wait(&ring->irq_queue, &wait, |
| 1265 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1266 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1267 | /* We need to check whether any gpu reset happened in between |
| 1268 | * the caller grabbing the seqno and now ... */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1269 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
| 1270 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
| 1271 | * is truely gone. */ |
| 1272 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1273 | if (ret == 0) |
| 1274 | ret = -EAGAIN; |
| 1275 | break; |
| 1276 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1277 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 1278 | if (i915_gem_request_completed(req, false)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1279 | ret = 0; |
| 1280 | break; |
| 1281 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1282 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1283 | if (interruptible && signal_pending(current)) { |
| 1284 | ret = -ERESTARTSYS; |
| 1285 | break; |
| 1286 | } |
| 1287 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1288 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1289 | ret = -ETIME; |
| 1290 | break; |
| 1291 | } |
| 1292 | |
| 1293 | timer.function = NULL; |
| 1294 | if (timeout || missed_irq(dev_priv, ring)) { |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1295 | unsigned long expire; |
| 1296 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1297 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1298 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1299 | mod_timer(&timer, expire); |
| 1300 | } |
| 1301 | |
Chris Wilson | 5035c27 | 2013-10-04 09:58:46 +0100 | [diff] [blame] | 1302 | io_schedule(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1303 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1304 | if (timer.function) { |
| 1305 | del_singleshot_timer_sync(&timer); |
| 1306 | destroy_timer_on_stack(&timer); |
| 1307 | } |
| 1308 | } |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1309 | if (!irq_test_in_progress) |
| 1310 | ring->irq_put(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1311 | |
| 1312 | finish_wait(&ring->irq_queue, &wait); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1313 | |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1314 | out: |
| 1315 | now = ktime_get_raw_ns(); |
| 1316 | trace_i915_gem_request_wait_end(req); |
| 1317 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1318 | if (timeout) { |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1319 | s64 tres = *timeout - (now - before); |
| 1320 | |
| 1321 | *timeout = tres < 0 ? 0 : tres; |
Daniel Vetter | 9cca306 | 2014-11-28 10:29:55 +0100 | [diff] [blame] | 1322 | |
| 1323 | /* |
| 1324 | * Apparently ktime isn't accurate enough and occasionally has a |
| 1325 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch |
| 1326 | * things up to make the test happy. We allow up to 1 jiffy. |
| 1327 | * |
| 1328 | * This is a regrssion from the timespec->ktime conversion. |
| 1329 | */ |
| 1330 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) |
| 1331 | *timeout = 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1332 | } |
| 1333 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1334 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1335 | } |
| 1336 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1337 | static inline void |
| 1338 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
| 1339 | { |
| 1340 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1341 | |
| 1342 | if (!file_priv) |
| 1343 | return; |
| 1344 | |
| 1345 | spin_lock(&file_priv->mm.lock); |
| 1346 | list_del(&request->client_list); |
| 1347 | request->file_priv = NULL; |
| 1348 | spin_unlock(&file_priv->mm.lock); |
| 1349 | } |
| 1350 | |
| 1351 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
| 1352 | { |
| 1353 | trace_i915_gem_request_retire(request); |
| 1354 | |
| 1355 | /* We know the GPU must have read the request to have |
| 1356 | * sent us the seqno + interrupt, so use the position |
| 1357 | * of tail of the request to update the last known position |
| 1358 | * of the GPU head. |
| 1359 | * |
| 1360 | * Note this requires that we are always called in request |
| 1361 | * completion order. |
| 1362 | */ |
| 1363 | request->ringbuf->last_retired_head = request->postfix; |
| 1364 | |
| 1365 | list_del_init(&request->list); |
| 1366 | i915_gem_request_remove_from_client(request); |
| 1367 | |
| 1368 | put_pid(request->pid); |
| 1369 | |
| 1370 | i915_gem_request_unreference(request); |
| 1371 | } |
| 1372 | |
| 1373 | static void |
| 1374 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) |
| 1375 | { |
| 1376 | struct intel_engine_cs *engine = req->ring; |
| 1377 | struct drm_i915_gem_request *tmp; |
| 1378 | |
| 1379 | lockdep_assert_held(&engine->dev->struct_mutex); |
| 1380 | |
| 1381 | if (list_empty(&req->list)) |
| 1382 | return; |
| 1383 | |
| 1384 | do { |
| 1385 | tmp = list_first_entry(&engine->request_list, |
| 1386 | typeof(*tmp), list); |
| 1387 | |
| 1388 | i915_gem_request_retire(tmp); |
| 1389 | } while (tmp != req); |
| 1390 | |
| 1391 | WARN_ON(i915_verify_lists(engine->dev)); |
| 1392 | } |
| 1393 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1394 | /** |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1395 | * Waits for a request to be signaled, and cleans up the |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1396 | * request and object lists appropriately for that event. |
| 1397 | */ |
| 1398 | int |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1399 | i915_wait_request(struct drm_i915_gem_request *req) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1400 | { |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1401 | struct drm_device *dev; |
| 1402 | struct drm_i915_private *dev_priv; |
| 1403 | bool interruptible; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1404 | int ret; |
| 1405 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1406 | BUG_ON(req == NULL); |
| 1407 | |
| 1408 | dev = req->ring->dev; |
| 1409 | dev_priv = dev->dev_private; |
| 1410 | interruptible = dev_priv->mm.interruptible; |
| 1411 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1412 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1413 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1414 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1415 | if (ret) |
| 1416 | return ret; |
| 1417 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1418 | ret = i915_gem_check_olr(req); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1419 | if (ret) |
| 1420 | return ret; |
| 1421 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1422 | ret = __i915_wait_request(req, |
| 1423 | atomic_read(&dev_priv->gpu_error.reset_counter), |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1424 | interruptible, NULL, NULL); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1425 | if (ret) |
| 1426 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1427 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1428 | __i915_gem_request_retire__upto(req); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1429 | return 0; |
| 1430 | } |
| 1431 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1432 | /** |
| 1433 | * Ensures that all rendering to the object has completed and the object is |
| 1434 | * safe to unbind from the GTT or access from the CPU. |
| 1435 | */ |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 1436 | int |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1437 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1438 | bool readonly) |
| 1439 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1440 | int ret, i; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1441 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1442 | if (!obj->active) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1443 | return 0; |
| 1444 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1445 | if (readonly) { |
| 1446 | if (obj->last_write_req != NULL) { |
| 1447 | ret = i915_wait_request(obj->last_write_req); |
| 1448 | if (ret) |
| 1449 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1450 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1451 | i = obj->last_write_req->ring->id; |
| 1452 | if (obj->last_read_req[i] == obj->last_write_req) |
| 1453 | i915_gem_object_retire__read(obj, i); |
| 1454 | else |
| 1455 | i915_gem_object_retire__write(obj); |
| 1456 | } |
| 1457 | } else { |
| 1458 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1459 | if (obj->last_read_req[i] == NULL) |
| 1460 | continue; |
| 1461 | |
| 1462 | ret = i915_wait_request(obj->last_read_req[i]); |
| 1463 | if (ret) |
| 1464 | return ret; |
| 1465 | |
| 1466 | i915_gem_object_retire__read(obj, i); |
| 1467 | } |
| 1468 | RQ_BUG_ON(obj->active); |
| 1469 | } |
| 1470 | |
| 1471 | return 0; |
| 1472 | } |
| 1473 | |
| 1474 | static void |
| 1475 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, |
| 1476 | struct drm_i915_gem_request *req) |
| 1477 | { |
| 1478 | int ring = req->ring->id; |
| 1479 | |
| 1480 | if (obj->last_read_req[ring] == req) |
| 1481 | i915_gem_object_retire__read(obj, ring); |
| 1482 | else if (obj->last_write_req == req) |
| 1483 | i915_gem_object_retire__write(obj); |
| 1484 | |
| 1485 | __i915_gem_request_retire__upto(req); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1486 | } |
| 1487 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1488 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1489 | * as the object state may change during this call. |
| 1490 | */ |
| 1491 | static __must_check int |
| 1492 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1493 | struct intel_rps_client *rps, |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1494 | bool readonly) |
| 1495 | { |
| 1496 | struct drm_device *dev = obj->base.dev; |
| 1497 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1498 | struct drm_i915_gem_request *requests[I915_NUM_RINGS]; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1499 | unsigned reset_counter; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1500 | int ret, i, n = 0; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1501 | |
| 1502 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1503 | BUG_ON(!dev_priv->mm.interruptible); |
| 1504 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1505 | if (!obj->active) |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1506 | return 0; |
| 1507 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1508 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1509 | if (ret) |
| 1510 | return ret; |
| 1511 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1512 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1513 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1514 | if (readonly) { |
| 1515 | struct drm_i915_gem_request *req; |
| 1516 | |
| 1517 | req = obj->last_write_req; |
| 1518 | if (req == NULL) |
| 1519 | return 0; |
| 1520 | |
| 1521 | ret = i915_gem_check_olr(req); |
| 1522 | if (ret) |
| 1523 | goto err; |
| 1524 | |
| 1525 | requests[n++] = i915_gem_request_reference(req); |
| 1526 | } else { |
| 1527 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1528 | struct drm_i915_gem_request *req; |
| 1529 | |
| 1530 | req = obj->last_read_req[i]; |
| 1531 | if (req == NULL) |
| 1532 | continue; |
| 1533 | |
| 1534 | ret = i915_gem_check_olr(req); |
| 1535 | if (ret) |
| 1536 | goto err; |
| 1537 | |
| 1538 | requests[n++] = i915_gem_request_reference(req); |
| 1539 | } |
| 1540 | } |
| 1541 | |
| 1542 | mutex_unlock(&dev->struct_mutex); |
| 1543 | for (i = 0; ret == 0 && i < n; i++) |
| 1544 | ret = __i915_wait_request(requests[i], reset_counter, true, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1545 | NULL, rps); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1546 | mutex_lock(&dev->struct_mutex); |
| 1547 | |
| 1548 | err: |
| 1549 | for (i = 0; i < n; i++) { |
| 1550 | if (ret == 0) |
| 1551 | i915_gem_object_retire_request(obj, requests[i]); |
| 1552 | i915_gem_request_unreference(requests[i]); |
| 1553 | } |
| 1554 | |
| 1555 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1556 | } |
| 1557 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1558 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
| 1559 | { |
| 1560 | struct drm_i915_file_private *fpriv = file->driver_priv; |
| 1561 | return &fpriv->rps; |
| 1562 | } |
| 1563 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1564 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1565 | * Called when user space prepares to use an object with the CPU, either |
| 1566 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1567 | */ |
| 1568 | int |
| 1569 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1570 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1571 | { |
| 1572 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1573 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1574 | uint32_t read_domains = args->read_domains; |
| 1575 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1576 | int ret; |
| 1577 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1578 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1579 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1580 | return -EINVAL; |
| 1581 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1582 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1583 | return -EINVAL; |
| 1584 | |
| 1585 | /* Having something in the write domain implies it's in the read |
| 1586 | * domain, and only that read domain. Enforce that in the request. |
| 1587 | */ |
| 1588 | if (write_domain != 0 && read_domains != write_domain) |
| 1589 | return -EINVAL; |
| 1590 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1591 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1592 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1593 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1594 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1595 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1596 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1597 | ret = -ENOENT; |
| 1598 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1599 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1600 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1601 | /* Try to flush the object off the GPU without holding the lock. |
| 1602 | * We will repeat the flush holding the lock in the normal manner |
| 1603 | * to catch cases where we are gazumped. |
| 1604 | */ |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1605 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1606 | to_rps_client(file), |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1607 | !write_domain); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1608 | if (ret) |
| 1609 | goto unref; |
| 1610 | |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 1611 | if (read_domains & I915_GEM_DOMAIN_GTT) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1612 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 1613 | else |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1614 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1615 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1616 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1617 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1618 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1619 | mutex_unlock(&dev->struct_mutex); |
| 1620 | return ret; |
| 1621 | } |
| 1622 | |
| 1623 | /** |
| 1624 | * Called when user space has done writes to this buffer |
| 1625 | */ |
| 1626 | int |
| 1627 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1628 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1629 | { |
| 1630 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1631 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1632 | int ret = 0; |
| 1633 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1634 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1635 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1636 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1637 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1638 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1639 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1640 | ret = -ENOENT; |
| 1641 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1642 | } |
| 1643 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1644 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1645 | if (obj->pin_display) |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 1646 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1647 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1648 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1649 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1650 | mutex_unlock(&dev->struct_mutex); |
| 1651 | return ret; |
| 1652 | } |
| 1653 | |
| 1654 | /** |
| 1655 | * Maps the contents of an object, returning the address it is mapped |
| 1656 | * into. |
| 1657 | * |
| 1658 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1659 | * imply a ref on the object itself. |
Daniel Vetter | 3436738 | 2014-10-16 12:28:18 +0200 | [diff] [blame] | 1660 | * |
| 1661 | * IMPORTANT: |
| 1662 | * |
| 1663 | * DRM driver writers who look a this function as an example for how to do GEM |
| 1664 | * mmap support, please don't implement mmap support like here. The modern way |
| 1665 | * to implement DRM mmap support is with an mmap offset ioctl (like |
| 1666 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
| 1667 | * That way debug tooling like valgrind will understand what's going on, hiding |
| 1668 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
| 1669 | * does cpu mmaps this way because we didn't know better. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1670 | */ |
| 1671 | int |
| 1672 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1673 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1674 | { |
| 1675 | struct drm_i915_gem_mmap *args = data; |
| 1676 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1677 | unsigned long addr; |
| 1678 | |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1679 | if (args->flags & ~(I915_MMAP_WC)) |
| 1680 | return -EINVAL; |
| 1681 | |
| 1682 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) |
| 1683 | return -ENODEV; |
| 1684 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1685 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1687 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1688 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1689 | /* prime objects have no backing filp to GEM mmap |
| 1690 | * pages from. |
| 1691 | */ |
| 1692 | if (!obj->filp) { |
| 1693 | drm_gem_object_unreference_unlocked(obj); |
| 1694 | return -EINVAL; |
| 1695 | } |
| 1696 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1697 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1698 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1699 | args->offset); |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1700 | if (args->flags & I915_MMAP_WC) { |
| 1701 | struct mm_struct *mm = current->mm; |
| 1702 | struct vm_area_struct *vma; |
| 1703 | |
| 1704 | down_write(&mm->mmap_sem); |
| 1705 | vma = find_vma(mm, addr); |
| 1706 | if (vma) |
| 1707 | vma->vm_page_prot = |
| 1708 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); |
| 1709 | else |
| 1710 | addr = -ENOMEM; |
| 1711 | up_write(&mm->mmap_sem); |
| 1712 | } |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1713 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1714 | if (IS_ERR((void *)addr)) |
| 1715 | return addr; |
| 1716 | |
| 1717 | args->addr_ptr = (uint64_t) addr; |
| 1718 | |
| 1719 | return 0; |
| 1720 | } |
| 1721 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1722 | /** |
| 1723 | * i915_gem_fault - fault a page into the GTT |
| 1724 | * vma: VMA in question |
| 1725 | * vmf: fault info |
| 1726 | * |
| 1727 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1728 | * from userspace. The fault handler takes care of binding the object to |
| 1729 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1730 | * only if needed based on whether the old reg is still valid or the object |
| 1731 | * is tiled) and inserting a new PTE into the faulting process. |
| 1732 | * |
| 1733 | * Note that the faulting process may involve evicting existing objects |
| 1734 | * from the GTT and/or fence registers to make room. So performance may |
| 1735 | * suffer if the GTT working set is large or there are few fence registers |
| 1736 | * left. |
| 1737 | */ |
| 1738 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1739 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1740 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1741 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1742 | struct drm_i915_private *dev_priv = dev->dev_private; |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1743 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1744 | pgoff_t page_offset; |
| 1745 | unsigned long pfn; |
| 1746 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1747 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1748 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1749 | intel_runtime_pm_get(dev_priv); |
| 1750 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1751 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1752 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1753 | PAGE_SHIFT; |
| 1754 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1755 | ret = i915_mutex_lock_interruptible(dev); |
| 1756 | if (ret) |
| 1757 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1758 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1759 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1760 | |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1761 | /* Try to flush the object off the GPU first without holding the lock. |
| 1762 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1763 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1764 | * where we are gazumped. |
| 1765 | */ |
| 1766 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1767 | if (ret) |
| 1768 | goto unlock; |
| 1769 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1770 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1771 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
Chris Wilson | ddeff6e | 2014-05-28 16:16:41 +0100 | [diff] [blame] | 1772 | ret = -EFAULT; |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1773 | goto unlock; |
| 1774 | } |
| 1775 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1776 | /* Use a partial view if the object is bigger than the aperture. */ |
Joonas Lahtinen | e7ded2d | 2015-05-08 14:37:39 +0300 | [diff] [blame] | 1777 | if (obj->base.size >= dev_priv->gtt.mappable_end && |
| 1778 | obj->tiling_mode == I915_TILING_NONE) { |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1779 | static const unsigned int chunk_size = 256; // 1 MiB |
Joonas Lahtinen | e7ded2d | 2015-05-08 14:37:39 +0300 | [diff] [blame] | 1780 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1781 | memset(&view, 0, sizeof(view)); |
| 1782 | view.type = I915_GGTT_VIEW_PARTIAL; |
| 1783 | view.params.partial.offset = rounddown(page_offset, chunk_size); |
| 1784 | view.params.partial.size = |
| 1785 | min_t(unsigned int, |
| 1786 | chunk_size, |
| 1787 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - |
| 1788 | view.params.partial.offset); |
| 1789 | } |
| 1790 | |
| 1791 | /* Now pin it into the GTT if needed */ |
| 1792 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1793 | if (ret) |
| 1794 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1795 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1796 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1797 | if (ret) |
| 1798 | goto unpin; |
| 1799 | |
| 1800 | ret = i915_gem_object_get_fence(obj); |
| 1801 | if (ret) |
| 1802 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1803 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1804 | /* Finally, remap it using the new GTT offset */ |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1805 | pfn = dev_priv->gtt.mappable_base + |
| 1806 | i915_gem_obj_ggtt_offset_view(obj, &view); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1807 | pfn >>= PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1808 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1809 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
| 1810 | /* Overriding existing pages in partial view does not cause |
| 1811 | * us any trouble as TLBs are still valid because the fault |
| 1812 | * is due to userspace losing part of the mapping or never |
| 1813 | * having accessed it before (at this partials' range). |
| 1814 | */ |
| 1815 | unsigned long base = vma->vm_start + |
| 1816 | (view.params.partial.offset << PAGE_SHIFT); |
| 1817 | unsigned int i; |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1818 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1819 | for (i = 0; i < view.params.partial.size; i++) { |
| 1820 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1821 | if (ret) |
| 1822 | break; |
| 1823 | } |
| 1824 | |
| 1825 | obj->fault_mappable = true; |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1826 | } else { |
| 1827 | if (!obj->fault_mappable) { |
| 1828 | unsigned long size = min_t(unsigned long, |
| 1829 | vma->vm_end - vma->vm_start, |
| 1830 | obj->base.size); |
| 1831 | int i; |
| 1832 | |
| 1833 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
| 1834 | ret = vm_insert_pfn(vma, |
| 1835 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1836 | pfn + i); |
| 1837 | if (ret) |
| 1838 | break; |
| 1839 | } |
| 1840 | |
| 1841 | obj->fault_mappable = true; |
| 1842 | } else |
| 1843 | ret = vm_insert_pfn(vma, |
| 1844 | (unsigned long)vmf->virtual_address, |
| 1845 | pfn + page_offset); |
| 1846 | } |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1847 | unpin: |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1848 | i915_gem_object_ggtt_unpin_view(obj, &view); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1849 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1850 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1851 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1852 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1853 | case -EIO: |
Daniel Vetter | 2232f03 | 2014-09-04 09:36:18 +0200 | [diff] [blame] | 1854 | /* |
| 1855 | * We eat errors when the gpu is terminally wedged to avoid |
| 1856 | * userspace unduly crashing (gl has no provisions for mmaps to |
| 1857 | * fail). But any other -EIO isn't ours (e.g. swap in failure) |
| 1858 | * and so needs to be reported. |
| 1859 | */ |
| 1860 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1861 | ret = VM_FAULT_SIGBUS; |
| 1862 | break; |
| 1863 | } |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1864 | case -EAGAIN: |
Daniel Vetter | 571c608 | 2013-09-12 17:57:28 +0200 | [diff] [blame] | 1865 | /* |
| 1866 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1867 | * handler to reset everything when re-faulting in |
| 1868 | * i915_mutex_lock_interruptible. |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1869 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1870 | case 0: |
| 1871 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1872 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1873 | case -EBUSY: |
| 1874 | /* |
| 1875 | * EBUSY is ok: this just means that another thread |
| 1876 | * already did the job. |
| 1877 | */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1878 | ret = VM_FAULT_NOPAGE; |
| 1879 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1880 | case -ENOMEM: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1881 | ret = VM_FAULT_OOM; |
| 1882 | break; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1883 | case -ENOSPC: |
Chris Wilson | 45d6781 | 2014-01-31 11:34:57 +0000 | [diff] [blame] | 1884 | case -EFAULT: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1885 | ret = VM_FAULT_SIGBUS; |
| 1886 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1887 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1888 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1889 | ret = VM_FAULT_SIGBUS; |
| 1890 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1891 | } |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1892 | |
| 1893 | intel_runtime_pm_put(dev_priv); |
| 1894 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1895 | } |
| 1896 | |
| 1897 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1898 | * i915_gem_release_mmap - remove physical page mappings |
| 1899 | * @obj: obj in question |
| 1900 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1901 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1902 | * relinquish ownership of the pages back to the system. |
| 1903 | * |
| 1904 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1905 | * object through the GTT and then lose the fence register due to |
| 1906 | * resource pressure. Similarly if the object has been moved out of the |
| 1907 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1908 | * mapping will then trigger a page fault on the next user access, allowing |
| 1909 | * fixup by i915_gem_fault(). |
| 1910 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1911 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1912 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1913 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1914 | if (!obj->fault_mappable) |
| 1915 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1916 | |
David Herrmann | 6796cb1 | 2014-01-03 14:24:19 +0100 | [diff] [blame] | 1917 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1918 | obj->base.dev->anon_inode->i_mapping); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1919 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1920 | } |
| 1921 | |
Chris Wilson | eedd10f | 2014-06-16 08:57:44 +0100 | [diff] [blame] | 1922 | void |
| 1923 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1924 | { |
| 1925 | struct drm_i915_gem_object *obj; |
| 1926 | |
| 1927 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1928 | i915_gem_release_mmap(obj); |
| 1929 | } |
| 1930 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1931 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1932 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1933 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1934 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1935 | |
| 1936 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1937 | tiling_mode == I915_TILING_NONE) |
| 1938 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1939 | |
| 1940 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1941 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1942 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1943 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1944 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1945 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1946 | while (gtt_size < size) |
| 1947 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1948 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1949 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1950 | } |
| 1951 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1952 | /** |
| 1953 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1954 | * @obj: object to check |
| 1955 | * |
| 1956 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1957 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1958 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1959 | uint32_t |
| 1960 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1961 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1962 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1963 | /* |
| 1964 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1965 | * if a fence register is needed for the object. |
| 1966 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1967 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1968 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1969 | return 4096; |
| 1970 | |
| 1971 | /* |
| 1972 | * Previous chips need to be aligned to the size of the smallest |
| 1973 | * fence register that can contain the object. |
| 1974 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1975 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1976 | } |
| 1977 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1978 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1979 | { |
| 1980 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1981 | int ret; |
| 1982 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1983 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1984 | return 0; |
| 1985 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1986 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1987 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1988 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1989 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1990 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1991 | |
| 1992 | /* Badly fragmented mmap space? The only way we can recover |
| 1993 | * space is by destroying unwanted objects. We can't randomly release |
| 1994 | * mmap_offsets as userspace expects them to be persistent for the |
| 1995 | * lifetime of the objects. The closest we can is to release the |
| 1996 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1997 | * which prevents userspace from ever using that object again. |
| 1998 | */ |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 1999 | i915_gem_shrink(dev_priv, |
| 2000 | obj->base.size >> PAGE_SHIFT, |
| 2001 | I915_SHRINK_BOUND | |
| 2002 | I915_SHRINK_UNBOUND | |
| 2003 | I915_SHRINK_PURGEABLE); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2004 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2005 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2006 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2007 | |
| 2008 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2009 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2010 | out: |
| 2011 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 2012 | |
| 2013 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2014 | } |
| 2015 | |
| 2016 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 2017 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2018 | drm_gem_free_mmap_offset(&obj->base); |
| 2019 | } |
| 2020 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2021 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2022 | i915_gem_mmap_gtt(struct drm_file *file, |
| 2023 | struct drm_device *dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2024 | uint32_t handle, |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2025 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2026 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2027 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2028 | int ret; |
| 2029 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 2030 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2031 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 2032 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2033 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2034 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 2035 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2036 | ret = -ENOENT; |
| 2037 | goto unlock; |
| 2038 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2039 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2040 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2041 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2042 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2043 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 2044 | } |
| 2045 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2046 | ret = i915_gem_object_create_mmap_offset(obj); |
| 2047 | if (ret) |
| 2048 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2049 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 2050 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2051 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2052 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2053 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2054 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2055 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2056 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2057 | } |
| 2058 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2059 | /** |
| 2060 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 2061 | * @dev: DRM device |
| 2062 | * @data: GTT mapping ioctl data |
| 2063 | * @file: GEM object info |
| 2064 | * |
| 2065 | * Simply returns the fake offset to userspace so it can mmap it. |
| 2066 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 2067 | * up so we can get faults in the handler above. |
| 2068 | * |
| 2069 | * The fault handler will take care of binding the object into the GTT |
| 2070 | * (since it may have been evicted to make room for something), allocating |
| 2071 | * a fence register, and mapping the appropriate aperture address into |
| 2072 | * userspace. |
| 2073 | */ |
| 2074 | int |
| 2075 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2076 | struct drm_file *file) |
| 2077 | { |
| 2078 | struct drm_i915_gem_mmap_gtt *args = data; |
| 2079 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2080 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2081 | } |
| 2082 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2083 | /* Immediately discard the backing storage */ |
| 2084 | static void |
| 2085 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2086 | { |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 2087 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2088 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 2089 | if (obj->base.filp == NULL) |
| 2090 | return; |
| 2091 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2092 | /* Our goal here is to return as much of the memory as |
| 2093 | * is possible back to the system as we are called from OOM. |
| 2094 | * To do this we must instruct the shmfs to drop all of its |
| 2095 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2096 | */ |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2097 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2098 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2099 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2100 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2101 | /* Try to discard unwanted pages */ |
| 2102 | static void |
| 2103 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2104 | { |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2105 | struct address_space *mapping; |
| 2106 | |
| 2107 | switch (obj->madv) { |
| 2108 | case I915_MADV_DONTNEED: |
| 2109 | i915_gem_object_truncate(obj); |
| 2110 | case __I915_MADV_PURGED: |
| 2111 | return; |
| 2112 | } |
| 2113 | |
| 2114 | if (obj->base.filp == NULL) |
| 2115 | return; |
| 2116 | |
| 2117 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 2118 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2119 | } |
| 2120 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2121 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2122 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2123 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2124 | struct sg_page_iter sg_iter; |
| 2125 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2126 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2127 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2128 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2129 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 2130 | if (ret) { |
| 2131 | /* In the event of a disaster, abandon all caches and |
| 2132 | * hope for the best. |
| 2133 | */ |
| 2134 | WARN_ON(ret != -EIO); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 2135 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2136 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2137 | } |
| 2138 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 2139 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2140 | i915_gem_object_save_bit_17_swizzle(obj); |
| 2141 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2142 | if (obj->madv == I915_MADV_DONTNEED) |
| 2143 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2144 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2145 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2146 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2147 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2148 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2149 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2150 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2151 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2152 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2153 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2154 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2155 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2156 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2157 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2158 | sg_free_table(obj->pages); |
| 2159 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2160 | } |
| 2161 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2162 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2163 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 2164 | { |
| 2165 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2166 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2167 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2168 | return 0; |
| 2169 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2170 | if (obj->pages_pin_count) |
| 2171 | return -EBUSY; |
| 2172 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 2173 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 2174 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2175 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 2176 | * array, hence protect them from being reaped by removing them from gtt |
| 2177 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2178 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2179 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2180 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2181 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2182 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2183 | i915_gem_object_invalidate(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2184 | |
| 2185 | return 0; |
| 2186 | } |
| 2187 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2188 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2189 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2190 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2191 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2192 | int page_count, i; |
| 2193 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2194 | struct sg_table *st; |
| 2195 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2196 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2197 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2198 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2199 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2200 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2201 | /* Assert that the object is not currently in any GPU domain. As it |
| 2202 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2203 | * a GPU cache |
| 2204 | */ |
| 2205 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2206 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2207 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2208 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2209 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2210 | return -ENOMEM; |
| 2211 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2212 | page_count = obj->base.size / PAGE_SIZE; |
| 2213 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2214 | kfree(st); |
| 2215 | return -ENOMEM; |
| 2216 | } |
| 2217 | |
| 2218 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2219 | * at this point until we release them. |
| 2220 | * |
| 2221 | * Fail silently without starting the shrinker |
| 2222 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 2223 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2224 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 2225 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2226 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2227 | sg = st->sgl; |
| 2228 | st->nents = 0; |
| 2229 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2230 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2231 | if (IS_ERR(page)) { |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2232 | i915_gem_shrink(dev_priv, |
| 2233 | page_count, |
| 2234 | I915_SHRINK_BOUND | |
| 2235 | I915_SHRINK_UNBOUND | |
| 2236 | I915_SHRINK_PURGEABLE); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2237 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2238 | } |
| 2239 | if (IS_ERR(page)) { |
| 2240 | /* We've tried hard to allocate the memory by reaping |
| 2241 | * our own buffer, now let the real VM do its job and |
| 2242 | * go down in flames if truly OOM. |
| 2243 | */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2244 | i915_gem_shrink_all(dev_priv); |
David Herrmann | f461d1b | 2014-05-25 14:34:10 +0200 | [diff] [blame] | 2245 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2246 | if (IS_ERR(page)) |
| 2247 | goto err_pages; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2248 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2249 | #ifdef CONFIG_SWIOTLB |
| 2250 | if (swiotlb_nr_tbl()) { |
| 2251 | st->nents++; |
| 2252 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2253 | sg = sg_next(sg); |
| 2254 | continue; |
| 2255 | } |
| 2256 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2257 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2258 | if (i) |
| 2259 | sg = sg_next(sg); |
| 2260 | st->nents++; |
| 2261 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2262 | } else { |
| 2263 | sg->length += PAGE_SIZE; |
| 2264 | } |
| 2265 | last_pfn = page_to_pfn(page); |
Daniel Vetter | 3bbbe70 | 2013-10-07 17:15:45 -0300 | [diff] [blame] | 2266 | |
| 2267 | /* Check that the i965g/gm workaround works. */ |
| 2268 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2269 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2270 | #ifdef CONFIG_SWIOTLB |
| 2271 | if (!swiotlb_nr_tbl()) |
| 2272 | #endif |
| 2273 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 2274 | obj->pages = st; |
| 2275 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2276 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2277 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2278 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2279 | if (obj->tiling_mode != I915_TILING_NONE && |
| 2280 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2281 | i915_gem_object_pin_pages(obj); |
| 2282 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2283 | return 0; |
| 2284 | |
| 2285 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2286 | sg_mark_end(sg); |
| 2287 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2288 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2289 | sg_free_table(st); |
| 2290 | kfree(st); |
Chris Wilson | 0820baf | 2014-03-25 13:23:03 +0000 | [diff] [blame] | 2291 | |
| 2292 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2293 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2294 | * ENOMEM for a genuine allocation failure. |
| 2295 | * |
| 2296 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2297 | * space and so want to translate the error from shmemfs back to our |
| 2298 | * usual understanding of ENOMEM. |
| 2299 | */ |
| 2300 | if (PTR_ERR(page) == -ENOSPC) |
| 2301 | return -ENOMEM; |
| 2302 | else |
| 2303 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2304 | } |
| 2305 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2306 | /* Ensure that the associated pages are gathered from the backing storage |
| 2307 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2308 | * multiple times before they are released by a single call to |
| 2309 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2310 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2311 | * or as the object is itself released. |
| 2312 | */ |
| 2313 | int |
| 2314 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2315 | { |
| 2316 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2317 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2318 | int ret; |
| 2319 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2320 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2321 | return 0; |
| 2322 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2323 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2324 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2325 | return -EFAULT; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2326 | } |
| 2327 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2328 | BUG_ON(obj->pages_pin_count); |
| 2329 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2330 | ret = ops->get_pages(obj); |
| 2331 | if (ret) |
| 2332 | return ret; |
| 2333 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2334 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | ee28637 | 2015-04-07 16:20:25 +0100 | [diff] [blame] | 2335 | |
| 2336 | obj->get_page.sg = obj->pages->sgl; |
| 2337 | obj->get_page.last = 0; |
| 2338 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2339 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2340 | } |
| 2341 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2342 | void i915_vma_move_to_active(struct i915_vma *vma, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2343 | struct intel_engine_cs *ring) |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2344 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2345 | struct drm_i915_gem_object *obj = vma->obj; |
| 2346 | |
| 2347 | /* Add a reference if we're newly entering the active list. */ |
| 2348 | if (obj->active == 0) |
| 2349 | drm_gem_object_reference(&obj->base); |
| 2350 | obj->active |= intel_ring_flag(ring); |
| 2351 | |
| 2352 | list_move_tail(&obj->ring_list[ring->id], &ring->active_list); |
| 2353 | i915_gem_request_assign(&obj->last_read_req[ring->id], |
| 2354 | intel_ring_get_request(ring)); |
| 2355 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2356 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2357 | } |
| 2358 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2359 | static void |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2360 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) |
| 2361 | { |
| 2362 | RQ_BUG_ON(obj->last_write_req == NULL); |
| 2363 | RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); |
| 2364 | |
| 2365 | i915_gem_request_assign(&obj->last_write_req, NULL); |
| 2366 | intel_fb_obj_flush(obj, true); |
| 2367 | } |
| 2368 | |
| 2369 | static void |
| 2370 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2371 | { |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2372 | struct i915_vma *vma; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2373 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2374 | RQ_BUG_ON(obj->last_read_req[ring] == NULL); |
| 2375 | RQ_BUG_ON(!(obj->active & (1 << ring))); |
| 2376 | |
| 2377 | list_del_init(&obj->ring_list[ring]); |
| 2378 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
| 2379 | |
| 2380 | if (obj->last_write_req && obj->last_write_req->ring->id == ring) |
| 2381 | i915_gem_object_retire__write(obj); |
| 2382 | |
| 2383 | obj->active &= ~(1 << ring); |
| 2384 | if (obj->active) |
| 2385 | return; |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2386 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2387 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 2388 | if (!list_empty(&vma->mm_list)) |
| 2389 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2390 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2391 | |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 2392 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2393 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2394 | } |
| 2395 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2396 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2397 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2398 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2399 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2400 | struct intel_engine_cs *ring; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2401 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2402 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2403 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2404 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2405 | ret = intel_ring_idle(ring); |
| 2406 | if (ret) |
| 2407 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2408 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2409 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2410 | |
| 2411 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2412 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2413 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2414 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2415 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
| 2416 | ring->semaphore.sync_seqno[j] = 0; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2417 | } |
| 2418 | |
| 2419 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2420 | } |
| 2421 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2422 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2423 | { |
| 2424 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2425 | int ret; |
| 2426 | |
| 2427 | if (seqno == 0) |
| 2428 | return -EINVAL; |
| 2429 | |
| 2430 | /* HWS page needs to be set less than what we |
| 2431 | * will inject to ring |
| 2432 | */ |
| 2433 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2434 | if (ret) |
| 2435 | return ret; |
| 2436 | |
| 2437 | /* Carefully set the last_seqno value so that wrap |
| 2438 | * detection still works |
| 2439 | */ |
| 2440 | dev_priv->next_seqno = seqno; |
| 2441 | dev_priv->last_seqno = seqno - 1; |
| 2442 | if (dev_priv->last_seqno == 0) |
| 2443 | dev_priv->last_seqno--; |
| 2444 | |
| 2445 | return 0; |
| 2446 | } |
| 2447 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2448 | int |
| 2449 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2450 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2451 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2452 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2453 | /* reserve 0 for non-seqno */ |
| 2454 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2455 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2456 | if (ret) |
| 2457 | return ret; |
| 2458 | |
| 2459 | dev_priv->next_seqno = 1; |
| 2460 | } |
| 2461 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2462 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2463 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2464 | } |
| 2465 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2466 | /* |
| 2467 | * NB: This function is not allowed to fail. Doing so would mean the the |
| 2468 | * request is not being tracked for completion but the work itself is |
| 2469 | * going to happen on the hardware. This would be a Bad Thing(tm). |
| 2470 | */ |
| 2471 | void __i915_add_request(struct intel_engine_cs *ring, |
| 2472 | struct drm_file *file, |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2473 | struct drm_i915_gem_object *obj, |
| 2474 | bool flush_caches) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2475 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2476 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2477 | struct drm_i915_gem_request *request; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2478 | struct intel_ringbuffer *ringbuf; |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2479 | u32 request_start; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2480 | int ret; |
| 2481 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 2482 | request = ring->outstanding_lazy_request; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2483 | if (WARN_ON(request == NULL)) |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2484 | return; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2485 | |
| 2486 | if (i915.enable_execlists) { |
Nick Hoath | 2107637 | 2015-01-15 13:10:38 +0000 | [diff] [blame] | 2487 | ringbuf = request->ctx->engine[ring->id].ringbuf; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2488 | } else |
| 2489 | ringbuf = ring->buffer; |
| 2490 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2491 | /* |
| 2492 | * To ensure that this call will not fail, space for its emissions |
| 2493 | * should already have been reserved in the ring buffer. Let the ring |
| 2494 | * know that it is time to use that space up. |
| 2495 | */ |
| 2496 | intel_ring_reserved_space_use(ringbuf); |
| 2497 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2498 | request_start = intel_ring_get_tail(ringbuf); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2499 | /* |
| 2500 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2501 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2502 | * things up similar to emitting the lazy request. The difference here |
| 2503 | * is that the flush _must_ happen before the next request, no matter |
| 2504 | * what. |
| 2505 | */ |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2506 | if (flush_caches) { |
| 2507 | if (i915.enable_execlists) |
| 2508 | ret = logical_ring_flush_all_caches(ringbuf, request->ctx); |
| 2509 | else |
| 2510 | ret = intel_ring_flush_all_caches(ring); |
| 2511 | /* Not allowed to fail! */ |
| 2512 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); |
| 2513 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2514 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2515 | /* Record the position of the start of the request so that |
| 2516 | * should we detect the updated seqno part-way through the |
| 2517 | * GPU processing the request, we never over-estimate the |
| 2518 | * position of the head. |
| 2519 | */ |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2520 | request->postfix = intel_ring_get_tail(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2521 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2522 | if (i915.enable_execlists) |
Nick Hoath | 72f95af | 2015-01-15 13:10:37 +0000 | [diff] [blame] | 2523 | ret = ring->emit_request(ringbuf, request); |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2524 | else { |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2525 | ret = ring->add_request(ring); |
Michel Thierry | 53292cd | 2015-04-15 18:11:33 +0100 | [diff] [blame] | 2526 | |
| 2527 | request->tail = intel_ring_get_tail(ringbuf); |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2528 | } |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2529 | /* Not allowed to fail! */ |
| 2530 | WARN(ret, "emit|add_request failed: %d!\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2531 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2532 | request->head = request_start; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2533 | |
| 2534 | /* Whilst this request exists, batch_obj will be on the |
| 2535 | * active_list, and so will hold the active reference. Only when this |
| 2536 | * request is retired will the the batch_obj be moved onto the |
| 2537 | * inactive_list and lose its active reference. Hence we do not need |
| 2538 | * to explicitly hold another reference here. |
| 2539 | */ |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2540 | request->batch_obj = obj; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2541 | |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2542 | WARN_ON(!i915.enable_execlists && (request->ctx != ring->last_context)); |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2543 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2544 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2545 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2546 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2547 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2548 | if (file) { |
| 2549 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2550 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2551 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2552 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2553 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2554 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2555 | spin_unlock(&file_priv->mm.lock); |
Mika Kuoppala | 071c92d | 2015-02-12 10:26:02 +0200 | [diff] [blame] | 2556 | |
| 2557 | request->pid = get_pid(task_pid(current)); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2558 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2559 | |
John Harrison | 74328ee | 2014-11-24 18:49:38 +0000 | [diff] [blame] | 2560 | trace_i915_gem_request_add(request); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 2561 | ring->outstanding_lazy_request = NULL; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2562 | |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 2563 | i915_queue_hangcheck(ring->dev); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2564 | |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 2565 | queue_delayed_work(dev_priv->wq, |
| 2566 | &dev_priv->mm.retire_work, |
| 2567 | round_jiffies_up_relative(HZ)); |
| 2568 | intel_mark_busy(dev_priv->dev); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2569 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2570 | /* Sanity check that the reserved size was large enough. */ |
| 2571 | intel_ring_reserved_space_end(ringbuf); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2572 | } |
| 2573 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2574 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2575 | const struct intel_context *ctx) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2576 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2577 | unsigned long elapsed; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2578 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2579 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2580 | |
| 2581 | if (ctx->hang_stats.banned) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2582 | return true; |
| 2583 | |
Chris Wilson | 676fa57 | 2014-12-24 08:13:39 -0800 | [diff] [blame] | 2584 | if (ctx->hang_stats.ban_period_seconds && |
| 2585 | elapsed <= ctx->hang_stats.ban_period_seconds) { |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2586 | if (!i915_gem_context_is_default(ctx)) { |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2587 | DRM_DEBUG("context hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2588 | return true; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 2589 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2590 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2591 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2592 | return true; |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2593 | } |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2594 | } |
| 2595 | |
| 2596 | return false; |
| 2597 | } |
| 2598 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2599 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2600 | struct intel_context *ctx, |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2601 | const bool guilty) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2602 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2603 | struct i915_ctx_hang_stats *hs; |
| 2604 | |
| 2605 | if (WARN_ON(!ctx)) |
| 2606 | return; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2607 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2608 | hs = &ctx->hang_stats; |
| 2609 | |
| 2610 | if (guilty) { |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2611 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2612 | hs->batch_active++; |
| 2613 | hs->guilty_ts = get_seconds(); |
| 2614 | } else { |
| 2615 | hs->batch_pending++; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2616 | } |
| 2617 | } |
| 2618 | |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2619 | void i915_gem_request_free(struct kref *req_ref) |
| 2620 | { |
| 2621 | struct drm_i915_gem_request *req = container_of(req_ref, |
| 2622 | typeof(*req), ref); |
| 2623 | struct intel_context *ctx = req->ctx; |
| 2624 | |
Thomas Daniel | 0794aed | 2014-11-25 10:39:25 +0000 | [diff] [blame] | 2625 | if (ctx) { |
| 2626 | if (i915.enable_execlists) { |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2627 | struct intel_engine_cs *ring = req->ring; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2628 | |
Thomas Daniel | 0794aed | 2014-11-25 10:39:25 +0000 | [diff] [blame] | 2629 | if (ctx != ring->default_context) |
| 2630 | intel_lr_context_unpin(ring, ctx); |
| 2631 | } |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2632 | |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2633 | i915_gem_context_unreference(ctx); |
| 2634 | } |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2635 | |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 2636 | kmem_cache_free(req->i915->requests, req); |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2637 | } |
| 2638 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2639 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
John Harrison | 217e46b | 2015-05-29 17:43:29 +0100 | [diff] [blame] | 2640 | struct intel_context *ctx, |
| 2641 | struct drm_i915_gem_request **req_out) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2642 | { |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 2643 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2644 | struct drm_i915_gem_request *req; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2645 | int ret; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2646 | |
John Harrison | 217e46b | 2015-05-29 17:43:29 +0100 | [diff] [blame] | 2647 | if (!req_out) |
| 2648 | return -EINVAL; |
| 2649 | |
| 2650 | if ((*req_out = ring->outstanding_lazy_request) != NULL) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2651 | return 0; |
| 2652 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2653 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
| 2654 | if (req == NULL) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2655 | return -ENOMEM; |
| 2656 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2657 | ret = i915_gem_get_seqno(ring->dev, &req->seqno); |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2658 | if (ret) |
| 2659 | goto err; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2660 | |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2661 | kref_init(&req->ref); |
| 2662 | req->i915 = dev_priv; |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2663 | req->ring = ring; |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2664 | req->ctx = ctx; |
| 2665 | i915_gem_context_reference(req->ctx); |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2666 | |
| 2667 | if (i915.enable_execlists) |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2668 | ret = intel_logical_ring_alloc_request_extras(req); |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2669 | else |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2670 | ret = intel_ring_alloc_request_extras(req); |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2671 | if (ret) { |
| 2672 | i915_gem_context_unreference(req->ctx); |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2673 | goto err; |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2674 | } |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2675 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2676 | /* |
| 2677 | * Reserve space in the ring buffer for all the commands required to |
| 2678 | * eventually emit this request. This is to guarantee that the |
| 2679 | * i915_add_request() call can't fail. Note that the reserve may need |
| 2680 | * to be redone if the request is not actually submitted straight |
| 2681 | * away, e.g. because a GPU scheduler has deferred it. |
| 2682 | * |
| 2683 | * Note further that this call merely notes the reserve request. A |
| 2684 | * subsequent call to *_ring_begin() is required to actually ensure |
| 2685 | * that the reservation is available. Without the begin, if the |
| 2686 | * request creator immediately submitted the request without adding |
| 2687 | * any commands to it then there might not actually be sufficient |
| 2688 | * room for the submission commands. Unfortunately, the current |
| 2689 | * *_ring_begin() implementations potentially call back here to |
| 2690 | * i915_gem_request_alloc(). Thus calling _begin() here would lead to |
| 2691 | * infinite recursion! Until that back call path is removed, it is |
| 2692 | * necessary to do a manual _begin() outside. |
| 2693 | */ |
| 2694 | intel_ring_reserved_space_reserve(req->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); |
| 2695 | |
John Harrison | 217e46b | 2015-05-29 17:43:29 +0100 | [diff] [blame] | 2696 | *req_out = ring->outstanding_lazy_request = req; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2697 | return 0; |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2698 | |
| 2699 | err: |
| 2700 | kmem_cache_free(dev_priv->requests, req); |
| 2701 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2702 | } |
| 2703 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2704 | void i915_gem_request_cancel(struct drm_i915_gem_request *req) |
| 2705 | { |
| 2706 | intel_ring_reserved_space_cancel(req->ringbuf); |
| 2707 | |
| 2708 | i915_gem_request_unreference(req); |
| 2709 | } |
| 2710 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2711 | struct drm_i915_gem_request * |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2712 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2713 | { |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2714 | struct drm_i915_gem_request *request; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2715 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2716 | list_for_each_entry(request, &ring->request_list, list) { |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2717 | if (i915_gem_request_completed(request, false)) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2718 | continue; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2719 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2720 | return request; |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2721 | } |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2722 | |
| 2723 | return NULL; |
| 2724 | } |
| 2725 | |
| 2726 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2727 | struct intel_engine_cs *ring) |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2728 | { |
| 2729 | struct drm_i915_gem_request *request; |
| 2730 | bool ring_hung; |
| 2731 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2732 | request = i915_gem_find_active_request(ring); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2733 | |
| 2734 | if (request == NULL) |
| 2735 | return; |
| 2736 | |
| 2737 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2738 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2739 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2740 | |
| 2741 | list_for_each_entry_continue(request, &ring->request_list, list) |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2742 | i915_set_reset_status(dev_priv, request->ctx, false); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2743 | } |
| 2744 | |
| 2745 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2746 | struct intel_engine_cs *ring) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2747 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2748 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2749 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2750 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2751 | obj = list_first_entry(&ring->active_list, |
| 2752 | struct drm_i915_gem_object, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2753 | ring_list[ring->id]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2754 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2755 | i915_gem_object_retire__read(obj, ring->id); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2756 | } |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2757 | |
| 2758 | /* |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2759 | * Clear the execlists queue up before freeing the requests, as those |
| 2760 | * are the ones that keep the context and ringbuffer backing objects |
| 2761 | * pinned in place. |
| 2762 | */ |
| 2763 | while (!list_empty(&ring->execlist_queue)) { |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2764 | struct drm_i915_gem_request *submit_req; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2765 | |
| 2766 | submit_req = list_first_entry(&ring->execlist_queue, |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2767 | struct drm_i915_gem_request, |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2768 | execlist_link); |
| 2769 | list_del(&submit_req->execlist_link); |
Mika Kuoppala | 1197b4f | 2015-01-13 11:32:24 +0200 | [diff] [blame] | 2770 | |
| 2771 | if (submit_req->ctx != ring->default_context) |
| 2772 | intel_lr_context_unpin(ring, submit_req->ctx); |
| 2773 | |
Nick Hoath | b3a3899 | 2015-02-19 16:30:47 +0000 | [diff] [blame] | 2774 | i915_gem_request_unreference(submit_req); |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2775 | } |
| 2776 | |
| 2777 | /* |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2778 | * We must free the requests after all the corresponding objects have |
| 2779 | * been moved off active lists. Which is the same order as the normal |
| 2780 | * retire_requests function does. This is important if object hold |
| 2781 | * implicit references on things like e.g. ppgtt address spaces through |
| 2782 | * the request. |
| 2783 | */ |
| 2784 | while (!list_empty(&ring->request_list)) { |
| 2785 | struct drm_i915_gem_request *request; |
| 2786 | |
| 2787 | request = list_first_entry(&ring->request_list, |
| 2788 | struct drm_i915_gem_request, |
| 2789 | list); |
| 2790 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2791 | i915_gem_request_retire(request); |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2792 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2793 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 2794 | /* This may not have been flushed before the reset, so clean it now */ |
| 2795 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2796 | } |
| 2797 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2798 | void i915_gem_restore_fences(struct drm_device *dev) |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2799 | { |
| 2800 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2801 | int i; |
| 2802 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2803 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2804 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2805 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2806 | /* |
| 2807 | * Commit delayed tiling changes if we have an object still |
| 2808 | * attached to the fence, otherwise just clear the fence. |
| 2809 | */ |
| 2810 | if (reg->obj) { |
| 2811 | i915_gem_object_update_fence(reg->obj, reg, |
| 2812 | reg->obj->tiling_mode); |
| 2813 | } else { |
| 2814 | i915_gem_write_fence(dev, i, NULL); |
| 2815 | } |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2816 | } |
| 2817 | } |
| 2818 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2819 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2820 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2821 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2822 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2823 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2824 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2825 | /* |
| 2826 | * Before we free the objects from the requests, we need to inspect |
| 2827 | * them for finding the guilty party. As the requests only borrow |
| 2828 | * their reference to the objects, the inspection must be done first. |
| 2829 | */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2830 | for_each_ring(ring, dev_priv, i) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2831 | i915_gem_reset_ring_status(dev_priv, ring); |
| 2832 | |
| 2833 | for_each_ring(ring, dev_priv, i) |
| 2834 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2835 | |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2836 | i915_gem_context_reset(dev); |
| 2837 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2838 | i915_gem_restore_fences(dev); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2839 | |
| 2840 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2841 | } |
| 2842 | |
| 2843 | /** |
| 2844 | * This function clears the request list as sequence numbers are passed. |
| 2845 | */ |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 2846 | void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2847 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2848 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2849 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2850 | |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2851 | /* Retire requests first as we use it above for the early return. |
| 2852 | * If we retire requests last, we may use a later seqno and so clear |
| 2853 | * the requests lists without clearing the active list, leading to |
| 2854 | * confusion. |
Chris Wilson | e910303 | 2014-01-07 11:45:14 +0000 | [diff] [blame] | 2855 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2856 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2857 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2858 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2859 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2860 | struct drm_i915_gem_request, |
| 2861 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2862 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2863 | if (!i915_gem_request_completed(request, true)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2864 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2865 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2866 | i915_gem_request_retire(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2867 | } |
| 2868 | |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2869 | /* Move any buffers on the active list that are no longer referenced |
| 2870 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2871 | * before we free the context associated with the requests. |
| 2872 | */ |
| 2873 | while (!list_empty(&ring->active_list)) { |
| 2874 | struct drm_i915_gem_object *obj; |
| 2875 | |
| 2876 | obj = list_first_entry(&ring->active_list, |
| 2877 | struct drm_i915_gem_object, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2878 | ring_list[ring->id]); |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2879 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2880 | if (!list_empty(&obj->last_read_req[ring->id]->list)) |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2881 | break; |
| 2882 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2883 | i915_gem_object_retire__read(obj, ring->id); |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2884 | } |
| 2885 | |
John Harrison | 581c26e8 | 2014-11-24 18:49:39 +0000 | [diff] [blame] | 2886 | if (unlikely(ring->trace_irq_req && |
| 2887 | i915_gem_request_completed(ring->trace_irq_req, true))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2888 | ring->irq_put(ring); |
John Harrison | 581c26e8 | 2014-11-24 18:49:39 +0000 | [diff] [blame] | 2889 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2890 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2891 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2892 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2893 | } |
| 2894 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2895 | bool |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2896 | i915_gem_retire_requests(struct drm_device *dev) |
| 2897 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2898 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2899 | struct intel_engine_cs *ring; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2900 | bool idle = true; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2901 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2902 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2903 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2904 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2905 | idle &= list_empty(&ring->request_list); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 2906 | if (i915.enable_execlists) { |
| 2907 | unsigned long flags; |
| 2908 | |
| 2909 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 2910 | idle &= list_empty(&ring->execlist_queue); |
| 2911 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 2912 | |
| 2913 | intel_execlists_retire_requests(ring); |
| 2914 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2915 | } |
| 2916 | |
| 2917 | if (idle) |
| 2918 | mod_delayed_work(dev_priv->wq, |
| 2919 | &dev_priv->mm.idle_work, |
| 2920 | msecs_to_jiffies(100)); |
| 2921 | |
| 2922 | return idle; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2923 | } |
| 2924 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2925 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2926 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2927 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2928 | struct drm_i915_private *dev_priv = |
| 2929 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 2930 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2931 | bool idle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2932 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2933 | /* Come back later if the device is busy... */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2934 | idle = false; |
| 2935 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2936 | idle = i915_gem_retire_requests(dev); |
| 2937 | mutex_unlock(&dev->struct_mutex); |
| 2938 | } |
| 2939 | if (!idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2940 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2941 | round_jiffies_up_relative(HZ)); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2942 | } |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2943 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2944 | static void |
| 2945 | i915_gem_idle_work_handler(struct work_struct *work) |
| 2946 | { |
| 2947 | struct drm_i915_private *dev_priv = |
| 2948 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 2949 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 423795c | 2015-04-07 16:21:08 +0100 | [diff] [blame] | 2950 | struct intel_engine_cs *ring; |
| 2951 | int i; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2952 | |
Chris Wilson | 423795c | 2015-04-07 16:21:08 +0100 | [diff] [blame] | 2953 | for_each_ring(ring, dev_priv, i) |
| 2954 | if (!list_empty(&ring->request_list)) |
| 2955 | return; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2956 | |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 2957 | intel_mark_idle(dev); |
| 2958 | |
| 2959 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2960 | struct intel_engine_cs *ring; |
| 2961 | int i; |
| 2962 | |
| 2963 | for_each_ring(ring, dev_priv, i) |
| 2964 | i915_gem_batch_pool_fini(&ring->batch_pool); |
| 2965 | |
| 2966 | mutex_unlock(&dev->struct_mutex); |
| 2967 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2968 | } |
| 2969 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2970 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2971 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2972 | * write domains, emitting any outstanding lazy request and retiring and |
| 2973 | * completed requests. |
| 2974 | */ |
| 2975 | static int |
| 2976 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2977 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2978 | int ret, i; |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2979 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2980 | if (!obj->active) |
| 2981 | return 0; |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 2982 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2983 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 2984 | struct drm_i915_gem_request *req; |
| 2985 | |
| 2986 | req = obj->last_read_req[i]; |
| 2987 | if (req == NULL) |
| 2988 | continue; |
| 2989 | |
| 2990 | if (list_empty(&req->list)) |
| 2991 | goto retire; |
| 2992 | |
| 2993 | ret = i915_gem_check_olr(req); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2994 | if (ret) |
| 2995 | return ret; |
| 2996 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2997 | if (i915_gem_request_completed(req, true)) { |
| 2998 | __i915_gem_request_retire__upto(req); |
| 2999 | retire: |
| 3000 | i915_gem_object_retire__read(obj, i); |
| 3001 | } |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3002 | } |
| 3003 | |
| 3004 | return 0; |
| 3005 | } |
| 3006 | |
| 3007 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3008 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 3009 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 3010 | * |
| 3011 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 3012 | * the timeout parameter. |
| 3013 | * -ETIME: object is still busy after timeout |
| 3014 | * -ERESTARTSYS: signal interrupted the wait |
| 3015 | * -ENONENT: object doesn't exist |
| 3016 | * Also possible, but rare: |
| 3017 | * -EAGAIN: GPU wedged |
| 3018 | * -ENOMEM: damn |
| 3019 | * -ENODEV: Internal IRQ fail |
| 3020 | * -E?: The add request failed |
| 3021 | * |
| 3022 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 3023 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 3024 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 3025 | * without holding struct_mutex the object may become re-busied before this |
| 3026 | * function completes. A similar but shorter * race condition exists in the busy |
| 3027 | * ioctl |
| 3028 | */ |
| 3029 | int |
| 3030 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 3031 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3032 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3033 | struct drm_i915_gem_wait *args = data; |
| 3034 | struct drm_i915_gem_object *obj; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3035 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3036 | unsigned reset_counter; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3037 | int i, n = 0; |
| 3038 | int ret; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3039 | |
Daniel Vetter | 11b5d51 | 2014-09-29 15:31:26 +0200 | [diff] [blame] | 3040 | if (args->flags != 0) |
| 3041 | return -EINVAL; |
| 3042 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3043 | ret = i915_mutex_lock_interruptible(dev); |
| 3044 | if (ret) |
| 3045 | return ret; |
| 3046 | |
| 3047 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 3048 | if (&obj->base == NULL) { |
| 3049 | mutex_unlock(&dev->struct_mutex); |
| 3050 | return -ENOENT; |
| 3051 | } |
| 3052 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3053 | /* Need to make sure the object gets inactive eventually. */ |
| 3054 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3055 | if (ret) |
| 3056 | goto out; |
| 3057 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3058 | if (!obj->active) |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 3059 | goto out; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3060 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3061 | /* Do this after OLR check to make sure we make forward progress polling |
Chris Wilson | 762e458 | 2015-03-04 18:09:26 +0000 | [diff] [blame] | 3062 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3063 | */ |
Chris Wilson | 762e458 | 2015-03-04 18:09:26 +0000 | [diff] [blame] | 3064 | if (args->timeout_ns == 0) { |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3065 | ret = -ETIME; |
| 3066 | goto out; |
| 3067 | } |
| 3068 | |
| 3069 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3070 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3071 | |
| 3072 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3073 | if (obj->last_read_req[i] == NULL) |
| 3074 | continue; |
| 3075 | |
| 3076 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); |
| 3077 | } |
| 3078 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3079 | mutex_unlock(&dev->struct_mutex); |
| 3080 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3081 | for (i = 0; i < n; i++) { |
| 3082 | if (ret == 0) |
| 3083 | ret = __i915_wait_request(req[i], reset_counter, true, |
| 3084 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
| 3085 | file->driver_priv); |
| 3086 | i915_gem_request_unreference__unlocked(req[i]); |
| 3087 | } |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 3088 | return ret; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3089 | |
| 3090 | out: |
| 3091 | drm_gem_object_unreference(&obj->base); |
| 3092 | mutex_unlock(&dev->struct_mutex); |
| 3093 | return ret; |
| 3094 | } |
| 3095 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3096 | static int |
| 3097 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3098 | struct intel_engine_cs *to, |
| 3099 | struct drm_i915_gem_request *req) |
| 3100 | { |
| 3101 | struct intel_engine_cs *from; |
| 3102 | int ret; |
| 3103 | |
| 3104 | from = i915_gem_request_get_ring(req); |
| 3105 | if (to == from) |
| 3106 | return 0; |
| 3107 | |
| 3108 | if (i915_gem_request_completed(req, true)) |
| 3109 | return 0; |
| 3110 | |
| 3111 | ret = i915_gem_check_olr(req); |
| 3112 | if (ret) |
| 3113 | return ret; |
| 3114 | |
| 3115 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
Chris Wilson | a6f766f | 2015-04-27 13:41:20 +0100 | [diff] [blame] | 3116 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3117 | ret = __i915_wait_request(req, |
Chris Wilson | a6f766f | 2015-04-27 13:41:20 +0100 | [diff] [blame] | 3118 | atomic_read(&i915->gpu_error.reset_counter), |
| 3119 | i915->mm.interruptible, |
| 3120 | NULL, |
| 3121 | &i915->rps.semaphores); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3122 | if (ret) |
| 3123 | return ret; |
| 3124 | |
| 3125 | i915_gem_object_retire_request(obj, req); |
| 3126 | } else { |
| 3127 | int idx = intel_ring_sync_index(from, to); |
| 3128 | u32 seqno = i915_gem_request_get_seqno(req); |
| 3129 | |
| 3130 | if (seqno <= from->semaphore.sync_seqno[idx]) |
| 3131 | return 0; |
| 3132 | |
| 3133 | trace_i915_gem_ring_sync_to(from, to, req); |
| 3134 | ret = to->semaphore.sync_to(to, from, seqno); |
| 3135 | if (ret) |
| 3136 | return ret; |
| 3137 | |
| 3138 | /* We use last_read_req because sync_to() |
| 3139 | * might have just caused seqno wrap under |
| 3140 | * the radar. |
| 3141 | */ |
| 3142 | from->semaphore.sync_seqno[idx] = |
| 3143 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); |
| 3144 | } |
| 3145 | |
| 3146 | return 0; |
| 3147 | } |
| 3148 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3149 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3150 | * i915_gem_object_sync - sync an object to a ring. |
| 3151 | * |
| 3152 | * @obj: object which may be in use on another ring. |
| 3153 | * @to: ring we wish to use the object on. May be NULL. |
| 3154 | * |
| 3155 | * This code is meant to abstract object synchronization with the GPU. |
| 3156 | * Calling with NULL implies synchronizing the object with the CPU |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3157 | * rather than a particular GPU ring. Conceptually we serialise writes |
| 3158 | * between engines inside the GPU. We only allow on engine to write |
| 3159 | * into a buffer at any time, but multiple readers. To ensure each has |
| 3160 | * a coherent view of memory, we must: |
| 3161 | * |
| 3162 | * - If there is an outstanding write request to the object, the new |
| 3163 | * request must wait for it to complete (either CPU or in hw, requests |
| 3164 | * on the same ring will be naturally ordered). |
| 3165 | * |
| 3166 | * - If we are a write request (pending_write_domain is set), the new |
| 3167 | * request must wait for outstanding read requests to complete. |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3168 | * |
| 3169 | * Returns 0 if successful, else propagates up the lower layer error. |
| 3170 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3171 | int |
| 3172 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3173 | struct intel_engine_cs *to) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3174 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3175 | const bool readonly = obj->base.pending_write_domain == 0; |
| 3176 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; |
| 3177 | int ret, i, n; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3178 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3179 | if (!obj->active) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3180 | return 0; |
| 3181 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3182 | if (to == NULL) |
| 3183 | return i915_gem_object_wait_rendering(obj, readonly); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3184 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3185 | n = 0; |
| 3186 | if (readonly) { |
| 3187 | if (obj->last_write_req) |
| 3188 | req[n++] = obj->last_write_req; |
| 3189 | } else { |
| 3190 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3191 | if (obj->last_read_req[i]) |
| 3192 | req[n++] = obj->last_read_req[i]; |
| 3193 | } |
| 3194 | for (i = 0; i < n; i++) { |
| 3195 | ret = __i915_gem_object_sync(obj, to, req[i]); |
| 3196 | if (ret) |
| 3197 | return ret; |
| 3198 | } |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3199 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3200 | return 0; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3201 | } |
| 3202 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3203 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 3204 | { |
| 3205 | u32 old_write_domain, old_read_domains; |
| 3206 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3207 | /* Force a pagefault for domain tracking on next user access */ |
| 3208 | i915_gem_release_mmap(obj); |
| 3209 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 3210 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3211 | return; |
| 3212 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 3213 | /* Wait for any direct GTT access to complete */ |
| 3214 | mb(); |
| 3215 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3216 | old_read_domains = obj->base.read_domains; |
| 3217 | old_write_domain = obj->base.write_domain; |
| 3218 | |
| 3219 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 3220 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 3221 | |
| 3222 | trace_i915_gem_object_change_domain(obj, |
| 3223 | old_read_domains, |
| 3224 | old_write_domain); |
| 3225 | } |
| 3226 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3227 | int i915_vma_unbind(struct i915_vma *vma) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3228 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3229 | struct drm_i915_gem_object *obj = vma->obj; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3230 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 3231 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3232 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3233 | if (list_empty(&vma->vma_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3234 | return 0; |
| 3235 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3236 | if (!drm_mm_node_allocated(&vma->node)) { |
| 3237 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3238 | return 0; |
| 3239 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 3240 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3241 | if (vma->pin_count) |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 3242 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 3244 | BUG_ON(obj->pages == NULL); |
| 3245 | |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 3246 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3247 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3248 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 3249 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 3250 | * should be safe and we need to cleanup or else we might |
| 3251 | * cause memory corruption through use-after-free. |
| 3252 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3253 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3254 | if (i915_is_ggtt(vma->vm) && |
| 3255 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3256 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3257 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3258 | /* release the fence reg _after_ flushing */ |
| 3259 | ret = i915_gem_object_put_fence(obj); |
| 3260 | if (ret) |
| 3261 | return ret; |
| 3262 | } |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 3263 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3264 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3265 | |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 3266 | vma->vm->unbind_vma(vma); |
Mika Kuoppala | 5e562f1 | 2015-04-30 11:02:31 +0300 | [diff] [blame] | 3267 | vma->bound = 0; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3268 | |
Chris Wilson | 64bf930 | 2014-02-25 14:23:28 +0000 | [diff] [blame] | 3269 | list_del_init(&vma->mm_list); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3270 | if (i915_is_ggtt(vma->vm)) { |
| 3271 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3272 | obj->map_and_fenceable = false; |
| 3273 | } else if (vma->ggtt_view.pages) { |
| 3274 | sg_free_table(vma->ggtt_view.pages); |
| 3275 | kfree(vma->ggtt_view.pages); |
| 3276 | vma->ggtt_view.pages = NULL; |
| 3277 | } |
| 3278 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3279 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3280 | drm_mm_remove_node(&vma->node); |
| 3281 | i915_gem_vma_destroy(vma); |
| 3282 | |
| 3283 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 3284 | * no more VMAs exist. */ |
Armin Reese | 9490edb | 2014-07-11 10:20:07 -0700 | [diff] [blame] | 3285 | if (list_empty(&obj->vma_list)) { |
| 3286 | i915_gem_gtt_finish_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3287 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Armin Reese | 9490edb | 2014-07-11 10:20:07 -0700 | [diff] [blame] | 3288 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3289 | |
Chris Wilson | 70903c3 | 2013-12-04 09:59:09 +0000 | [diff] [blame] | 3290 | /* And finally now the object is completely decoupled from this vma, |
| 3291 | * we can drop its hold on the backing storage and allow it to be |
| 3292 | * reaped by the shrinker. |
| 3293 | */ |
| 3294 | i915_gem_object_unpin_pages(obj); |
| 3295 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3296 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 3297 | } |
| 3298 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3299 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3300 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3301 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3302 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3303 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3304 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3305 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3306 | for_each_ring(ring, dev_priv, i) { |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3307 | if (!i915.enable_execlists) { |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3308 | struct drm_i915_gem_request *req; |
| 3309 | |
| 3310 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3311 | if (ret) |
| 3312 | return ret; |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3313 | |
| 3314 | ret = i915_switch_context(req->ring, ring->default_context); |
| 3315 | if (ret) { |
| 3316 | i915_gem_request_cancel(req); |
| 3317 | return ret; |
| 3318 | } |
| 3319 | |
| 3320 | i915_add_request_no_flush(req->ring); |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3321 | } |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 3322 | |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3323 | WARN_ON(ring->outstanding_lazy_request); |
| 3324 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3325 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3326 | if (ret) |
| 3327 | return ret; |
| 3328 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3329 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3330 | WARN_ON(i915_verify_lists(dev)); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3331 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3332 | } |
| 3333 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3334 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 3335 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3336 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3337 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3338 | int fence_reg; |
| 3339 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3340 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3341 | if (INTEL_INFO(dev)->gen >= 6) { |
| 3342 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 3343 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 3344 | } else { |
| 3345 | fence_reg = FENCE_REG_965_0; |
| 3346 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 3347 | } |
| 3348 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3349 | fence_reg += reg * 8; |
| 3350 | |
| 3351 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 3352 | * we split the 64-bit update into two 32-bit writes. In order |
| 3353 | * for a partial fence not to be evaluated between writes, we |
| 3354 | * precede the update with write to turn off the fence register, |
| 3355 | * and only enable the fence as the last step. |
| 3356 | * |
| 3357 | * For extra levels of paranoia, we make sure each step lands |
| 3358 | * before applying the next step. |
| 3359 | */ |
| 3360 | I915_WRITE(fence_reg, 0); |
| 3361 | POSTING_READ(fence_reg); |
| 3362 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3363 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3364 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3365 | uint64_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3366 | |
Bob Paauwe | af1a730 | 2014-12-18 09:51:26 -0800 | [diff] [blame] | 3367 | /* Adjust fence size to match tiled area */ |
| 3368 | if (obj->tiling_mode != I915_TILING_NONE) { |
| 3369 | uint32_t row_size = obj->stride * |
| 3370 | (obj->tiling_mode == I915_TILING_Y ? 32 : 8); |
| 3371 | size = (size / row_size) * row_size; |
| 3372 | } |
| 3373 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3374 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3375 | 0xfffff000) << 32; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3376 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3377 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3378 | if (obj->tiling_mode == I915_TILING_Y) |
| 3379 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 3380 | val |= I965_FENCE_REG_VALID; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 3381 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3382 | I915_WRITE(fence_reg + 4, val >> 32); |
| 3383 | POSTING_READ(fence_reg + 4); |
| 3384 | |
| 3385 | I915_WRITE(fence_reg + 0, val); |
| 3386 | POSTING_READ(fence_reg); |
| 3387 | } else { |
| 3388 | I915_WRITE(fence_reg + 4, 0); |
| 3389 | POSTING_READ(fence_reg + 4); |
| 3390 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3391 | } |
| 3392 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3393 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 3394 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3395 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3396 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3397 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3398 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3399 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3400 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3401 | int pitch_val; |
| 3402 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3403 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3404 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3405 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3406 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3407 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 3408 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3409 | |
| 3410 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 3411 | tile_width = 128; |
| 3412 | else |
| 3413 | tile_width = 512; |
| 3414 | |
| 3415 | /* Note: pitch better be a power of two tile widths */ |
| 3416 | pitch_val = obj->stride / tile_width; |
| 3417 | pitch_val = ffs(pitch_val) - 1; |
| 3418 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3419 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3420 | if (obj->tiling_mode == I915_TILING_Y) |
| 3421 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3422 | val |= I915_FENCE_SIZE_BITS(size); |
| 3423 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3424 | val |= I830_FENCE_REG_VALID; |
| 3425 | } else |
| 3426 | val = 0; |
| 3427 | |
| 3428 | if (reg < 8) |
| 3429 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3430 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3431 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 3432 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3433 | I915_WRITE(reg, val); |
| 3434 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3435 | } |
| 3436 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3437 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 3438 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3439 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3440 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3441 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3442 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3443 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3444 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3445 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3446 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3447 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3448 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3449 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3450 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 3451 | i915_gem_obj_ggtt_offset(obj), size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 3452 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3453 | pitch_val = obj->stride / 128; |
| 3454 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3455 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3456 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3457 | if (obj->tiling_mode == I915_TILING_Y) |
| 3458 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3459 | val |= I830_FENCE_SIZE_BITS(size); |
| 3460 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3461 | val |= I830_FENCE_REG_VALID; |
| 3462 | } else |
| 3463 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 3464 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3465 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 3466 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 3467 | } |
| 3468 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3469 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 3470 | { |
| 3471 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 3472 | } |
| 3473 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3474 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 3475 | struct drm_i915_gem_object *obj) |
| 3476 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3477 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3478 | |
| 3479 | /* Ensure that all CPU reads are completed before installing a fence |
| 3480 | * and all writes before removing the fence. |
| 3481 | */ |
| 3482 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 3483 | mb(); |
| 3484 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3485 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 3486 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 3487 | obj->stride, obj->tiling_mode); |
| 3488 | |
Rodrigo Vivi | ce38ab0 | 2014-12-04 06:48:10 -0800 | [diff] [blame] | 3489 | if (IS_GEN2(dev)) |
| 3490 | i830_write_fence_reg(dev, reg, obj); |
| 3491 | else if (IS_GEN3(dev)) |
| 3492 | i915_write_fence_reg(dev, reg, obj); |
| 3493 | else if (INTEL_INFO(dev)->gen >= 4) |
| 3494 | i965_write_fence_reg(dev, reg, obj); |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3495 | |
| 3496 | /* And similarly be paranoid that no direct access to this region |
| 3497 | * is reordered to before the fence is installed. |
| 3498 | */ |
| 3499 | if (i915_gem_object_needs_mb(obj)) |
| 3500 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3501 | } |
| 3502 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3503 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 3504 | struct drm_i915_fence_reg *fence) |
| 3505 | { |
| 3506 | return fence - dev_priv->fence_regs; |
| 3507 | } |
| 3508 | |
| 3509 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 3510 | struct drm_i915_fence_reg *fence, |
| 3511 | bool enable) |
| 3512 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 3513 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3514 | int reg = fence_number(dev_priv, fence); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3515 | |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3516 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3517 | |
| 3518 | if (enable) { |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3519 | obj->fence_reg = reg; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3520 | fence->obj = obj; |
| 3521 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 3522 | } else { |
| 3523 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3524 | fence->obj = NULL; |
| 3525 | list_del_init(&fence->lru_list); |
| 3526 | } |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3527 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3528 | } |
| 3529 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3530 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3531 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3532 | { |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 3533 | if (obj->last_fenced_req) { |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 3534 | int ret = i915_wait_request(obj->last_fenced_req); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 3535 | if (ret) |
| 3536 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3537 | |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 3538 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3539 | } |
| 3540 | |
| 3541 | return 0; |
| 3542 | } |
| 3543 | |
| 3544 | int |
| 3545 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 3546 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3547 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3548 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3549 | int ret; |
| 3550 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3551 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3552 | if (ret) |
| 3553 | return ret; |
| 3554 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3555 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 3556 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3557 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3558 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 3559 | |
Daniel Vetter | aff10b30 | 2014-02-14 14:06:05 +0100 | [diff] [blame] | 3560 | if (WARN_ON(fence->pin_count)) |
| 3561 | return -EBUSY; |
| 3562 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3563 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3564 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3565 | |
| 3566 | return 0; |
| 3567 | } |
| 3568 | |
| 3569 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 3570 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3571 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3572 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3573 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3574 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3575 | |
| 3576 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3577 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3578 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 3579 | reg = &dev_priv->fence_regs[i]; |
| 3580 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3581 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3582 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3583 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3584 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3585 | } |
| 3586 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3587 | if (avail == NULL) |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3588 | goto deadlock; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3589 | |
| 3590 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3591 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3592 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3593 | continue; |
| 3594 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3595 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3596 | } |
| 3597 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3598 | deadlock: |
| 3599 | /* Wait for completion of pending flips which consume fences */ |
| 3600 | if (intel_has_pending_fb_unpin(dev)) |
| 3601 | return ERR_PTR(-EAGAIN); |
| 3602 | |
| 3603 | return ERR_PTR(-EDEADLK); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3604 | } |
| 3605 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3606 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3607 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3608 | * @obj: object to map through a fence reg |
| 3609 | * |
| 3610 | * When mapping objects through the GTT, userspace wants to be able to write |
| 3611 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3612 | * This function walks the fence regs looking for a free one for @obj, |
| 3613 | * stealing one if it can't find any. |
| 3614 | * |
| 3615 | * It then sets up the reg based on the object's properties: address, pitch |
| 3616 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3617 | * |
| 3618 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3619 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3620 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 3621 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3622 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3623 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3624 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3625 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3626 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3627 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3628 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3629 | /* Have we updated the tiling parameters upon the object and so |
| 3630 | * will need to serialise the write to the associated fence register? |
| 3631 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3632 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3633 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3634 | if (ret) |
| 3635 | return ret; |
| 3636 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3637 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3638 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3639 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3640 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3641 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3642 | list_move_tail(®->lru_list, |
| 3643 | &dev_priv->mm.fence_list); |
| 3644 | return 0; |
| 3645 | } |
| 3646 | } else if (enable) { |
Chris Wilson | e6a8446 | 2014-08-11 12:00:12 +0200 | [diff] [blame] | 3647 | if (WARN_ON(!obj->map_and_fenceable)) |
| 3648 | return -EINVAL; |
| 3649 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3650 | reg = i915_find_fence_reg(dev); |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3651 | if (IS_ERR(reg)) |
| 3652 | return PTR_ERR(reg); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3653 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3654 | if (reg->obj) { |
| 3655 | struct drm_i915_gem_object *old = reg->obj; |
| 3656 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3657 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3658 | if (ret) |
| 3659 | return ret; |
| 3660 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3661 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3662 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3663 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3664 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3665 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3666 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3667 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3668 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3669 | } |
| 3670 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3671 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3672 | unsigned long cache_level) |
| 3673 | { |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3674 | struct drm_mm_node *gtt_space = &vma->node; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3675 | struct drm_mm_node *other; |
| 3676 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3677 | /* |
| 3678 | * On some machines we have to be careful when putting differing types |
| 3679 | * of snoopable memory together to avoid the prefetcher crossing memory |
| 3680 | * domains and dying. During vm initialisation, we decide whether or not |
| 3681 | * these constraints apply and set the drm_mm.color_adjust |
| 3682 | * appropriately. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3683 | */ |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3684 | if (vma->vm->mm.color_adjust == NULL) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3685 | return true; |
| 3686 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3687 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3688 | return true; |
| 3689 | |
| 3690 | if (list_empty(>t_space->node_list)) |
| 3691 | return true; |
| 3692 | |
| 3693 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3694 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3695 | return false; |
| 3696 | |
| 3697 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3698 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3699 | return false; |
| 3700 | |
| 3701 | return true; |
| 3702 | } |
| 3703 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3704 | /** |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3705 | * Finds free space in the GTT aperture and binds the object or a view of it |
| 3706 | * there. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3707 | */ |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3708 | static struct i915_vma * |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3709 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3710 | struct i915_address_space *vm, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3711 | const struct i915_ggtt_view *ggtt_view, |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3712 | unsigned alignment, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3713 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3714 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3715 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3716 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3717 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3718 | unsigned long start = |
| 3719 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3720 | unsigned long end = |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3721 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3722 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3723 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3724 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3725 | if (i915_is_ggtt(vm)) { |
| 3726 | u32 view_size; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3727 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3728 | if (WARN_ON(!ggtt_view)) |
| 3729 | return ERR_PTR(-EINVAL); |
| 3730 | |
| 3731 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
| 3732 | |
| 3733 | fence_size = i915_gem_get_gtt_size(dev, |
| 3734 | view_size, |
| 3735 | obj->tiling_mode); |
| 3736 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3737 | view_size, |
| 3738 | obj->tiling_mode, |
| 3739 | true); |
| 3740 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, |
| 3741 | view_size, |
| 3742 | obj->tiling_mode, |
| 3743 | false); |
| 3744 | size = flags & PIN_MAPPABLE ? fence_size : view_size; |
| 3745 | } else { |
| 3746 | fence_size = i915_gem_get_gtt_size(dev, |
| 3747 | obj->base.size, |
| 3748 | obj->tiling_mode); |
| 3749 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3750 | obj->base.size, |
| 3751 | obj->tiling_mode, |
| 3752 | true); |
| 3753 | unfenced_alignment = |
| 3754 | i915_gem_get_gtt_alignment(dev, |
| 3755 | obj->base.size, |
| 3756 | obj->tiling_mode, |
| 3757 | false); |
| 3758 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
| 3759 | } |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3760 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3761 | if (alignment == 0) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3762 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3763 | unfenced_alignment; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3764 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3765 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
| 3766 | ggtt_view ? ggtt_view->type : 0, |
| 3767 | alignment); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3768 | return ERR_PTR(-EINVAL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3769 | } |
| 3770 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3771 | /* If binding the object/GGTT view requires more space than the entire |
| 3772 | * aperture has, reject it early before evicting everything in a vain |
| 3773 | * attempt to find space. |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3774 | */ |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3775 | if (size > end) { |
| 3776 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n", |
| 3777 | ggtt_view ? ggtt_view->type : 0, |
| 3778 | size, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3779 | flags & PIN_MAPPABLE ? "mappable" : "total", |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3780 | end); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3781 | return ERR_PTR(-E2BIG); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3782 | } |
| 3783 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3784 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3785 | if (ret) |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3786 | return ERR_PTR(ret); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3787 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3788 | i915_gem_object_pin_pages(obj); |
| 3789 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3790 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
| 3791 | i915_gem_obj_lookup_or_create_vma(obj, vm); |
| 3792 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3793 | if (IS_ERR(vma)) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3794 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3795 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3796 | search_free: |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3797 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3798 | size, alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3799 | obj->cache_level, |
| 3800 | start, end, |
Lauri Kasanen | 62347f9 | 2014-04-02 20:03:57 +0300 | [diff] [blame] | 3801 | DRM_MM_SEARCH_DEFAULT, |
| 3802 | DRM_MM_CREATE_DEFAULT); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3803 | if (ret) { |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 3804 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3805 | obj->cache_level, |
| 3806 | start, end, |
| 3807 | flags); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3808 | if (ret == 0) |
| 3809 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3810 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3811 | goto err_free_vma; |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3812 | } |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3813 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3814 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3815 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3816 | } |
| 3817 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 3818 | ret = i915_gem_gtt_prepare_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3819 | if (ret) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3820 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3821 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3822 | trace_i915_vma_bind(vma, flags); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 3823 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3824 | if (ret) |
| 3825 | goto err_finish_gtt; |
| 3826 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3827 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3828 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3829 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3830 | return vma; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3831 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3832 | err_finish_gtt: |
| 3833 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3834 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3835 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3836 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3837 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3838 | vma = ERR_PTR(ret); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3839 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3840 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3841 | return vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3842 | } |
| 3843 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3844 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3845 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3846 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3847 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3848 | /* If we don't have a page list set up, then we're not pinned |
| 3849 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3850 | * again at bind time. |
| 3851 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3852 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3853 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3854 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3855 | /* |
| 3856 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3857 | * marked as wc by the system, or the system is cache-coherent. |
| 3858 | */ |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 3859 | if (obj->stolen || obj->phys_handle) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3860 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3861 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3862 | /* If the GPU is snooping the contents of the CPU cache, |
| 3863 | * we do not need to manually clear the CPU cache lines. However, |
| 3864 | * the caches are only snooped when the render cache is |
| 3865 | * flushed/invalidated. As we always have to emit invalidations |
| 3866 | * and flushes when moving into and out of the RENDER domain, correct |
| 3867 | * snooping behaviour occurs naturally as the result of our domain |
| 3868 | * tracking. |
| 3869 | */ |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3870 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
| 3871 | obj->cache_dirty = true; |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3872 | return false; |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3873 | } |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3874 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3875 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3876 | drm_clflush_sg(obj->pages); |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3877 | obj->cache_dirty = false; |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3878 | |
| 3879 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3880 | } |
| 3881 | |
| 3882 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3883 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3884 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3885 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3886 | uint32_t old_write_domain; |
| 3887 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3888 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3889 | return; |
| 3890 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3891 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3892 | * to it immediately go to main memory as far as we know, so there's |
| 3893 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3894 | * |
| 3895 | * However, we do have to enforce the order so that all writes through |
| 3896 | * the GTT land before any writes to the device, such as updates to |
| 3897 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3898 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3899 | wmb(); |
| 3900 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3901 | old_write_domain = obj->base.write_domain; |
| 3902 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3903 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3904 | intel_fb_obj_flush(obj, false); |
| 3905 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3906 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3907 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3908 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3909 | } |
| 3910 | |
| 3911 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3912 | static void |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3913 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3914 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3915 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3916 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3917 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3918 | return; |
| 3919 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3920 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3921 | i915_gem_chipset_flush(obj->base.dev); |
| 3922 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3923 | old_write_domain = obj->base.write_domain; |
| 3924 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3925 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3926 | intel_fb_obj_flush(obj, false); |
| 3927 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3928 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3929 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3930 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3931 | } |
| 3932 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3933 | /** |
| 3934 | * Moves a single object to the GTT read, and possibly write domain. |
| 3935 | * |
| 3936 | * This function returns when the move is complete, including waiting on |
| 3937 | * flushes to occur. |
| 3938 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3939 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3940 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3941 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3942 | uint32_t old_write_domain, old_read_domains; |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3943 | struct i915_vma *vma; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3944 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3945 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3946 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3947 | return 0; |
| 3948 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3949 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3950 | if (ret) |
| 3951 | return ret; |
| 3952 | |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3953 | /* Flush and acquire obj->pages so that we are coherent through |
| 3954 | * direct access in memory with previous cached writes through |
| 3955 | * shmemfs and that our cache domain tracking remains valid. |
| 3956 | * For example, if the obj->filp was moved to swap without us |
| 3957 | * being notified and releasing the pages, we would mistakenly |
| 3958 | * continue to assume that the obj remained out of the CPU cached |
| 3959 | * domain. |
| 3960 | */ |
| 3961 | ret = i915_gem_object_get_pages(obj); |
| 3962 | if (ret) |
| 3963 | return ret; |
| 3964 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3965 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3966 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3967 | /* Serialise direct access to this object with the barriers for |
| 3968 | * coherent writes from the GPU, by effectively invalidating the |
| 3969 | * GTT domain upon first access. |
| 3970 | */ |
| 3971 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3972 | mb(); |
| 3973 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3974 | old_write_domain = obj->base.write_domain; |
| 3975 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3976 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3977 | /* It should now be out of any other write domains, and we can update |
| 3978 | * the domain values for our changes. |
| 3979 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3980 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3981 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3982 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3983 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3984 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3985 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3986 | } |
| 3987 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3988 | if (write) |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 3989 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3990 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3991 | trace_i915_gem_object_change_domain(obj, |
| 3992 | old_read_domains, |
| 3993 | old_write_domain); |
| 3994 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3995 | /* And bump the LRU for this access */ |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3996 | vma = i915_gem_obj_to_ggtt(obj); |
| 3997 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3998 | list_move_tail(&vma->mm_list, |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3999 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 4000 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4001 | return 0; |
| 4002 | } |
| 4003 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4004 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 4005 | enum i915_cache_level cache_level) |
| 4006 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 4007 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 4008 | struct i915_vma *vma, *next; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4009 | int ret; |
| 4010 | |
| 4011 | if (obj->cache_level == cache_level) |
| 4012 | return 0; |
| 4013 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4014 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4015 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 4016 | return -EBUSY; |
| 4017 | } |
| 4018 | |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 4019 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 4020 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4021 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 4022 | if (ret) |
| 4023 | return ret; |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 4024 | } |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 4025 | } |
| 4026 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 4027 | if (i915_gem_obj_bound_any(obj)) { |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 4028 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4029 | if (ret) |
| 4030 | return ret; |
| 4031 | |
| 4032 | i915_gem_object_finish_gtt(obj); |
| 4033 | |
| 4034 | /* Before SandyBridge, you could not use tiling or fence |
| 4035 | * registers with snooped memory, so relinquish any fences |
| 4036 | * currently pointing to our region in the aperture. |
| 4037 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 4038 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4039 | ret = i915_gem_object_put_fence(obj); |
| 4040 | if (ret) |
| 4041 | return ret; |
| 4042 | } |
| 4043 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 4044 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4045 | if (drm_mm_node_allocated(&vma->node)) { |
| 4046 | ret = i915_vma_bind(vma, cache_level, |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 4047 | PIN_UPDATE); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4048 | if (ret) |
| 4049 | return ret; |
| 4050 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4051 | } |
| 4052 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 4053 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4054 | vma->node.color = cache_level; |
| 4055 | obj->cache_level = cache_level; |
| 4056 | |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 4057 | if (obj->cache_dirty && |
| 4058 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 4059 | cpu_write_needs_clflush(obj)) { |
| 4060 | if (i915_gem_clflush_object(obj, true)) |
| 4061 | i915_gem_chipset_flush(obj->base.dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4062 | } |
| 4063 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 4064 | return 0; |
| 4065 | } |
| 4066 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4067 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 4068 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4069 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4070 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4071 | struct drm_i915_gem_object *obj; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4072 | |
| 4073 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 432be69 | 2015-05-07 12:14:55 +0100 | [diff] [blame] | 4074 | if (&obj->base == NULL) |
| 4075 | return -ENOENT; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4076 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 4077 | switch (obj->cache_level) { |
| 4078 | case I915_CACHE_LLC: |
| 4079 | case I915_CACHE_L3_LLC: |
| 4080 | args->caching = I915_CACHING_CACHED; |
| 4081 | break; |
| 4082 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 4083 | case I915_CACHE_WT: |
| 4084 | args->caching = I915_CACHING_DISPLAY; |
| 4085 | break; |
| 4086 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 4087 | default: |
| 4088 | args->caching = I915_CACHING_NONE; |
| 4089 | break; |
| 4090 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4091 | |
Chris Wilson | 432be69 | 2015-05-07 12:14:55 +0100 | [diff] [blame] | 4092 | drm_gem_object_unreference_unlocked(&obj->base); |
| 4093 | return 0; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4094 | } |
| 4095 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4096 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 4097 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4098 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4099 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4100 | struct drm_i915_gem_object *obj; |
| 4101 | enum i915_cache_level level; |
| 4102 | int ret; |
| 4103 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4104 | switch (args->caching) { |
| 4105 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4106 | level = I915_CACHE_NONE; |
| 4107 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4108 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4109 | level = I915_CACHE_LLC; |
| 4110 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 4111 | case I915_CACHING_DISPLAY: |
| 4112 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 4113 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4114 | default: |
| 4115 | return -EINVAL; |
| 4116 | } |
| 4117 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 4118 | ret = i915_mutex_lock_interruptible(dev); |
| 4119 | if (ret) |
| 4120 | return ret; |
| 4121 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4122 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4123 | if (&obj->base == NULL) { |
| 4124 | ret = -ENOENT; |
| 4125 | goto unlock; |
| 4126 | } |
| 4127 | |
| 4128 | ret = i915_gem_object_set_cache_level(obj, level); |
| 4129 | |
| 4130 | drm_gem_object_unreference(&obj->base); |
| 4131 | unlock: |
| 4132 | mutex_unlock(&dev->struct_mutex); |
| 4133 | return ret; |
| 4134 | } |
| 4135 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4136 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4137 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 4138 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 4139 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4140 | */ |
| 4141 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4142 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 4143 | u32 alignment, |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4144 | struct intel_engine_cs *pipelined, |
| 4145 | const struct i915_ggtt_view *view) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4146 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4147 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4148 | int ret; |
| 4149 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4150 | ret = i915_gem_object_sync(obj, pipelined); |
| 4151 | if (ret) |
| 4152 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4153 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4154 | /* Mark the pin_display early so that we account for the |
| 4155 | * display coherency whilst setting up the cache domains. |
| 4156 | */ |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4157 | obj->pin_display++; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4158 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4159 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 4160 | * a result, we make sure that the pinning that is about to occur is |
| 4161 | * done with uncached PTEs. This is lowest common denominator for all |
| 4162 | * chipsets. |
| 4163 | * |
| 4164 | * However for gen6+, we could do better by using the GFDT bit instead |
| 4165 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 4166 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 4167 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 4168 | ret = i915_gem_object_set_cache_level(obj, |
| 4169 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4170 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4171 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4172 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4173 | /* As the user may map the buffer once pinned in the display plane |
| 4174 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 4175 | * always use map_and_fenceable for all scanout buffers. |
| 4176 | */ |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 4177 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
| 4178 | view->type == I915_GGTT_VIEW_NORMAL ? |
| 4179 | PIN_MAPPABLE : 0); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4180 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4181 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4182 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 4183 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 4184 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4185 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4186 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4187 | |
| 4188 | /* It should now be out of any other write domains, and we can update |
| 4189 | * the domain values for our changes. |
| 4190 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 4191 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4192 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4193 | |
| 4194 | trace_i915_gem_object_change_domain(obj, |
| 4195 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4196 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4197 | |
| 4198 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4199 | |
| 4200 | err_unpin_display: |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4201 | obj->pin_display--; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4202 | return ret; |
| 4203 | } |
| 4204 | |
| 4205 | void |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4206 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
| 4207 | const struct i915_ggtt_view *view) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4208 | { |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4209 | if (WARN_ON(obj->pin_display == 0)) |
| 4210 | return; |
| 4211 | |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4212 | i915_gem_object_ggtt_unpin_view(obj, view); |
| 4213 | |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4214 | obj->pin_display--; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4215 | } |
| 4216 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4217 | /** |
| 4218 | * Moves a single object to the CPU read, and possibly write domain. |
| 4219 | * |
| 4220 | * This function returns when the move is complete, including waiting on |
| 4221 | * flushes to occur. |
| 4222 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 4223 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 4224 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4225 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4226 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4227 | int ret; |
| 4228 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 4229 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 4230 | return 0; |
| 4231 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 4232 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 4233 | if (ret) |
| 4234 | return ret; |
| 4235 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4236 | i915_gem_object_flush_gtt_write_domain(obj); |
| 4237 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4238 | old_write_domain = obj->base.write_domain; |
| 4239 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4240 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4241 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4242 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 4243 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4244 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4245 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4246 | } |
| 4247 | |
| 4248 | /* It should now be out of any other write domains, and we can update |
| 4249 | * the domain values for our changes. |
| 4250 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4251 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4252 | |
| 4253 | /* If we're writing through the CPU, then the GPU read domains will |
| 4254 | * need to be invalidated at next use. |
| 4255 | */ |
| 4256 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4257 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4258 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4259 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4260 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4261 | if (write) |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 4262 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4263 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4264 | trace_i915_gem_object_change_domain(obj, |
| 4265 | old_read_domains, |
| 4266 | old_write_domain); |
| 4267 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4268 | return 0; |
| 4269 | } |
| 4270 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4271 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4272 | * emitted over 20 msec ago. |
| 4273 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4274 | * Note that if we were to use the current jiffies each time around the loop, |
| 4275 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4276 | * render a frame was over 20ms. |
| 4277 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4278 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4279 | * relatively low latency when blocking on a particular request to finish. |
| 4280 | */ |
| 4281 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4282 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4283 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4284 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4285 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Chris Wilson | d0bc54f | 2015-05-21 21:01:48 +0100 | [diff] [blame] | 4286 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4287 | struct drm_i915_gem_request *request, *target = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 4288 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4289 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4290 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 4291 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4292 | if (ret) |
| 4293 | return ret; |
| 4294 | |
| 4295 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 4296 | if (ret) |
| 4297 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 4298 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4299 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4300 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4301 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4302 | break; |
| 4303 | |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4304 | target = request; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4305 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 4306 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 4307 | if (target) |
| 4308 | i915_gem_request_reference(target); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4309 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4310 | |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4311 | if (target == NULL) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4312 | return 0; |
| 4313 | |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 4314 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4315 | if (ret == 0) |
| 4316 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4317 | |
Chris Wilson | 41037f9 | 2015-03-27 11:01:36 +0000 | [diff] [blame] | 4318 | i915_gem_request_unreference__unlocked(target); |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 4319 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4320 | return ret; |
| 4321 | } |
| 4322 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4323 | static bool |
| 4324 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4325 | { |
| 4326 | struct drm_i915_gem_object *obj = vma->obj; |
| 4327 | |
| 4328 | if (alignment && |
| 4329 | vma->node.start & (alignment - 1)) |
| 4330 | return true; |
| 4331 | |
| 4332 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4333 | return true; |
| 4334 | |
| 4335 | if (flags & PIN_OFFSET_BIAS && |
| 4336 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4337 | return true; |
| 4338 | |
| 4339 | return false; |
| 4340 | } |
| 4341 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4342 | static int |
| 4343 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, |
| 4344 | struct i915_address_space *vm, |
| 4345 | const struct i915_ggtt_view *ggtt_view, |
| 4346 | uint32_t alignment, |
| 4347 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4348 | { |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4349 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4350 | struct i915_vma *vma; |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4351 | unsigned bound; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4352 | int ret; |
| 4353 | |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4354 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4355 | return -ENODEV; |
| 4356 | |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 4357 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4358 | return -EINVAL; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4359 | |
Chris Wilson | c826c44 | 2014-10-31 13:53:53 +0000 | [diff] [blame] | 4360 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
| 4361 | return -EINVAL; |
| 4362 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4363 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
| 4364 | return -EINVAL; |
| 4365 | |
| 4366 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : |
| 4367 | i915_gem_obj_to_vma(obj, vm); |
| 4368 | |
| 4369 | if (IS_ERR(vma)) |
| 4370 | return PTR_ERR(vma); |
| 4371 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4372 | if (vma) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4373 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4374 | return -EBUSY; |
| 4375 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4376 | if (i915_vma_misplaced(vma, alignment, flags)) { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4377 | unsigned long offset; |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 4378 | offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4379 | i915_gem_obj_offset(obj, vm); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4380 | WARN(vma->pin_count, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4381 | "bo is already pinned in %s with incorrect alignment:" |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4382 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4383 | " obj->map_and_fenceable=%d\n", |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4384 | ggtt_view ? "ggtt" : "ppgtt", |
| 4385 | offset, |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4386 | alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4387 | !!(flags & PIN_MAPPABLE), |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4388 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4389 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4390 | if (ret) |
| 4391 | return ret; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4392 | |
| 4393 | vma = NULL; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4394 | } |
| 4395 | } |
| 4396 | |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4397 | bound = vma ? vma->bound : 0; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4398 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4399 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
| 4400 | flags); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 4401 | if (IS_ERR(vma)) |
| 4402 | return PTR_ERR(vma); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 4403 | } else { |
| 4404 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4405 | if (ret) |
| 4406 | return ret; |
| 4407 | } |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 4408 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 4409 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
| 4410 | (bound ^ vma->bound) & GLOBAL_BIND) { |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4411 | bool mappable, fenceable; |
| 4412 | u32 fence_size, fence_alignment; |
| 4413 | |
| 4414 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
| 4415 | obj->base.size, |
| 4416 | obj->tiling_mode); |
| 4417 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
| 4418 | obj->base.size, |
| 4419 | obj->tiling_mode, |
| 4420 | true); |
| 4421 | |
| 4422 | fenceable = (vma->node.size == fence_size && |
| 4423 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 4424 | |
Chris Wilson | e8dec1d | 2015-02-27 13:58:43 +0000 | [diff] [blame] | 4425 | mappable = (vma->node.start + fence_size <= |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4426 | dev_priv->gtt.mappable_end); |
| 4427 | |
| 4428 | obj->map_and_fenceable = mappable && fenceable; |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4429 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 4430 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 4431 | } |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4432 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4433 | vma->pin_count++; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4434 | return 0; |
| 4435 | } |
| 4436 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4437 | int |
| 4438 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4439 | struct i915_address_space *vm, |
| 4440 | uint32_t alignment, |
| 4441 | uint64_t flags) |
| 4442 | { |
| 4443 | return i915_gem_object_do_pin(obj, vm, |
| 4444 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, |
| 4445 | alignment, flags); |
| 4446 | } |
| 4447 | |
| 4448 | int |
| 4449 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
| 4450 | const struct i915_ggtt_view *view, |
| 4451 | uint32_t alignment, |
| 4452 | uint64_t flags) |
| 4453 | { |
| 4454 | if (WARN_ONCE(!view, "no view specified")) |
| 4455 | return -EINVAL; |
| 4456 | |
| 4457 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, |
Tvrtko Ursulin | 6fafab7 | 2015-03-17 15:36:51 +0000 | [diff] [blame] | 4458 | alignment, flags | PIN_GLOBAL); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4459 | } |
| 4460 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4461 | void |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4462 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
| 4463 | const struct i915_ggtt_view *view) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4464 | { |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4465 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4466 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4467 | BUG_ON(!vma); |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4468 | WARN_ON(vma->pin_count == 0); |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 4469 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4470 | |
Chris Wilson | 3015465 | 2015-04-07 17:28:24 +0100 | [diff] [blame] | 4471 | --vma->pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4472 | } |
| 4473 | |
Daniel Vetter | d8ffa60 | 2014-05-13 12:11:26 +0200 | [diff] [blame] | 4474 | bool |
| 4475 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 4476 | { |
| 4477 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4478 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4479 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
| 4480 | |
| 4481 | WARN_ON(!ggtt_vma || |
| 4482 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
| 4483 | ggtt_vma->pin_count); |
| 4484 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
| 4485 | return true; |
| 4486 | } else |
| 4487 | return false; |
| 4488 | } |
| 4489 | |
| 4490 | void |
| 4491 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 4492 | { |
| 4493 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4494 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4495 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
| 4496 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 4497 | } |
| 4498 | } |
| 4499 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4500 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4501 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4502 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4503 | { |
| 4504 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4505 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4506 | int ret; |
| 4507 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4508 | ret = i915_mutex_lock_interruptible(dev); |
| 4509 | if (ret) |
| 4510 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4511 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4512 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4513 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4514 | ret = -ENOENT; |
| 4515 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4516 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4517 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4518 | /* Count all active objects as busy, even if they are currently not used |
| 4519 | * by the gpu. Users of this interface expect objects to eventually |
| 4520 | * become non-busy without any further actions, therefore emit any |
| 4521 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4522 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4523 | ret = i915_gem_object_flush_active(obj); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4524 | if (ret) |
| 4525 | goto unref; |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4526 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4527 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 4528 | args->busy = obj->active << 16; |
| 4529 | if (obj->last_write_req) |
| 4530 | args->busy |= obj->last_write_req->ring->id; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4531 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4532 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4533 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4534 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4535 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4536 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4537 | } |
| 4538 | |
| 4539 | int |
| 4540 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4541 | struct drm_file *file_priv) |
| 4542 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 4543 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4544 | } |
| 4545 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4546 | int |
| 4547 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4548 | struct drm_file *file_priv) |
| 4549 | { |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4550 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4551 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4552 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4553 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4554 | |
| 4555 | switch (args->madv) { |
| 4556 | case I915_MADV_DONTNEED: |
| 4557 | case I915_MADV_WILLNEED: |
| 4558 | break; |
| 4559 | default: |
| 4560 | return -EINVAL; |
| 4561 | } |
| 4562 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4563 | ret = i915_mutex_lock_interruptible(dev); |
| 4564 | if (ret) |
| 4565 | return ret; |
| 4566 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4567 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4568 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4569 | ret = -ENOENT; |
| 4570 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4571 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4572 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4573 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4574 | ret = -EINVAL; |
| 4575 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4576 | } |
| 4577 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4578 | if (obj->pages && |
| 4579 | obj->tiling_mode != I915_TILING_NONE && |
| 4580 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
| 4581 | if (obj->madv == I915_MADV_WILLNEED) |
| 4582 | i915_gem_object_unpin_pages(obj); |
| 4583 | if (args->madv == I915_MADV_WILLNEED) |
| 4584 | i915_gem_object_pin_pages(obj); |
| 4585 | } |
| 4586 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4587 | if (obj->madv != __I915_MADV_PURGED) |
| 4588 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4589 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4590 | /* if the object is no longer attached, discard its backing storage */ |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 4591 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4592 | i915_gem_object_truncate(obj); |
| 4593 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4594 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4595 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4596 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4597 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4598 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4599 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4600 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4601 | } |
| 4602 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4603 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4604 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4605 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4606 | int i; |
| 4607 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4608 | INIT_LIST_HEAD(&obj->global_list); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4609 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4610 | INIT_LIST_HEAD(&obj->ring_list[i]); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4611 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4612 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 4613 | INIT_LIST_HEAD(&obj->batch_pool_link); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4614 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4615 | obj->ops = ops; |
| 4616 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4617 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4618 | obj->madv = I915_MADV_WILLNEED; |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4619 | |
| 4620 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4621 | } |
| 4622 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4623 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4624 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4625 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4626 | }; |
| 4627 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4628 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4629 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4630 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4631 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4632 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4633 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4634 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4635 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4636 | if (obj == NULL) |
| 4637 | return NULL; |
| 4638 | |
| 4639 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4640 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4641 | return NULL; |
| 4642 | } |
| 4643 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4644 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4645 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4646 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4647 | mask &= ~__GFP_HIGHMEM; |
| 4648 | mask |= __GFP_DMA32; |
| 4649 | } |
| 4650 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4651 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4652 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4653 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4654 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4655 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4656 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4657 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4658 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4659 | if (HAS_LLC(dev)) { |
| 4660 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4661 | * cache) for about a 10% performance improvement |
| 4662 | * compared to uncached. Graphics requests other than |
| 4663 | * display scanout are coherent with the CPU in |
| 4664 | * accessing this cache. This means in this mode we |
| 4665 | * don't need to clflush on the CPU side, and on the |
| 4666 | * GPU side we only need to flush internal caches to |
| 4667 | * get data visible to the CPU. |
| 4668 | * |
| 4669 | * However, we maintain the display planes as UC, and so |
| 4670 | * need to rebind when first used as such. |
| 4671 | */ |
| 4672 | obj->cache_level = I915_CACHE_LLC; |
| 4673 | } else |
| 4674 | obj->cache_level = I915_CACHE_NONE; |
| 4675 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4676 | trace_i915_gem_object_create(obj); |
| 4677 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4678 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4679 | } |
| 4680 | |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4681 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4682 | { |
| 4683 | /* If we are the last user of the backing storage (be it shmemfs |
| 4684 | * pages or stolen etc), we know that the pages are going to be |
| 4685 | * immediately released. In this case, we can then skip copying |
| 4686 | * back the contents from the GPU. |
| 4687 | */ |
| 4688 | |
| 4689 | if (obj->madv != I915_MADV_WILLNEED) |
| 4690 | return false; |
| 4691 | |
| 4692 | if (obj->base.filp == NULL) |
| 4693 | return true; |
| 4694 | |
| 4695 | /* At first glance, this looks racy, but then again so would be |
| 4696 | * userspace racing mmap against close. However, the first external |
| 4697 | * reference to the filp can only be obtained through the |
| 4698 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4699 | * acquiring such a reference whilst we are in the middle of |
| 4700 | * freeing the object. |
| 4701 | */ |
| 4702 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4703 | } |
| 4704 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4705 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4706 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4707 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4708 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4709 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4710 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4711 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4712 | intel_runtime_pm_get(dev_priv); |
| 4713 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4714 | trace_i915_gem_object_destroy(obj); |
| 4715 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4716 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4717 | int ret; |
| 4718 | |
| 4719 | vma->pin_count = 0; |
| 4720 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4721 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4722 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4723 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4724 | was_interruptible = dev_priv->mm.interruptible; |
| 4725 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4726 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4727 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4728 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4729 | dev_priv->mm.interruptible = was_interruptible; |
| 4730 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4731 | } |
| 4732 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4733 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4734 | * before progressing. */ |
| 4735 | if (obj->stolen) |
| 4736 | i915_gem_object_unpin_pages(obj); |
| 4737 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4738 | WARN_ON(obj->frontbuffer_bits); |
| 4739 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4740 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
| 4741 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
| 4742 | obj->tiling_mode != I915_TILING_NONE) |
| 4743 | i915_gem_object_unpin_pages(obj); |
| 4744 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4745 | if (WARN_ON(obj->pages_pin_count)) |
| 4746 | obj->pages_pin_count = 0; |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4747 | if (discard_backing_storage(obj)) |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 4748 | obj->madv = I915_MADV_DONTNEED; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4749 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4750 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4751 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4752 | BUG_ON(obj->pages); |
| 4753 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4754 | if (obj->base.import_attach) |
| 4755 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4756 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 4757 | if (obj->ops->release) |
| 4758 | obj->ops->release(obj); |
| 4759 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4760 | drm_gem_object_release(&obj->base); |
| 4761 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4762 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4763 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4764 | i915_gem_object_free(obj); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4765 | |
| 4766 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4767 | } |
| 4768 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4769 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 4770 | struct i915_address_space *vm) |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4771 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4772 | struct i915_vma *vma; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4773 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 4774 | if (i915_is_ggtt(vma->vm) && |
| 4775 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 4776 | continue; |
| 4777 | if (vma->vm == vm) |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4778 | return vma; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4779 | } |
| 4780 | return NULL; |
| 4781 | } |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4782 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4783 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
| 4784 | const struct i915_ggtt_view *view) |
| 4785 | { |
| 4786 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
| 4787 | struct i915_vma *vma; |
| 4788 | |
| 4789 | if (WARN_ONCE(!view, "no view specified")) |
| 4790 | return ERR_PTR(-EINVAL); |
| 4791 | |
| 4792 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 4793 | if (vma->vm == ggtt && |
| 4794 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4795 | return vma; |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4796 | return NULL; |
| 4797 | } |
| 4798 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4799 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4800 | { |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4801 | struct i915_address_space *vm = NULL; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4802 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4803 | |
| 4804 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4805 | if (!list_empty(&vma->exec_list)) |
| 4806 | return; |
| 4807 | |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4808 | vm = vma->vm; |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4809 | |
Daniel Vetter | 841cd77 | 2014-08-06 15:04:48 +0200 | [diff] [blame] | 4810 | if (!i915_is_ggtt(vm)) |
| 4811 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4812 | |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4813 | list_del(&vma->vma_link); |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4814 | |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 4815 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4816 | } |
| 4817 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4818 | static void |
| 4819 | i915_gem_stop_ringbuffers(struct drm_device *dev) |
| 4820 | { |
| 4821 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4822 | struct intel_engine_cs *ring; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4823 | int i; |
| 4824 | |
| 4825 | for_each_ring(ring, dev_priv, i) |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4826 | dev_priv->gt.stop_ring(ring); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4827 | } |
| 4828 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4829 | int |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4830 | i915_gem_suspend(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4831 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4832 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4833 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4834 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4835 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4836 | ret = i915_gpu_idle(dev); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4837 | if (ret) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4838 | goto err; |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4839 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4840 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4841 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4842 | i915_gem_stop_ringbuffers(dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4843 | mutex_unlock(&dev->struct_mutex); |
| 4844 | |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 4845 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4846 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
Deepak S | 274fa1c | 2014-08-05 07:51:20 -0700 | [diff] [blame] | 4847 | flush_delayed_work(&dev_priv->mm.idle_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4848 | |
Chris Wilson | bdcf120 | 2014-11-25 11:56:33 +0000 | [diff] [blame] | 4849 | /* Assert that we sucessfully flushed all the work and |
| 4850 | * reset the GPU back to its idle, low power state. |
| 4851 | */ |
| 4852 | WARN_ON(dev_priv->mm.busy); |
| 4853 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4854 | return 0; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4855 | |
| 4856 | err: |
| 4857 | mutex_unlock(&dev->struct_mutex); |
| 4858 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4859 | } |
| 4860 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4861 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4862 | { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4863 | struct drm_device *dev = ring->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4864 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4865 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4866 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4867 | int i, ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4868 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 4869 | if (!HAS_L3_DPF(dev) || !remap_info) |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4870 | return 0; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4871 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4872 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
| 4873 | if (ret) |
| 4874 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4875 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4876 | /* |
| 4877 | * Note: We do not worry about the concurrent register cacheline hang |
| 4878 | * here because no other code should access these registers other than |
| 4879 | * at initialization time. |
| 4880 | */ |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4881 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4882 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 4883 | intel_ring_emit(ring, reg_base + i); |
| 4884 | intel_ring_emit(ring, remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4885 | } |
| 4886 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4887 | intel_ring_advance(ring); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4888 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4889 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4890 | } |
| 4891 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4892 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4893 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4894 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4895 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4896 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4897 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4898 | return; |
| 4899 | |
| 4900 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4901 | DISP_TILE_SURFACE_SWIZZLING); |
| 4902 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4903 | if (IS_GEN5(dev)) |
| 4904 | return; |
| 4905 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4906 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4907 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4908 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4909 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4910 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 31a5336 | 2013-11-02 21:07:04 -0700 | [diff] [blame] | 4911 | else if (IS_GEN8(dev)) |
| 4912 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4913 | else |
| 4914 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4915 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4916 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4917 | static bool |
| 4918 | intel_enable_blt(struct drm_device *dev) |
| 4919 | { |
| 4920 | if (!HAS_BLT(dev)) |
| 4921 | return false; |
| 4922 | |
| 4923 | /* The blitter was dysfunctional on early prototypes */ |
| 4924 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4925 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4926 | " graphics performance will be degraded.\n"); |
| 4927 | return false; |
| 4928 | } |
| 4929 | |
| 4930 | return true; |
| 4931 | } |
| 4932 | |
Ville Syrjälä | 81e7f20 | 2014-08-15 01:21:55 +0300 | [diff] [blame] | 4933 | static void init_unused_ring(struct drm_device *dev, u32 base) |
| 4934 | { |
| 4935 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4936 | |
| 4937 | I915_WRITE(RING_CTL(base), 0); |
| 4938 | I915_WRITE(RING_HEAD(base), 0); |
| 4939 | I915_WRITE(RING_TAIL(base), 0); |
| 4940 | I915_WRITE(RING_START(base), 0); |
| 4941 | } |
| 4942 | |
| 4943 | static void init_unused_rings(struct drm_device *dev) |
| 4944 | { |
| 4945 | if (IS_I830(dev)) { |
| 4946 | init_unused_ring(dev, PRB1_BASE); |
| 4947 | init_unused_ring(dev, SRB0_BASE); |
| 4948 | init_unused_ring(dev, SRB1_BASE); |
| 4949 | init_unused_ring(dev, SRB2_BASE); |
| 4950 | init_unused_ring(dev, SRB3_BASE); |
| 4951 | } else if (IS_GEN2(dev)) { |
| 4952 | init_unused_ring(dev, SRB0_BASE); |
| 4953 | init_unused_ring(dev, SRB1_BASE); |
| 4954 | } else if (IS_GEN3(dev)) { |
| 4955 | init_unused_ring(dev, PRB1_BASE); |
| 4956 | init_unused_ring(dev, PRB2_BASE); |
| 4957 | } |
| 4958 | } |
| 4959 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4960 | int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4961 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4962 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4963 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4964 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4965 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4966 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4967 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4968 | |
| 4969 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4970 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4971 | if (ret) |
| 4972 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4973 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4974 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4975 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4976 | ret = intel_init_blt_ring_buffer(dev); |
| 4977 | if (ret) |
| 4978 | goto cleanup_bsd_ring; |
| 4979 | } |
| 4980 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4981 | if (HAS_VEBOX(dev)) { |
| 4982 | ret = intel_init_vebox_ring_buffer(dev); |
| 4983 | if (ret) |
| 4984 | goto cleanup_blt_ring; |
| 4985 | } |
| 4986 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4987 | if (HAS_BSD2(dev)) { |
| 4988 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4989 | if (ret) |
| 4990 | goto cleanup_vebox_ring; |
| 4991 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4992 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4993 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4994 | if (ret) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4995 | goto cleanup_bsd2_ring; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4996 | |
| 4997 | return 0; |
| 4998 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4999 | cleanup_bsd2_ring: |
| 5000 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 5001 | cleanup_vebox_ring: |
| 5002 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 5003 | cleanup_blt_ring: |
| 5004 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 5005 | cleanup_bsd_ring: |
| 5006 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 5007 | cleanup_render_ring: |
| 5008 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 5009 | |
| 5010 | return ret; |
| 5011 | } |
| 5012 | |
| 5013 | int |
| 5014 | i915_gem_init_hw(struct drm_device *dev) |
| 5015 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5016 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 5017 | struct intel_engine_cs *ring; |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 5018 | int ret, i, j; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 5019 | |
| 5020 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 5021 | return -EIO; |
| 5022 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 5023 | /* Double layer security blanket, see i915_gem_init() */ |
| 5024 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 5025 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 5026 | if (dev_priv->ellc_size) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 5027 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 5028 | |
Ville Syrjälä | 0bf2134 | 2013-11-29 14:56:12 +0200 | [diff] [blame] | 5029 | if (IS_HASWELL(dev)) |
| 5030 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 5031 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 5032 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 5033 | if (HAS_PCH_NOP(dev)) { |
Daniel Vetter | 6ba844b | 2014-01-22 23:39:30 +0100 | [diff] [blame] | 5034 | if (IS_IVYBRIDGE(dev)) { |
| 5035 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 5036 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 5037 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 5038 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 5039 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 5040 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 5041 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 5042 | } |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 5043 | } |
| 5044 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 5045 | i915_gem_init_swizzling(dev); |
| 5046 | |
Daniel Vetter | d5abdfd | 2014-11-20 09:45:19 +0100 | [diff] [blame] | 5047 | /* |
| 5048 | * At least 830 can leave some of the unused rings |
| 5049 | * "active" (ie. head != tail) after resume which |
| 5050 | * will prevent c3 entry. Makes sure all unused rings |
| 5051 | * are totally idle. |
| 5052 | */ |
| 5053 | init_unused_rings(dev); |
| 5054 | |
John Harrison | 90638cc | 2015-05-29 17:43:37 +0100 | [diff] [blame] | 5055 | BUG_ON(!dev_priv->ring[RCS].default_context); |
| 5056 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 5057 | ret = i915_ppgtt_init_hw(dev); |
| 5058 | if (ret) { |
| 5059 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); |
| 5060 | goto out; |
| 5061 | } |
| 5062 | |
| 5063 | /* Need to do basic initialisation of all rings first: */ |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 5064 | for_each_ring(ring, dev_priv, i) { |
| 5065 | ret = ring->init_hw(ring); |
| 5066 | if (ret) |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 5067 | goto out; |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 5068 | } |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 5069 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 5070 | /* Now it is safe to go back round and do everything else: */ |
| 5071 | for_each_ring(ring, dev_priv, i) { |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 5072 | struct drm_i915_gem_request *req; |
| 5073 | |
John Harrison | 90638cc | 2015-05-29 17:43:37 +0100 | [diff] [blame] | 5074 | WARN_ON(!ring->default_context); |
| 5075 | |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 5076 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); |
| 5077 | if (ret) { |
| 5078 | i915_gem_cleanup_ringbuffer(dev); |
| 5079 | goto out; |
| 5080 | } |
| 5081 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 5082 | if (ring->id == RCS) { |
| 5083 | for (j = 0; j < NUM_L3_SLICES(dev); j++) |
| 5084 | i915_gem_l3_remap(ring, j); |
| 5085 | } |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 5086 | |
John Harrison | b3dd6b9 | 2015-05-29 17:43:40 +0100 | [diff] [blame^] | 5087 | ret = i915_ppgtt_init_ring(req); |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 5088 | if (ret && ret != -EIO) { |
| 5089 | DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret); |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 5090 | i915_gem_request_cancel(req); |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 5091 | i915_gem_cleanup_ringbuffer(dev); |
| 5092 | goto out; |
| 5093 | } |
David Woodhouse | f48a016 | 2015-01-20 17:21:42 +0000 | [diff] [blame] | 5094 | |
John Harrison | b3dd6b9 | 2015-05-29 17:43:40 +0100 | [diff] [blame^] | 5095 | ret = i915_gem_context_enable(req); |
John Harrison | 90638cc | 2015-05-29 17:43:37 +0100 | [diff] [blame] | 5096 | if (ret && ret != -EIO) { |
| 5097 | DRM_ERROR("Context enable ring #%d failed %d\n", i, ret); |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 5098 | i915_gem_request_cancel(req); |
John Harrison | 90638cc | 2015-05-29 17:43:37 +0100 | [diff] [blame] | 5099 | i915_gem_cleanup_ringbuffer(dev); |
| 5100 | goto out; |
| 5101 | } |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 5102 | |
| 5103 | i915_add_request_no_flush(ring); |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 5104 | } |
| 5105 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 5106 | out: |
| 5107 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 5108 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5109 | } |
| 5110 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5111 | int i915_gem_init(struct drm_device *dev) |
| 5112 | { |
| 5113 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5114 | int ret; |
| 5115 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 5116 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
| 5117 | i915.enable_execlists); |
| 5118 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5119 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 5120 | |
| 5121 | if (IS_VALLEYVIEW(dev)) { |
| 5122 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
Imre Deak | 981a5ae | 2014-04-14 20:24:22 +0300 | [diff] [blame] | 5123 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
| 5124 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
| 5125 | VLV_GTLC_ALLOWWAKEACK), 10)) |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 5126 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 5127 | } |
| 5128 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 5129 | if (!i915.enable_execlists) { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 5130 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 5131 | dev_priv->gt.init_rings = i915_gem_init_rings; |
| 5132 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
| 5133 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 5134 | } else { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 5135 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 5136 | dev_priv->gt.init_rings = intel_logical_rings_init; |
| 5137 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; |
| 5138 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 5139 | } |
| 5140 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 5141 | /* This is just a security blanket to placate dragons. |
| 5142 | * On some systems, we very sporadically observe that the first TLBs |
| 5143 | * used by the CS may be stale, despite us poking the TLB reset. If |
| 5144 | * we hold the forcewake during initialisation these problems |
| 5145 | * just magically go away. |
| 5146 | */ |
| 5147 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 5148 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 5149 | ret = i915_gem_init_userptr(dev); |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5150 | if (ret) |
| 5151 | goto out_unlock; |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 5152 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 5153 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 5154 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 5155 | ret = i915_gem_context_init(dev); |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5156 | if (ret) |
| 5157 | goto out_unlock; |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 5158 | |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 5159 | ret = dev_priv->gt.init_rings(dev); |
| 5160 | if (ret) |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5161 | goto out_unlock; |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 5162 | |
| 5163 | ret = i915_gem_init_hw(dev); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5164 | if (ret == -EIO) { |
| 5165 | /* Allow ring initialisation to fail by marking the GPU as |
| 5166 | * wedged. But we only want to do this where the GPU is angry, |
| 5167 | * for all other failure, such as an allocation failure, bail. |
| 5168 | */ |
| 5169 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
| 5170 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 5171 | ret = 0; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5172 | } |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5173 | |
| 5174 | out_unlock: |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 5175 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5176 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5177 | |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5178 | return ret; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5179 | } |
| 5180 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5181 | void |
| 5182 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 5183 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5184 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 5185 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 5186 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5187 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 5188 | for_each_ring(ring, dev_priv, i) |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 5189 | dev_priv->gt.cleanup_ring(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5190 | } |
| 5191 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5192 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 5193 | init_ring_lists(struct intel_engine_cs *ring) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5194 | { |
| 5195 | INIT_LIST_HEAD(&ring->active_list); |
| 5196 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5197 | } |
| 5198 | |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 5199 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 5200 | struct i915_address_space *vm) |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5201 | { |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 5202 | if (!i915_is_ggtt(vm)) |
| 5203 | drm_mm_init(&vm->mm, vm->start, vm->total); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5204 | vm->dev = dev_priv->dev; |
| 5205 | INIT_LIST_HEAD(&vm->active_list); |
| 5206 | INIT_LIST_HEAD(&vm->inactive_list); |
| 5207 | INIT_LIST_HEAD(&vm->global_link); |
Chris Wilson | f72d21e | 2014-01-09 22:57:22 +0000 | [diff] [blame] | 5208 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5209 | } |
| 5210 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5211 | void |
| 5212 | i915_gem_load(struct drm_device *dev) |
| 5213 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5214 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 5215 | int i; |
| 5216 | |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 5217 | dev_priv->objects = |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 5218 | kmem_cache_create("i915_gem_object", |
| 5219 | sizeof(struct drm_i915_gem_object), 0, |
| 5220 | SLAB_HWCACHE_ALIGN, |
| 5221 | NULL); |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 5222 | dev_priv->vmas = |
| 5223 | kmem_cache_create("i915_gem_vma", |
| 5224 | sizeof(struct i915_vma), 0, |
| 5225 | SLAB_HWCACHE_ALIGN, |
| 5226 | NULL); |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 5227 | dev_priv->requests = |
| 5228 | kmem_cache_create("i915_gem_request", |
| 5229 | sizeof(struct drm_i915_gem_request), 0, |
| 5230 | SLAB_HWCACHE_ALIGN, |
| 5231 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5232 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5233 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 5234 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 5235 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 5236 | INIT_LIST_HEAD(&dev_priv->context_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 5237 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 5238 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 5239 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 5240 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 5241 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 5242 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 5243 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5244 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 5245 | i915_gem_retire_work_handler); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5246 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 5247 | i915_gem_idle_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 5248 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5249 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 5250 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 5251 | |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 5252 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 5253 | dev_priv->num_fence_regs = 32; |
| 5254 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 5255 | dev_priv->num_fence_regs = 16; |
| 5256 | else |
| 5257 | dev_priv->num_fence_regs = 8; |
| 5258 | |
Yu Zhang | eb82289 | 2015-02-10 19:05:49 +0800 | [diff] [blame] | 5259 | if (intel_vgpu_active(dev)) |
| 5260 | dev_priv->num_fence_regs = |
| 5261 | I915_READ(vgtif_reg(avail_rs.fence_num)); |
| 5262 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 5263 | /* Initialize fence registers to zero */ |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 5264 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 5265 | i915_gem_restore_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 5266 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5267 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5268 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5269 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 5270 | dev_priv->mm.interruptible = true; |
| 5271 | |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 5272 | i915_gem_shrinker_init(dev_priv); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 5273 | |
| 5274 | mutex_init(&dev_priv->fb_tracking.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5275 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5276 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5277 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5278 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5279 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5280 | |
| 5281 | /* Clean up our request list when the client is going away, so that |
| 5282 | * later retire_requests won't dereference our soon-to-be-gone |
| 5283 | * file_priv. |
| 5284 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5285 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5286 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5287 | struct drm_i915_gem_request *request; |
| 5288 | |
| 5289 | request = list_first_entry(&file_priv->mm.request_list, |
| 5290 | struct drm_i915_gem_request, |
| 5291 | client_list); |
| 5292 | list_del(&request->client_list); |
| 5293 | request->file_priv = NULL; |
| 5294 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5295 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5296 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5297 | if (!list_empty(&file_priv->rps.link)) { |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 5298 | spin_lock(&to_i915(dev)->rps.client_lock); |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5299 | list_del(&file_priv->rps.link); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 5300 | spin_unlock(&to_i915(dev)->rps.client_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 5301 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5302 | } |
| 5303 | |
| 5304 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5305 | { |
| 5306 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5307 | int ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5308 | |
| 5309 | DRM_DEBUG_DRIVER("\n"); |
| 5310 | |
| 5311 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5312 | if (!file_priv) |
| 5313 | return -ENOMEM; |
| 5314 | |
| 5315 | file->driver_priv = file_priv; |
| 5316 | file_priv->dev_priv = dev->dev_private; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 5317 | file_priv->file = file; |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5318 | INIT_LIST_HEAD(&file_priv->rps.link); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5319 | |
| 5320 | spin_lock_init(&file_priv->mm.lock); |
| 5321 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5322 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5323 | ret = i915_gem_context_open(dev, file); |
| 5324 | if (ret) |
| 5325 | kfree(file_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5326 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5327 | return ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5328 | } |
| 5329 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 5330 | /** |
| 5331 | * i915_gem_track_fb - update frontbuffer tracking |
| 5332 | * old: current GEM buffer for the frontbuffer slots |
| 5333 | * new: new GEM buffer for the frontbuffer slots |
| 5334 | * frontbuffer_bits: bitmask of frontbuffer slots |
| 5335 | * |
| 5336 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
| 5337 | * from @old and setting them in @new. Both @old and @new can be NULL. |
| 5338 | */ |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 5339 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5340 | struct drm_i915_gem_object *new, |
| 5341 | unsigned frontbuffer_bits) |
| 5342 | { |
| 5343 | if (old) { |
| 5344 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5345 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5346 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5347 | } |
| 5348 | |
| 5349 | if (new) { |
| 5350 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5351 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5352 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5353 | } |
| 5354 | } |
| 5355 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5356 | /* All the new VM stuff */ |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5357 | unsigned long |
| 5358 | i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5359 | struct i915_address_space *vm) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5360 | { |
| 5361 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5362 | struct i915_vma *vma; |
| 5363 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5364 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5365 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5366 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5367 | if (i915_is_ggtt(vma->vm) && |
| 5368 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5369 | continue; |
| 5370 | if (vma->vm == vm) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5371 | return vma->node.start; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5372 | } |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5373 | |
Daniel Vetter | f25748ea | 2014-06-17 22:34:38 +0200 | [diff] [blame] | 5374 | WARN(1, "%s vma for this object not found.\n", |
| 5375 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5376 | return -1; |
| 5377 | } |
| 5378 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5379 | unsigned long |
| 5380 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5381 | const struct i915_ggtt_view *view) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5382 | { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5383 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5384 | struct i915_vma *vma; |
| 5385 | |
| 5386 | list_for_each_entry(vma, &o->vma_list, vma_link) |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5387 | if (vma->vm == ggtt && |
| 5388 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5389 | return vma->node.start; |
| 5390 | |
Tvrtko Ursulin | 5678ad7 | 2015-03-17 14:45:29 +0000 | [diff] [blame] | 5391 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5392 | return -1; |
| 5393 | } |
| 5394 | |
| 5395 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5396 | struct i915_address_space *vm) |
| 5397 | { |
| 5398 | struct i915_vma *vma; |
| 5399 | |
| 5400 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5401 | if (i915_is_ggtt(vma->vm) && |
| 5402 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5403 | continue; |
| 5404 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
| 5405 | return true; |
| 5406 | } |
| 5407 | |
| 5408 | return false; |
| 5409 | } |
| 5410 | |
| 5411 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5412 | const struct i915_ggtt_view *view) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5413 | { |
| 5414 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
| 5415 | struct i915_vma *vma; |
| 5416 | |
| 5417 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5418 | if (vma->vm == ggtt && |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5419 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 5420 | drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5421 | return true; |
| 5422 | |
| 5423 | return false; |
| 5424 | } |
| 5425 | |
| 5426 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5427 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5428 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5429 | |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5430 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5431 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5432 | return true; |
| 5433 | |
| 5434 | return false; |
| 5435 | } |
| 5436 | |
| 5437 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 5438 | struct i915_address_space *vm) |
| 5439 | { |
| 5440 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5441 | struct i915_vma *vma; |
| 5442 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5443 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5444 | |
| 5445 | BUG_ON(list_empty(&o->vma_list)); |
| 5446 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5447 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5448 | if (i915_is_ggtt(vma->vm) && |
| 5449 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5450 | continue; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5451 | if (vma->vm == vm) |
| 5452 | return vma->node.size; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5453 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5454 | return 0; |
| 5455 | } |
| 5456 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5457 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5458 | { |
| 5459 | struct i915_vma *vma; |
Joonas Lahtinen | a6631ae | 2015-05-06 14:34:58 +0300 | [diff] [blame] | 5460 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5461 | if (vma->pin_count > 0) |
| 5462 | return true; |
Joonas Lahtinen | a6631ae | 2015-05-06 14:34:58 +0300 | [diff] [blame] | 5463 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5464 | return false; |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5465 | } |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5466 | |