Sakthivel K | f586099 | 2013-04-17 16:37:02 +0530 | [diff] [blame] | 1 | /* |
| 2 | * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver |
| 3 | * |
| 4 | * Copyright (c) 2008-2009 USI Co., Ltd. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions, and the following disclaimer, |
| 12 | * without modification. |
| 13 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 14 | * substantially similar to the "NO WARRANTY" disclaimer below |
| 15 | * ("Disclaimer") and any redistribution must be conditioned upon |
| 16 | * including a substantially similar Disclaimer requirement for further |
| 17 | * binary redistribution. |
| 18 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 19 | * of any contributors may be used to endorse or promote products derived |
| 20 | * from this software without specific prior written permission. |
| 21 | * |
| 22 | * Alternatively, this software may be distributed under the terms of the |
| 23 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 24 | * Software Foundation. |
| 25 | * |
| 26 | * NO WARRANTY |
| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
| 30 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 31 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 32 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 33 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 34 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 35 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 36 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 37 | * POSSIBILITY OF SUCH DAMAGES. |
| 38 | * |
| 39 | */ |
| 40 | |
| 41 | #ifndef _PMC8001_REG_H_ |
| 42 | #define _PMC8001_REG_H_ |
| 43 | |
| 44 | #include <linux/types.h> |
| 45 | #include <scsi/libsas.h> |
| 46 | |
| 47 | /* for Request Opcode of IOMB */ |
| 48 | #define OPC_INB_ECHO 1 /* 0x000 */ |
| 49 | #define OPC_INB_PHYSTART 4 /* 0x004 */ |
| 50 | #define OPC_INB_PHYSTOP 5 /* 0x005 */ |
| 51 | #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */ |
| 52 | #define OPC_INB_SSPINITMSTART 7 /* 0x007 */ |
| 53 | /* 0x8 RESV IN SPCv */ |
| 54 | #define OPC_INB_RSVD 8 /* 0x008 */ |
| 55 | #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */ |
| 56 | #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */ |
| 57 | #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */ |
| 58 | /* 0xC, 0xD, 0xE removed in SPCv */ |
| 59 | #define OPC_INB_SSP_ABORT 15 /* 0x00F */ |
| 60 | #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */ |
| 61 | #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */ |
| 62 | #define OPC_INB_SMP_REQUEST 18 /* 0x012 */ |
| 63 | /* 0x13 SMP_RESPONSE is removed in SPCv */ |
| 64 | #define OPC_INB_SMP_ABORT 20 /* 0x014 */ |
| 65 | /* 0x16 RESV IN SPCv */ |
| 66 | #define OPC_INB_RSVD1 22 /* 0x016 */ |
| 67 | #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */ |
| 68 | #define OPC_INB_SATA_ABORT 24 /* 0x018 */ |
| 69 | #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */ |
| 70 | /* 0x1A RESV IN SPCv */ |
| 71 | #define OPC_INB_RSVD2 26 /* 0x01A */ |
| 72 | #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */ |
| 73 | #define OPC_INB_GPIO 34 /* 0x022 */ |
| 74 | #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */ |
| 75 | #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */ |
| 76 | /* 0x25 RESV IN SPCv */ |
| 77 | #define OPC_INB_RSVD3 37 /* 0x025 */ |
| 78 | #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */ |
| 79 | #define OPC_INB_PORT_CONTROL 39 /* 0x027 */ |
| 80 | #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */ |
| 81 | #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */ |
| 82 | #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */ |
| 83 | #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */ |
| 84 | #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */ |
| 85 | /* 0x2D RESV IN SPCv */ |
| 86 | #define OPC_INB_RSVD4 45 /* 0x02D */ |
| 87 | #define OPC_INB_SGPIO_REGISTER 46 /* 0x02E */ |
| 88 | #define OPC_INB_PCIE_DIAG_EXEC 47 /* 0x02F */ |
| 89 | #define OPC_INB_SET_CONTROLLER_CONFIG 48 /* 0x030 */ |
| 90 | #define OPC_INB_GET_CONTROLLER_CONFIG 49 /* 0x031 */ |
| 91 | #define OPC_INB_REG_DEV 50 /* 0x032 */ |
| 92 | #define OPC_INB_SAS_HW_EVENT_ACK 51 /* 0x033 */ |
| 93 | #define OPC_INB_GET_DEVICE_INFO 52 /* 0x034 */ |
| 94 | #define OPC_INB_GET_PHY_PROFILE 53 /* 0x035 */ |
| 95 | #define OPC_INB_FLASH_OP_EXT 54 /* 0x036 */ |
| 96 | #define OPC_INB_SET_PHY_PROFILE 55 /* 0x037 */ |
| 97 | #define OPC_INB_KEK_MANAGEMENT 256 /* 0x100 */ |
| 98 | #define OPC_INB_DEK_MANAGEMENT 257 /* 0x101 */ |
| 99 | #define OPC_INB_SSP_INI_DIF_ENC_IO 258 /* 0x102 */ |
| 100 | #define OPC_INB_SATA_DIF_ENC_IO 259 /* 0x103 */ |
| 101 | |
| 102 | /* for Response Opcode of IOMB */ |
| 103 | #define OPC_OUB_ECHO 1 /* 0x001 */ |
| 104 | #define OPC_OUB_RSVD 4 /* 0x004 */ |
| 105 | #define OPC_OUB_SSP_COMP 5 /* 0x005 */ |
| 106 | #define OPC_OUB_SMP_COMP 6 /* 0x006 */ |
| 107 | #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */ |
| 108 | #define OPC_OUB_RSVD1 10 /* 0x00A */ |
| 109 | #define OPC_OUB_DEREG_DEV 11 /* 0x00B */ |
| 110 | #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */ |
| 111 | #define OPC_OUB_SATA_COMP 13 /* 0x00D */ |
| 112 | #define OPC_OUB_SATA_EVENT 14 /* 0x00E */ |
| 113 | #define OPC_OUB_SSP_EVENT 15 /* 0x00F */ |
| 114 | #define OPC_OUB_RSVD2 16 /* 0x010 */ |
| 115 | /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/ |
| 116 | #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */ |
| 117 | #define OPC_OUB_RSVD3 19 /* 0x013 */ |
| 118 | #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */ |
| 119 | #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */ |
| 120 | #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */ |
| 121 | #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */ |
| 122 | #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */ |
| 123 | #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */ |
| 124 | #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */ |
| 125 | #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */ |
| 126 | #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */ |
| 127 | #define OPC_OUB_RSVD4 31 /* 0x01F */ |
| 128 | #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */ |
| 129 | #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */ |
| 130 | #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */ |
| 131 | #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */ |
| 132 | #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */ |
| 133 | #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */ |
| 134 | #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */ |
| 135 | #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */ |
| 136 | #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */ |
| 137 | #define OPC_OUB_RSVD5 41 /* 0x029 */ |
| 138 | #define OPC_OUB_HW_EVENT 1792 /* 0x700 */ |
| 139 | #define OPC_OUB_DEV_HANDLE_ARRIV 1824 /* 0x720 */ |
| 140 | #define OPC_OUB_THERM_HW_EVENT 1840 /* 0x730 */ |
| 141 | #define OPC_OUB_SGPIO_RESP 2094 /* 0x82E */ |
| 142 | #define OPC_OUB_PCIE_DIAG_EXECUTE 2095 /* 0x82F */ |
| 143 | #define OPC_OUB_DEV_REGIST 2098 /* 0x832 */ |
| 144 | #define OPC_OUB_SAS_HW_EVENT_ACK 2099 /* 0x833 */ |
| 145 | #define OPC_OUB_GET_DEVICE_INFO 2100 /* 0x834 */ |
| 146 | /* spcv specific commands */ |
| 147 | #define OPC_OUB_PHY_START_RESP 2052 /* 0x804 */ |
| 148 | #define OPC_OUB_PHY_STOP_RESP 2053 /* 0x805 */ |
| 149 | #define OPC_OUB_SET_CONTROLLER_CONFIG 2096 /* 0x830 */ |
| 150 | #define OPC_OUB_GET_CONTROLLER_CONFIG 2097 /* 0x831 */ |
| 151 | #define OPC_OUB_GET_PHY_PROFILE 2101 /* 0x835 */ |
| 152 | #define OPC_OUB_FLASH_OP_EXT 2102 /* 0x836 */ |
| 153 | #define OPC_OUB_SET_PHY_PROFILE 2103 /* 0x837 */ |
| 154 | #define OPC_OUB_KEK_MANAGEMENT_RESP 2304 /* 0x900 */ |
| 155 | #define OPC_OUB_DEK_MANAGEMENT_RESP 2305 /* 0x901 */ |
| 156 | #define OPC_OUB_SSP_COALESCED_COMP_RESP 2306 /* 0x902 */ |
| 157 | |
| 158 | /* for phy start*/ |
| 159 | #define SSC_DISABLE_15 (0x01 << 16) |
| 160 | #define SSC_DISABLE_30 (0x02 << 16) |
| 161 | #define SSC_DISABLE_60 (0x04 << 16) |
| 162 | #define SAS_ASE (0x01 << 15) |
| 163 | #define SPINHOLD_DISABLE (0x00 << 14) |
| 164 | #define SPINHOLD_ENABLE (0x01 << 14) |
| 165 | #define LINKMODE_SAS (0x01 << 12) |
| 166 | #define LINKMODE_DSATA (0x02 << 12) |
| 167 | #define LINKMODE_AUTO (0x03 << 12) |
| 168 | #define LINKRATE_15 (0x01 << 8) |
| 169 | #define LINKRATE_30 (0x02 << 8) |
| 170 | #define LINKRATE_60 (0x06 << 8) |
| 171 | |
| 172 | /* Thermal related */ |
| 173 | #define THERMAL_ENABLE 0x1 |
| 174 | #define THERMAL_LOG_ENABLE 0x1 |
| 175 | #define THERMAL_OP_CODE 0x6 |
| 176 | #define LTEMPHIL 70 |
| 177 | #define RTEMPHIL 100 |
| 178 | |
| 179 | /* Encryption info */ |
| 180 | #define SCRATCH_PAD3_ENC_DISABLED 0x00000000 |
| 181 | #define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001 |
| 182 | #define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002 |
| 183 | #define SCRATCH_PAD3_ENC_READY 0x00000003 |
| 184 | #define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY |
| 185 | |
| 186 | #define SCRATCH_PAD3_XTS_ENABLED (1 << 14) |
| 187 | #define SCRATCH_PAD3_SMA_ENABLED (1 << 4) |
| 188 | #define SCRATCH_PAD3_SMB_ENABLED (1 << 5) |
| 189 | #define SCRATCH_PAD3_SMF_ENABLED 0 |
| 190 | #define SCRATCH_PAD3_SM_MASK 0x000000F0 |
| 191 | #define SCRATCH_PAD3_ERR_CODE 0x00FF0000 |
| 192 | |
| 193 | #define SEC_MODE_SMF 0x0 |
| 194 | #define SEC_MODE_SMA 0x100 |
| 195 | #define SEC_MODE_SMB 0x200 |
| 196 | #define CIPHER_MODE_ECB 0x00000001 |
| 197 | #define CIPHER_MODE_XTS 0x00000002 |
| 198 | #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4 |
| 199 | |
Sakthivel K | a6cb3d0 | 2013-03-19 18:08:40 +0530 | [diff] [blame] | 200 | /* SAS protocol timer configuration page */ |
| 201 | #define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04 |
| 202 | #define STP_MCT_TMO 32 |
| 203 | #define SSP_MCT_TMO 32 |
| 204 | #define SAS_MAX_OPEN_TIME 5 |
| 205 | #define SMP_MAX_CONN_TIMER 0xFF |
| 206 | #define STP_FRM_TIMER 0 |
| 207 | #define STP_IDLE_TIME 5 /* 5 us; controller default */ |
| 208 | #define SAS_MFD 0 |
| 209 | #define SAS_OPNRJT_RTRY_INTVL 2 |
| 210 | #define SAS_DOPNRJT_RTRY_TMO 128 |
| 211 | #define SAS_COPNRJT_RTRY_TMO 128 |
| 212 | |
| 213 | /* |
| 214 | Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second. |
| 215 | Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128 |
| 216 | is DOPNRJT_RTRY_TMO |
| 217 | */ |
| 218 | #define SAS_DOPNRJT_RTRY_THR 23438 |
| 219 | #define SAS_COPNRJT_RTRY_THR 23438 |
| 220 | #define SAS_MAX_AIP 0x200000 |
| 221 | #define IT_NEXUS_TIMEOUT 0x7D0 |
| 222 | #define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30) |
| 223 | |
Sakthivel K | f586099 | 2013-04-17 16:37:02 +0530 | [diff] [blame] | 224 | struct mpi_msg_hdr { |
| 225 | __le32 header; /* Bits [11:0] - Message operation code */ |
| 226 | /* Bits [15:12] - Message Category */ |
| 227 | /* Bits [21:16] - Outboundqueue ID for the |
| 228 | operation completion message */ |
| 229 | /* Bits [23:22] - Reserved */ |
| 230 | /* Bits [28:24] - Buffer Count, indicates how |
| 231 | many buffer are allocated for the massage */ |
| 232 | /* Bits [30:29] - Reserved */ |
| 233 | /* Bits [31] - Message Valid bit */ |
| 234 | } __attribute__((packed, aligned(4))); |
| 235 | |
| 236 | /* |
| 237 | * brief the data structure of PHY Start Command |
| 238 | * use to describe enable the phy (128 bytes) |
| 239 | */ |
| 240 | struct phy_start_req { |
| 241 | __le32 tag; |
| 242 | __le32 ase_sh_lm_slr_phyid; |
| 243 | struct sas_identify_frame sas_identify; /* 28 Bytes */ |
| 244 | __le32 spasti; |
| 245 | u32 reserved[21]; |
| 246 | } __attribute__((packed, aligned(4))); |
| 247 | |
| 248 | /* |
| 249 | * brief the data structure of PHY Start Command |
| 250 | * use to disable the phy (128 bytes) |
| 251 | */ |
| 252 | struct phy_stop_req { |
| 253 | __le32 tag; |
| 254 | __le32 phy_id; |
| 255 | u32 reserved[29]; |
| 256 | } __attribute__((packed, aligned(4))); |
| 257 | |
| 258 | /* set device bits fis - device to host */ |
| 259 | struct set_dev_bits_fis { |
| 260 | u8 fis_type; /* 0xA1*/ |
| 261 | u8 n_i_pmport; |
| 262 | /* b7 : n Bit. Notification bit. If set device needs attention. */ |
| 263 | /* b6 : i Bit. Interrupt Bit */ |
| 264 | /* b5-b4: reserved2 */ |
| 265 | /* b3-b0: PM Port */ |
| 266 | u8 status; |
| 267 | u8 error; |
| 268 | u32 _r_a; |
| 269 | } __attribute__ ((packed)); |
| 270 | /* PIO setup FIS - device to host */ |
| 271 | struct pio_setup_fis { |
| 272 | u8 fis_type; /* 0x5f */ |
| 273 | u8 i_d_pmPort; |
| 274 | /* b7 : reserved */ |
| 275 | /* b6 : i bit. Interrupt bit */ |
| 276 | /* b5 : d bit. data transfer direction. set to 1 for device to host |
| 277 | xfer */ |
| 278 | /* b4 : reserved */ |
| 279 | /* b3-b0: PM Port */ |
| 280 | u8 status; |
| 281 | u8 error; |
| 282 | u8 lbal; |
| 283 | u8 lbam; |
| 284 | u8 lbah; |
| 285 | u8 device; |
| 286 | u8 lbal_exp; |
| 287 | u8 lbam_exp; |
| 288 | u8 lbah_exp; |
| 289 | u8 _r_a; |
| 290 | u8 sector_count; |
| 291 | u8 sector_count_exp; |
| 292 | u8 _r_b; |
| 293 | u8 e_status; |
| 294 | u8 _r_c[2]; |
| 295 | u8 transfer_count; |
| 296 | } __attribute__ ((packed)); |
| 297 | |
| 298 | /* |
| 299 | * brief the data structure of SATA Completion Response |
| 300 | * use to describe the sata task response (64 bytes) |
| 301 | */ |
| 302 | struct sata_completion_resp { |
| 303 | __le32 tag; |
| 304 | __le32 status; |
| 305 | __le32 param; |
| 306 | u32 sata_resp[12]; |
| 307 | } __attribute__((packed, aligned(4))); |
| 308 | |
| 309 | /* |
| 310 | * brief the data structure of SAS HW Event Notification |
| 311 | * use to alert the host about the hardware event(64 bytes) |
| 312 | */ |
| 313 | /* updated outbound struct for spcv */ |
| 314 | |
| 315 | struct hw_event_resp { |
| 316 | __le32 lr_status_evt_portid; |
| 317 | __le32 evt_param; |
| 318 | __le32 phyid_npip_portstate; |
| 319 | struct sas_identify_frame sas_identify; |
| 320 | struct dev_to_host_fis sata_fis; |
| 321 | } __attribute__((packed, aligned(4))); |
| 322 | |
| 323 | /* |
| 324 | * brief the data structure for thermal event notification |
| 325 | */ |
| 326 | |
| 327 | struct thermal_hw_event { |
| 328 | __le32 thermal_event; |
| 329 | __le32 rht_lht; |
| 330 | } __attribute__((packed, aligned(4))); |
| 331 | |
| 332 | /* |
| 333 | * brief the data structure of REGISTER DEVICE Command |
| 334 | * use to describe MPI REGISTER DEVICE Command (64 bytes) |
| 335 | */ |
| 336 | |
| 337 | struct reg_dev_req { |
| 338 | __le32 tag; |
| 339 | __le32 phyid_portid; |
| 340 | __le32 dtype_dlr_mcn_ir_retry; |
| 341 | __le32 firstburstsize_ITNexustimeout; |
| 342 | u8 sas_addr[SAS_ADDR_SIZE]; |
| 343 | __le32 upper_device_id; |
| 344 | u32 reserved[24]; |
| 345 | } __attribute__((packed, aligned(4))); |
| 346 | |
| 347 | /* |
| 348 | * brief the data structure of DEREGISTER DEVICE Command |
| 349 | * use to request spc to remove all internal resources associated |
| 350 | * with the device id (64 bytes) |
| 351 | */ |
| 352 | |
| 353 | struct dereg_dev_req { |
| 354 | __le32 tag; |
| 355 | __le32 device_id; |
| 356 | u32 reserved[29]; |
| 357 | } __attribute__((packed, aligned(4))); |
| 358 | |
| 359 | /* |
| 360 | * brief the data structure of DEVICE_REGISTRATION Response |
| 361 | * use to notify the completion of the device registration (64 bytes) |
| 362 | */ |
| 363 | struct dev_reg_resp { |
| 364 | __le32 tag; |
| 365 | __le32 status; |
| 366 | __le32 device_id; |
| 367 | u32 reserved[12]; |
| 368 | } __attribute__((packed, aligned(4))); |
| 369 | |
| 370 | /* |
| 371 | * brief the data structure of Local PHY Control Command |
| 372 | * use to issue PHY CONTROL to local phy (64 bytes) |
| 373 | */ |
| 374 | struct local_phy_ctl_req { |
| 375 | __le32 tag; |
| 376 | __le32 phyop_phyid; |
| 377 | u32 reserved1[29]; |
| 378 | } __attribute__((packed, aligned(4))); |
| 379 | |
| 380 | /** |
| 381 | * brief the data structure of Local Phy Control Response |
| 382 | * use to describe MPI Local Phy Control Response (64 bytes) |
| 383 | */ |
| 384 | struct local_phy_ctl_resp { |
| 385 | __le32 tag; |
| 386 | __le32 phyop_phyid; |
| 387 | __le32 status; |
| 388 | u32 reserved[12]; |
| 389 | } __attribute__((packed, aligned(4))); |
| 390 | |
| 391 | #define OP_BITS 0x0000FF00 |
| 392 | #define ID_BITS 0x000000FF |
| 393 | |
| 394 | /* |
| 395 | * brief the data structure of PORT Control Command |
| 396 | * use to control port properties (64 bytes) |
| 397 | */ |
| 398 | |
| 399 | struct port_ctl_req { |
| 400 | __le32 tag; |
| 401 | __le32 portop_portid; |
| 402 | __le32 param0; |
| 403 | __le32 param1; |
| 404 | u32 reserved1[27]; |
| 405 | } __attribute__((packed, aligned(4))); |
| 406 | |
| 407 | /* |
| 408 | * brief the data structure of HW Event Ack Command |
| 409 | * use to acknowledge receive HW event (64 bytes) |
| 410 | */ |
| 411 | struct hw_event_ack_req { |
| 412 | __le32 tag; |
| 413 | __le32 phyid_sea_portid; |
| 414 | __le32 param0; |
| 415 | __le32 param1; |
| 416 | u32 reserved1[27]; |
| 417 | } __attribute__((packed, aligned(4))); |
| 418 | |
| 419 | /* |
| 420 | * brief the data structure of PHY_START Response Command |
| 421 | * indicates the completion of PHY_START command (64 bytes) |
| 422 | */ |
| 423 | struct phy_start_resp { |
| 424 | __le32 tag; |
| 425 | __le32 status; |
| 426 | __le32 phyid; |
| 427 | u32 reserved[12]; |
| 428 | } __attribute__((packed, aligned(4))); |
| 429 | |
| 430 | /* |
| 431 | * brief the data structure of PHY_STOP Response Command |
| 432 | * indicates the completion of PHY_STOP command (64 bytes) |
| 433 | */ |
| 434 | struct phy_stop_resp { |
| 435 | __le32 tag; |
| 436 | __le32 status; |
| 437 | __le32 phyid; |
| 438 | u32 reserved[12]; |
| 439 | } __attribute__((packed, aligned(4))); |
| 440 | |
| 441 | /* |
| 442 | * brief the data structure of SSP Completion Response |
| 443 | * use to indicate a SSP Completion (n bytes) |
| 444 | */ |
| 445 | struct ssp_completion_resp { |
| 446 | __le32 tag; |
| 447 | __le32 status; |
| 448 | __le32 param; |
| 449 | __le32 ssptag_rescv_rescpad; |
| 450 | struct ssp_response_iu ssp_resp_iu; |
| 451 | __le32 residual_count; |
| 452 | } __attribute__((packed, aligned(4))); |
| 453 | |
| 454 | #define SSP_RESCV_BIT 0x00010000 |
| 455 | |
| 456 | /* |
| 457 | * brief the data structure of SATA EVNET response |
| 458 | * use to indicate a SATA Completion (64 bytes) |
| 459 | */ |
| 460 | struct sata_event_resp { |
| 461 | __le32 tag; |
| 462 | __le32 event; |
| 463 | __le32 port_id; |
| 464 | __le32 device_id; |
| 465 | u32 reserved; |
| 466 | __le32 event_param0; |
| 467 | __le32 event_param1; |
| 468 | __le32 sata_addr_h32; |
| 469 | __le32 sata_addr_l32; |
| 470 | __le32 e_udt1_udt0_crc; |
| 471 | __le32 e_udt5_udt4_udt3_udt2; |
| 472 | __le32 a_udt1_udt0_crc; |
| 473 | __le32 a_udt5_udt4_udt3_udt2; |
| 474 | __le32 hwdevid_diferr; |
| 475 | __le32 err_framelen_byteoffset; |
| 476 | __le32 err_dataframe; |
| 477 | } __attribute__((packed, aligned(4))); |
| 478 | |
| 479 | /* |
| 480 | * brief the data structure of SSP EVNET esponse |
| 481 | * use to indicate a SSP Completion (64 bytes) |
| 482 | */ |
| 483 | struct ssp_event_resp { |
| 484 | __le32 tag; |
| 485 | __le32 event; |
| 486 | __le32 port_id; |
| 487 | __le32 device_id; |
| 488 | __le32 ssp_tag; |
| 489 | __le32 event_param0; |
| 490 | __le32 event_param1; |
| 491 | __le32 sas_addr_h32; |
| 492 | __le32 sas_addr_l32; |
| 493 | __le32 e_udt1_udt0_crc; |
| 494 | __le32 e_udt5_udt4_udt3_udt2; |
| 495 | __le32 a_udt1_udt0_crc; |
| 496 | __le32 a_udt5_udt4_udt3_udt2; |
| 497 | __le32 hwdevid_diferr; |
| 498 | __le32 err_framelen_byteoffset; |
| 499 | __le32 err_dataframe; |
| 500 | } __attribute__((packed, aligned(4))); |
| 501 | |
| 502 | /** |
| 503 | * brief the data structure of General Event Notification Response |
| 504 | * use to describe MPI General Event Notification Response (64 bytes) |
| 505 | */ |
| 506 | struct general_event_resp { |
| 507 | __le32 status; |
| 508 | __le32 inb_IOMB_payload[14]; |
| 509 | } __attribute__((packed, aligned(4))); |
| 510 | |
| 511 | #define GENERAL_EVENT_PAYLOAD 14 |
| 512 | #define OPCODE_BITS 0x00000fff |
| 513 | |
| 514 | /* |
| 515 | * brief the data structure of SMP Request Command |
| 516 | * use to describe MPI SMP REQUEST Command (64 bytes) |
| 517 | */ |
| 518 | struct smp_req { |
| 519 | __le32 tag; |
| 520 | __le32 device_id; |
| 521 | __le32 len_ip_ir; |
| 522 | /* Bits [0] - Indirect response */ |
| 523 | /* Bits [1] - Indirect Payload */ |
| 524 | /* Bits [15:2] - Reserved */ |
| 525 | /* Bits [23:16] - direct payload Len */ |
| 526 | /* Bits [31:24] - Reserved */ |
| 527 | u8 smp_req16[16]; |
| 528 | union { |
| 529 | u8 smp_req[32]; |
| 530 | struct { |
| 531 | __le64 long_req_addr;/* sg dma address, LE */ |
| 532 | __le32 long_req_size;/* LE */ |
| 533 | u32 _r_a; |
| 534 | __le64 long_resp_addr;/* sg dma address, LE */ |
| 535 | __le32 long_resp_size;/* LE */ |
| 536 | u32 _r_b; |
| 537 | } long_smp_req;/* sequencer extension */ |
| 538 | }; |
| 539 | __le32 rsvd[16]; |
| 540 | } __attribute__((packed, aligned(4))); |
| 541 | /* |
| 542 | * brief the data structure of SMP Completion Response |
| 543 | * use to describe MPI SMP Completion Response (64 bytes) |
| 544 | */ |
| 545 | struct smp_completion_resp { |
| 546 | __le32 tag; |
| 547 | __le32 status; |
| 548 | __le32 param; |
| 549 | u8 _r_a[252]; |
| 550 | } __attribute__((packed, aligned(4))); |
| 551 | |
| 552 | /* |
| 553 | *brief the data structure of SSP SMP SATA Abort Command |
| 554 | * use to describe MPI SSP SMP & SATA Abort Command (64 bytes) |
| 555 | */ |
| 556 | struct task_abort_req { |
| 557 | __le32 tag; |
| 558 | __le32 device_id; |
| 559 | __le32 tag_to_abort; |
| 560 | __le32 abort_all; |
| 561 | u32 reserved[27]; |
| 562 | } __attribute__((packed, aligned(4))); |
| 563 | |
| 564 | /* These flags used for SSP SMP & SATA Abort */ |
| 565 | #define ABORT_MASK 0x3 |
| 566 | #define ABORT_SINGLE 0x0 |
| 567 | #define ABORT_ALL 0x1 |
| 568 | |
| 569 | /** |
| 570 | * brief the data structure of SSP SATA SMP Abort Response |
| 571 | * use to describe SSP SMP & SATA Abort Response ( 64 bytes) |
| 572 | */ |
| 573 | struct task_abort_resp { |
| 574 | __le32 tag; |
| 575 | __le32 status; |
| 576 | __le32 scp; |
| 577 | u32 reserved[12]; |
| 578 | } __attribute__((packed, aligned(4))); |
| 579 | |
| 580 | /** |
| 581 | * brief the data structure of SAS Diagnostic Start/End Command |
| 582 | * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) |
| 583 | */ |
| 584 | struct sas_diag_start_end_req { |
| 585 | __le32 tag; |
| 586 | __le32 operation_phyid; |
| 587 | u32 reserved[29]; |
| 588 | } __attribute__((packed, aligned(4))); |
| 589 | |
| 590 | /** |
| 591 | * brief the data structure of SAS Diagnostic Execute Command |
| 592 | * use to describe MPI SAS Diagnostic Execute Command (64 bytes) |
| 593 | */ |
| 594 | struct sas_diag_execute_req { |
| 595 | __le32 tag; |
| 596 | __le32 cmdtype_cmddesc_phyid; |
| 597 | __le32 pat1_pat2; |
| 598 | __le32 threshold; |
| 599 | __le32 codepat_errmsk; |
| 600 | __le32 pmon; |
| 601 | __le32 pERF1CTL; |
| 602 | u32 reserved[24]; |
| 603 | } __attribute__((packed, aligned(4))); |
| 604 | |
| 605 | #define SAS_DIAG_PARAM_BYTES 24 |
| 606 | |
| 607 | /* |
| 608 | * brief the data structure of Set Device State Command |
| 609 | * use to describe MPI Set Device State Command (64 bytes) |
| 610 | */ |
| 611 | struct set_dev_state_req { |
| 612 | __le32 tag; |
| 613 | __le32 device_id; |
| 614 | __le32 nds; |
| 615 | u32 reserved[28]; |
| 616 | } __attribute__((packed, aligned(4))); |
| 617 | |
| 618 | /* |
| 619 | * brief the data structure of SATA Start Command |
| 620 | * use to describe MPI SATA IO Start Command (64 bytes) |
| 621 | * Note: This structure is common for normal / encryption I/O |
| 622 | */ |
| 623 | |
| 624 | struct sata_start_req { |
| 625 | __le32 tag; |
| 626 | __le32 device_id; |
| 627 | __le32 data_len; |
| 628 | __le32 ncqtag_atap_dir_m_dad; |
| 629 | struct host_to_dev_fis sata_fis; |
| 630 | u32 reserved1; |
| 631 | u32 reserved2; /* dword 11. rsvd for normal I/O. */ |
| 632 | /* EPLE Descl for enc I/O */ |
| 633 | u32 addr_low; /* dword 12. rsvd for enc I/O */ |
| 634 | u32 addr_high; /* dword 13. reserved for enc I/O */ |
| 635 | __le32 len; /* dword 14: length for normal I/O. */ |
| 636 | /* EPLE Desch for enc I/O */ |
| 637 | __le32 esgl; /* dword 15. rsvd for enc I/O */ |
| 638 | __le32 atapi_scsi_cdb[4]; /* dword 16-19. rsvd for enc I/O */ |
| 639 | /* The below fields are reserved for normal I/O */ |
| 640 | __le32 key_index_mode; /* dword 20 */ |
| 641 | __le32 sector_cnt_enss;/* dword 21 */ |
| 642 | __le32 keytagl; /* dword 22 */ |
| 643 | __le32 keytagh; /* dword 23 */ |
| 644 | __le32 twk_val0; /* dword 24 */ |
| 645 | __le32 twk_val1; /* dword 25 */ |
| 646 | __le32 twk_val2; /* dword 26 */ |
| 647 | __le32 twk_val3; /* dword 27 */ |
| 648 | __le32 enc_addr_low; /* dword 28. Encryption SGL address high */ |
| 649 | __le32 enc_addr_high; /* dword 29. Encryption SGL address low */ |
| 650 | __le32 enc_len; /* dword 30. Encryption length */ |
| 651 | __le32 enc_esgl; /* dword 31. Encryption esgl bit */ |
| 652 | } __attribute__((packed, aligned(4))); |
| 653 | |
| 654 | /** |
| 655 | * brief the data structure of SSP INI TM Start Command |
| 656 | * use to describe MPI SSP INI TM Start Command (64 bytes) |
| 657 | */ |
| 658 | struct ssp_ini_tm_start_req { |
| 659 | __le32 tag; |
| 660 | __le32 device_id; |
| 661 | __le32 relate_tag; |
| 662 | __le32 tmf; |
| 663 | u8 lun[8]; |
| 664 | __le32 ds_ads_m; |
| 665 | u32 reserved[24]; |
| 666 | } __attribute__((packed, aligned(4))); |
| 667 | |
| 668 | struct ssp_info_unit { |
| 669 | u8 lun[8];/* SCSI Logical Unit Number */ |
| 670 | u8 reserved1;/* reserved */ |
| 671 | u8 efb_prio_attr; |
| 672 | /* B7 : enabledFirstBurst */ |
| 673 | /* B6-3 : taskPriority */ |
| 674 | /* B2-0 : taskAttribute */ |
| 675 | u8 reserved2; /* reserved */ |
| 676 | u8 additional_cdb_len; |
| 677 | /* B7-2 : additional_cdb_len */ |
| 678 | /* B1-0 : reserved */ |
| 679 | u8 cdb[16];/* The SCSI CDB up to 16 bytes length */ |
| 680 | } __attribute__((packed, aligned(4))); |
| 681 | |
| 682 | /** |
| 683 | * brief the data structure of SSP INI IO Start Command |
| 684 | * use to describe MPI SSP INI IO Start Command (64 bytes) |
| 685 | * Note: This structure is common for normal / encryption I/O |
| 686 | */ |
| 687 | struct ssp_ini_io_start_req { |
| 688 | __le32 tag; |
| 689 | __le32 device_id; |
| 690 | __le32 data_len; |
| 691 | __le32 dad_dir_m_tlr; |
| 692 | struct ssp_info_unit ssp_iu; |
| 693 | __le32 addr_low; /* dword 12: sgl low for normal I/O. */ |
| 694 | /* epl_descl for encryption I/O */ |
| 695 | __le32 addr_high; /* dword 13: sgl hi for normal I/O */ |
| 696 | /* dpl_descl for encryption I/O */ |
| 697 | __le32 len; /* dword 14: len for normal I/O. */ |
| 698 | /* edpl_desch for encryption I/O */ |
| 699 | __le32 esgl; /* dword 15: ESGL bit for normal I/O. */ |
| 700 | /* user defined tag mask for enc I/O */ |
| 701 | /* The below fields are reserved for normal I/O */ |
| 702 | u8 udt[12]; /* dword 16-18 */ |
| 703 | __le32 sectcnt_ios; /* dword 19 */ |
| 704 | __le32 key_cmode; /* dword 20 */ |
| 705 | __le32 ks_enss; /* dword 21 */ |
| 706 | __le32 keytagl; /* dword 22 */ |
| 707 | __le32 keytagh; /* dword 23 */ |
| 708 | __le32 twk_val0; /* dword 24 */ |
| 709 | __le32 twk_val1; /* dword 25 */ |
| 710 | __le32 twk_val2; /* dword 26 */ |
| 711 | __le32 twk_val3; /* dword 27 */ |
| 712 | __le32 enc_addr_low; /* dword 28: Encryption sgl addr low */ |
| 713 | __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */ |
| 714 | __le32 enc_len; /* dword 30: Encryption length */ |
| 715 | __le32 enc_esgl; /* dword 31: ESGL bit for encryption */ |
| 716 | } __attribute__((packed, aligned(4))); |
| 717 | |
| 718 | /** |
| 719 | * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND |
| 720 | * use to initiate SSP I/O operation with optional DIF/ENC |
| 721 | */ |
| 722 | struct ssp_dif_enc_io_req { |
| 723 | __le32 tag; |
| 724 | __le32 device_id; |
| 725 | __le32 data_len; |
| 726 | __le32 dirMTlr; |
| 727 | __le32 sspiu0; |
| 728 | __le32 sspiu1; |
| 729 | __le32 sspiu2; |
| 730 | __le32 sspiu3; |
| 731 | __le32 sspiu4; |
| 732 | __le32 sspiu5; |
| 733 | __le32 sspiu6; |
| 734 | __le32 epl_des; |
| 735 | __le32 dpl_desl_ndplr; |
| 736 | __le32 dpl_desh; |
| 737 | __le32 uum_uuv_bss_difbits; |
| 738 | u8 udt[12]; |
| 739 | __le32 sectcnt_ios; |
| 740 | __le32 key_cmode; |
| 741 | __le32 ks_enss; |
| 742 | __le32 keytagl; |
| 743 | __le32 keytagh; |
| 744 | __le32 twk_val0; |
| 745 | __le32 twk_val1; |
| 746 | __le32 twk_val2; |
| 747 | __le32 twk_val3; |
| 748 | __le32 addr_low; |
| 749 | __le32 addr_high; |
| 750 | __le32 len; |
| 751 | __le32 esgl; |
| 752 | } __attribute__((packed, aligned(4))); |
| 753 | |
| 754 | /** |
| 755 | * brief the data structure of Firmware download |
| 756 | * use to describe MPI FW DOWNLOAD Command (64 bytes) |
| 757 | */ |
| 758 | struct fw_flash_Update_req { |
| 759 | __le32 tag; |
| 760 | __le32 cur_image_offset; |
| 761 | __le32 cur_image_len; |
| 762 | __le32 total_image_len; |
| 763 | u32 reserved0[7]; |
| 764 | __le32 sgl_addr_lo; |
| 765 | __le32 sgl_addr_hi; |
| 766 | __le32 len; |
| 767 | __le32 ext_reserved; |
| 768 | u32 reserved1[16]; |
| 769 | } __attribute__((packed, aligned(4))); |
| 770 | |
| 771 | #define FWFLASH_IOMB_RESERVED_LEN 0x07 |
| 772 | /** |
| 773 | * brief the data structure of FW_FLASH_UPDATE Response |
| 774 | * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) |
| 775 | * |
| 776 | */ |
| 777 | struct fw_flash_Update_resp { |
| 778 | __le32 tag; |
| 779 | __le32 status; |
| 780 | u32 reserved[13]; |
| 781 | } __attribute__((packed, aligned(4))); |
| 782 | |
| 783 | /** |
| 784 | * brief the data structure of Get NVM Data Command |
| 785 | * use to get data from NVM in HBA(64 bytes) |
| 786 | */ |
| 787 | struct get_nvm_data_req { |
| 788 | __le32 tag; |
| 789 | __le32 len_ir_vpdd; |
| 790 | __le32 vpd_offset; |
| 791 | u32 reserved[8]; |
| 792 | __le32 resp_addr_lo; |
| 793 | __le32 resp_addr_hi; |
| 794 | __le32 resp_len; |
| 795 | u32 reserved1[17]; |
| 796 | } __attribute__((packed, aligned(4))); |
| 797 | |
| 798 | struct set_nvm_data_req { |
| 799 | __le32 tag; |
| 800 | __le32 len_ir_vpdd; |
| 801 | __le32 vpd_offset; |
| 802 | u32 reserved[8]; |
| 803 | __le32 resp_addr_lo; |
| 804 | __le32 resp_addr_hi; |
| 805 | __le32 resp_len; |
| 806 | u32 reserved1[17]; |
| 807 | } __attribute__((packed, aligned(4))); |
| 808 | |
| 809 | /** |
| 810 | * brief the data structure for SET CONTROLLER CONFIG COMMAND |
| 811 | * use to modify controller configuration |
| 812 | */ |
| 813 | struct set_ctrl_cfg_req { |
| 814 | __le32 tag; |
| 815 | __le32 cfg_pg[14]; |
| 816 | u32 reserved[16]; |
| 817 | } __attribute__((packed, aligned(4))); |
| 818 | |
| 819 | /** |
| 820 | * brief the data structure for GET CONTROLLER CONFIG COMMAND |
| 821 | * use to get controller configuration page |
| 822 | */ |
| 823 | struct get_ctrl_cfg_req { |
| 824 | __le32 tag; |
| 825 | __le32 pgcd; |
| 826 | __le32 int_vec; |
| 827 | u32 reserved[28]; |
| 828 | } __attribute__((packed, aligned(4))); |
| 829 | |
| 830 | /** |
| 831 | * brief the data structure for KEK_MANAGEMENT COMMAND |
| 832 | * use for KEK management |
| 833 | */ |
| 834 | struct kek_mgmt_req { |
| 835 | __le32 tag; |
| 836 | __le32 new_curidx_ksop; |
| 837 | u32 reserved; |
| 838 | __le32 kblob[12]; |
| 839 | u32 reserved1[16]; |
| 840 | } __attribute__((packed, aligned(4))); |
| 841 | |
| 842 | /** |
| 843 | * brief the data structure for DEK_MANAGEMENT COMMAND |
| 844 | * use for DEK management |
| 845 | */ |
| 846 | struct dek_mgmt_req { |
| 847 | __le32 tag; |
| 848 | __le32 kidx_dsop; |
| 849 | __le32 dekidx; |
| 850 | __le32 addr_l; |
| 851 | __le32 addr_h; |
| 852 | __le32 nent; |
| 853 | __le32 dbf_tblsize; |
| 854 | u32 reserved[24]; |
| 855 | } __attribute__((packed, aligned(4))); |
| 856 | |
| 857 | /** |
| 858 | * brief the data structure for SET PHY PROFILE COMMAND |
| 859 | * use to retrive phy specific information |
| 860 | */ |
| 861 | struct set_phy_profile_req { |
| 862 | __le32 tag; |
| 863 | __le32 ppc_phyid; |
| 864 | u32 reserved[29]; |
| 865 | } __attribute__((packed, aligned(4))); |
| 866 | |
| 867 | /** |
| 868 | * brief the data structure for GET PHY PROFILE COMMAND |
| 869 | * use to retrive phy specific information |
| 870 | */ |
| 871 | struct get_phy_profile_req { |
| 872 | __le32 tag; |
| 873 | __le32 ppc_phyid; |
| 874 | __le32 profile[29]; |
| 875 | } __attribute__((packed, aligned(4))); |
| 876 | |
| 877 | /** |
| 878 | * brief the data structure for EXT FLASH PARTITION |
| 879 | * use to manage ext flash partition |
| 880 | */ |
| 881 | struct ext_flash_partition_req { |
| 882 | __le32 tag; |
| 883 | __le32 cmd; |
| 884 | __le32 offset; |
| 885 | __le32 len; |
| 886 | u32 reserved[7]; |
| 887 | __le32 addr_low; |
| 888 | __le32 addr_high; |
| 889 | __le32 len1; |
| 890 | __le32 ext; |
| 891 | u32 reserved1[16]; |
| 892 | } __attribute__((packed, aligned(4))); |
| 893 | |
| 894 | #define TWI_DEVICE 0x0 |
| 895 | #define C_SEEPROM 0x1 |
| 896 | #define VPD_FLASH 0x4 |
| 897 | #define AAP1_RDUMP 0x5 |
| 898 | #define IOP_RDUMP 0x6 |
| 899 | #define EXPAN_ROM 0x7 |
| 900 | |
| 901 | #define IPMode 0x80000000 |
| 902 | #define NVMD_TYPE 0x0000000F |
| 903 | #define NVMD_STAT 0x0000FFFF |
| 904 | #define NVMD_LEN 0xFF000000 |
| 905 | /** |
| 906 | * brief the data structure of Get NVMD Data Response |
| 907 | * use to describe MPI Get NVMD Data Response (64 bytes) |
| 908 | */ |
| 909 | struct get_nvm_data_resp { |
| 910 | __le32 tag; |
| 911 | __le32 ir_tda_bn_dps_das_nvm; |
| 912 | __le32 dlen_status; |
| 913 | __le32 nvm_data[12]; |
| 914 | } __attribute__((packed, aligned(4))); |
| 915 | |
| 916 | /** |
| 917 | * brief the data structure of SAS Diagnostic Start/End Response |
| 918 | * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) |
| 919 | * |
| 920 | */ |
| 921 | struct sas_diag_start_end_resp { |
| 922 | __le32 tag; |
| 923 | __le32 status; |
| 924 | u32 reserved[13]; |
| 925 | } __attribute__((packed, aligned(4))); |
| 926 | |
| 927 | /** |
| 928 | * brief the data structure of SAS Diagnostic Execute Response |
| 929 | * use to describe MPI SAS Diagnostic Execute Response (64 bytes) |
| 930 | * |
| 931 | */ |
| 932 | struct sas_diag_execute_resp { |
| 933 | __le32 tag; |
| 934 | __le32 cmdtype_cmddesc_phyid; |
| 935 | __le32 Status; |
| 936 | __le32 ReportData; |
| 937 | u32 reserved[11]; |
| 938 | } __attribute__((packed, aligned(4))); |
| 939 | |
| 940 | /** |
| 941 | * brief the data structure of Set Device State Response |
| 942 | * use to describe MPI Set Device State Response (64 bytes) |
| 943 | * |
| 944 | */ |
| 945 | struct set_dev_state_resp { |
| 946 | __le32 tag; |
| 947 | __le32 status; |
| 948 | __le32 device_id; |
| 949 | __le32 pds_nds; |
| 950 | u32 reserved[11]; |
| 951 | } __attribute__((packed, aligned(4))); |
| 952 | |
| 953 | /* new outbound structure for spcv - begins */ |
| 954 | /** |
| 955 | * brief the data structure for SET CONTROLLER CONFIG COMMAND |
| 956 | * use to modify controller configuration |
| 957 | */ |
| 958 | struct set_ctrl_cfg_resp { |
| 959 | __le32 tag; |
| 960 | __le32 status; |
| 961 | __le32 err_qlfr_pgcd; |
| 962 | u32 reserved[12]; |
| 963 | } __attribute__((packed, aligned(4))); |
| 964 | |
| 965 | struct get_ctrl_cfg_resp { |
| 966 | __le32 tag; |
| 967 | __le32 status; |
| 968 | __le32 err_qlfr; |
| 969 | __le32 confg_page[12]; |
| 970 | } __attribute__((packed, aligned(4))); |
| 971 | |
| 972 | struct kek_mgmt_resp { |
| 973 | __le32 tag; |
| 974 | __le32 status; |
| 975 | __le32 kidx_new_curr_ksop; |
| 976 | __le32 err_qlfr; |
| 977 | u32 reserved[11]; |
| 978 | } __attribute__((packed, aligned(4))); |
| 979 | |
| 980 | struct dek_mgmt_resp { |
| 981 | __le32 tag; |
| 982 | __le32 status; |
| 983 | __le32 kekidx_tbls_dsop; |
| 984 | __le32 dekidx; |
| 985 | __le32 err_qlfr; |
| 986 | u32 reserved[10]; |
| 987 | } __attribute__((packed, aligned(4))); |
| 988 | |
| 989 | struct get_phy_profile_resp { |
| 990 | __le32 tag; |
| 991 | __le32 status; |
| 992 | __le32 ppc_phyid; |
| 993 | __le32 ppc_specific_rsp[12]; |
| 994 | } __attribute__((packed, aligned(4))); |
| 995 | |
| 996 | struct flash_op_ext_resp { |
| 997 | __le32 tag; |
| 998 | __le32 cmd; |
| 999 | __le32 status; |
| 1000 | __le32 epart_size; |
| 1001 | __le32 epart_sect_size; |
| 1002 | u32 reserved[10]; |
| 1003 | } __attribute__((packed, aligned(4))); |
| 1004 | |
| 1005 | struct set_phy_profile_resp { |
| 1006 | __le32 tag; |
| 1007 | __le32 status; |
| 1008 | __le32 ppc_phyid; |
| 1009 | __le32 ppc_specific_rsp[12]; |
| 1010 | } __attribute__((packed, aligned(4))); |
| 1011 | |
| 1012 | struct ssp_coalesced_comp_resp { |
| 1013 | __le32 coal_cnt; |
| 1014 | __le32 tag0; |
| 1015 | __le32 ssp_tag0; |
| 1016 | __le32 tag1; |
| 1017 | __le32 ssp_tag1; |
| 1018 | __le32 add_tag_ssp_tag[10]; |
| 1019 | } __attribute__((packed, aligned(4))); |
| 1020 | |
| 1021 | /* new outbound structure for spcv - ends */ |
| 1022 | |
Sakthivel K | a6cb3d0 | 2013-03-19 18:08:40 +0530 | [diff] [blame] | 1023 | /* brief data structure for SAS protocol timer configuration page. |
| 1024 | * |
| 1025 | */ |
| 1026 | struct SASProtocolTimerConfig { |
| 1027 | __le32 pageCode; /* 0 */ |
| 1028 | __le32 MST_MSI; /* 1 */ |
| 1029 | __le32 STP_SSP_MCT_TMO; /* 2 */ |
| 1030 | __le32 STP_FRM_TMO; /* 3 */ |
| 1031 | __le32 STP_IDLE_TMO; /* 4 */ |
| 1032 | __le32 OPNRJT_RTRY_INTVL; /* 5 */ |
| 1033 | __le32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */ |
| 1034 | __le32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */ |
| 1035 | __le32 MAX_AIP; /* 8 */ |
| 1036 | } __attribute__((packed, aligned(4))); |
| 1037 | |
| 1038 | typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t; |
| 1039 | |
Sakthivel K | f586099 | 2013-04-17 16:37:02 +0530 | [diff] [blame] | 1040 | #define NDS_BITS 0x0F |
| 1041 | #define PDS_BITS 0xF0 |
| 1042 | |
| 1043 | /* |
| 1044 | * HW Events type |
| 1045 | */ |
| 1046 | |
| 1047 | #define HW_EVENT_RESET_START 0x01 |
| 1048 | #define HW_EVENT_CHIP_RESET_COMPLETE 0x02 |
| 1049 | #define HW_EVENT_PHY_STOP_STATUS 0x03 |
| 1050 | #define HW_EVENT_SAS_PHY_UP 0x04 |
| 1051 | #define HW_EVENT_SATA_PHY_UP 0x05 |
| 1052 | #define HW_EVENT_SATA_SPINUP_HOLD 0x06 |
| 1053 | #define HW_EVENT_PHY_DOWN 0x07 |
| 1054 | #define HW_EVENT_PORT_INVALID 0x08 |
| 1055 | #define HW_EVENT_BROADCAST_CHANGE 0x09 |
| 1056 | #define HW_EVENT_PHY_ERROR 0x0A |
| 1057 | #define HW_EVENT_BROADCAST_SES 0x0B |
| 1058 | #define HW_EVENT_INBOUND_CRC_ERROR 0x0C |
| 1059 | #define HW_EVENT_HARD_RESET_RECEIVED 0x0D |
| 1060 | #define HW_EVENT_MALFUNCTION 0x0E |
| 1061 | #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F |
| 1062 | #define HW_EVENT_BROADCAST_EXP 0x10 |
| 1063 | #define HW_EVENT_PHY_START_STATUS 0x11 |
| 1064 | #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12 |
| 1065 | #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13 |
| 1066 | #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14 |
| 1067 | #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15 |
| 1068 | #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16 |
| 1069 | #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 |
| 1070 | #define HW_EVENT_PORT_RECOVER 0x18 |
| 1071 | #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19 |
| 1072 | #define HW_EVENT_PORT_RESET_COMPLETE 0x20 |
| 1073 | #define EVENT_BROADCAST_ASYNCH_EVENT 0x21 |
| 1074 | |
| 1075 | /* port state */ |
| 1076 | #define PORT_NOT_ESTABLISHED 0x00 |
| 1077 | #define PORT_VALID 0x01 |
| 1078 | #define PORT_LOSTCOMM 0x02 |
| 1079 | #define PORT_IN_RESET 0x04 |
| 1080 | #define PORT_3RD_PARTY_RESET 0x07 |
| 1081 | #define PORT_INVALID 0x08 |
| 1082 | |
| 1083 | /* |
| 1084 | * SSP/SMP/SATA IO Completion Status values |
| 1085 | */ |
| 1086 | |
| 1087 | #define IO_SUCCESS 0x00 |
| 1088 | #define IO_ABORTED 0x01 |
| 1089 | #define IO_OVERFLOW 0x02 |
| 1090 | #define IO_UNDERFLOW 0x03 |
| 1091 | #define IO_FAILED 0x04 |
| 1092 | #define IO_ABORT_RESET 0x05 |
| 1093 | #define IO_NOT_VALID 0x06 |
| 1094 | #define IO_NO_DEVICE 0x07 |
| 1095 | #define IO_ILLEGAL_PARAMETER 0x08 |
| 1096 | #define IO_LINK_FAILURE 0x09 |
| 1097 | #define IO_PROG_ERROR 0x0A |
| 1098 | |
| 1099 | #define IO_EDC_IN_ERROR 0x0B |
| 1100 | #define IO_EDC_OUT_ERROR 0x0C |
| 1101 | #define IO_ERROR_HW_TIMEOUT 0x0D |
| 1102 | #define IO_XFER_ERROR_BREAK 0x0E |
| 1103 | #define IO_XFER_ERROR_PHY_NOT_READY 0x0F |
| 1104 | #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10 |
| 1105 | #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11 |
| 1106 | #define IO_OPEN_CNX_ERROR_BREAK 0x12 |
| 1107 | #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13 |
| 1108 | #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14 |
| 1109 | #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15 |
| 1110 | #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16 |
| 1111 | #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17 |
| 1112 | /* This error code 0x18 is not used on SPCv */ |
| 1113 | #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18 |
| 1114 | #define IO_XFER_ERROR_NAK_RECEIVED 0x19 |
| 1115 | #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A |
| 1116 | #define IO_XFER_ERROR_PEER_ABORTED 0x1B |
| 1117 | #define IO_XFER_ERROR_RX_FRAME 0x1C |
| 1118 | #define IO_XFER_ERROR_DMA 0x1D |
| 1119 | #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E |
| 1120 | #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F |
| 1121 | #define IO_XFER_ERROR_SATA 0x20 |
| 1122 | |
| 1123 | /* This error code 0x22 is not used on SPCv */ |
| 1124 | #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22 |
| 1125 | #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21 |
| 1126 | #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23 |
| 1127 | #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24 |
| 1128 | /* This error code 0x25 is not used on SPCv */ |
| 1129 | #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25 |
| 1130 | #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26 |
| 1131 | #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27 |
| 1132 | #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28 |
| 1133 | #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30 |
| 1134 | |
| 1135 | /* The following error code 0x31 and 0x32 are not using (obsolete) */ |
| 1136 | #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31 |
| 1137 | #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32 |
| 1138 | |
| 1139 | #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34 |
| 1140 | #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35 |
| 1141 | #define IO_XFER_CMD_FRAME_ISSUED 0x36 |
| 1142 | #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37 |
| 1143 | #define IO_PORT_IN_RESET 0x38 |
| 1144 | #define IO_DS_NON_OPERATIONAL 0x39 |
| 1145 | #define IO_DS_IN_RECOVERY 0x3A |
| 1146 | #define IO_TM_TAG_NOT_FOUND 0x3B |
| 1147 | #define IO_XFER_PIO_SETUP_ERROR 0x3C |
| 1148 | #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D |
| 1149 | #define IO_DS_IN_ERROR 0x3E |
| 1150 | #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F |
| 1151 | #define IO_ABORT_IN_PROGRESS 0x40 |
| 1152 | #define IO_ABORT_DELAYED 0x41 |
| 1153 | #define IO_INVALID_LENGTH 0x42 |
| 1154 | |
| 1155 | /********** additional response event values *****************/ |
| 1156 | |
| 1157 | #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43 |
| 1158 | #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44 |
| 1159 | #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45 |
| 1160 | #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46 |
| 1161 | #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47 |
| 1162 | #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48 |
| 1163 | #define IO_DS_INVALID 0x49 |
| 1164 | /* WARNING: the value is not contiguous from here */ |
| 1165 | #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52 |
Sakthivel K | a6cb3d0 | 2013-03-19 18:08:40 +0530 | [diff] [blame] | 1166 | #define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53 |
| 1167 | #define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54 |
Sakthivel K | f586099 | 2013-04-17 16:37:02 +0530 | [diff] [blame] | 1168 | #define MPI_IO_RQE_BUSY_FULL 0x55 |
| 1169 | #define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56 |
| 1170 | #define IO_XFR_ERROR_INVALID_SSP_RSP_FRAME 0x57 |
| 1171 | #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58 |
| 1172 | |
| 1173 | #define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 |
| 1174 | #define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024 |
| 1175 | |
| 1176 | #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040 |
| 1177 | /* |
| 1178 | * An encryption IO request failed due to DEK Key Tag mismatch. |
| 1179 | * The key tag supplied in the encryption IOMB does not match with |
| 1180 | * the Key Tag in the referenced DEK Entry. |
| 1181 | */ |
| 1182 | #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041 |
| 1183 | #define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042 |
| 1184 | /* |
| 1185 | * An encryption I/O request failed because the initial value (IV) |
| 1186 | * in the unwrapped DEK blob didn't match the IV used to unwrap it. |
| 1187 | */ |
| 1188 | #define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043 |
| 1189 | /* An encryption I/O request failed due to an internal RAM ECC or |
| 1190 | * interface error while unwrapping the DEK. */ |
| 1191 | #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044 |
| 1192 | /* An encryption I/O request failed due to an internal RAM ECC or |
| 1193 | * interface error while unwrapping the DEK. */ |
| 1194 | #define IO_XFR_ERROR_INTERNAL_RAM 0x2045 |
| 1195 | /* |
| 1196 | * An encryption I/O request failed |
| 1197 | * because the DEK index specified in the I/O was outside the bounds of |
| 1198 | * the total number of entries in the host DEK table. |
| 1199 | */ |
| 1200 | #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046 |
| 1201 | |
| 1202 | /* define DIF IO response error status code */ |
| 1203 | #define IO_XFR_ERROR_DIF_MISMATCH 0x3000 |
| 1204 | #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 |
| 1205 | #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 |
| 1206 | #define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 |
| 1207 | |
| 1208 | /* define operator management response status and error qualifier code */ |
| 1209 | #define OPR_MGMT_OP_NOT_SUPPORTED 0x2060 |
| 1210 | #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 |
| 1211 | #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 |
| 1212 | #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 |
| 1213 | #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 |
| 1214 | #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022 |
| 1215 | #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023 |
| 1216 | /***************** additional response event values ***************/ |
| 1217 | |
| 1218 | /* WARNING: This error code must always be the last number. |
| 1219 | * If you add error code, modify this code also |
| 1220 | * It is used as an index |
| 1221 | */ |
| 1222 | #define IO_ERROR_UNKNOWN_GENERIC 0x2023 |
| 1223 | |
| 1224 | /* MSGU CONFIGURATION TABLE*/ |
| 1225 | |
| 1226 | #define SPCv_MSGU_CFG_TABLE_UPDATE 0x01 |
| 1227 | #define SPCv_MSGU_CFG_TABLE_RESET 0x02 |
| 1228 | #define SPCv_MSGU_CFG_TABLE_FREEZE 0x04 |
| 1229 | #define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x08 |
| 1230 | #define MSGU_IBDB_SET 0x00 |
| 1231 | #define MSGU_HOST_INT_STATUS 0x08 |
| 1232 | #define MSGU_HOST_INT_MASK 0x0C |
| 1233 | #define MSGU_IOPIB_INT_STATUS 0x18 |
| 1234 | #define MSGU_IOPIB_INT_MASK 0x1C |
| 1235 | #define MSGU_IBDB_CLEAR 0x20 |
| 1236 | |
| 1237 | #define MSGU_MSGU_CONTROL 0x24 |
| 1238 | #define MSGU_ODR 0x20 |
| 1239 | #define MSGU_ODCR 0x28 |
| 1240 | |
| 1241 | #define MSGU_ODMR 0x30 |
| 1242 | #define MSGU_ODMR_U 0x34 |
| 1243 | #define MSGU_ODMR_CLR 0x38 |
| 1244 | #define MSGU_ODMR_CLR_U 0x3C |
| 1245 | #define MSGU_OD_RSVD 0x40 |
| 1246 | |
| 1247 | #define MSGU_SCRATCH_PAD_0 0x44 |
| 1248 | #define MSGU_SCRATCH_PAD_1 0x48 |
| 1249 | #define MSGU_SCRATCH_PAD_2 0x4C |
| 1250 | #define MSGU_SCRATCH_PAD_3 0x50 |
| 1251 | #define MSGU_HOST_SCRATCH_PAD_0 0x54 |
| 1252 | #define MSGU_HOST_SCRATCH_PAD_1 0x58 |
| 1253 | #define MSGU_HOST_SCRATCH_PAD_2 0x5C |
| 1254 | #define MSGU_HOST_SCRATCH_PAD_3 0x60 |
| 1255 | #define MSGU_HOST_SCRATCH_PAD_4 0x64 |
| 1256 | #define MSGU_HOST_SCRATCH_PAD_5 0x68 |
| 1257 | #define MSGU_HOST_SCRATCH_PAD_6 0x6C |
| 1258 | #define MSGU_HOST_SCRATCH_PAD_7 0x70 |
| 1259 | |
| 1260 | /* bit definition for ODMR register */ |
| 1261 | #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all |
| 1262 | interrupt vector */ |
| 1263 | #define ODMR_CLEAR_ALL 0 /* clear all |
| 1264 | interrupt vector */ |
| 1265 | /* bit definition for ODCR register */ |
| 1266 | #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all |
| 1267 | interrupt vector*/ |
| 1268 | /* MSIX Interupts */ |
| 1269 | #define MSIX_TABLE_OFFSET 0x2000 |
| 1270 | #define MSIX_TABLE_ELEMENT_SIZE 0x10 |
| 1271 | #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC |
| 1272 | #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \ |
| 1273 | MSIX_INTERRUPT_CONTROL_OFFSET) |
| 1274 | #define MSIX_INTERRUPT_DISABLE 0x1 |
| 1275 | #define MSIX_INTERRUPT_ENABLE 0x0 |
| 1276 | |
| 1277 | /* state definition for Scratch Pad1 register */ |
| 1278 | #define SCRATCH_PAD_RAAE_READY 0x3 |
| 1279 | #define SCRATCH_PAD_ILA_READY 0xC |
| 1280 | #define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0 |
| 1281 | #define SCRATCH_PAD_IOP0_READY 0xC00 |
| 1282 | #define SCRATCH_PAD_IOP1_READY 0x3000 |
| 1283 | |
| 1284 | /* boot loader state */ |
| 1285 | #define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */ |
| 1286 | #define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0 /* Load successful */ |
| 1287 | #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10 /* HDA SEEPROM */ |
| 1288 | #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20 /* HDA BootStrap Pins */ |
| 1289 | #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30 /* HDA Soft Reset */ |
| 1290 | #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40 /* HDA critical error */ |
| 1291 | #define SCRATCH_PAD1_BOOTSTATE_R1 0x50 /* Reserved */ |
| 1292 | #define SCRATCH_PAD1_BOOTSTATE_R2 0x60 /* Reserved */ |
| 1293 | #define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70 /* Fatal Error */ |
| 1294 | |
| 1295 | /* state definition for Scratch Pad2 register */ |
| 1296 | #define SCRATCH_PAD2_POR 0x00 /* power on state */ |
| 1297 | #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */ |
| 1298 | #define SCRATCH_PAD2_ERR 0x02 /* error state */ |
| 1299 | #define SCRATCH_PAD2_RDY 0x03 /* ready state */ |
| 1300 | #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW rdy for soft reset flag */ |
| 1301 | #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */ |
| 1302 | #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2 |
| 1303 | Mask, bit1-0 State */ |
| 1304 | #define SCRATCH_PAD2_RESERVED 0x000003FC/* Scratch Pad1 |
| 1305 | Reserved bit 2 to 9 */ |
| 1306 | |
| 1307 | #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */ |
| 1308 | #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */ |
| 1309 | |
| 1310 | /* main configuration offset - byte offset */ |
| 1311 | #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */ |
| 1312 | #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */ |
| 1313 | #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */ |
| 1314 | #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */ |
| 1315 | #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */ |
| 1316 | #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */ |
| 1317 | #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */ |
| 1318 | #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */ |
| 1319 | #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */ |
| 1320 | #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */ |
| 1321 | |
| 1322 | /* 0x28 - 0x4C - RSVD */ |
Sakthivel K | c6b9ef5 | 2013-03-19 18:08:08 +0530 | [diff] [blame] | 1323 | #define MAIN_EVENT_CRC_CHECK 0x48 /* DWORD 0x12 */ |
Sakthivel K | f586099 | 2013-04-17 16:37:02 +0530 | [diff] [blame] | 1324 | #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */ |
| 1325 | #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */ |
| 1326 | #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */ |
| 1327 | #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */ |
| 1328 | #define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */ |
| 1329 | #define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */ |
| 1330 | #define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */ |
| 1331 | #define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */ |
| 1332 | #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */ |
| 1333 | #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */ |
| 1334 | #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */ |
| 1335 | #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */ |
| 1336 | #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */ |
| 1337 | #define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */ |
| 1338 | #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */ |
| 1339 | |
| 1340 | #define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */ |
| 1341 | #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */ |
| 1342 | #define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */ |
| 1343 | #define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */ |
| 1344 | |
| 1345 | /* Gereral Status Table offset - byte offset */ |
| 1346 | #define GST_GSTLEN_MPIS_OFFSET 0x00 |
| 1347 | #define GST_IQ_FREEZE_STATE0_OFFSET 0x04 |
| 1348 | #define GST_IQ_FREEZE_STATE1_OFFSET 0x08 |
| 1349 | #define GST_MSGUTCNT_OFFSET 0x0C |
| 1350 | #define GST_IOPTCNT_OFFSET 0x10 |
| 1351 | /* 0x14 - 0x34 - RSVD */ |
| 1352 | #define GST_GPIO_INPUT_VAL 0x38 |
| 1353 | /* 0x3c - 0x40 - RSVD */ |
| 1354 | #define GST_RERRINFO_OFFSET0 0x44 |
| 1355 | #define GST_RERRINFO_OFFSET1 0x48 |
| 1356 | #define GST_RERRINFO_OFFSET2 0x4c |
| 1357 | #define GST_RERRINFO_OFFSET3 0x50 |
| 1358 | #define GST_RERRINFO_OFFSET4 0x54 |
| 1359 | #define GST_RERRINFO_OFFSET5 0x58 |
| 1360 | #define GST_RERRINFO_OFFSET6 0x5c |
| 1361 | #define GST_RERRINFO_OFFSET7 0x60 |
| 1362 | |
| 1363 | /* General Status Table - MPI state */ |
| 1364 | #define GST_MPI_STATE_UNINIT 0x00 |
| 1365 | #define GST_MPI_STATE_INIT 0x01 |
| 1366 | #define GST_MPI_STATE_TERMINATION 0x02 |
| 1367 | #define GST_MPI_STATE_ERROR 0x03 |
| 1368 | #define GST_MPI_STATE_MASK 0x07 |
| 1369 | |
| 1370 | /* Per SAS PHY Attributes */ |
| 1371 | |
| 1372 | #define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */ |
| 1373 | #define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */ |
| 1374 | #define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */ |
| 1375 | #define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */ |
| 1376 | #define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */ |
| 1377 | #define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */ |
| 1378 | #define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */ |
| 1379 | #define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */ |
| 1380 | #define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */ |
| 1381 | #define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */ |
| 1382 | #define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */ |
| 1383 | #define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */ |
| 1384 | #define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */ |
| 1385 | #define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */ |
| 1386 | #define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */ |
| 1387 | #define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */ |
| 1388 | #define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */ |
| 1389 | #define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */ |
| 1390 | #define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */ |
| 1391 | #define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */ |
| 1392 | #define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */ |
| 1393 | #define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */ |
| 1394 | #define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */ |
| 1395 | #define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */ |
| 1396 | #define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */ |
| 1397 | #define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */ |
| 1398 | #define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */ |
| 1399 | #define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */ |
| 1400 | #define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */ |
| 1401 | #define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */ |
| 1402 | #define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */ |
| 1403 | #define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */ |
| 1404 | /* end PSPA */ |
| 1405 | |
| 1406 | /* inbound queue configuration offset - byte offset */ |
| 1407 | #define IB_PROPERITY_OFFSET 0x00 |
| 1408 | #define IB_BASE_ADDR_HI_OFFSET 0x04 |
| 1409 | #define IB_BASE_ADDR_LO_OFFSET 0x08 |
| 1410 | #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C |
| 1411 | #define IB_CI_BASE_ADDR_LO_OFFSET 0x10 |
| 1412 | #define IB_PIPCI_BAR 0x14 |
| 1413 | #define IB_PIPCI_BAR_OFFSET 0x18 |
| 1414 | #define IB_RESERVED_OFFSET 0x1C |
| 1415 | |
| 1416 | /* outbound queue configuration offset - byte offset */ |
| 1417 | #define OB_PROPERITY_OFFSET 0x00 |
| 1418 | #define OB_BASE_ADDR_HI_OFFSET 0x04 |
| 1419 | #define OB_BASE_ADDR_LO_OFFSET 0x08 |
| 1420 | #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C |
| 1421 | #define OB_PI_BASE_ADDR_LO_OFFSET 0x10 |
| 1422 | #define OB_CIPCI_BAR 0x14 |
| 1423 | #define OB_CIPCI_BAR_OFFSET 0x18 |
| 1424 | #define OB_INTERRUPT_COALES_OFFSET 0x1C |
| 1425 | #define OB_DYNAMIC_COALES_OFFSET 0x20 |
| 1426 | #define OB_PROPERTY_INT_ENABLE 0x40000000 |
| 1427 | |
| 1428 | #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418 |
| 1429 | #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418 |
| 1430 | /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ |
| 1431 | #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040 |
| 1432 | #define PCIE_EVENT_INTERRUPT 0x003044 |
| 1433 | #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048 |
| 1434 | #define PCIE_ERROR_INTERRUPT 0x00304C |
| 1435 | |
| 1436 | /* SPCV soft reset */ |
| 1437 | #define SPC_REG_SOFT_RESET 0x00001000 |
| 1438 | #define SPCv_NORMAL_RESET_VALUE 0x1 |
| 1439 | |
| 1440 | #define SPCv_SOFT_RESET_READ_MASK 0xC0 |
| 1441 | #define SPCv_SOFT_RESET_NO_RESET 0x0 |
| 1442 | #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40 |
| 1443 | #define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80 |
| 1444 | #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0 |
| 1445 | |
| 1446 | /* signature definition for host scratch pad0 register */ |
| 1447 | #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd |
| 1448 | /* Signature for Soft Reset */ |
| 1449 | |
| 1450 | /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ |
| 1451 | #define SPC_REG_RESET 0x000000/* reset register */ |
| 1452 | |
| 1453 | /* bit definition for SPC_RESET register */ |
| 1454 | #define SPC_REG_RESET_OSSP 0x00000001 |
| 1455 | #define SPC_REG_RESET_RAAE 0x00000002 |
| 1456 | #define SPC_REG_RESET_PCS_SPBC 0x00000004 |
| 1457 | #define SPC_REG_RESET_PCS_IOP_SS 0x00000008 |
| 1458 | #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010 |
| 1459 | #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020 |
| 1460 | #define SPC_REG_RESET_PCS_LM 0x00000040 |
| 1461 | #define SPC_REG_RESET_PCS 0x00000080 |
| 1462 | #define SPC_REG_RESET_GSM 0x00000100 |
| 1463 | #define SPC_REG_RESET_DDR2 0x00010000 |
| 1464 | #define SPC_REG_RESET_BDMA_CORE 0x00020000 |
| 1465 | #define SPC_REG_RESET_BDMA_SXCBI 0x00040000 |
| 1466 | #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000 |
| 1467 | #define SPC_REG_RESET_PCIE_PWR 0x00100000 |
| 1468 | #define SPC_REG_RESET_PCIE_SFT 0x00200000 |
| 1469 | #define SPC_REG_RESET_PCS_SXCBI 0x00400000 |
| 1470 | #define SPC_REG_RESET_LMS_SXCBI 0x00800000 |
| 1471 | #define SPC_REG_RESET_PMIC_SXCBI 0x01000000 |
| 1472 | #define SPC_REG_RESET_PMIC_CORE 0x02000000 |
| 1473 | #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000 |
| 1474 | #define SPC_REG_RESET_DEVICE 0x80000000 |
| 1475 | |
| 1476 | /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ |
| 1477 | #define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010 |
| 1478 | |
| 1479 | #define MBIC_AAP1_ADDR_BASE 0x060000 |
| 1480 | #define MBIC_IOP_ADDR_BASE 0x070000 |
| 1481 | #define GSM_ADDR_BASE 0x0700000 |
| 1482 | /* Dynamic map through Bar4 - 0x00700000 */ |
| 1483 | #define GSM_CONFIG_RESET 0x00000000 |
| 1484 | #define RAM_ECC_DB_ERR 0x00000018 |
| 1485 | #define GSM_READ_ADDR_PARITY_INDIC 0x00000058 |
| 1486 | #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060 |
| 1487 | #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068 |
| 1488 | #define GSM_READ_ADDR_PARITY_CHECK 0x00000038 |
| 1489 | #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040 |
| 1490 | #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048 |
| 1491 | |
| 1492 | #define RB6_ACCESS_REG 0x6A0000 |
| 1493 | #define HDAC_EXEC_CMD 0x0002 |
| 1494 | #define HDA_C_PA 0xcb |
| 1495 | #define HDA_SEQ_ID_BITS 0x00ff0000 |
| 1496 | #define HDA_GSM_OFFSET_BITS 0x00FFFFFF |
| 1497 | #define HDA_GSM_CMD_OFFSET_BITS 0x42C0 |
| 1498 | #define HDA_GSM_RSP_OFFSET_BITS 0x42E0 |
| 1499 | |
| 1500 | #define MBIC_AAP1_ADDR_BASE 0x060000 |
| 1501 | #define MBIC_IOP_ADDR_BASE 0x070000 |
| 1502 | #define GSM_ADDR_BASE 0x0700000 |
| 1503 | #define SPC_TOP_LEVEL_ADDR_BASE 0x000000 |
| 1504 | #define GSM_CONFIG_RESET_VALUE 0x00003b00 |
| 1505 | #define GPIO_ADDR_BASE 0x00090000 |
| 1506 | #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c |
| 1507 | |
| 1508 | /* RB6 offset */ |
| 1509 | #define SPC_RB6_OFFSET 0x80C0 |
| 1510 | /* Magic number of soft reset for RB6 */ |
| 1511 | #define RB6_MAGIC_NUMBER_RST 0x1234 |
| 1512 | |
| 1513 | /* Device Register status */ |
| 1514 | #define DEVREG_SUCCESS 0x00 |
| 1515 | #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01 |
| 1516 | #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 |
| 1517 | #define DEVREG_FAILURE_INVALID_PHY_ID 0x03 |
| 1518 | #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 |
| 1519 | #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 |
| 1520 | #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06 |
| 1521 | #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 |
| 1522 | |
| 1523 | #endif |