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Linus Walleije3726fc2010-08-19 12:36:01 +01001/*
Martin Perssone0befb22010-12-08 15:13:28 +01002 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
Linus Walleije3726fc2010-08-19 12:36:01 +01004 *
5 * License Terms: GNU General Public License v2
Martin Perssone0befb22010-12-08 15:13:28 +01006 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
Linus Walleije3726fc2010-08-19 12:36:01 +01008 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
Martin Perssone0befb22010-12-08 15:13:28 +010010 * U8500 PRCM Unit interface driver
11 *
Linus Walleije3726fc2010-08-19 12:36:01 +010012 */
Linus Walleije3726fc2010-08-19 12:36:01 +010013#include <linux/module.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020014#include <linux/kernel.h>
15#include <linux/delay.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010016#include <linux/errno.h>
17#include <linux/err.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020018#include <linux/spinlock.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010019#include <linux/io.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020020#include <linux/slab.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010021#include <linux/mutex.h>
22#include <linux/completion.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020023#include <linux/irq.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010024#include <linux/jiffies.h>
25#include <linux/bitops.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020026#include <linux/fs.h>
27#include <linux/platform_device.h>
28#include <linux/uaccess.h>
29#include <linux/mfd/core.h>
Mattias Nilsson73180f82011-08-12 10:28:10 +020030#include <linux/mfd/dbx500-prcmu.h>
Lee Jones3a8e39c2012-07-06 12:46:23 +020031#include <linux/mfd/abx500/ab8500.h>
Bengt Jonsson1032fbf2011-04-01 14:43:33 +020032#include <linux/regulator/db8500-prcmu.h>
33#include <linux/regulator/machine.h>
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +010034#include <asm/hardware/gic.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010035#include <mach/hardware.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020036#include <mach/irqs.h>
37#include <mach/db8500-regs.h>
38#include <mach/id.h>
Mattias Nilsson73180f82011-08-12 10:28:10 +020039#include "dbx500-prcmu-regs.h"
Linus Walleije3726fc2010-08-19 12:36:01 +010040
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020041/* Offset for the firmware version within the TCPM */
42#define PRCMU_FW_VERSION_OFFSET 0xA4
Linus Walleije3726fc2010-08-19 12:36:01 +010043
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020044/* Index of different voltages to be used when accessing AVSData */
45#define PRCM_AVS_BASE 0x2FC
46#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
47#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
48#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
49#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
50#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
51#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
52#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
53#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
54#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
55#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
56#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
57#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
58#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
Martin Perssone0befb22010-12-08 15:13:28 +010059
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020060#define PRCM_AVS_VOLTAGE 0
61#define PRCM_AVS_VOLTAGE_MASK 0x3f
62#define PRCM_AVS_ISSLOWSTARTUP 6
63#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
Martin Perssone0befb22010-12-08 15:13:28 +010064#define PRCM_AVS_ISMODEENABLE 7
65#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
66
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020067#define PRCM_BOOT_STATUS 0xFFF
68#define PRCM_ROMCODE_A2P 0xFFE
69#define PRCM_ROMCODE_P2A 0xFFD
70#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
Linus Walleije3726fc2010-08-19 12:36:01 +010071
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020072#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
73
74#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
75#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
76#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
77#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
78#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
79#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
80#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
81#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
82
83/* Req Mailboxes */
84#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
85#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
86#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
87#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
88#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
89#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
90
91/* Ack Mailboxes */
92#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
93#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
94#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
95#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
96#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
97#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
98
99/* Mailbox 0 headers */
100#define MB0H_POWER_STATE_TRANS 0
101#define MB0H_CONFIG_WAKEUPS_EXE 1
102#define MB0H_READ_WAKEUP_ACK 3
103#define MB0H_CONFIG_WAKEUPS_SLEEP 4
104
105#define MB0H_WAKEUP_EXE 2
106#define MB0H_WAKEUP_SLEEP 5
107
108/* Mailbox 0 REQs */
109#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
110#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
111#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
112#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
113#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
114#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
115
116/* Mailbox 0 ACKs */
117#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
118#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
119#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
120#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
121#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
122#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
123#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
124
125/* Mailbox 1 headers */
126#define MB1H_ARM_APE_OPP 0x0
127#define MB1H_RESET_MODEM 0x2
128#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
129#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
130#define MB1H_RELEASE_USB_WAKEUP 0x5
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200131#define MB1H_PLL_ON_OFF 0x6
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200132
133/* Mailbox 1 Requests */
134#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
135#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200136#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100137#define PLL_SOC0_OFF 0x1
138#define PLL_SOC0_ON 0x2
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200139#define PLL_SOC1_OFF 0x4
140#define PLL_SOC1_ON 0x8
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200141
142/* Mailbox 1 ACKs */
143#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
144#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
145#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
146#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
147
148/* Mailbox 2 headers */
149#define MB2H_DPS 0x0
150#define MB2H_AUTO_PWR 0x1
151
152/* Mailbox 2 REQs */
153#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
154#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
155#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
156#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
157#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
158#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
159#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
160#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
161#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
162#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
163
164/* Mailbox 2 ACKs */
165#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
166#define HWACC_PWR_ST_OK 0xFE
167
168/* Mailbox 3 headers */
169#define MB3H_ANC 0x0
170#define MB3H_SIDETONE 0x1
171#define MB3H_SYSCLK 0xE
172
173/* Mailbox 3 Requests */
174#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
175#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
176#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
177#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
178#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
179#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
180#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
181
182/* Mailbox 4 headers */
183#define MB4H_DDR_INIT 0x0
184#define MB4H_MEM_ST 0x1
185#define MB4H_HOTDOG 0x12
186#define MB4H_HOTMON 0x13
187#define MB4H_HOT_PERIOD 0x14
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200188#define MB4H_A9WDOG_CONF 0x16
189#define MB4H_A9WDOG_EN 0x17
190#define MB4H_A9WDOG_DIS 0x18
191#define MB4H_A9WDOG_LOAD 0x19
192#define MB4H_A9WDOG_KICK 0x20
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200193
194/* Mailbox 4 Requests */
195#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
196#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
197#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
198#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
199#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
200#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
201#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
202#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
203#define HOTMON_CONFIG_LOW BIT(0)
204#define HOTMON_CONFIG_HIGH BIT(1)
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200205#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
206#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
207#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
208#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
209#define A9WDOG_AUTO_OFF_EN BIT(7)
210#define A9WDOG_AUTO_OFF_DIS 0
211#define A9WDOG_ID_MASK 0xf
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200212
213/* Mailbox 5 Requests */
214#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
215#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
216#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
217#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
218#define PRCMU_I2C_WRITE(slave) \
219 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
220#define PRCMU_I2C_READ(slave) \
221 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
222#define PRCMU_I2C_STOP_EN BIT(3)
223
224/* Mailbox 5 ACKs */
225#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
226#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
227#define I2C_WR_OK 0x1
228#define I2C_RD_OK 0x2
229
230#define NUM_MB 8
231#define MBOX_BIT BIT
232#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
233
234/*
235 * Wakeups/IRQs
236 */
237
238#define WAKEUP_BIT_RTC BIT(0)
239#define WAKEUP_BIT_RTT0 BIT(1)
240#define WAKEUP_BIT_RTT1 BIT(2)
241#define WAKEUP_BIT_HSI0 BIT(3)
242#define WAKEUP_BIT_HSI1 BIT(4)
243#define WAKEUP_BIT_CA_WAKE BIT(5)
244#define WAKEUP_BIT_USB BIT(6)
245#define WAKEUP_BIT_ABB BIT(7)
246#define WAKEUP_BIT_ABB_FIFO BIT(8)
247#define WAKEUP_BIT_SYSCLK_OK BIT(9)
248#define WAKEUP_BIT_CA_SLEEP BIT(10)
249#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
250#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
251#define WAKEUP_BIT_ANC_OK BIT(13)
252#define WAKEUP_BIT_SW_ERROR BIT(14)
253#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
254#define WAKEUP_BIT_ARM BIT(17)
255#define WAKEUP_BIT_HOTMON_LOW BIT(18)
256#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
257#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
258#define WAKEUP_BIT_GPIO0 BIT(23)
259#define WAKEUP_BIT_GPIO1 BIT(24)
260#define WAKEUP_BIT_GPIO2 BIT(25)
261#define WAKEUP_BIT_GPIO3 BIT(26)
262#define WAKEUP_BIT_GPIO4 BIT(27)
263#define WAKEUP_BIT_GPIO5 BIT(28)
264#define WAKEUP_BIT_GPIO6 BIT(29)
265#define WAKEUP_BIT_GPIO7 BIT(30)
266#define WAKEUP_BIT_GPIO8 BIT(31)
267
Mattias Nilssonb58d12f2012-01-13 16:20:10 +0100268static struct {
269 bool valid;
270 struct prcmu_fw_version version;
271} fw_info;
272
Lee Jonesf3f1f0a2012-09-24 09:11:46 +0100273static struct irq_domain *db8500_irq_domain;
274
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200275/*
276 * This vector maps irq numbers to the bits in the bit field used in
277 * communication with the PRCMU firmware.
278 *
279 * The reason for having this is to keep the irq numbers contiguous even though
280 * the bits in the bit field are not. (The bits also have a tendency to move
281 * around, to further complicate matters.)
282 */
283#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
284#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
285static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
286 IRQ_ENTRY(RTC),
287 IRQ_ENTRY(RTT0),
288 IRQ_ENTRY(RTT1),
289 IRQ_ENTRY(HSI0),
290 IRQ_ENTRY(HSI1),
291 IRQ_ENTRY(CA_WAKE),
292 IRQ_ENTRY(USB),
293 IRQ_ENTRY(ABB),
294 IRQ_ENTRY(ABB_FIFO),
295 IRQ_ENTRY(CA_SLEEP),
296 IRQ_ENTRY(ARM),
297 IRQ_ENTRY(HOTMON_LOW),
298 IRQ_ENTRY(HOTMON_HIGH),
299 IRQ_ENTRY(MODEM_SW_RESET_REQ),
300 IRQ_ENTRY(GPIO0),
301 IRQ_ENTRY(GPIO1),
302 IRQ_ENTRY(GPIO2),
303 IRQ_ENTRY(GPIO3),
304 IRQ_ENTRY(GPIO4),
305 IRQ_ENTRY(GPIO5),
306 IRQ_ENTRY(GPIO6),
307 IRQ_ENTRY(GPIO7),
308 IRQ_ENTRY(GPIO8)
Martin Perssone0befb22010-12-08 15:13:28 +0100309};
310
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200311#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
312#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
313static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
314 WAKEUP_ENTRY(RTC),
315 WAKEUP_ENTRY(RTT0),
316 WAKEUP_ENTRY(RTT1),
317 WAKEUP_ENTRY(HSI0),
318 WAKEUP_ENTRY(HSI1),
319 WAKEUP_ENTRY(USB),
320 WAKEUP_ENTRY(ABB),
321 WAKEUP_ENTRY(ABB_FIFO),
322 WAKEUP_ENTRY(ARM)
323};
324
325/*
326 * mb0_transfer - state needed for mailbox 0 communication.
327 * @lock: The transaction lock.
328 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
329 * the request data.
330 * @mask_work: Work structure used for (un)masking wakeup interrupts.
331 * @req: Request data that need to persist between requests.
332 */
333static struct {
334 spinlock_t lock;
335 spinlock_t dbb_irqs_lock;
336 struct work_struct mask_work;
337 struct mutex ac_wake_lock;
338 struct completion ac_wake_work;
339 struct {
340 u32 dbb_irqs;
341 u32 dbb_wakeups;
342 u32 abb_events;
343 } req;
344} mb0_transfer;
345
346/*
347 * mb1_transfer - state needed for mailbox 1 communication.
348 * @lock: The transaction lock.
349 * @work: The transaction completion structure.
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100350 * @ape_opp: The current APE OPP.
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200351 * @ack: Reply ("acknowledge") data.
352 */
Martin Perssone0befb22010-12-08 15:13:28 +0100353static struct {
354 struct mutex lock;
355 struct completion work;
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100356 u8 ape_opp;
Martin Perssone0befb22010-12-08 15:13:28 +0100357 struct {
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200358 u8 header;
Martin Perssone0befb22010-12-08 15:13:28 +0100359 u8 arm_opp;
360 u8 ape_opp;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200361 u8 ape_voltage_status;
Martin Perssone0befb22010-12-08 15:13:28 +0100362 } ack;
363} mb1_transfer;
364
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200365/*
366 * mb2_transfer - state needed for mailbox 2 communication.
367 * @lock: The transaction lock.
368 * @work: The transaction completion structure.
369 * @auto_pm_lock: The autonomous power management configuration lock.
370 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
371 * @req: Request data that need to persist between requests.
372 * @ack: Reply ("acknowledge") data.
373 */
Linus Walleije3726fc2010-08-19 12:36:01 +0100374static struct {
375 struct mutex lock;
376 struct completion work;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200377 spinlock_t auto_pm_lock;
378 bool auto_pm_enabled;
379 struct {
380 u8 status;
381 } ack;
382} mb2_transfer;
383
384/*
385 * mb3_transfer - state needed for mailbox 3 communication.
386 * @lock: The request lock.
387 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
388 * @sysclk_work: Work structure used for sysclk requests.
389 */
390static struct {
391 spinlock_t lock;
392 struct mutex sysclk_lock;
393 struct completion sysclk_work;
394} mb3_transfer;
395
396/*
397 * mb4_transfer - state needed for mailbox 4 communication.
398 * @lock: The transaction lock.
399 * @work: The transaction completion structure.
400 */
401static struct {
402 struct mutex lock;
403 struct completion work;
404} mb4_transfer;
405
406/*
407 * mb5_transfer - state needed for mailbox 5 communication.
408 * @lock: The transaction lock.
409 * @work: The transaction completion structure.
410 * @ack: Reply ("acknowledge") data.
411 */
412static struct {
413 struct mutex lock;
414 struct completion work;
Linus Walleije3726fc2010-08-19 12:36:01 +0100415 struct {
416 u8 status;
417 u8 value;
418 } ack;
419} mb5_transfer;
420
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200421static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
422
Michel Jaouen20aee5b2012-08-31 14:21:30 +0200423/* Functions definition */
424static void compute_armss_rate(void);
425
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200426/* Spinlocks */
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100427static DEFINE_SPINLOCK(prcmu_lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200428static DEFINE_SPINLOCK(clkout_lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200429
430/* Global var to runtime determine TCDM base for v2 or v1 */
431static __iomem void *tcdm_base;
432
433struct clk_mgt {
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100434 void __iomem *reg;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200435 u32 pllsw;
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100436 int branch;
437 bool clk38div;
438};
439
440enum {
441 PLL_RAW,
442 PLL_FIX,
443 PLL_DIV
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200444};
445
446static DEFINE_SPINLOCK(clk_mgt_lock);
447
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100448#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
449 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200450struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100451 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
452 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
453 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
454 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
455 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
456 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
457 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
458 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
459 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
460 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
461 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
462 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
463 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
464 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
465 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
466 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
467 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
468 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
469 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
470 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
471 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
472 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
474 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
475 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
476 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
477 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
478 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
479 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
480};
481
482struct dsiclk {
483 u32 divsel_mask;
484 u32 divsel_shift;
485 u32 divsel;
486};
487
488static struct dsiclk dsiclk[2] = {
489 {
490 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
491 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
492 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
493 },
494 {
495 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
496 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
497 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
498 }
499};
500
501struct dsiescclk {
502 u32 en;
503 u32 div_mask;
504 u32 div_shift;
505};
506
507static struct dsiescclk dsiescclk[3] = {
508 {
509 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
510 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
511 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
512 },
513 {
514 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
515 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
516 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
517 },
518 {
519 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
520 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
521 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
522 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200523};
524
Michel Jaouen20aee5b2012-08-31 14:21:30 +0200525
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200526/*
527* Used by MCDE to setup all necessary PRCMU registers
528*/
529#define PRCMU_RESET_DSIPLL 0x00004000
530#define PRCMU_UNCLAMP_DSIPLL 0x00400800
531
532#define PRCMU_CLK_PLL_DIV_SHIFT 0
533#define PRCMU_CLK_PLL_SW_SHIFT 5
534#define PRCMU_CLK_38 (1 << 9)
535#define PRCMU_CLK_38_SRC (1 << 10)
536#define PRCMU_CLK_38_DIV (1 << 11)
537
538/* PLLDIV=12, PLLSW=4 (PLLDDR) */
539#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
540
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200541/* DPI 50000000 Hz */
542#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
543 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
544#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
545
546/* D=101, N=1, R=4, SELDIV2=0 */
547#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
548
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200549#define PRCMU_ENABLE_PLLDSI 0x00000001
550#define PRCMU_DISABLE_PLLDSI 0x00000000
551#define PRCMU_RELEASE_RESET_DSS 0x0000400C
552#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
553/* ESC clk, div0=1, div1=1, div2=3 */
554#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
555#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
556#define PRCMU_DSI_RESET_SW 0x00000007
557
558#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
559
Mattias Nilsson73180f82011-08-12 10:28:10 +0200560int db8500_prcmu_enable_dsipll(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200561{
562 int i;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200563
564 /* Clear DSIPLL_RESETN */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200565 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200566 /* Unclamp DSIPLL in/out */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200567 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200568
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200569 /* Set DSI PLL FREQ */
Daniel Willerudc72fe852012-01-13 16:20:03 +0100570 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200571 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200572 /* Enable Escape clocks */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200573 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200574
575 /* Start DSI PLL */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200576 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200577 /* Reset DSI PLL */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200578 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200579 for (i = 0; i < 10; i++) {
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200580 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200581 == PRCMU_PLLDSI_LOCKP_LOCKED)
582 break;
583 udelay(100);
584 }
585 /* Set DSIPLL_RESETN */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200586 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200587 return 0;
588}
589
Mattias Nilsson73180f82011-08-12 10:28:10 +0200590int db8500_prcmu_disable_dsipll(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200591{
592 /* Disable dsi pll */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200593 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200594 /* Disable escapeclock */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200595 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200596 return 0;
597}
598
Mattias Nilsson73180f82011-08-12 10:28:10 +0200599int db8500_prcmu_set_display_clocks(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200600{
601 unsigned long flags;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200602
603 spin_lock_irqsave(&clk_mgt_lock, flags);
604
605 /* Grab the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200606 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200607 cpu_relax();
608
Daniel Willerudc72fe852012-01-13 16:20:03 +0100609 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200610 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
611 writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200612
613 /* Release the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200614 writel(0, PRCM_SEM);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200615
616 spin_unlock_irqrestore(&clk_mgt_lock, flags);
617
618 return 0;
619}
620
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100621u32 db8500_prcmu_read(unsigned int reg)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200622{
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100623 return readl(_PRCMU_BASE + reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200624}
625
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100626void db8500_prcmu_write(unsigned int reg, u32 value)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200627{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200628 unsigned long flags;
629
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100630 spin_lock_irqsave(&prcmu_lock, flags);
631 writel(value, (_PRCMU_BASE + reg));
632 spin_unlock_irqrestore(&prcmu_lock, flags);
633}
634
635void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
636{
637 u32 val;
638 unsigned long flags;
639
640 spin_lock_irqsave(&prcmu_lock, flags);
641 val = readl(_PRCMU_BASE + reg);
642 val = ((val & ~mask) | (value & mask));
643 writel(val, (_PRCMU_BASE + reg));
644 spin_unlock_irqrestore(&prcmu_lock, flags);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200645}
646
Mattias Nilssonb58d12f2012-01-13 16:20:10 +0100647struct prcmu_fw_version *prcmu_get_fw_version(void)
648{
649 return fw_info.valid ? &fw_info.version : NULL;
650}
651
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200652bool prcmu_has_arm_maxopp(void)
653{
654 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
655 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
656}
657
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200658/**
659 * prcmu_get_boot_status - PRCMU boot status checking
660 * Returns: the current PRCMU boot status
661 */
662int prcmu_get_boot_status(void)
663{
664 return readb(tcdm_base + PRCM_BOOT_STATUS);
665}
666
667/**
668 * prcmu_set_rc_a2p - This function is used to run few power state sequences
669 * @val: Value to be set, i.e. transition requested
670 * Returns: 0 on success, -EINVAL on invalid argument
671 *
672 * This function is used to run the following power state sequences -
673 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
674 */
675int prcmu_set_rc_a2p(enum romcode_write val)
676{
677 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
678 return -EINVAL;
679 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
680 return 0;
681}
682
683/**
684 * prcmu_get_rc_p2a - This function is used to get power state sequences
685 * Returns: the power transition that has last happened
686 *
687 * This function can return the following transitions-
688 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
689 */
690enum romcode_read prcmu_get_rc_p2a(void)
691{
692 return readb(tcdm_base + PRCM_ROMCODE_P2A);
693}
694
695/**
696 * prcmu_get_current_mode - Return the current XP70 power mode
697 * Returns: Returns the current AP(ARM) power mode: init,
698 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
699 */
700enum ap_pwrst prcmu_get_xp70_current_state(void)
701{
702 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
703}
704
705/**
706 * prcmu_config_clkout - Configure one of the programmable clock outputs.
707 * @clkout: The CLKOUT number (0 or 1).
708 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
709 * @div: The divider to be applied.
710 *
711 * Configures one of the programmable clock outputs (CLKOUTs).
712 * @div should be in the range [1,63] to request a configuration, or 0 to
713 * inform that the configuration is no longer requested.
714 */
715int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
716{
717 static int requests[2];
718 int r = 0;
719 unsigned long flags;
720 u32 val;
721 u32 bits;
722 u32 mask;
723 u32 div_mask;
724
725 BUG_ON(clkout > 1);
726 BUG_ON(div > 63);
727 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
728
729 if (!div && !requests[clkout])
730 return -EINVAL;
731
732 switch (clkout) {
733 case 0:
734 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
735 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
736 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
737 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
738 break;
739 case 1:
740 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
741 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
742 PRCM_CLKOCR_CLK1TYPE);
743 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
744 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
745 break;
746 }
747 bits &= mask;
748
749 spin_lock_irqsave(&clkout_lock, flags);
750
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200751 val = readl(PRCM_CLKOCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200752 if (val & div_mask) {
753 if (div) {
754 if ((val & mask) != bits) {
755 r = -EBUSY;
756 goto unlock_and_return;
757 }
758 } else {
759 if ((val & mask & ~div_mask) != bits) {
760 r = -EINVAL;
761 goto unlock_and_return;
762 }
763 }
764 }
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200765 writel((bits | (val & ~mask)), PRCM_CLKOCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200766 requests[clkout] += (div ? 1 : -1);
767
768unlock_and_return:
769 spin_unlock_irqrestore(&clkout_lock, flags);
770
771 return r;
772}
773
Mattias Nilsson73180f82011-08-12 10:28:10 +0200774int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200775{
776 unsigned long flags;
777
778 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
779
780 spin_lock_irqsave(&mb0_transfer.lock, flags);
781
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200782 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200783 cpu_relax();
784
785 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
786 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
787 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
788 writeb((keep_ulp_clk ? 1 : 0),
789 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
790 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200791 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200792
793 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
794
795 return 0;
796}
797
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100798u8 db8500_prcmu_get_power_state_result(void)
799{
800 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
801}
802
Daniel Lezcano485540d2012-02-20 12:30:26 +0100803/* This function decouple the gic from the prcmu */
804int db8500_prcmu_gic_decouple(void)
805{
Daniel Lezcano801448e2012-02-28 22:46:05 +0100806 u32 val = readl(PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100807
808 /* Set bit 0 register value to 1 */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100809 writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
810 PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100811
812 /* Make sure the register is updated */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100813 readl(PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100814
815 /* Wait a few cycles for the gic mask completion */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100816 udelay(1);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100817
818 return 0;
819}
820
821/* This function recouple the gic with the prcmu */
822int db8500_prcmu_gic_recouple(void)
823{
Daniel Lezcano801448e2012-02-28 22:46:05 +0100824 u32 val = readl(PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100825
826 /* Set bit 0 register value to 0 */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100827 writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100828
829 return 0;
830}
831
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +0100832#define PRCMU_GIC_NUMBER_REGS 5
833
834/*
835 * This function checks if there are pending irq on the gic. It only
836 * makes sense if the gic has been decoupled before with the
837 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
838 * disables the forwarding of the interrupt to any CPU interface. It
839 * does not prevent the interrupt from changing state, for example
840 * becoming pending, or active and pending if it is already
841 * active. Hence, we have to check the interrupt is pending *and* is
842 * active.
843 */
844bool db8500_prcmu_gic_pending_irq(void)
845{
846 u32 pr; /* Pending register */
847 u32 er; /* Enable register */
848 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
849 int i;
850
851 /* 5 registers. STI & PPI not skipped */
852 for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
853
854 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
855 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
856
857 if (pr & er)
858 return true; /* There is a pending interrupt */
859 }
860
861 return false;
862}
863
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100864/*
Daniel Lezcano9ab492e2012-02-28 22:46:08 +0100865 * This function checks if there are pending interrupt on the
866 * prcmu which has been delegated to monitor the irqs with the
867 * db8500_prcmu_copy_gic_settings function.
868 */
869bool db8500_prcmu_pending_irq(void)
870{
871 u32 it, im;
872 int i;
873
874 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
875 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
876 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
877 if (it & im)
878 return true; /* There is a pending interrupt */
879 }
880
881 return false;
882}
883
884/*
Daniel Lezcano34fe6f12012-02-28 22:46:09 +0100885 * This function checks if the specified cpu is in in WFI. It's usage
886 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
887 * function. Of course passing smp_processor_id() to this function will
888 * always return false...
889 */
890bool db8500_prcmu_is_cpu_in_wfi(int cpu)
891{
892 return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
893 PRCM_ARM_WFI_STANDBY_WFI0;
894}
895
896/*
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100897 * This function copies the gic SPI settings to the prcmu in order to
898 * monitor them and abort/finish the retention/off sequence or state.
899 */
900int db8500_prcmu_copy_gic_settings(void)
901{
902 u32 er; /* Enable register */
903 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
904 int i;
905
906 /* We skip the STI and PPI */
907 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
908 er = readl_relaxed(dist_base +
909 GIC_DIST_ENABLE_SET + (i + 1) * 4);
910 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
911 }
912
913 return 0;
914}
915
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200916/* This function should only be called while mb0_transfer.lock is held. */
917static void config_wakeups(void)
918{
919 const u8 header[2] = {
920 MB0H_CONFIG_WAKEUPS_EXE,
921 MB0H_CONFIG_WAKEUPS_SLEEP
922 };
923 static u32 last_dbb_events;
924 static u32 last_abb_events;
925 u32 dbb_events;
926 u32 abb_events;
927 unsigned int i;
928
929 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
930 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
931
932 abb_events = mb0_transfer.req.abb_events;
933
934 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
935 return;
936
937 for (i = 0; i < 2; i++) {
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200938 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200939 cpu_relax();
940 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
941 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
942 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200943 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200944 }
945 last_dbb_events = dbb_events;
946 last_abb_events = abb_events;
947}
948
Mattias Nilsson73180f82011-08-12 10:28:10 +0200949void db8500_prcmu_enable_wakeups(u32 wakeups)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200950{
951 unsigned long flags;
952 u32 bits;
953 int i;
954
955 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
956
957 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
958 if (wakeups & BIT(i))
959 bits |= prcmu_wakeup_bit[i];
960 }
961
962 spin_lock_irqsave(&mb0_transfer.lock, flags);
963
964 mb0_transfer.req.dbb_wakeups = bits;
965 config_wakeups();
966
967 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
968}
969
Mattias Nilsson73180f82011-08-12 10:28:10 +0200970void db8500_prcmu_config_abb_event_readout(u32 abb_events)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200971{
972 unsigned long flags;
973
974 spin_lock_irqsave(&mb0_transfer.lock, flags);
975
976 mb0_transfer.req.abb_events = abb_events;
977 config_wakeups();
978
979 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
980}
981
Mattias Nilsson73180f82011-08-12 10:28:10 +0200982void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200983{
984 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
985 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
986 else
987 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
988}
989
990/**
Mattias Nilsson73180f82011-08-12 10:28:10 +0200991 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200992 * @opp: The new ARM operating point to which transition is to be made
993 * Returns: 0 on success, non-zero on failure
994 *
995 * This function sets the the operating point of the ARM.
996 */
Mattias Nilsson73180f82011-08-12 10:28:10 +0200997int db8500_prcmu_set_arm_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200998{
999 int r;
1000
1001 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
1002 return -EINVAL;
1003
1004 r = 0;
1005
1006 mutex_lock(&mb1_transfer.lock);
1007
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001008 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001009 cpu_relax();
1010
1011 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1012 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1013 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1014
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001015 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001016 wait_for_completion(&mb1_transfer.work);
1017
1018 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1019 (mb1_transfer.ack.arm_opp != opp))
1020 r = -EIO;
1021
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001022 compute_armss_rate();
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001023 mutex_unlock(&mb1_transfer.lock);
1024
1025 return r;
1026}
1027
1028/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001029 * db8500_prcmu_get_arm_opp - get the current ARM OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001030 *
1031 * Returns: the current ARM OPP
1032 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001033int db8500_prcmu_get_arm_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001034{
1035 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1036}
1037
1038/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001039 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001040 *
1041 * Returns: the current DDR OPP
1042 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001043int db8500_prcmu_get_ddr_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001044{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001045 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001046}
1047
1048/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001049 * db8500_set_ddr_opp - set the appropriate DDR OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001050 * @opp: The new DDR operating point to which transition is to be made
1051 * Returns: 0 on success, non-zero on failure
1052 *
1053 * This function sets the operating point of the DDR.
1054 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001055int db8500_prcmu_set_ddr_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001056{
1057 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1058 return -EINVAL;
1059 /* Changing the DDR OPP can hang the hardware pre-v21 */
1060 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001061 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001062
1063 return 0;
1064}
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001065
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001066/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1067static void request_even_slower_clocks(bool enable)
1068{
1069 void __iomem *clock_reg[] = {
1070 PRCM_ACLK_MGT,
1071 PRCM_DMACLK_MGT
1072 };
1073 unsigned long flags;
1074 unsigned int i;
1075
1076 spin_lock_irqsave(&clk_mgt_lock, flags);
1077
1078 /* Grab the HW semaphore. */
1079 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1080 cpu_relax();
1081
1082 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1083 u32 val;
1084 u32 div;
1085
1086 val = readl(clock_reg[i]);
1087 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1088 if (enable) {
1089 if ((div <= 1) || (div > 15)) {
1090 pr_err("prcmu: Bad clock divider %d in %s\n",
1091 div, __func__);
1092 goto unlock_and_return;
1093 }
1094 div <<= 1;
1095 } else {
1096 if (div <= 2)
1097 goto unlock_and_return;
1098 div >>= 1;
1099 }
1100 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1101 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1102 writel(val, clock_reg[i]);
1103 }
1104
1105unlock_and_return:
1106 /* Release the HW semaphore. */
1107 writel(0, PRCM_SEM);
1108
1109 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1110}
1111
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001112/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001113 * db8500_set_ape_opp - set the appropriate APE OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001114 * @opp: The new APE operating point to which transition is to be made
1115 * Returns: 0 on success, non-zero on failure
1116 *
1117 * This function sets the operating point of the APE.
1118 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001119int db8500_prcmu_set_ape_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001120{
1121 int r = 0;
1122
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001123 if (opp == mb1_transfer.ape_opp)
1124 return 0;
1125
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001126 mutex_lock(&mb1_transfer.lock);
1127
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001128 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1129 request_even_slower_clocks(false);
1130
1131 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1132 goto skip_message;
1133
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001134 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001135 cpu_relax();
1136
1137 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1138 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001139 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1140 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001141
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001142 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001143 wait_for_completion(&mb1_transfer.work);
1144
1145 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1146 (mb1_transfer.ack.ape_opp != opp))
1147 r = -EIO;
1148
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001149skip_message:
1150 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1151 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1152 request_even_slower_clocks(true);
1153 if (!r)
1154 mb1_transfer.ape_opp = opp;
1155
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001156 mutex_unlock(&mb1_transfer.lock);
1157
1158 return r;
1159}
1160
1161/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001162 * db8500_prcmu_get_ape_opp - get the current APE OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001163 *
1164 * Returns: the current APE OPP
1165 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001166int db8500_prcmu_get_ape_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001167{
1168 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1169}
1170
1171/**
1172 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1173 * @enable: true to request the higher voltage, false to drop a request.
1174 *
1175 * Calls to this function to enable and disable requests must be balanced.
1176 */
1177int prcmu_request_ape_opp_100_voltage(bool enable)
1178{
1179 int r = 0;
1180 u8 header;
1181 static unsigned int requests;
1182
1183 mutex_lock(&mb1_transfer.lock);
1184
1185 if (enable) {
1186 if (0 != requests++)
1187 goto unlock_and_return;
1188 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1189 } else {
1190 if (requests == 0) {
1191 r = -EIO;
1192 goto unlock_and_return;
1193 } else if (1 != requests--) {
1194 goto unlock_and_return;
1195 }
1196 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1197 }
1198
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001199 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001200 cpu_relax();
1201
1202 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1203
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001204 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001205 wait_for_completion(&mb1_transfer.work);
1206
1207 if ((mb1_transfer.ack.header != header) ||
1208 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1209 r = -EIO;
1210
1211unlock_and_return:
1212 mutex_unlock(&mb1_transfer.lock);
1213
1214 return r;
1215}
1216
1217/**
1218 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1219 *
1220 * This function releases the power state requirements of a USB wakeup.
1221 */
1222int prcmu_release_usb_wakeup_state(void)
1223{
1224 int r = 0;
1225
1226 mutex_lock(&mb1_transfer.lock);
1227
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001228 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001229 cpu_relax();
1230
1231 writeb(MB1H_RELEASE_USB_WAKEUP,
1232 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1233
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001234 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001235 wait_for_completion(&mb1_transfer.work);
1236
1237 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1238 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1239 r = -EIO;
1240
1241 mutex_unlock(&mb1_transfer.lock);
1242
1243 return r;
1244}
1245
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001246static int request_pll(u8 clock, bool enable)
1247{
1248 int r = 0;
1249
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001250 if (clock == PRCMU_PLLSOC0)
1251 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1252 else if (clock == PRCMU_PLLSOC1)
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001253 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1254 else
1255 return -EINVAL;
1256
1257 mutex_lock(&mb1_transfer.lock);
1258
1259 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1260 cpu_relax();
1261
1262 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1263 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1264
1265 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1266 wait_for_completion(&mb1_transfer.work);
1267
1268 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1269 r = -EIO;
1270
1271 mutex_unlock(&mb1_transfer.lock);
1272
1273 return r;
1274}
1275
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001276/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001277 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001278 * @epod_id: The EPOD to set
1279 * @epod_state: The new EPOD state
1280 *
1281 * This function sets the state of a EPOD (power domain). It may not be called
1282 * from interrupt context.
1283 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001284int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001285{
1286 int r = 0;
1287 bool ram_retention = false;
1288 int i;
1289
1290 /* check argument */
1291 BUG_ON(epod_id >= NUM_EPOD_ID);
1292
1293 /* set flag if retention is possible */
1294 switch (epod_id) {
1295 case EPOD_ID_SVAMMDSP:
1296 case EPOD_ID_SIAMMDSP:
1297 case EPOD_ID_ESRAM12:
1298 case EPOD_ID_ESRAM34:
1299 ram_retention = true;
1300 break;
1301 }
1302
1303 /* check argument */
1304 BUG_ON(epod_state > EPOD_STATE_ON);
1305 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1306
1307 /* get lock */
1308 mutex_lock(&mb2_transfer.lock);
1309
1310 /* wait for mailbox */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001311 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001312 cpu_relax();
1313
1314 /* fill in mailbox */
1315 for (i = 0; i < NUM_EPOD_ID; i++)
1316 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1317 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1318
1319 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1320
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001321 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001322
1323 /*
1324 * The current firmware version does not handle errors correctly,
1325 * and we cannot recover if there is an error.
1326 * This is expected to change when the firmware is updated.
1327 */
1328 if (!wait_for_completion_timeout(&mb2_transfer.work,
1329 msecs_to_jiffies(20000))) {
1330 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1331 __func__);
1332 r = -EIO;
1333 goto unlock_and_return;
1334 }
1335
1336 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1337 r = -EIO;
1338
1339unlock_and_return:
1340 mutex_unlock(&mb2_transfer.lock);
1341 return r;
1342}
1343
1344/**
1345 * prcmu_configure_auto_pm - Configure autonomous power management.
1346 * @sleep: Configuration for ApSleep.
1347 * @idle: Configuration for ApIdle.
1348 */
1349void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1350 struct prcmu_auto_pm_config *idle)
1351{
1352 u32 sleep_cfg;
1353 u32 idle_cfg;
1354 unsigned long flags;
1355
1356 BUG_ON((sleep == NULL) || (idle == NULL));
1357
1358 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1359 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1360 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1361 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1362 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1363 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1364
1365 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1366 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1367 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1368 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1369 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1370 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1371
1372 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1373
1374 /*
1375 * The autonomous power management configuration is done through
1376 * fields in mailbox 2, but these fields are only used as shared
1377 * variables - i.e. there is no need to send a message.
1378 */
1379 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1380 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1381
1382 mb2_transfer.auto_pm_enabled =
1383 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1384 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1385 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1386 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1387
1388 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1389}
1390EXPORT_SYMBOL(prcmu_configure_auto_pm);
1391
1392bool prcmu_is_auto_pm_enabled(void)
1393{
1394 return mb2_transfer.auto_pm_enabled;
1395}
1396
1397static int request_sysclk(bool enable)
1398{
1399 int r;
1400 unsigned long flags;
1401
1402 r = 0;
1403
1404 mutex_lock(&mb3_transfer.sysclk_lock);
1405
1406 spin_lock_irqsave(&mb3_transfer.lock, flags);
1407
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001408 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001409 cpu_relax();
1410
1411 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1412
1413 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001414 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001415
1416 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1417
1418 /*
1419 * The firmware only sends an ACK if we want to enable the
1420 * SysClk, and it succeeds.
1421 */
1422 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1423 msecs_to_jiffies(20000))) {
1424 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1425 __func__);
1426 r = -EIO;
1427 }
1428
1429 mutex_unlock(&mb3_transfer.sysclk_lock);
1430
1431 return r;
1432}
1433
1434static int request_timclk(bool enable)
1435{
1436 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1437
1438 if (!enable)
1439 val |= PRCM_TCR_STOP_TIMERS;
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001440 writel(val, PRCM_TCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001441
1442 return 0;
1443}
1444
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001445static int request_clock(u8 clock, bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001446{
1447 u32 val;
1448 unsigned long flags;
1449
1450 spin_lock_irqsave(&clk_mgt_lock, flags);
1451
1452 /* Grab the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001453 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001454 cpu_relax();
1455
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001456 val = readl(clk_mgt[clock].reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001457 if (enable) {
1458 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1459 } else {
1460 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1461 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1462 }
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001463 writel(val, clk_mgt[clock].reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001464
1465 /* Release the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001466 writel(0, PRCM_SEM);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001467
1468 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1469
1470 return 0;
1471}
1472
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001473static int request_sga_clock(u8 clock, bool enable)
1474{
1475 u32 val;
1476 int ret;
1477
1478 if (enable) {
1479 val = readl(PRCM_CGATING_BYPASS);
1480 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1481 }
1482
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001483 ret = request_clock(clock, enable);
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001484
1485 if (!ret && !enable) {
1486 val = readl(PRCM_CGATING_BYPASS);
1487 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1488 }
1489
1490 return ret;
1491}
1492
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001493static inline bool plldsi_locked(void)
1494{
1495 return (readl(PRCM_PLLDSI_LOCKP) &
1496 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1497 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1498 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1499 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1500}
1501
1502static int request_plldsi(bool enable)
1503{
1504 int r = 0;
1505 u32 val;
1506
1507 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1508 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1509 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1510
1511 val = readl(PRCM_PLLDSI_ENABLE);
1512 if (enable)
1513 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1514 else
1515 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1516 writel(val, PRCM_PLLDSI_ENABLE);
1517
1518 if (enable) {
1519 unsigned int i;
1520 bool locked = plldsi_locked();
1521
1522 for (i = 10; !locked && (i > 0); --i) {
1523 udelay(100);
1524 locked = plldsi_locked();
1525 }
1526 if (locked) {
1527 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1528 PRCM_APE_RESETN_SET);
1529 } else {
1530 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1531 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1532 PRCM_MMIP_LS_CLAMP_SET);
1533 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1534 writel(val, PRCM_PLLDSI_ENABLE);
1535 r = -EAGAIN;
1536 }
1537 } else {
1538 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1539 }
1540 return r;
1541}
1542
1543static int request_dsiclk(u8 n, bool enable)
1544{
1545 u32 val;
1546
1547 val = readl(PRCM_DSI_PLLOUT_SEL);
1548 val &= ~dsiclk[n].divsel_mask;
1549 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1550 dsiclk[n].divsel_shift);
1551 writel(val, PRCM_DSI_PLLOUT_SEL);
1552 return 0;
1553}
1554
1555static int request_dsiescclk(u8 n, bool enable)
1556{
1557 u32 val;
1558
1559 val = readl(PRCM_DSITVCLK_DIV);
1560 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1561 writel(val, PRCM_DSITVCLK_DIV);
1562 return 0;
1563}
1564
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001565/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001566 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001567 * @clock: The clock for which the request is made.
1568 * @enable: Whether the clock should be enabled (true) or disabled (false).
1569 *
1570 * This function should only be used by the clock implementation.
1571 * Do not use it from any other place!
1572 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001573int db8500_prcmu_request_clock(u8 clock, bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001574{
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001575 if (clock == PRCMU_SGACLK)
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001576 return request_sga_clock(clock, enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001577 else if (clock < PRCMU_NUM_REG_CLOCKS)
1578 return request_clock(clock, enable);
1579 else if (clock == PRCMU_TIMCLK)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001580 return request_timclk(enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001581 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1582 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1583 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1584 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1585 else if (clock == PRCMU_PLLDSI)
1586 return request_plldsi(enable);
1587 else if (clock == PRCMU_SYSCLK)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001588 return request_sysclk(enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001589 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001590 return request_pll(clock, enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001591 else
1592 return -EINVAL;
1593}
1594
1595static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1596 int branch)
1597{
1598 u64 rate;
1599 u32 val;
1600 u32 d;
1601 u32 div = 1;
1602
1603 val = readl(reg);
1604
1605 rate = src_rate;
1606 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1607
1608 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1609 if (d > 1)
1610 div *= d;
1611
1612 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1613 if (d > 1)
1614 div *= d;
1615
1616 if (val & PRCM_PLL_FREQ_SELDIV2)
1617 div *= 2;
1618
1619 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1620 (val & PRCM_PLL_FREQ_DIV2EN) &&
1621 ((reg == PRCM_PLLSOC0_FREQ) ||
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001622 (reg == PRCM_PLLARM_FREQ) ||
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001623 (reg == PRCM_PLLDDR_FREQ))))
1624 div *= 2;
1625
1626 (void)do_div(rate, div);
1627
1628 return (unsigned long)rate;
1629}
1630
1631#define ROOT_CLOCK_RATE 38400000
1632
1633static unsigned long clock_rate(u8 clock)
1634{
1635 u32 val;
1636 u32 pllsw;
1637 unsigned long rate = ROOT_CLOCK_RATE;
1638
1639 val = readl(clk_mgt[clock].reg);
1640
1641 if (val & PRCM_CLK_MGT_CLK38) {
1642 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1643 rate /= 2;
1644 return rate;
Linus Walleije62ccf32011-10-10 12:14:14 +02001645 }
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001646
1647 val |= clk_mgt[clock].pllsw;
1648 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1649
1650 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1651 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1652 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1653 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1654 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1655 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1656 else
1657 return 0;
1658
1659 if ((clock == PRCMU_SGACLK) &&
1660 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1661 u64 r = (rate * 10);
1662
1663 (void)do_div(r, 25);
1664 return (unsigned long)r;
1665 }
1666 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1667 if (val)
1668 return rate / val;
1669 else
1670 return 0;
1671}
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001672static unsigned long latest_armss_rate;
1673static unsigned long armss_rate(void)
1674{
1675 return latest_armss_rate;
1676}
1677
1678static void compute_armss_rate(void)
1679{
1680 u32 r;
1681 unsigned long rate;
1682
1683 r = readl(PRCM_ARM_CHGCLKREQ);
1684
1685 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1686 /* External ARMCLKFIX clock */
1687
1688 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1689
1690 /* Check PRCM_ARM_CHGCLKREQ divider */
1691 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1692 rate /= 2;
1693
1694 /* Check PRCM_ARMCLKFIX_MGT divider */
1695 r = readl(PRCM_ARMCLKFIX_MGT);
1696 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1697 rate /= r;
1698
1699 } else {/* ARM PLL */
1700 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1701 }
1702
1703 latest_armss_rate = rate;
1704}
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001705
1706static unsigned long dsiclk_rate(u8 n)
1707{
1708 u32 divsel;
1709 u32 div = 1;
1710
1711 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1712 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1713
1714 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1715 divsel = dsiclk[n].divsel;
1716
1717 switch (divsel) {
1718 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1719 div *= 2;
1720 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1721 div *= 2;
1722 case PRCM_DSI_PLLOUT_SEL_PHI:
1723 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1724 PLL_RAW) / div;
1725 default:
1726 return 0;
1727 }
1728}
1729
1730static unsigned long dsiescclk_rate(u8 n)
1731{
1732 u32 div;
1733
1734 div = readl(PRCM_DSITVCLK_DIV);
1735 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1736 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1737}
1738
1739unsigned long prcmu_clock_rate(u8 clock)
1740{
Linus Walleije62ccf32011-10-10 12:14:14 +02001741 if (clock < PRCMU_NUM_REG_CLOCKS)
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001742 return clock_rate(clock);
1743 else if (clock == PRCMU_TIMCLK)
1744 return ROOT_CLOCK_RATE / 16;
1745 else if (clock == PRCMU_SYSCLK)
1746 return ROOT_CLOCK_RATE;
1747 else if (clock == PRCMU_PLLSOC0)
1748 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1749 else if (clock == PRCMU_PLLSOC1)
1750 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001751 else if (clock == PRCMU_ARMSS)
1752 return armss_rate();
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001753 else if (clock == PRCMU_PLLDDR)
1754 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1755 else if (clock == PRCMU_PLLDSI)
1756 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1757 PLL_RAW);
1758 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1759 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1760 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1761 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1762 else
1763 return 0;
1764}
1765
1766static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1767{
1768 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1769 return ROOT_CLOCK_RATE;
1770 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1771 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1772 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1773 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1774 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1775 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1776 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1777 else
1778 return 0;
1779}
1780
1781static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1782{
1783 u32 div;
1784
1785 div = (src_rate / rate);
1786 if (div == 0)
1787 return 1;
1788 if (rate < (src_rate / div))
1789 div++;
1790 return div;
1791}
1792
1793static long round_clock_rate(u8 clock, unsigned long rate)
1794{
1795 u32 val;
1796 u32 div;
1797 unsigned long src_rate;
1798 long rounded_rate;
1799
1800 val = readl(clk_mgt[clock].reg);
1801 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1802 clk_mgt[clock].branch);
1803 div = clock_divider(src_rate, rate);
1804 if (val & PRCM_CLK_MGT_CLK38) {
1805 if (clk_mgt[clock].clk38div) {
1806 if (div > 2)
1807 div = 2;
1808 } else {
1809 div = 1;
1810 }
1811 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1812 u64 r = (src_rate * 10);
1813
1814 (void)do_div(r, 25);
1815 if (r <= rate)
1816 return (unsigned long)r;
1817 }
1818 rounded_rate = (src_rate / min(div, (u32)31));
1819
1820 return rounded_rate;
1821}
1822
1823#define MIN_PLL_VCO_RATE 600000000ULL
1824#define MAX_PLL_VCO_RATE 1680640000ULL
1825
1826static long round_plldsi_rate(unsigned long rate)
1827{
1828 long rounded_rate = 0;
1829 unsigned long src_rate;
1830 unsigned long rem;
1831 u32 r;
1832
1833 src_rate = clock_rate(PRCMU_HDMICLK);
1834 rem = rate;
1835
1836 for (r = 7; (rem > 0) && (r > 0); r--) {
1837 u64 d;
1838
1839 d = (r * rate);
1840 (void)do_div(d, src_rate);
1841 if (d < 6)
1842 d = 6;
1843 else if (d > 255)
1844 d = 255;
1845 d *= src_rate;
1846 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1847 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1848 continue;
1849 (void)do_div(d, r);
1850 if (rate < d) {
1851 if (rounded_rate == 0)
1852 rounded_rate = (long)d;
1853 break;
1854 }
1855 if ((rate - d) < rem) {
1856 rem = (rate - d);
1857 rounded_rate = (long)d;
1858 }
1859 }
1860 return rounded_rate;
1861}
1862
1863static long round_dsiclk_rate(unsigned long rate)
1864{
1865 u32 div;
1866 unsigned long src_rate;
1867 long rounded_rate;
1868
1869 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1870 PLL_RAW);
1871 div = clock_divider(src_rate, rate);
1872 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1873
1874 return rounded_rate;
1875}
1876
1877static long round_dsiescclk_rate(unsigned long rate)
1878{
1879 u32 div;
1880 unsigned long src_rate;
1881 long rounded_rate;
1882
1883 src_rate = clock_rate(PRCMU_TVCLK);
1884 div = clock_divider(src_rate, rate);
1885 rounded_rate = (src_rate / min(div, (u32)255));
1886
1887 return rounded_rate;
1888}
1889
1890long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1891{
1892 if (clock < PRCMU_NUM_REG_CLOCKS)
1893 return round_clock_rate(clock, rate);
1894 else if (clock == PRCMU_PLLDSI)
1895 return round_plldsi_rate(rate);
1896 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1897 return round_dsiclk_rate(rate);
1898 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1899 return round_dsiescclk_rate(rate);
1900 else
1901 return (long)prcmu_clock_rate(clock);
1902}
1903
1904static void set_clock_rate(u8 clock, unsigned long rate)
1905{
1906 u32 val;
1907 u32 div;
1908 unsigned long src_rate;
1909 unsigned long flags;
1910
1911 spin_lock_irqsave(&clk_mgt_lock, flags);
1912
1913 /* Grab the HW semaphore. */
1914 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1915 cpu_relax();
1916
1917 val = readl(clk_mgt[clock].reg);
1918 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1919 clk_mgt[clock].branch);
1920 div = clock_divider(src_rate, rate);
1921 if (val & PRCM_CLK_MGT_CLK38) {
1922 if (clk_mgt[clock].clk38div) {
1923 if (div > 1)
1924 val |= PRCM_CLK_MGT_CLK38DIV;
1925 else
1926 val &= ~PRCM_CLK_MGT_CLK38DIV;
1927 }
1928 } else if (clock == PRCMU_SGACLK) {
1929 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1930 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1931 if (div == 3) {
1932 u64 r = (src_rate * 10);
1933
1934 (void)do_div(r, 25);
1935 if (r <= rate) {
1936 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1937 div = 0;
1938 }
1939 }
1940 val |= min(div, (u32)31);
1941 } else {
1942 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1943 val |= min(div, (u32)31);
1944 }
1945 writel(val, clk_mgt[clock].reg);
1946
1947 /* Release the HW semaphore. */
1948 writel(0, PRCM_SEM);
1949
1950 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1951}
1952
1953static int set_plldsi_rate(unsigned long rate)
1954{
1955 unsigned long src_rate;
1956 unsigned long rem;
1957 u32 pll_freq = 0;
1958 u32 r;
1959
1960 src_rate = clock_rate(PRCMU_HDMICLK);
1961 rem = rate;
1962
1963 for (r = 7; (rem > 0) && (r > 0); r--) {
1964 u64 d;
1965 u64 hwrate;
1966
1967 d = (r * rate);
1968 (void)do_div(d, src_rate);
1969 if (d < 6)
1970 d = 6;
1971 else if (d > 255)
1972 d = 255;
1973 hwrate = (d * src_rate);
1974 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1975 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1976 continue;
1977 (void)do_div(hwrate, r);
1978 if (rate < hwrate) {
1979 if (pll_freq == 0)
1980 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1981 (r << PRCM_PLL_FREQ_R_SHIFT));
1982 break;
1983 }
1984 if ((rate - hwrate) < rem) {
1985 rem = (rate - hwrate);
1986 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1987 (r << PRCM_PLL_FREQ_R_SHIFT));
1988 }
1989 }
1990 if (pll_freq == 0)
1991 return -EINVAL;
1992
1993 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1994 writel(pll_freq, PRCM_PLLDSI_FREQ);
1995
1996 return 0;
1997}
1998
1999static void set_dsiclk_rate(u8 n, unsigned long rate)
2000{
2001 u32 val;
2002 u32 div;
2003
2004 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
2005 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
2006
2007 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
2008 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
2009 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
2010
2011 val = readl(PRCM_DSI_PLLOUT_SEL);
2012 val &= ~dsiclk[n].divsel_mask;
2013 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
2014 writel(val, PRCM_DSI_PLLOUT_SEL);
2015}
2016
2017static void set_dsiescclk_rate(u8 n, unsigned long rate)
2018{
2019 u32 val;
2020 u32 div;
2021
2022 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
2023 val = readl(PRCM_DSITVCLK_DIV);
2024 val &= ~dsiescclk[n].div_mask;
2025 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
2026 writel(val, PRCM_DSITVCLK_DIV);
2027}
2028
2029int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2030{
2031 if (clock < PRCMU_NUM_REG_CLOCKS)
2032 set_clock_rate(clock, rate);
2033 else if (clock == PRCMU_PLLDSI)
2034 return set_plldsi_rate(rate);
2035 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2036 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
2037 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2038 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
2039 return 0;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002040}
2041
Mattias Nilsson73180f82011-08-12 10:28:10 +02002042int db8500_prcmu_config_esram0_deep_sleep(u8 state)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002043{
2044 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2045 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2046 return -EINVAL;
2047
2048 mutex_lock(&mb4_transfer.lock);
2049
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002050 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002051 cpu_relax();
2052
2053 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2054 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2055 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2056 writeb(DDR_PWR_STATE_ON,
2057 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2058 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2059
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002060 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002061 wait_for_completion(&mb4_transfer.work);
2062
2063 mutex_unlock(&mb4_transfer.lock);
2064
2065 return 0;
2066}
2067
Mattias Nilsson05089012012-01-13 16:20:20 +01002068int db8500_prcmu_config_hotdog(u8 threshold)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002069{
2070 mutex_lock(&mb4_transfer.lock);
2071
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002072 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002073 cpu_relax();
2074
2075 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2076 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2077
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002078 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002079 wait_for_completion(&mb4_transfer.work);
2080
2081 mutex_unlock(&mb4_transfer.lock);
2082
2083 return 0;
2084}
2085
Mattias Nilsson05089012012-01-13 16:20:20 +01002086int db8500_prcmu_config_hotmon(u8 low, u8 high)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002087{
2088 mutex_lock(&mb4_transfer.lock);
2089
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002090 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002091 cpu_relax();
2092
2093 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2094 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2095 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2096 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2097 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2098
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002099 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002100 wait_for_completion(&mb4_transfer.work);
2101
2102 mutex_unlock(&mb4_transfer.lock);
2103
2104 return 0;
2105}
2106
2107static int config_hot_period(u16 val)
2108{
2109 mutex_lock(&mb4_transfer.lock);
2110
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002111 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002112 cpu_relax();
2113
2114 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2115 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2116
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002117 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002118 wait_for_completion(&mb4_transfer.work);
2119
2120 mutex_unlock(&mb4_transfer.lock);
2121
2122 return 0;
2123}
2124
Mattias Nilsson05089012012-01-13 16:20:20 +01002125int db8500_prcmu_start_temp_sense(u16 cycles32k)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002126{
2127 if (cycles32k == 0xFFFF)
2128 return -EINVAL;
2129
2130 return config_hot_period(cycles32k);
2131}
2132
Mattias Nilsson05089012012-01-13 16:20:20 +01002133int db8500_prcmu_stop_temp_sense(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002134{
2135 return config_hot_period(0xFFFF);
2136}
2137
Jonas Aberg84165b82011-08-12 10:28:33 +02002138static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2139{
2140
2141 mutex_lock(&mb4_transfer.lock);
2142
2143 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2144 cpu_relax();
2145
2146 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2147 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2148 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2149 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2150
2151 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2152
2153 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2154 wait_for_completion(&mb4_transfer.work);
2155
2156 mutex_unlock(&mb4_transfer.lock);
2157
2158 return 0;
2159
2160}
2161
Mattias Nilsson05089012012-01-13 16:20:20 +01002162int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
Jonas Aberg84165b82011-08-12 10:28:33 +02002163{
2164 BUG_ON(num == 0 || num > 0xf);
2165 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2166 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2167 A9WDOG_AUTO_OFF_DIS);
2168}
2169
Mattias Nilsson05089012012-01-13 16:20:20 +01002170int db8500_prcmu_enable_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002171{
2172 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2173}
2174
Mattias Nilsson05089012012-01-13 16:20:20 +01002175int db8500_prcmu_disable_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002176{
2177 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2178}
2179
Mattias Nilsson05089012012-01-13 16:20:20 +01002180int db8500_prcmu_kick_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002181{
2182 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2183}
2184
2185/*
2186 * timeout is 28 bit, in ms.
2187 */
Mattias Nilsson05089012012-01-13 16:20:20 +01002188int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
Jonas Aberg84165b82011-08-12 10:28:33 +02002189{
Jonas Aberg84165b82011-08-12 10:28:33 +02002190 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2191 (id & A9WDOG_ID_MASK) |
2192 /*
2193 * Put the lowest 28 bits of timeout at
2194 * offset 4. Four first bits are used for id.
2195 */
2196 (u8)((timeout << 4) & 0xf0),
2197 (u8)((timeout >> 4) & 0xff),
2198 (u8)((timeout >> 12) & 0xff),
2199 (u8)((timeout >> 20) & 0xff));
2200}
2201
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002202/**
Linus Walleije3726fc2010-08-19 12:36:01 +01002203 * prcmu_abb_read() - Read register value(s) from the ABB.
2204 * @slave: The I2C slave address.
2205 * @reg: The (start) register address.
2206 * @value: The read out value(s).
2207 * @size: The number of registers to read.
2208 *
2209 * Reads register value(s) from the ABB.
2210 * @size has to be 1 for the current firmware version.
2211 */
2212int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2213{
2214 int r;
2215
2216 if (size != 1)
2217 return -EINVAL;
2218
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002219 mutex_lock(&mb5_transfer.lock);
Linus Walleije3726fc2010-08-19 12:36:01 +01002220
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002221 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
Linus Walleije3726fc2010-08-19 12:36:01 +01002222 cpu_relax();
2223
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002224 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002225 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2226 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2227 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2228 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
Linus Walleije3726fc2010-08-19 12:36:01 +01002229
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002230 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002231
Linus Walleije3726fc2010-08-19 12:36:01 +01002232 if (!wait_for_completion_timeout(&mb5_transfer.work,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002233 msecs_to_jiffies(20000))) {
2234 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2235 __func__);
Linus Walleije3726fc2010-08-19 12:36:01 +01002236 r = -EIO;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002237 } else {
2238 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
Linus Walleije3726fc2010-08-19 12:36:01 +01002239 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002240
Linus Walleije3726fc2010-08-19 12:36:01 +01002241 if (!r)
2242 *value = mb5_transfer.ack.value;
2243
Linus Walleije3726fc2010-08-19 12:36:01 +01002244 mutex_unlock(&mb5_transfer.lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002245
Linus Walleije3726fc2010-08-19 12:36:01 +01002246 return r;
2247}
Linus Walleije3726fc2010-08-19 12:36:01 +01002248
2249/**
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002250 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
Linus Walleije3726fc2010-08-19 12:36:01 +01002251 * @slave: The I2C slave address.
2252 * @reg: The (start) register address.
2253 * @value: The value(s) to write.
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002254 * @mask: The mask(s) to use.
Linus Walleije3726fc2010-08-19 12:36:01 +01002255 * @size: The number of registers to write.
2256 *
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002257 * Writes masked register value(s) to the ABB.
2258 * For each @value, only the bits set to 1 in the corresponding @mask
2259 * will be written. The other bits are not changed.
Linus Walleije3726fc2010-08-19 12:36:01 +01002260 * @size has to be 1 for the current firmware version.
2261 */
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002262int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
Linus Walleije3726fc2010-08-19 12:36:01 +01002263{
2264 int r;
2265
2266 if (size != 1)
2267 return -EINVAL;
2268
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002269 mutex_lock(&mb5_transfer.lock);
Linus Walleije3726fc2010-08-19 12:36:01 +01002270
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002271 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
Linus Walleije3726fc2010-08-19 12:36:01 +01002272 cpu_relax();
2273
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002274 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002275 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2276 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2277 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2278 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
Linus Walleije3726fc2010-08-19 12:36:01 +01002279
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002280 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002281
Linus Walleije3726fc2010-08-19 12:36:01 +01002282 if (!wait_for_completion_timeout(&mb5_transfer.work,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002283 msecs_to_jiffies(20000))) {
2284 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2285 __func__);
Linus Walleije3726fc2010-08-19 12:36:01 +01002286 r = -EIO;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002287 } else {
2288 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
Linus Walleije3726fc2010-08-19 12:36:01 +01002289 }
Linus Walleije3726fc2010-08-19 12:36:01 +01002290
Linus Walleije3726fc2010-08-19 12:36:01 +01002291 mutex_unlock(&mb5_transfer.lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002292
Linus Walleije3726fc2010-08-19 12:36:01 +01002293 return r;
2294}
Linus Walleije3726fc2010-08-19 12:36:01 +01002295
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002296/**
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002297 * prcmu_abb_write() - Write register value(s) to the ABB.
2298 * @slave: The I2C slave address.
2299 * @reg: The (start) register address.
2300 * @value: The value(s) to write.
2301 * @size: The number of registers to write.
2302 *
2303 * Writes register value(s) to the ABB.
2304 * @size has to be 1 for the current firmware version.
2305 */
2306int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2307{
2308 u8 mask = ~0;
2309
2310 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2311}
2312
2313/**
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002314 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2315 */
Arun Murthy5261e102012-05-21 14:28:21 +05302316int prcmu_ac_wake_req(void)
Martin Perssone0befb22010-12-08 15:13:28 +01002317{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002318 u32 val;
Arun Murthy5261e102012-05-21 14:28:21 +05302319 int ret = 0;
Martin Perssone0befb22010-12-08 15:13:28 +01002320
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002321 mutex_lock(&mb0_transfer.ac_wake_lock);
Martin Perssone0befb22010-12-08 15:13:28 +01002322
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002323 val = readl(PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002324 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2325 goto unlock_and_return;
2326
2327 atomic_set(&ac_wake_req_state, 1);
2328
Arun Murthy5261e102012-05-21 14:28:21 +05302329 /*
2330 * Force Modem Wake-up before hostaccess_req ping-pong.
2331 * It prevents Modem to enter in Sleep while acking the hostaccess
2332 * request. The 31us delay has been calculated by HWI.
2333 */
2334 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2335 writel(val, PRCM_HOSTACCESS_REQ);
2336
2337 udelay(31);
2338
2339 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2340 writel(val, PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002341
2342 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
Mattias Nilssond6e30022011-08-12 10:28:43 +02002343 msecs_to_jiffies(5000))) {
Arun Murthy5261e102012-05-21 14:28:21 +05302344#if defined(CONFIG_DBX500_PRCMU_DEBUG)
2345 db8500_prcmu_debug_dump(__func__, true, true);
2346#endif
Linus Walleij57265bc2011-10-10 13:04:44 +02002347 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
Mattias Nilssond6e30022011-08-12 10:28:43 +02002348 __func__);
Arun Murthy5261e102012-05-21 14:28:21 +05302349 ret = -EFAULT;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002350 }
2351
2352unlock_and_return:
2353 mutex_unlock(&mb0_transfer.ac_wake_lock);
Arun Murthy5261e102012-05-21 14:28:21 +05302354 return ret;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002355}
2356
2357/**
2358 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2359 */
2360void prcmu_ac_sleep_req()
2361{
2362 u32 val;
2363
2364 mutex_lock(&mb0_transfer.ac_wake_lock);
2365
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002366 val = readl(PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002367 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2368 goto unlock_and_return;
2369
2370 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002371 PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002372
2373 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
Mattias Nilssond6e30022011-08-12 10:28:43 +02002374 msecs_to_jiffies(5000))) {
Linus Walleij57265bc2011-10-10 13:04:44 +02002375 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002376 __func__);
2377 }
2378
2379 atomic_set(&ac_wake_req_state, 0);
2380
2381unlock_and_return:
2382 mutex_unlock(&mb0_transfer.ac_wake_lock);
2383}
2384
Mattias Nilsson73180f82011-08-12 10:28:10 +02002385bool db8500_prcmu_is_ac_wake_requested(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002386{
2387 return (atomic_read(&ac_wake_req_state) != 0);
2388}
2389
2390/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02002391 * db8500_prcmu_system_reset - System reset
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002392 *
Mattias Nilsson73180f82011-08-12 10:28:10 +02002393 * Saves the reset reason code and then sets the APE_SOFTRST register which
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002394 * fires interrupt to fw
2395 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02002396void db8500_prcmu_system_reset(u16 reset_code)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002397{
2398 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002399 writel(1, PRCM_APE_SOFTRST);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002400}
2401
2402/**
Sebastian Rasmussen597045d2011-08-12 10:28:53 +02002403 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2404 *
2405 * Retrieves the reset reason code stored by prcmu_system_reset() before
2406 * last restart.
2407 */
2408u16 db8500_prcmu_get_reset_code(void)
2409{
2410 return readw(tcdm_base + PRCM_SW_RST_REASON);
2411}
2412
2413/**
Mattias Nilsson05089012012-01-13 16:20:20 +01002414 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002415 */
Mattias Nilsson05089012012-01-13 16:20:20 +01002416void db8500_prcmu_modem_reset(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002417{
Martin Perssone0befb22010-12-08 15:13:28 +01002418 mutex_lock(&mb1_transfer.lock);
2419
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002420 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Martin Perssone0befb22010-12-08 15:13:28 +01002421 cpu_relax();
2422
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002423 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002424 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Martin Perssone0befb22010-12-08 15:13:28 +01002425 wait_for_completion(&mb1_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002426
2427 /*
2428 * No need to check return from PRCMU as modem should go in reset state
2429 * This state is already managed by upper layer
2430 */
Martin Perssone0befb22010-12-08 15:13:28 +01002431
2432 mutex_unlock(&mb1_transfer.lock);
Martin Perssone0befb22010-12-08 15:13:28 +01002433}
2434
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002435static void ack_dbb_wakeup(void)
Martin Perssone0befb22010-12-08 15:13:28 +01002436{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002437 unsigned long flags;
Martin Perssone0befb22010-12-08 15:13:28 +01002438
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002439 spin_lock_irqsave(&mb0_transfer.lock, flags);
Martin Perssone0befb22010-12-08 15:13:28 +01002440
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002441 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002442 cpu_relax();
Martin Perssone0befb22010-12-08 15:13:28 +01002443
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002444 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002445 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Martin Perssone0befb22010-12-08 15:13:28 +01002446
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002447 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
Martin Perssone0befb22010-12-08 15:13:28 +01002448}
2449
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002450static inline void print_unknown_header_warning(u8 n, u8 header)
Linus Walleije3726fc2010-08-19 12:36:01 +01002451{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002452 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2453 header, n);
Linus Walleije3726fc2010-08-19 12:36:01 +01002454}
2455
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002456static bool read_mailbox_0(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002457{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002458 bool r;
2459 u32 ev;
2460 unsigned int n;
2461 u8 header;
2462
2463 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2464 switch (header) {
2465 case MB0H_WAKEUP_EXE:
2466 case MB0H_WAKEUP_SLEEP:
2467 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2468 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2469 else
2470 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2471
2472 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2473 complete(&mb0_transfer.ac_wake_work);
2474 if (ev & WAKEUP_BIT_SYSCLK_OK)
2475 complete(&mb3_transfer.sysclk_work);
2476
2477 ev &= mb0_transfer.req.dbb_irqs;
2478
2479 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2480 if (ev & prcmu_irq_bit[n])
2481 generic_handle_irq(IRQ_PRCMU_BASE + n);
2482 }
2483 r = true;
2484 break;
2485 default:
2486 print_unknown_header_warning(0, header);
2487 r = false;
2488 break;
2489 }
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002490 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002491 return r;
2492}
2493
2494static bool read_mailbox_1(void)
2495{
2496 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2497 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2498 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2499 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2500 PRCM_ACK_MB1_CURRENT_APE_OPP);
2501 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2502 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002503 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
Martin Perssone0befb22010-12-08 15:13:28 +01002504 complete(&mb1_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002505 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002506}
2507
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002508static bool read_mailbox_2(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002509{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002510 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002511 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002512 complete(&mb2_transfer.work);
2513 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002514}
2515
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002516static bool read_mailbox_3(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002517{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002518 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002519 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002520}
2521
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002522static bool read_mailbox_4(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002523{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002524 u8 header;
2525 bool do_complete = true;
2526
2527 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2528 switch (header) {
2529 case MB4H_MEM_ST:
2530 case MB4H_HOTDOG:
2531 case MB4H_HOTMON:
2532 case MB4H_HOT_PERIOD:
Mattias Nilssona592c2e2011-08-12 10:27:41 +02002533 case MB4H_A9WDOG_CONF:
2534 case MB4H_A9WDOG_EN:
2535 case MB4H_A9WDOG_DIS:
2536 case MB4H_A9WDOG_LOAD:
2537 case MB4H_A9WDOG_KICK:
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002538 break;
2539 default:
2540 print_unknown_header_warning(4, header);
2541 do_complete = false;
2542 break;
2543 }
2544
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002545 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002546
2547 if (do_complete)
2548 complete(&mb4_transfer.work);
2549
2550 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002551}
2552
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002553static bool read_mailbox_5(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002554{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002555 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2556 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002557 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
Linus Walleije3726fc2010-08-19 12:36:01 +01002558 complete(&mb5_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002559 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002560}
2561
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002562static bool read_mailbox_6(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002563{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002564 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002565 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002566}
2567
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002568static bool read_mailbox_7(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002569{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002570 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002571 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002572}
2573
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002574static bool (* const read_mailbox[NUM_MB])(void) = {
Linus Walleije3726fc2010-08-19 12:36:01 +01002575 read_mailbox_0,
2576 read_mailbox_1,
2577 read_mailbox_2,
2578 read_mailbox_3,
2579 read_mailbox_4,
2580 read_mailbox_5,
2581 read_mailbox_6,
2582 read_mailbox_7
2583};
2584
2585static irqreturn_t prcmu_irq_handler(int irq, void *data)
2586{
2587 u32 bits;
2588 u8 n;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002589 irqreturn_t r;
Linus Walleije3726fc2010-08-19 12:36:01 +01002590
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002591 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
Linus Walleije3726fc2010-08-19 12:36:01 +01002592 if (unlikely(!bits))
2593 return IRQ_NONE;
2594
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002595 r = IRQ_HANDLED;
Linus Walleije3726fc2010-08-19 12:36:01 +01002596 for (n = 0; bits; n++) {
2597 if (bits & MBOX_BIT(n)) {
2598 bits -= MBOX_BIT(n);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002599 if (read_mailbox[n]())
2600 r = IRQ_WAKE_THREAD;
Linus Walleije3726fc2010-08-19 12:36:01 +01002601 }
2602 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002603 return r;
2604}
2605
2606static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2607{
2608 ack_dbb_wakeup();
Linus Walleije3726fc2010-08-19 12:36:01 +01002609 return IRQ_HANDLED;
2610}
2611
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002612static void prcmu_mask_work(struct work_struct *work)
2613{
2614 unsigned long flags;
2615
2616 spin_lock_irqsave(&mb0_transfer.lock, flags);
2617
2618 config_wakeups();
2619
2620 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2621}
2622
2623static void prcmu_irq_mask(struct irq_data *d)
2624{
2625 unsigned long flags;
2626
2627 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2628
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002629 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002630
2631 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2632
2633 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2634 schedule_work(&mb0_transfer.mask_work);
2635}
2636
2637static void prcmu_irq_unmask(struct irq_data *d)
2638{
2639 unsigned long flags;
2640
2641 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2642
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002643 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002644
2645 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2646
2647 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2648 schedule_work(&mb0_transfer.mask_work);
2649}
2650
2651static void noop(struct irq_data *d)
2652{
2653}
2654
2655static struct irq_chip prcmu_irq_chip = {
2656 .name = "prcmu",
2657 .irq_disable = prcmu_irq_mask,
2658 .irq_ack = noop,
2659 .irq_mask = prcmu_irq_mask,
2660 .irq_unmask = prcmu_irq_unmask,
2661};
2662
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002663static char *fw_project_name(u8 project)
2664{
2665 switch (project) {
2666 case PRCMU_FW_PROJECT_U8500:
2667 return "U8500";
2668 case PRCMU_FW_PROJECT_U8500_C2:
2669 return "U8500 C2";
2670 case PRCMU_FW_PROJECT_U9500:
2671 return "U9500";
2672 case PRCMU_FW_PROJECT_U9500_C2:
2673 return "U9500 C2";
Bengt Jonsson5f96a1a62012-03-15 19:50:40 +01002674 case PRCMU_FW_PROJECT_U8520:
2675 return "U8520";
Bengt Jonsson1927ddf2012-03-15 19:50:51 +01002676 case PRCMU_FW_PROJECT_U8420:
2677 return "U8420";
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002678 default:
2679 return "Unknown";
2680 }
2681}
2682
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002683static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2684 irq_hw_number_t hwirq)
2685{
2686 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2687 handle_simple_irq);
2688 set_irq_flags(virq, IRQF_VALID);
2689
2690 return 0;
2691}
2692
2693static struct irq_domain_ops db8500_irq_ops = {
2694 .map = db8500_irq_map,
2695 .xlate = irq_domain_xlate_twocell,
2696};
2697
2698static int db8500_irq_init(struct device_node *np)
2699{
2700 db8500_irq_domain = irq_domain_add_legacy(
2701 np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE,
2702 0, &db8500_irq_ops, NULL);
2703
2704 if (!db8500_irq_domain) {
2705 pr_err("Failed to create irqdomain\n");
2706 return -ENOSYS;
2707 }
2708
2709 return 0;
2710}
2711
Mattias Nilsson73180f82011-08-12 10:28:10 +02002712void __init db8500_prcmu_early_init(void)
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002713{
Linus Walleij3e2762c2012-01-02 14:17:40 +01002714 if (cpu_is_u8500v2()) {
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002715 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2716
2717 if (tcpm_base != NULL) {
Linus Walleij3e2762c2012-01-02 14:17:40 +01002718 u32 version;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002719 version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002720 fw_info.version.project = version & 0xFF;
2721 fw_info.version.api_version = (version >> 8) & 0xFF;
2722 fw_info.version.func_version = (version >> 16) & 0xFF;
2723 fw_info.version.errata = (version >> 24) & 0xFF;
2724 fw_info.valid = true;
2725 pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2726 fw_project_name(fw_info.version.project),
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002727 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2728 (version >> 24) & 0xFF);
2729 iounmap(tcpm_base);
2730 }
2731
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002732 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2733 } else {
2734 pr_err("prcmu: Unsupported chip version\n");
2735 BUG();
2736 }
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002737
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002738 spin_lock_init(&mb0_transfer.lock);
2739 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2740 mutex_init(&mb0_transfer.ac_wake_lock);
2741 init_completion(&mb0_transfer.ac_wake_work);
Martin Perssone0befb22010-12-08 15:13:28 +01002742 mutex_init(&mb1_transfer.lock);
2743 init_completion(&mb1_transfer.work);
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01002744 mb1_transfer.ape_opp = APE_NO_CHANGE;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002745 mutex_init(&mb2_transfer.lock);
2746 init_completion(&mb2_transfer.work);
2747 spin_lock_init(&mb2_transfer.auto_pm_lock);
2748 spin_lock_init(&mb3_transfer.lock);
2749 mutex_init(&mb3_transfer.sysclk_lock);
2750 init_completion(&mb3_transfer.sysclk_work);
2751 mutex_init(&mb4_transfer.lock);
2752 init_completion(&mb4_transfer.work);
Linus Walleije3726fc2010-08-19 12:36:01 +01002753 mutex_init(&mb5_transfer.lock);
2754 init_completion(&mb5_transfer.work);
2755
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002756 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
Linus Walleije3726fc2010-08-19 12:36:01 +01002757
Michel Jaouen20aee5b2012-08-31 14:21:30 +02002758 compute_armss_rate();
Linus Walleije3726fc2010-08-19 12:36:01 +01002759}
2760
Mattias Nilsson05089012012-01-13 16:20:20 +01002761static void __init init_prcm_registers(void)
Mattias Nilssond65e12d2011-08-12 10:27:50 +02002762{
2763 u32 val;
2764
2765 val = readl(PRCM_A9PL_FORCE_CLKEN);
2766 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2767 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2768 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2769}
2770
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002771/*
2772 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2773 */
2774static struct regulator_consumer_supply db8500_vape_consumers[] = {
2775 REGULATOR_SUPPLY("v-ape", NULL),
2776 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2777 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2778 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2779 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
Lee Jonesae840632012-05-04 19:23:20 +01002780 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002781 /* "v-mmc" changed to "vcore" in the mainline kernel */
2782 REGULATOR_SUPPLY("vcore", "sdi0"),
2783 REGULATOR_SUPPLY("vcore", "sdi1"),
2784 REGULATOR_SUPPLY("vcore", "sdi2"),
2785 REGULATOR_SUPPLY("vcore", "sdi3"),
2786 REGULATOR_SUPPLY("vcore", "sdi4"),
2787 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2788 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2789 /* "v-uart" changed to "vcore" in the mainline kernel */
2790 REGULATOR_SUPPLY("vcore", "uart0"),
2791 REGULATOR_SUPPLY("vcore", "uart1"),
2792 REGULATOR_SUPPLY("vcore", "uart2"),
2793 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
Bengt Jonsson992b1332012-01-13 16:20:36 +01002794 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
Lee Jonesbc367482012-05-03 11:23:47 +01002795 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002796};
2797
2798static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002799 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2800 /* AV8100 regulator */
2801 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2802};
2803
2804static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002805 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002806 REGULATOR_SUPPLY("vsupply", "mcde"),
2807};
2808
2809/* SVA MMDSP regulator switch */
2810static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2811 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2812};
2813
2814/* SVA pipe regulator switch */
2815static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2816 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2817};
2818
2819/* SIA MMDSP regulator switch */
2820static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2821 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2822};
2823
2824/* SIA pipe regulator switch */
2825static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2826 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2827};
2828
2829static struct regulator_consumer_supply db8500_sga_consumers[] = {
2830 REGULATOR_SUPPLY("v-mali", NULL),
2831};
2832
2833/* ESRAM1 and 2 regulator switch */
2834static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2835 REGULATOR_SUPPLY("esram12", "cm_control"),
2836};
2837
2838/* ESRAM3 and 4 regulator switch */
2839static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2840 REGULATOR_SUPPLY("v-esram34", "mcde"),
2841 REGULATOR_SUPPLY("esram34", "cm_control"),
Bengt Jonsson992b1332012-01-13 16:20:36 +01002842 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002843};
2844
2845static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2846 [DB8500_REGULATOR_VAPE] = {
2847 .constraints = {
2848 .name = "db8500-vape",
2849 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
Mark Brown1e458602012-04-13 13:11:50 +01002850 .always_on = true,
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002851 },
2852 .consumer_supplies = db8500_vape_consumers,
2853 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2854 },
2855 [DB8500_REGULATOR_VARM] = {
2856 .constraints = {
2857 .name = "db8500-varm",
2858 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2859 },
2860 },
2861 [DB8500_REGULATOR_VMODEM] = {
2862 .constraints = {
2863 .name = "db8500-vmodem",
2864 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2865 },
2866 },
2867 [DB8500_REGULATOR_VPLL] = {
2868 .constraints = {
2869 .name = "db8500-vpll",
2870 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2871 },
2872 },
2873 [DB8500_REGULATOR_VSMPS1] = {
2874 .constraints = {
2875 .name = "db8500-vsmps1",
2876 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2877 },
2878 },
2879 [DB8500_REGULATOR_VSMPS2] = {
2880 .constraints = {
2881 .name = "db8500-vsmps2",
2882 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2883 },
2884 .consumer_supplies = db8500_vsmps2_consumers,
2885 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2886 },
2887 [DB8500_REGULATOR_VSMPS3] = {
2888 .constraints = {
2889 .name = "db8500-vsmps3",
2890 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2891 },
2892 },
2893 [DB8500_REGULATOR_VRF1] = {
2894 .constraints = {
2895 .name = "db8500-vrf1",
2896 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2897 },
2898 },
2899 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002900 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002901 .constraints = {
2902 .name = "db8500-sva-mmdsp",
2903 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2904 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002905 .consumer_supplies = db8500_svammdsp_consumers,
2906 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002907 },
2908 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2909 .constraints = {
2910 /* "ret" means "retention" */
2911 .name = "db8500-sva-mmdsp-ret",
2912 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2913 },
2914 },
2915 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002916 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002917 .constraints = {
2918 .name = "db8500-sva-pipe",
2919 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002921 .consumer_supplies = db8500_svapipe_consumers,
2922 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002923 },
2924 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002925 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002926 .constraints = {
2927 .name = "db8500-sia-mmdsp",
2928 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2929 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002930 .consumer_supplies = db8500_siammdsp_consumers,
2931 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002932 },
2933 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2934 .constraints = {
2935 .name = "db8500-sia-mmdsp-ret",
2936 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2937 },
2938 },
2939 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002940 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002941 .constraints = {
2942 .name = "db8500-sia-pipe",
2943 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2944 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002945 .consumer_supplies = db8500_siapipe_consumers,
2946 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002947 },
2948 [DB8500_REGULATOR_SWITCH_SGA] = {
2949 .supply_regulator = "db8500-vape",
2950 .constraints = {
2951 .name = "db8500-sga",
2952 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2953 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002954 .consumer_supplies = db8500_sga_consumers,
2955 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2956
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002957 },
2958 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2959 .supply_regulator = "db8500-vape",
2960 .constraints = {
2961 .name = "db8500-b2r2-mcde",
2962 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2963 },
2964 .consumer_supplies = db8500_b2r2_mcde_consumers,
2965 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2966 },
2967 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002968 /*
2969 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2970 * no need to hold Vape
2971 */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002972 .constraints = {
2973 .name = "db8500-esram12",
2974 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2975 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002976 .consumer_supplies = db8500_esram12_consumers,
2977 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002978 },
2979 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2980 .constraints = {
2981 .name = "db8500-esram12-ret",
2982 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2983 },
2984 },
2985 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002986 /*
2987 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2988 * no need to hold Vape
2989 */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002990 .constraints = {
2991 .name = "db8500-esram34",
2992 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2993 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002994 .consumer_supplies = db8500_esram34_consumers,
2995 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002996 },
2997 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2998 .constraints = {
2999 .name = "db8500-esram34-ret",
3000 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3001 },
3002 },
3003};
3004
Lee Jones6d11d132012-06-29 17:13:35 +02003005static struct resource ab8500_resources[] = {
3006 [0] = {
3007 .start = IRQ_DB8500_AB8500,
3008 .end = IRQ_DB8500_AB8500,
3009 .flags = IORESOURCE_IRQ
3010 }
3011};
3012
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003013static struct mfd_cell db8500_prcmu_devs[] = {
3014 {
3015 .name = "db8500-prcmu-regulators",
Lee Jones5d903222012-06-20 13:56:41 +01003016 .of_compatible = "stericsson,db8500-prcmu-regulator",
Mattias Wallin1ed78912011-05-27 11:49:43 +02003017 .platform_data = &db8500_regulators,
3018 .pdata_size = sizeof(db8500_regulators),
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003019 },
3020 {
3021 .name = "cpufreq-u8500",
Lee Jones5d903222012-06-20 13:56:41 +01003022 .of_compatible = "stericsson,cpufreq-u8500",
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003023 },
Lee Jones6d11d132012-06-29 17:13:35 +02003024 {
3025 .name = "ab8500-core",
3026 .of_compatible = "stericsson,ab8500",
3027 .num_resources = ARRAY_SIZE(ab8500_resources),
3028 .resources = ab8500_resources,
3029 .id = AB8500_VERSION_AB8500,
3030 },
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003031};
3032
3033/**
3034 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3035 *
3036 */
Lee Jones9fc63f62012-04-19 21:36:41 +01003037static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003038{
Lee Jones3a8e39c2012-07-06 12:46:23 +02003039 struct ab8500_platform_data *ab8500_platdata = pdev->dev.platform_data;
Lee Jonesca7edd12012-05-09 17:19:25 +02003040 struct device_node *np = pdev->dev.of_node;
Lee Jones3a8e39c2012-07-06 12:46:23 +02003041 int irq = 0, err = 0, i;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003042
3043 if (ux500_is_svp())
3044 return -ENODEV;
3045
Mattias Nilsson05089012012-01-13 16:20:20 +01003046 init_prcm_registers();
Mattias Nilssond65e12d2011-08-12 10:27:50 +02003047
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003048 /* Clean up the mailbox interrupts after pre-kernel code. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02003049 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003050
Lee Jonesca7edd12012-05-09 17:19:25 +02003051 if (np)
3052 irq = platform_get_irq(pdev, 0);
3053
3054 if (!np || irq <= 0)
3055 irq = IRQ_DB8500_PRCMU1;
3056
3057 err = request_threaded_irq(irq, prcmu_irq_handler,
3058 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003059 if (err < 0) {
3060 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3061 err = -EBUSY;
3062 goto no_irq_return;
3063 }
3064
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01003065 db8500_irq_init(np);
3066
Lee Jones3a8e39c2012-07-06 12:46:23 +02003067 for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
3068 if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
3069 db8500_prcmu_devs[i].platform_data = ab8500_platdata;
Lee Jones3c1534c2012-07-27 13:38:50 +01003070 db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
Lee Jones3a8e39c2012-07-06 12:46:23 +02003071 }
3072 }
3073
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003074 if (cpu_is_u8500v20_or_later())
3075 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3076
Lee Jones5d903222012-06-20 13:56:41 +01003077 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
Mark Brown0848c942012-09-11 15:16:36 +08003078 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL);
Lee Jones5d903222012-06-20 13:56:41 +01003079 if (err) {
3080 pr_err("prcmu: Failed to add subdevices\n");
3081 return err;
Lee Jonesca7edd12012-05-09 17:19:25 +02003082 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003083
Lee Jonesca7edd12012-05-09 17:19:25 +02003084 pr_info("DB8500 PRCMU initialized\n");
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003085
3086no_irq_return:
3087 return err;
3088}
Lee Jones3c144762012-06-29 15:41:38 +02003089static const struct of_device_id db8500_prcmu_match[] = {
3090 { .compatible = "stericsson,db8500-prcmu"},
3091 { },
3092};
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003093
3094static struct platform_driver db8500_prcmu_driver = {
3095 .driver = {
3096 .name = "db8500-prcmu",
3097 .owner = THIS_MODULE,
Lee Jones3c144762012-06-29 15:41:38 +02003098 .of_match_table = db8500_prcmu_match,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003099 },
Lee Jones9fc63f62012-04-19 21:36:41 +01003100 .probe = db8500_prcmu_probe,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003101};
3102
3103static int __init db8500_prcmu_init(void)
3104{
Lee Jones9fc63f62012-04-19 21:36:41 +01003105 return platform_driver_register(&db8500_prcmu_driver);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003106}
3107
Lee Jonesa661aca2012-06-11 16:24:59 +01003108core_initcall(db8500_prcmu_init);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003109
3110MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3111MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3112MODULE_LICENSE("GPL v2");