blob: dc25bee8d33f1d6f93deea0030712a681579b1d0 [file] [log] [blame]
Stephen Streete0c99052006-03-07 23:53:24 -08001/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/ioport.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
Sebastian Andrzej Siewior8348c252010-11-22 17:12:15 -080026#include <linux/spi/pxa2xx_spi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080027#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/workqueue.h>
Stephen Streete0c99052006-03-07 23:53:24 -080030#include <linux/delay.h>
Eric Miaoa7bb3902009-04-06 19:00:54 -070031#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Stephen Streete0c99052006-03-07 23:53:24 -080033
34#include <asm/io.h>
35#include <asm/irq.h>
Stephen Streete0c99052006-03-07 23:53:24 -080036#include <asm/delay.h>
Stephen Streete0c99052006-03-07 23:53:24 -080037
Stephen Streete0c99052006-03-07 23:53:24 -080038
39MODULE_AUTHOR("Stephen Street");
Will Newton037cdaf2007-12-10 15:49:25 -080040MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
Stephen Streete0c99052006-03-07 23:53:24 -080041MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -070042MODULE_ALIAS("platform:pxa2xx-spi");
Stephen Streete0c99052006-03-07 23:53:24 -080043
44#define MAX_BUSES 3
45
Vernon Sauderf1f640a2008-10-15 22:02:43 -070046#define TIMOUT_DFLT 1000
47
Ned Forrester7e964452008-09-13 02:33:18 -070048#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
Mike Rapoport20b918d2008-10-01 10:39:24 -070050#define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
Ned Forrester7e964452008-09-13 02:33:18 -070051#define MAX_DMA_LEN 8191
Mike Rapoport7ad0ba92009-04-06 19:00:57 -070052#define DMA_ALIGNMENT 8
Stephen Streete0c99052006-03-07 23:53:24 -080053
Ned Forresterb97c74b2008-02-23 15:23:40 -080054/*
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
60 */
61#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
Stephen Street8d94cc52006-12-10 02:18:54 -080062 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
Ned Forresterb97c74b2008-02-23 15:23:40 -080063 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
Stephen Street8d94cc52006-12-10 02:18:54 -080067
Stephen Streete0c99052006-03-07 23:53:24 -080068#define DEFINE_SSP_REG(reg, off) \
David Brownellcf433692008-04-28 02:14:17 -070069static inline u32 read_##reg(void const __iomem *p) \
70{ return __raw_readl(p + (off)); } \
71\
72static inline void write_##reg(u32 v, void __iomem *p) \
73{ __raw_writel(v, p + (off)); }
Stephen Streete0c99052006-03-07 23:53:24 -080074
75DEFINE_SSP_REG(SSCR0, 0x00)
76DEFINE_SSP_REG(SSCR1, 0x04)
77DEFINE_SSP_REG(SSSR, 0x08)
78DEFINE_SSP_REG(SSITR, 0x0c)
79DEFINE_SSP_REG(SSDR, 0x10)
80DEFINE_SSP_REG(SSTO, 0x28)
81DEFINE_SSP_REG(SSPSP, 0x2c)
82
83#define START_STATE ((void*)0)
84#define RUNNING_STATE ((void*)1)
85#define DONE_STATE ((void*)2)
86#define ERROR_STATE ((void*)-1)
87
88#define QUEUE_RUNNING 0
89#define QUEUE_STOPPED 1
90
91struct driver_data {
92 /* Driver model hookup */
93 struct platform_device *pdev;
94
eric miao2f1a74e2007-11-21 18:50:53 +080095 /* SSP Info */
96 struct ssp_device *ssp;
97
Stephen Streete0c99052006-03-07 23:53:24 -080098 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type;
100 struct spi_master *master;
101
102 /* PXA hookup */
103 struct pxa2xx_spi_master *master_info;
104
105 /* DMA setup stuff */
106 int rx_channel;
107 int tx_channel;
108 u32 *null_dma_buf;
109
110 /* SSP register addresses */
David Brownellcf433692008-04-28 02:14:17 -0700111 void __iomem *ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800112 u32 ssdr_physical;
113
114 /* SSP masks*/
115 u32 dma_cr1;
116 u32 int_cr1;
117 u32 clear_sr;
118 u32 mask_sr;
119
120 /* Driver message queue */
121 struct workqueue_struct *workqueue;
122 struct work_struct pump_messages;
123 spinlock_t lock;
124 struct list_head queue;
125 int busy;
126 int run;
127
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers;
130
131 /* Current message transfer state info */
132 struct spi_message* cur_msg;
133 struct spi_transfer* cur_transfer;
134 struct chip_data *cur_chip;
135 size_t len;
136 void *tx;
137 void *tx_end;
138 void *rx;
139 void *rx_end;
140 int dma_mapped;
141 dma_addr_t rx_dma;
142 dma_addr_t tx_dma;
143 size_t rx_map_len;
144 size_t tx_map_len;
Stephen Street9708c122006-03-28 14:05:23 -0800145 u8 n_bytes;
146 u32 dma_width;
Stephen Street8d94cc52006-12-10 02:18:54 -0800147 int (*write)(struct driver_data *drv_data);
148 int (*read)(struct driver_data *drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800149 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
150 void (*cs_control)(u32 command);
151};
152
153struct chip_data {
154 u32 cr0;
155 u32 cr1;
Stephen Streete0c99052006-03-07 23:53:24 -0800156 u32 psp;
157 u32 timeout;
158 u8 n_bytes;
159 u32 dma_width;
160 u32 dma_burst_size;
161 u32 threshold;
162 u32 dma_threshold;
163 u8 enable_dma;
Stephen Street9708c122006-03-28 14:05:23 -0800164 u8 bits_per_word;
165 u32 speed_hz;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800166 union {
167 int gpio_cs;
168 unsigned int frm;
169 };
Eric Miaoa7bb3902009-04-06 19:00:54 -0700170 int gpio_cs_inverted;
Stephen Street8d94cc52006-12-10 02:18:54 -0800171 int (*write)(struct driver_data *drv_data);
172 int (*read)(struct driver_data *drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800173 void (*cs_control)(u32 command);
174};
175
David Howells6d5aefb2006-12-05 19:36:26 +0000176static void pump_messages(struct work_struct *work);
Stephen Streete0c99052006-03-07 23:53:24 -0800177
Eric Miaoa7bb3902009-04-06 19:00:54 -0700178static void cs_assert(struct driver_data *drv_data)
179{
180 struct chip_data *chip = drv_data->cur_chip;
181
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800182 if (drv_data->ssp_type == CE4100_SSP) {
183 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
184 return;
185 }
186
Eric Miaoa7bb3902009-04-06 19:00:54 -0700187 if (chip->cs_control) {
188 chip->cs_control(PXA2XX_CS_ASSERT);
189 return;
190 }
191
192 if (gpio_is_valid(chip->gpio_cs))
193 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
194}
195
196static void cs_deassert(struct driver_data *drv_data)
197{
198 struct chip_data *chip = drv_data->cur_chip;
199
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800200 if (drv_data->ssp_type == CE4100_SSP)
201 return;
202
Eric Miaoa7bb3902009-04-06 19:00:54 -0700203 if (chip->cs_control) {
Daniel Ribeiro2b2562d2009-04-08 22:48:03 -0300204 chip->cs_control(PXA2XX_CS_DEASSERT);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700205 return;
206 }
207
208 if (gpio_is_valid(chip->gpio_cs))
209 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
210}
211
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800212static void write_SSSR_CS(struct driver_data *drv_data, u32 val)
213{
214 void __iomem *reg = drv_data->ioaddr;
215
216 if (drv_data->ssp_type == CE4100_SSP)
217 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
218
219 write_SSSR(val, reg);
220}
221
222static int pxa25x_ssp_comp(struct driver_data *drv_data)
223{
224 if (drv_data->ssp_type == PXA25x_SSP)
225 return 1;
226 if (drv_data->ssp_type == CE4100_SSP)
227 return 1;
228 return 0;
229}
230
Stephen Streete0c99052006-03-07 23:53:24 -0800231static int flush(struct driver_data *drv_data)
232{
233 unsigned long limit = loops_per_jiffy << 1;
234
David Brownellcf433692008-04-28 02:14:17 -0700235 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800236
237 do {
238 while (read_SSSR(reg) & SSSR_RNE) {
239 read_SSDR(reg);
240 }
Roel Kluin306c68a2009-04-21 12:24:46 -0700241 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800242 write_SSSR_CS(drv_data, SSSR_ROR);
Stephen Streete0c99052006-03-07 23:53:24 -0800243
244 return limit;
245}
246
Stephen Street8d94cc52006-12-10 02:18:54 -0800247static int null_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800248{
David Brownellcf433692008-04-28 02:14:17 -0700249 void __iomem *reg = drv_data->ioaddr;
Stephen Street9708c122006-03-28 14:05:23 -0800250 u8 n_bytes = drv_data->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800251
Sebastian Andrzej Siewior4a256052010-11-22 17:12:15 -0800252 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
Stephen Street8d94cc52006-12-10 02:18:54 -0800253 || (drv_data->tx == drv_data->tx_end))
254 return 0;
255
256 write_SSDR(0, reg);
257 drv_data->tx += n_bytes;
258
259 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800260}
261
Stephen Street8d94cc52006-12-10 02:18:54 -0800262static int null_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800263{
David Brownellcf433692008-04-28 02:14:17 -0700264 void __iomem *reg = drv_data->ioaddr;
Stephen Street9708c122006-03-28 14:05:23 -0800265 u8 n_bytes = drv_data->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800266
267 while ((read_SSSR(reg) & SSSR_RNE)
Stephen Street8d94cc52006-12-10 02:18:54 -0800268 && (drv_data->rx < drv_data->rx_end)) {
Stephen Streete0c99052006-03-07 23:53:24 -0800269 read_SSDR(reg);
270 drv_data->rx += n_bytes;
271 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800272
273 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800274}
275
Stephen Street8d94cc52006-12-10 02:18:54 -0800276static int u8_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800277{
David Brownellcf433692008-04-28 02:14:17 -0700278 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800279
Sebastian Andrzej Siewior4a256052010-11-22 17:12:15 -0800280 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
Stephen Street8d94cc52006-12-10 02:18:54 -0800281 || (drv_data->tx == drv_data->tx_end))
282 return 0;
283
284 write_SSDR(*(u8 *)(drv_data->tx), reg);
285 ++drv_data->tx;
286
287 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800288}
289
Stephen Street8d94cc52006-12-10 02:18:54 -0800290static int u8_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800291{
David Brownellcf433692008-04-28 02:14:17 -0700292 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800293
294 while ((read_SSSR(reg) & SSSR_RNE)
Stephen Street8d94cc52006-12-10 02:18:54 -0800295 && (drv_data->rx < drv_data->rx_end)) {
Stephen Streete0c99052006-03-07 23:53:24 -0800296 *(u8 *)(drv_data->rx) = read_SSDR(reg);
297 ++drv_data->rx;
298 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800299
300 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800301}
302
Stephen Street8d94cc52006-12-10 02:18:54 -0800303static int u16_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800304{
David Brownellcf433692008-04-28 02:14:17 -0700305 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800306
Sebastian Andrzej Siewior4a256052010-11-22 17:12:15 -0800307 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
Stephen Street8d94cc52006-12-10 02:18:54 -0800308 || (drv_data->tx == drv_data->tx_end))
309 return 0;
310
311 write_SSDR(*(u16 *)(drv_data->tx), reg);
312 drv_data->tx += 2;
313
314 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800315}
316
Stephen Street8d94cc52006-12-10 02:18:54 -0800317static int u16_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800318{
David Brownellcf433692008-04-28 02:14:17 -0700319 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800320
321 while ((read_SSSR(reg) & SSSR_RNE)
Stephen Street8d94cc52006-12-10 02:18:54 -0800322 && (drv_data->rx < drv_data->rx_end)) {
Stephen Streete0c99052006-03-07 23:53:24 -0800323 *(u16 *)(drv_data->rx) = read_SSDR(reg);
324 drv_data->rx += 2;
325 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800326
327 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800328}
Stephen Street8d94cc52006-12-10 02:18:54 -0800329
330static int u32_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800331{
David Brownellcf433692008-04-28 02:14:17 -0700332 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800333
Sebastian Andrzej Siewior4a256052010-11-22 17:12:15 -0800334 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
Stephen Street8d94cc52006-12-10 02:18:54 -0800335 || (drv_data->tx == drv_data->tx_end))
336 return 0;
337
338 write_SSDR(*(u32 *)(drv_data->tx), reg);
339 drv_data->tx += 4;
340
341 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800342}
343
Stephen Street8d94cc52006-12-10 02:18:54 -0800344static int u32_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800345{
David Brownellcf433692008-04-28 02:14:17 -0700346 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800347
348 while ((read_SSSR(reg) & SSSR_RNE)
Stephen Street8d94cc52006-12-10 02:18:54 -0800349 && (drv_data->rx < drv_data->rx_end)) {
Stephen Streete0c99052006-03-07 23:53:24 -0800350 *(u32 *)(drv_data->rx) = read_SSDR(reg);
351 drv_data->rx += 4;
352 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800353
354 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800355}
356
357static void *next_transfer(struct driver_data *drv_data)
358{
359 struct spi_message *msg = drv_data->cur_msg;
360 struct spi_transfer *trans = drv_data->cur_transfer;
361
362 /* Move to next transfer */
363 if (trans->transfer_list.next != &msg->transfers) {
364 drv_data->cur_transfer =
365 list_entry(trans->transfer_list.next,
366 struct spi_transfer,
367 transfer_list);
368 return RUNNING_STATE;
369 } else
370 return DONE_STATE;
371}
372
373static int map_dma_buffers(struct driver_data *drv_data)
374{
375 struct spi_message *msg = drv_data->cur_msg;
376 struct device *dev = &msg->spi->dev;
377
378 if (!drv_data->cur_chip->enable_dma)
379 return 0;
380
381 if (msg->is_dma_mapped)
382 return drv_data->rx_dma && drv_data->tx_dma;
383
384 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
385 return 0;
386
387 /* Modify setup if rx buffer is null */
388 if (drv_data->rx == NULL) {
389 *drv_data->null_dma_buf = 0;
390 drv_data->rx = drv_data->null_dma_buf;
391 drv_data->rx_map_len = 4;
392 } else
393 drv_data->rx_map_len = drv_data->len;
394
395
396 /* Modify setup if tx buffer is null */
397 if (drv_data->tx == NULL) {
398 *drv_data->null_dma_buf = 0;
399 drv_data->tx = drv_data->null_dma_buf;
400 drv_data->tx_map_len = 4;
401 } else
402 drv_data->tx_map_len = drv_data->len;
403
Ned Forrester393df742008-11-19 15:36:21 -0800404 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
405 * so we flush the cache *before* invalidating it, in case
406 * the tx and rx buffers overlap.
407 */
408 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
409 drv_data->tx_map_len, DMA_TO_DEVICE);
410 if (dma_mapping_error(dev, drv_data->tx_dma))
Stephen Streete0c99052006-03-07 23:53:24 -0800411 return 0;
412
Ned Forrester393df742008-11-19 15:36:21 -0800413 /* Stream map the rx buffer */
414 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
Stephen Streete0c99052006-03-07 23:53:24 -0800415 drv_data->rx_map_len, DMA_FROM_DEVICE);
Ned Forrester393df742008-11-19 15:36:21 -0800416 if (dma_mapping_error(dev, drv_data->rx_dma)) {
417 dma_unmap_single(dev, drv_data->tx_dma,
418 drv_data->tx_map_len, DMA_TO_DEVICE);
Stephen Streete0c99052006-03-07 23:53:24 -0800419 return 0;
420 }
421
422 return 1;
423}
424
425static void unmap_dma_buffers(struct driver_data *drv_data)
426{
427 struct device *dev;
428
429 if (!drv_data->dma_mapped)
430 return;
431
432 if (!drv_data->cur_msg->is_dma_mapped) {
433 dev = &drv_data->cur_msg->spi->dev;
434 dma_unmap_single(dev, drv_data->rx_dma,
435 drv_data->rx_map_len, DMA_FROM_DEVICE);
436 dma_unmap_single(dev, drv_data->tx_dma,
437 drv_data->tx_map_len, DMA_TO_DEVICE);
438 }
439
440 drv_data->dma_mapped = 0;
441}
442
443/* caller already set message->status; dma and pio irqs are blocked */
Stephen Street5daa3ba2006-05-20 15:00:19 -0700444static void giveback(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800445{
446 struct spi_transfer* last_transfer;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700447 unsigned long flags;
448 struct spi_message *msg;
Stephen Streete0c99052006-03-07 23:53:24 -0800449
Stephen Street5daa3ba2006-05-20 15:00:19 -0700450 spin_lock_irqsave(&drv_data->lock, flags);
451 msg = drv_data->cur_msg;
452 drv_data->cur_msg = NULL;
453 drv_data->cur_transfer = NULL;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700454 queue_work(drv_data->workqueue, &drv_data->pump_messages);
455 spin_unlock_irqrestore(&drv_data->lock, flags);
456
457 last_transfer = list_entry(msg->transfers.prev,
Stephen Streete0c99052006-03-07 23:53:24 -0800458 struct spi_transfer,
459 transfer_list);
460
Ned Forrester84235972008-09-13 02:33:17 -0700461 /* Delay if requested before any change in chip select */
462 if (last_transfer->delay_usecs)
463 udelay(last_transfer->delay_usecs);
464
465 /* Drop chip select UNLESS cs_change is true or we are returning
466 * a message with an error, or next message is for another chip
467 */
Stephen Streete0c99052006-03-07 23:53:24 -0800468 if (!last_transfer->cs_change)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700469 cs_deassert(drv_data);
Ned Forrester84235972008-09-13 02:33:17 -0700470 else {
471 struct spi_message *next_msg;
472
473 /* Holding of cs was hinted, but we need to make sure
474 * the next message is for the same chip. Don't waste
475 * time with the following tests unless this was hinted.
476 *
477 * We cannot postpone this until pump_messages, because
478 * after calling msg->complete (below) the driver that
479 * sent the current message could be unloaded, which
480 * could invalidate the cs_control() callback...
481 */
482
483 /* get a pointer to the next message, if any */
484 spin_lock_irqsave(&drv_data->lock, flags);
485 if (list_empty(&drv_data->queue))
486 next_msg = NULL;
487 else
488 next_msg = list_entry(drv_data->queue.next,
489 struct spi_message, queue);
490 spin_unlock_irqrestore(&drv_data->lock, flags);
491
492 /* see if the next and current messages point
493 * to the same chip
494 */
495 if (next_msg && next_msg->spi != msg->spi)
496 next_msg = NULL;
497 if (!next_msg || msg->state == ERROR_STATE)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700498 cs_deassert(drv_data);
Ned Forrester84235972008-09-13 02:33:17 -0700499 }
Stephen Streete0c99052006-03-07 23:53:24 -0800500
Stephen Street5daa3ba2006-05-20 15:00:19 -0700501 msg->state = NULL;
502 if (msg->complete)
503 msg->complete(msg->context);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700504
505 drv_data->cur_chip = NULL;
Stephen Streete0c99052006-03-07 23:53:24 -0800506}
507
David Brownellcf433692008-04-28 02:14:17 -0700508static int wait_ssp_rx_stall(void const __iomem *ioaddr)
Stephen Streete0c99052006-03-07 23:53:24 -0800509{
510 unsigned long limit = loops_per_jiffy << 1;
511
Roel Kluin306c68a2009-04-21 12:24:46 -0700512 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
Stephen Streete0c99052006-03-07 23:53:24 -0800513 cpu_relax();
514
515 return limit;
516}
517
518static int wait_dma_channel_stop(int channel)
519{
520 unsigned long limit = loops_per_jiffy << 1;
521
Roel Kluin306c68a2009-04-21 12:24:46 -0700522 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
Stephen Streete0c99052006-03-07 23:53:24 -0800523 cpu_relax();
524
525 return limit;
526}
527
David Brownellcf433692008-04-28 02:14:17 -0700528static void dma_error_stop(struct driver_data *drv_data, const char *msg)
Stephen Street8d94cc52006-12-10 02:18:54 -0800529{
David Brownellcf433692008-04-28 02:14:17 -0700530 void __iomem *reg = drv_data->ioaddr;
Stephen Street8d94cc52006-12-10 02:18:54 -0800531
532 /* Stop and reset */
533 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
534 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800535 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street8d94cc52006-12-10 02:18:54 -0800536 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800537 if (!pxa25x_ssp_comp(drv_data))
Stephen Street8d94cc52006-12-10 02:18:54 -0800538 write_SSTO(0, reg);
539 flush(drv_data);
540 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
541
542 unmap_dma_buffers(drv_data);
543
544 dev_err(&drv_data->pdev->dev, "%s\n", msg);
545
546 drv_data->cur_msg->state = ERROR_STATE;
547 tasklet_schedule(&drv_data->pump_transfers);
548}
549
550static void dma_transfer_complete(struct driver_data *drv_data)
551{
David Brownellcf433692008-04-28 02:14:17 -0700552 void __iomem *reg = drv_data->ioaddr;
Stephen Street8d94cc52006-12-10 02:18:54 -0800553 struct spi_message *msg = drv_data->cur_msg;
554
555 /* Clear and disable interrupts on SSP and DMA channels*/
556 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800557 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street8d94cc52006-12-10 02:18:54 -0800558 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
559 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
560
561 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
562 dev_err(&drv_data->pdev->dev,
563 "dma_handler: dma rx channel stop failed\n");
564
565 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
566 dev_err(&drv_data->pdev->dev,
567 "dma_transfer: ssp rx stall failed\n");
568
569 unmap_dma_buffers(drv_data);
570
571 /* update the buffer pointer for the amount completed in dma */
572 drv_data->rx += drv_data->len -
573 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
574
575 /* read trailing data from fifo, it does not matter how many
576 * bytes are in the fifo just read until buffer is full
577 * or fifo is empty, which ever occurs first */
578 drv_data->read(drv_data);
579
580 /* return count of what was actually read */
581 msg->actual_length += drv_data->len -
582 (drv_data->rx_end - drv_data->rx);
583
Ned Forrester84235972008-09-13 02:33:17 -0700584 /* Transfer delays and chip select release are
585 * handled in pump_transfers or giveback
586 */
Stephen Street8d94cc52006-12-10 02:18:54 -0800587
588 /* Move to next transfer */
589 msg->state = next_transfer(drv_data);
590
591 /* Schedule transfer tasklet */
592 tasklet_schedule(&drv_data->pump_transfers);
593}
594
David Howells7d12e782006-10-05 14:55:46 +0100595static void dma_handler(int channel, void *data)
Stephen Streete0c99052006-03-07 23:53:24 -0800596{
597 struct driver_data *drv_data = data;
Stephen Streete0c99052006-03-07 23:53:24 -0800598 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
Stephen Streete0c99052006-03-07 23:53:24 -0800599
600 if (irq_status & DCSR_BUSERR) {
601
Stephen Streete0c99052006-03-07 23:53:24 -0800602 if (channel == drv_data->tx_channel)
Stephen Street8d94cc52006-12-10 02:18:54 -0800603 dma_error_stop(drv_data,
604 "dma_handler: "
605 "bad bus address on tx channel");
Stephen Streete0c99052006-03-07 23:53:24 -0800606 else
Stephen Street8d94cc52006-12-10 02:18:54 -0800607 dma_error_stop(drv_data,
608 "dma_handler: "
609 "bad bus address on rx channel");
610 return;
Stephen Streete0c99052006-03-07 23:53:24 -0800611 }
612
613 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
Stephen Street8d94cc52006-12-10 02:18:54 -0800614 if ((channel == drv_data->tx_channel)
615 && (irq_status & DCSR_ENDINTR)
616 && (drv_data->ssp_type == PXA25x_SSP)) {
Stephen Streete0c99052006-03-07 23:53:24 -0800617
618 /* Wait for rx to stall */
619 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
620 dev_err(&drv_data->pdev->dev,
621 "dma_handler: ssp rx stall failed\n");
622
Stephen Street8d94cc52006-12-10 02:18:54 -0800623 /* finish this transfer, start the next */
624 dma_transfer_complete(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800625 }
626}
627
628static irqreturn_t dma_transfer(struct driver_data *drv_data)
629{
630 u32 irq_status;
David Brownellcf433692008-04-28 02:14:17 -0700631 void __iomem *reg = drv_data->ioaddr;
Stephen Streete0c99052006-03-07 23:53:24 -0800632
633 irq_status = read_SSSR(reg) & drv_data->mask_sr;
634 if (irq_status & SSSR_ROR) {
Stephen Street8d94cc52006-12-10 02:18:54 -0800635 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
Stephen Streete0c99052006-03-07 23:53:24 -0800636 return IRQ_HANDLED;
637 }
638
639 /* Check for false positive timeout */
Stephen Street8d94cc52006-12-10 02:18:54 -0800640 if ((irq_status & SSSR_TINT)
641 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
Stephen Streete0c99052006-03-07 23:53:24 -0800642 write_SSSR(SSSR_TINT, reg);
643 return IRQ_HANDLED;
644 }
645
646 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
647
Stephen Street8d94cc52006-12-10 02:18:54 -0800648 /* Clear and disable timeout interrupt, do the rest in
649 * dma_transfer_complete */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800650 if (!pxa25x_ssp_comp(drv_data))
Stephen Streete0c99052006-03-07 23:53:24 -0800651 write_SSTO(0, reg);
Stephen Streete0c99052006-03-07 23:53:24 -0800652
Stephen Street8d94cc52006-12-10 02:18:54 -0800653 /* finish this transfer, start the next */
654 dma_transfer_complete(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800655
656 return IRQ_HANDLED;
657 }
658
659 /* Opps problem detected */
660 return IRQ_NONE;
661}
662
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800663static void reset_sccr1(struct driver_data *drv_data)
664{
665 void __iomem *reg = drv_data->ioaddr;
666 struct chip_data *chip = drv_data->cur_chip;
667 u32 sccr1_reg;
668
669 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
670 sccr1_reg &= ~SSCR1_RFT;
671 sccr1_reg |= chip->threshold;
672 write_SSCR1(sccr1_reg, reg);
673}
674
Stephen Street8d94cc52006-12-10 02:18:54 -0800675static void int_error_stop(struct driver_data *drv_data, const char* msg)
676{
David Brownellcf433692008-04-28 02:14:17 -0700677 void __iomem *reg = drv_data->ioaddr;
Stephen Street8d94cc52006-12-10 02:18:54 -0800678
679 /* Stop and reset SSP */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800680 write_SSSR_CS(drv_data, drv_data->clear_sr);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800681 reset_sccr1(drv_data);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800682 if (!pxa25x_ssp_comp(drv_data))
Stephen Street8d94cc52006-12-10 02:18:54 -0800683 write_SSTO(0, reg);
684 flush(drv_data);
685 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
686
687 dev_err(&drv_data->pdev->dev, "%s\n", msg);
688
689 drv_data->cur_msg->state = ERROR_STATE;
690 tasklet_schedule(&drv_data->pump_transfers);
691}
692
693static void int_transfer_complete(struct driver_data *drv_data)
694{
David Brownellcf433692008-04-28 02:14:17 -0700695 void __iomem *reg = drv_data->ioaddr;
Stephen Street8d94cc52006-12-10 02:18:54 -0800696
697 /* Stop SSP */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800698 write_SSSR_CS(drv_data, drv_data->clear_sr);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800699 reset_sccr1(drv_data);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800700 if (!pxa25x_ssp_comp(drv_data))
Stephen Street8d94cc52006-12-10 02:18:54 -0800701 write_SSTO(0, reg);
702
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300703 /* Update total byte transferred return count actual bytes read */
Stephen Street8d94cc52006-12-10 02:18:54 -0800704 drv_data->cur_msg->actual_length += drv_data->len -
705 (drv_data->rx_end - drv_data->rx);
706
Ned Forrester84235972008-09-13 02:33:17 -0700707 /* Transfer delays and chip select release are
708 * handled in pump_transfers or giveback
709 */
Stephen Street8d94cc52006-12-10 02:18:54 -0800710
711 /* Move to next transfer */
712 drv_data->cur_msg->state = next_transfer(drv_data);
713
714 /* Schedule transfer tasklet */
715 tasklet_schedule(&drv_data->pump_transfers);
716}
717
Stephen Streete0c99052006-03-07 23:53:24 -0800718static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
719{
David Brownellcf433692008-04-28 02:14:17 -0700720 void __iomem *reg = drv_data->ioaddr;
Stephen Street8d94cc52006-12-10 02:18:54 -0800721
Stephen Street5daa3ba2006-05-20 15:00:19 -0700722 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
723 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
Stephen Streete0c99052006-03-07 23:53:24 -0800724
Stephen Street8d94cc52006-12-10 02:18:54 -0800725 u32 irq_status = read_SSSR(reg) & irq_mask;
Stephen Streete0c99052006-03-07 23:53:24 -0800726
Stephen Street8d94cc52006-12-10 02:18:54 -0800727 if (irq_status & SSSR_ROR) {
728 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
729 return IRQ_HANDLED;
730 }
Stephen Streete0c99052006-03-07 23:53:24 -0800731
Stephen Street8d94cc52006-12-10 02:18:54 -0800732 if (irq_status & SSSR_TINT) {
733 write_SSSR(SSSR_TINT, reg);
734 if (drv_data->read(drv_data)) {
735 int_transfer_complete(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800736 return IRQ_HANDLED;
737 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800738 }
Stephen Streete0c99052006-03-07 23:53:24 -0800739
Stephen Street8d94cc52006-12-10 02:18:54 -0800740 /* Drain rx fifo, Fill tx fifo and prevent overruns */
741 do {
742 if (drv_data->read(drv_data)) {
743 int_transfer_complete(drv_data);
744 return IRQ_HANDLED;
Stephen Streete0c99052006-03-07 23:53:24 -0800745 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800746 } while (drv_data->write(drv_data));
Stephen Streete0c99052006-03-07 23:53:24 -0800747
Stephen Street8d94cc52006-12-10 02:18:54 -0800748 if (drv_data->read(drv_data)) {
749 int_transfer_complete(drv_data);
750 return IRQ_HANDLED;
751 }
Stephen Streete0c99052006-03-07 23:53:24 -0800752
Stephen Street8d94cc52006-12-10 02:18:54 -0800753 if (drv_data->tx == drv_data->tx_end) {
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800754 u32 bytes_left;
755 u32 sccr1_reg;
756
757 sccr1_reg = read_SSCR1(reg);
758 sccr1_reg &= ~SSCR1_TIE;
759
760 /*
761 * PXA25x_SSP has no timeout, set up rx threshould for the
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300762 * remaining RX bytes.
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800763 */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800764 if (pxa25x_ssp_comp(drv_data)) {
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800765
766 sccr1_reg &= ~SSCR1_RFT;
767
768 bytes_left = drv_data->rx_end - drv_data->rx;
769 switch (drv_data->n_bytes) {
770 case 4:
771 bytes_left >>= 1;
772 case 2:
773 bytes_left >>= 1;
Stephen Street8d94cc52006-12-10 02:18:54 -0800774 }
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800775
776 if (bytes_left > RX_THRESH_DFLT)
777 bytes_left = RX_THRESH_DFLT;
778
779 sccr1_reg |= SSCR1_RxTresh(bytes_left);
Stephen Streete0c99052006-03-07 23:53:24 -0800780 }
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800781 write_SSCR1(sccr1_reg, reg);
Stephen Streete0c99052006-03-07 23:53:24 -0800782 }
783
Stephen Street5daa3ba2006-05-20 15:00:19 -0700784 /* We did something */
785 return IRQ_HANDLED;
Stephen Streete0c99052006-03-07 23:53:24 -0800786}
787
David Howells7d12e782006-10-05 14:55:46 +0100788static irqreturn_t ssp_int(int irq, void *dev_id)
Stephen Streete0c99052006-03-07 23:53:24 -0800789{
Jeff Garzikc7bec5a2006-10-06 15:00:58 -0400790 struct driver_data *drv_data = dev_id;
David Brownellcf433692008-04-28 02:14:17 -0700791 void __iomem *reg = drv_data->ioaddr;
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -0800792 u32 sccr1_reg = read_SSCR1(reg);
793 u32 mask = drv_data->mask_sr;
794 u32 status;
795
796 status = read_SSSR(reg);
797
798 /* Ignore possible writes if we don't need to write */
799 if (!(sccr1_reg & SSCR1_TIE))
800 mask &= ~SSSR_TFS;
801
802 if (!(status & mask))
803 return IRQ_NONE;
Stephen Streete0c99052006-03-07 23:53:24 -0800804
805 if (!drv_data->cur_msg) {
Stephen Street5daa3ba2006-05-20 15:00:19 -0700806
807 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
808 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800809 if (!pxa25x_ssp_comp(drv_data))
Stephen Street5daa3ba2006-05-20 15:00:19 -0700810 write_SSTO(0, reg);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800811 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street5daa3ba2006-05-20 15:00:19 -0700812
Stephen Streete0c99052006-03-07 23:53:24 -0800813 dev_err(&drv_data->pdev->dev, "bad message state "
Stephen Street8d94cc52006-12-10 02:18:54 -0800814 "in interrupt handler\n");
Stephen Street5daa3ba2006-05-20 15:00:19 -0700815
Stephen Streete0c99052006-03-07 23:53:24 -0800816 /* Never fail */
817 return IRQ_HANDLED;
818 }
819
820 return drv_data->transfer_handler(drv_data);
821}
822
David Brownellcf433692008-04-28 02:14:17 -0700823static int set_dma_burst_and_threshold(struct chip_data *chip,
824 struct spi_device *spi,
Stephen Street8d94cc52006-12-10 02:18:54 -0800825 u8 bits_per_word, u32 *burst_code,
826 u32 *threshold)
827{
828 struct pxa2xx_spi_chip *chip_info =
829 (struct pxa2xx_spi_chip *)spi->controller_data;
830 int bytes_per_word;
831 int burst_bytes;
832 int thresh_words;
833 int req_burst_size;
834 int retval = 0;
835
836 /* Set the threshold (in registers) to equal the same amount of data
837 * as represented by burst size (in bytes). The computation below
838 * is (burst_size rounded up to nearest 8 byte, word or long word)
839 * divided by (bytes/register); the tx threshold is the inverse of
840 * the rx, so that there will always be enough data in the rx fifo
841 * to satisfy a burst, and there will always be enough space in the
842 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
843 * there is not enough space), there must always remain enough empty
844 * space in the rx fifo for any data loaded to the tx fifo.
845 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
846 * will be 8, or half the fifo;
847 * The threshold can only be set to 2, 4 or 8, but not 16, because
848 * to burst 16 to the tx fifo, the fifo would have to be empty;
849 * however, the minimum fifo trigger level is 1, and the tx will
850 * request service when the fifo is at this level, with only 15 spaces.
851 */
852
853 /* find bytes/word */
854 if (bits_per_word <= 8)
855 bytes_per_word = 1;
856 else if (bits_per_word <= 16)
857 bytes_per_word = 2;
858 else
859 bytes_per_word = 4;
860
861 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
862 if (chip_info)
863 req_burst_size = chip_info->dma_burst_size;
864 else {
865 switch (chip->dma_burst_size) {
866 default:
867 /* if the default burst size is not set,
868 * do it now */
869 chip->dma_burst_size = DCMD_BURST8;
870 case DCMD_BURST8:
871 req_burst_size = 8;
872 break;
873 case DCMD_BURST16:
874 req_burst_size = 16;
875 break;
876 case DCMD_BURST32:
877 req_burst_size = 32;
878 break;
879 }
880 }
881 if (req_burst_size <= 8) {
882 *burst_code = DCMD_BURST8;
883 burst_bytes = 8;
884 } else if (req_burst_size <= 16) {
885 if (bytes_per_word == 1) {
886 /* don't burst more than 1/2 the fifo */
887 *burst_code = DCMD_BURST8;
888 burst_bytes = 8;
889 retval = 1;
890 } else {
891 *burst_code = DCMD_BURST16;
892 burst_bytes = 16;
893 }
894 } else {
895 if (bytes_per_word == 1) {
896 /* don't burst more than 1/2 the fifo */
897 *burst_code = DCMD_BURST8;
898 burst_bytes = 8;
899 retval = 1;
900 } else if (bytes_per_word == 2) {
901 /* don't burst more than 1/2 the fifo */
902 *burst_code = DCMD_BURST16;
903 burst_bytes = 16;
904 retval = 1;
905 } else {
906 *burst_code = DCMD_BURST32;
907 burst_bytes = 32;
908 }
909 }
910
911 thresh_words = burst_bytes / bytes_per_word;
912
913 /* thresh_words will be between 2 and 8 */
914 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
915 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
916
917 return retval;
918}
919
eric miao2f1a74e2007-11-21 18:50:53 +0800920static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
921{
922 unsigned long ssp_clk = clk_get_rate(ssp->clk);
923
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800924 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
eric miao2f1a74e2007-11-21 18:50:53 +0800925 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
926 else
927 return ((ssp_clk / rate - 1) & 0xfff) << 8;
928}
929
Stephen Streete0c99052006-03-07 23:53:24 -0800930static void pump_transfers(unsigned long data)
931{
932 struct driver_data *drv_data = (struct driver_data *)data;
933 struct spi_message *message = NULL;
934 struct spi_transfer *transfer = NULL;
935 struct spi_transfer *previous = NULL;
936 struct chip_data *chip = NULL;
eric miao2f1a74e2007-11-21 18:50:53 +0800937 struct ssp_device *ssp = drv_data->ssp;
David Brownellcf433692008-04-28 02:14:17 -0700938 void __iomem *reg = drv_data->ioaddr;
Stephen Street9708c122006-03-28 14:05:23 -0800939 u32 clk_div = 0;
940 u8 bits = 0;
941 u32 speed = 0;
942 u32 cr0;
Stephen Street8d94cc52006-12-10 02:18:54 -0800943 u32 cr1;
944 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
945 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
Stephen Streete0c99052006-03-07 23:53:24 -0800946
947 /* Get current state information */
948 message = drv_data->cur_msg;
949 transfer = drv_data->cur_transfer;
950 chip = drv_data->cur_chip;
951
952 /* Handle for abort */
953 if (message->state == ERROR_STATE) {
954 message->status = -EIO;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700955 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800956 return;
957 }
958
959 /* Handle end of message */
960 if (message->state == DONE_STATE) {
961 message->status = 0;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700962 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800963 return;
964 }
965
Ned Forrester84235972008-09-13 02:33:17 -0700966 /* Delay if requested at end of transfer before CS change */
Stephen Streete0c99052006-03-07 23:53:24 -0800967 if (message->state == RUNNING_STATE) {
968 previous = list_entry(transfer->transfer_list.prev,
969 struct spi_transfer,
970 transfer_list);
971 if (previous->delay_usecs)
972 udelay(previous->delay_usecs);
Ned Forrester84235972008-09-13 02:33:17 -0700973
974 /* Drop chip select only if cs_change is requested */
975 if (previous->cs_change)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700976 cs_deassert(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800977 }
978
Ned Forrester7e964452008-09-13 02:33:18 -0700979 /* Check for transfers that need multiple DMA segments */
980 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
981
982 /* reject already-mapped transfers; PIO won't always work */
983 if (message->is_dma_mapped
984 || transfer->rx_dma || transfer->tx_dma) {
985 dev_err(&drv_data->pdev->dev,
986 "pump_transfers: mapped transfer length "
Mike Rapoport20b918d2008-10-01 10:39:24 -0700987 "of %u is greater than %d\n",
Ned Forrester7e964452008-09-13 02:33:18 -0700988 transfer->len, MAX_DMA_LEN);
989 message->status = -EINVAL;
990 giveback(drv_data);
991 return;
992 }
993
994 /* warn ... we force this to PIO mode */
995 if (printk_ratelimit())
996 dev_warn(&message->spi->dev, "pump_transfers: "
997 "DMA disabled for transfer length %ld "
998 "greater than %d\n",
999 (long)drv_data->len, MAX_DMA_LEN);
Stephen Street8d94cc52006-12-10 02:18:54 -08001000 }
1001
Stephen Streete0c99052006-03-07 23:53:24 -08001002 /* Setup the transfer state based on the type of transfer */
1003 if (flush(drv_data) == 0) {
1004 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1005 message->status = -EIO;
Stephen Street5daa3ba2006-05-20 15:00:19 -07001006 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001007 return;
1008 }
Stephen Street9708c122006-03-28 14:05:23 -08001009 drv_data->n_bytes = chip->n_bytes;
1010 drv_data->dma_width = chip->dma_width;
Stephen Streete0c99052006-03-07 23:53:24 -08001011 drv_data->tx = (void *)transfer->tx_buf;
1012 drv_data->tx_end = drv_data->tx + transfer->len;
1013 drv_data->rx = transfer->rx_buf;
1014 drv_data->rx_end = drv_data->rx + transfer->len;
1015 drv_data->rx_dma = transfer->rx_dma;
1016 drv_data->tx_dma = transfer->tx_dma;
Stephen Street8d94cc52006-12-10 02:18:54 -08001017 drv_data->len = transfer->len & DCMD_LENGTH;
Stephen Streete0c99052006-03-07 23:53:24 -08001018 drv_data->write = drv_data->tx ? chip->write : null_writer;
1019 drv_data->read = drv_data->rx ? chip->read : null_reader;
Stephen Street9708c122006-03-28 14:05:23 -08001020
1021 /* Change speed and bit per word on a per transfer */
Stephen Street8d94cc52006-12-10 02:18:54 -08001022 cr0 = chip->cr0;
Stephen Street9708c122006-03-28 14:05:23 -08001023 if (transfer->speed_hz || transfer->bits_per_word) {
1024
Stephen Street9708c122006-03-28 14:05:23 -08001025 bits = chip->bits_per_word;
1026 speed = chip->speed_hz;
1027
1028 if (transfer->speed_hz)
1029 speed = transfer->speed_hz;
1030
1031 if (transfer->bits_per_word)
1032 bits = transfer->bits_per_word;
1033
eric miao2f1a74e2007-11-21 18:50:53 +08001034 clk_div = ssp_get_clk_div(ssp, speed);
Stephen Street9708c122006-03-28 14:05:23 -08001035
1036 if (bits <= 8) {
1037 drv_data->n_bytes = 1;
1038 drv_data->dma_width = DCMD_WIDTH1;
1039 drv_data->read = drv_data->read != null_reader ?
1040 u8_reader : null_reader;
1041 drv_data->write = drv_data->write != null_writer ?
1042 u8_writer : null_writer;
1043 } else if (bits <= 16) {
1044 drv_data->n_bytes = 2;
1045 drv_data->dma_width = DCMD_WIDTH2;
1046 drv_data->read = drv_data->read != null_reader ?
1047 u16_reader : null_reader;
1048 drv_data->write = drv_data->write != null_writer ?
1049 u16_writer : null_writer;
1050 } else if (bits <= 32) {
1051 drv_data->n_bytes = 4;
1052 drv_data->dma_width = DCMD_WIDTH4;
1053 drv_data->read = drv_data->read != null_reader ?
1054 u32_reader : null_reader;
1055 drv_data->write = drv_data->write != null_writer ?
1056 u32_writer : null_writer;
1057 }
Stephen Street8d94cc52006-12-10 02:18:54 -08001058 /* if bits/word is changed in dma mode, then must check the
1059 * thresholds and burst also */
1060 if (chip->enable_dma) {
1061 if (set_dma_burst_and_threshold(chip, message->spi,
1062 bits, &dma_burst,
1063 &dma_thresh))
1064 if (printk_ratelimit())
1065 dev_warn(&message->spi->dev,
Ned Forrester7e964452008-09-13 02:33:18 -07001066 "pump_transfers: "
Stephen Street8d94cc52006-12-10 02:18:54 -08001067 "DMA burst size reduced to "
1068 "match bits_per_word\n");
1069 }
Stephen Street9708c122006-03-28 14:05:23 -08001070
1071 cr0 = clk_div
1072 | SSCR0_Motorola
Stephen Street5daa3ba2006-05-20 15:00:19 -07001073 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
Stephen Street9708c122006-03-28 14:05:23 -08001074 | SSCR0_SSE
1075 | (bits > 16 ? SSCR0_EDSS : 0);
Stephen Street9708c122006-03-28 14:05:23 -08001076 }
1077
Stephen Streete0c99052006-03-07 23:53:24 -08001078 message->state = RUNNING_STATE;
1079
Ned Forrester7e964452008-09-13 02:33:18 -07001080 /* Try to map dma buffer and do a dma transfer if successful, but
1081 * only if the length is non-zero and less than MAX_DMA_LEN.
1082 *
1083 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1084 * of PIO instead. Care is needed above because the transfer may
1085 * have have been passed with buffers that are already dma mapped.
1086 * A zero-length transfer in PIO mode will not try to write/read
1087 * to/from the buffers
1088 *
1089 * REVISIT large transfers are exactly where we most want to be
1090 * using DMA. If this happens much, split those transfers into
1091 * multiple DMA segments rather than forcing PIO.
1092 */
1093 drv_data->dma_mapped = 0;
1094 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1095 drv_data->dma_mapped = map_dma_buffers(drv_data);
1096 if (drv_data->dma_mapped) {
Stephen Streete0c99052006-03-07 23:53:24 -08001097
1098 /* Ensure we have the correct interrupt handler */
1099 drv_data->transfer_handler = dma_transfer;
1100
1101 /* Setup rx DMA Channel */
1102 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1103 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1104 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1105 if (drv_data->rx == drv_data->null_dma_buf)
1106 /* No target address increment */
1107 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
Stephen Street9708c122006-03-28 14:05:23 -08001108 | drv_data->dma_width
Stephen Street8d94cc52006-12-10 02:18:54 -08001109 | dma_burst
Stephen Streete0c99052006-03-07 23:53:24 -08001110 | drv_data->len;
1111 else
1112 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1113 | DCMD_FLOWSRC
Stephen Street9708c122006-03-28 14:05:23 -08001114 | drv_data->dma_width
Stephen Street8d94cc52006-12-10 02:18:54 -08001115 | dma_burst
Stephen Streete0c99052006-03-07 23:53:24 -08001116 | drv_data->len;
1117
1118 /* Setup tx DMA Channel */
1119 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1120 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1121 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1122 if (drv_data->tx == drv_data->null_dma_buf)
1123 /* No source address increment */
1124 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
Stephen Street9708c122006-03-28 14:05:23 -08001125 | drv_data->dma_width
Stephen Street8d94cc52006-12-10 02:18:54 -08001126 | dma_burst
Stephen Streete0c99052006-03-07 23:53:24 -08001127 | drv_data->len;
1128 else
1129 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1130 | DCMD_FLOWTRG
Stephen Street9708c122006-03-28 14:05:23 -08001131 | drv_data->dma_width
Stephen Street8d94cc52006-12-10 02:18:54 -08001132 | dma_burst
Stephen Streete0c99052006-03-07 23:53:24 -08001133 | drv_data->len;
1134
1135 /* Enable dma end irqs on SSP to detect end of transfer */
1136 if (drv_data->ssp_type == PXA25x_SSP)
1137 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1138
Stephen Street8d94cc52006-12-10 02:18:54 -08001139 /* Clear status and start DMA engine */
1140 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
Stephen Streete0c99052006-03-07 23:53:24 -08001141 write_SSSR(drv_data->clear_sr, reg);
1142 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1143 DCSR(drv_data->tx_channel) |= DCSR_RUN;
Stephen Streete0c99052006-03-07 23:53:24 -08001144 } else {
1145 /* Ensure we have the correct interrupt handler */
1146 drv_data->transfer_handler = interrupt_transfer;
1147
Stephen Street8d94cc52006-12-10 02:18:54 -08001148 /* Clear status */
1149 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001150 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street8d94cc52006-12-10 02:18:54 -08001151 }
1152
1153 /* see if we need to reload the config registers */
1154 if ((read_SSCR0(reg) != cr0)
1155 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1156 (cr1 & SSCR1_CHANGE_MASK)) {
1157
Ned Forresterb97c74b2008-02-23 15:23:40 -08001158 /* stop the SSP, and update the other bits */
Stephen Street8d94cc52006-12-10 02:18:54 -08001159 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001160 if (!pxa25x_ssp_comp(drv_data))
Stephen Streete0c99052006-03-07 23:53:24 -08001161 write_SSTO(chip->timeout, reg);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001162 /* first set CR1 without interrupt and service enables */
1163 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1164 /* restart the SSP */
Stephen Street8d94cc52006-12-10 02:18:54 -08001165 write_SSCR0(cr0, reg);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001166
Stephen Street8d94cc52006-12-10 02:18:54 -08001167 } else {
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001168 if (!pxa25x_ssp_comp(drv_data))
Stephen Street8d94cc52006-12-10 02:18:54 -08001169 write_SSTO(chip->timeout, reg);
Stephen Streete0c99052006-03-07 23:53:24 -08001170 }
Ned Forresterb97c74b2008-02-23 15:23:40 -08001171
Eric Miaoa7bb3902009-04-06 19:00:54 -07001172 cs_assert(drv_data);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001173
1174 /* after chip select, release the data by enabling service
1175 * requests and interrupts, without changing any mode bits */
1176 write_SSCR1(cr1, reg);
Stephen Streete0c99052006-03-07 23:53:24 -08001177}
1178
David Howells6d5aefb2006-12-05 19:36:26 +00001179static void pump_messages(struct work_struct *work)
Stephen Streete0c99052006-03-07 23:53:24 -08001180{
David Howells6d5aefb2006-12-05 19:36:26 +00001181 struct driver_data *drv_data =
1182 container_of(work, struct driver_data, pump_messages);
Stephen Streete0c99052006-03-07 23:53:24 -08001183 unsigned long flags;
1184
1185 /* Lock queue and check for queue work */
1186 spin_lock_irqsave(&drv_data->lock, flags);
1187 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1188 drv_data->busy = 0;
1189 spin_unlock_irqrestore(&drv_data->lock, flags);
1190 return;
1191 }
1192
1193 /* Make sure we are not already running a message */
1194 if (drv_data->cur_msg) {
1195 spin_unlock_irqrestore(&drv_data->lock, flags);
1196 return;
1197 }
1198
1199 /* Extract head of queue */
1200 drv_data->cur_msg = list_entry(drv_data->queue.next,
1201 struct spi_message, queue);
1202 list_del_init(&drv_data->cur_msg->queue);
Stephen Streete0c99052006-03-07 23:53:24 -08001203
1204 /* Initial message state*/
1205 drv_data->cur_msg->state = START_STATE;
1206 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1207 struct spi_transfer,
1208 transfer_list);
1209
Stephen Street8d94cc52006-12-10 02:18:54 -08001210 /* prepare to setup the SSP, in pump_transfers, using the per
1211 * chip configuration */
Stephen Streete0c99052006-03-07 23:53:24 -08001212 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
Stephen Streete0c99052006-03-07 23:53:24 -08001213
1214 /* Mark as busy and launch transfers */
1215 tasklet_schedule(&drv_data->pump_transfers);
Stephen Street5daa3ba2006-05-20 15:00:19 -07001216
1217 drv_data->busy = 1;
1218 spin_unlock_irqrestore(&drv_data->lock, flags);
Stephen Streete0c99052006-03-07 23:53:24 -08001219}
1220
1221static int transfer(struct spi_device *spi, struct spi_message *msg)
1222{
1223 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1224 unsigned long flags;
1225
1226 spin_lock_irqsave(&drv_data->lock, flags);
1227
1228 if (drv_data->run == QUEUE_STOPPED) {
1229 spin_unlock_irqrestore(&drv_data->lock, flags);
1230 return -ESHUTDOWN;
1231 }
1232
1233 msg->actual_length = 0;
1234 msg->status = -EINPROGRESS;
1235 msg->state = START_STATE;
1236
1237 list_add_tail(&msg->queue, &drv_data->queue);
1238
1239 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1240 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1241
1242 spin_unlock_irqrestore(&drv_data->lock, flags);
1243
1244 return 0;
1245}
1246
Eric Miaoa7bb3902009-04-06 19:00:54 -07001247static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1248 struct pxa2xx_spi_chip *chip_info)
1249{
1250 int err = 0;
1251
1252 if (chip == NULL || chip_info == NULL)
1253 return 0;
1254
1255 /* NOTE: setup() can be called multiple times, possibly with
1256 * different chip_info, release previously requested GPIO
1257 */
1258 if (gpio_is_valid(chip->gpio_cs))
1259 gpio_free(chip->gpio_cs);
1260
1261 /* If (*cs_control) is provided, ignore GPIO chip select */
1262 if (chip_info->cs_control) {
1263 chip->cs_control = chip_info->cs_control;
1264 return 0;
1265 }
1266
1267 if (gpio_is_valid(chip_info->gpio_cs)) {
1268 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1269 if (err) {
1270 dev_err(&spi->dev, "failed to request chip select "
1271 "GPIO%d\n", chip_info->gpio_cs);
1272 return err;
1273 }
1274
1275 chip->gpio_cs = chip_info->gpio_cs;
1276 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1277
1278 err = gpio_direction_output(chip->gpio_cs,
1279 !chip->gpio_cs_inverted);
1280 }
1281
1282 return err;
1283}
1284
Stephen Streete0c99052006-03-07 23:53:24 -08001285static int setup(struct spi_device *spi)
1286{
1287 struct pxa2xx_spi_chip *chip_info = NULL;
1288 struct chip_data *chip;
1289 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
eric miao2f1a74e2007-11-21 18:50:53 +08001290 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001291 unsigned int clk_div;
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001292 uint tx_thres = TX_THRESH_DFLT;
1293 uint rx_thres = RX_THRESH_DFLT;
Stephen Streete0c99052006-03-07 23:53:24 -08001294
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001295 if (!pxa25x_ssp_comp(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -08001296 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1297 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1298 "b/w not 4-32 for type non-PXA25x_SSP\n",
1299 drv_data->ssp_type, spi->bits_per_word);
Stephen Streete0c99052006-03-07 23:53:24 -08001300 return -EINVAL;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001301 } else if (pxa25x_ssp_comp(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -08001302 && (spi->bits_per_word < 4
1303 || spi->bits_per_word > 16)) {
1304 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1305 "b/w not 4-16 for type PXA25x_SSP\n",
1306 drv_data->ssp_type, spi->bits_per_word);
Stephen Streete0c99052006-03-07 23:53:24 -08001307 return -EINVAL;
Stephen Street8d94cc52006-12-10 02:18:54 -08001308 }
Stephen Streete0c99052006-03-07 23:53:24 -08001309
Stephen Street8d94cc52006-12-10 02:18:54 -08001310 /* Only alloc on first setup */
Stephen Streete0c99052006-03-07 23:53:24 -08001311 chip = spi_get_ctldata(spi);
Stephen Street8d94cc52006-12-10 02:18:54 -08001312 if (!chip) {
Stephen Streete0c99052006-03-07 23:53:24 -08001313 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Stephen Street8d94cc52006-12-10 02:18:54 -08001314 if (!chip) {
1315 dev_err(&spi->dev,
1316 "failed setup: can't allocate chip data\n");
Stephen Streete0c99052006-03-07 23:53:24 -08001317 return -ENOMEM;
Stephen Street8d94cc52006-12-10 02:18:54 -08001318 }
Stephen Streete0c99052006-03-07 23:53:24 -08001319
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001320 if (drv_data->ssp_type == CE4100_SSP) {
1321 if (spi->chip_select > 4) {
1322 dev_err(&spi->dev, "failed setup: "
1323 "cs number must not be > 4.\n");
1324 kfree(chip);
1325 return -EINVAL;
1326 }
1327
1328 chip->frm = spi->chip_select;
1329 } else
1330 chip->gpio_cs = -1;
Stephen Streete0c99052006-03-07 23:53:24 -08001331 chip->enable_dma = 0;
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001332 chip->timeout = TIMOUT_DFLT;
Stephen Streete0c99052006-03-07 23:53:24 -08001333 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1334 DCMD_BURST8 : 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001335 }
1336
Stephen Street8d94cc52006-12-10 02:18:54 -08001337 /* protocol drivers may change the chip settings, so...
1338 * if chip_info exists, use it */
1339 chip_info = spi->controller_data;
1340
Stephen Streete0c99052006-03-07 23:53:24 -08001341 /* chip_info isn't always needed */
Stephen Street8d94cc52006-12-10 02:18:54 -08001342 chip->cr1 = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001343 if (chip_info) {
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001344 if (chip_info->timeout)
1345 chip->timeout = chip_info->timeout;
1346 if (chip_info->tx_threshold)
1347 tx_thres = chip_info->tx_threshold;
1348 if (chip_info->rx_threshold)
1349 rx_thres = chip_info->rx_threshold;
1350 chip->enable_dma = drv_data->master_info->enable_dma;
Stephen Streete0c99052006-03-07 23:53:24 -08001351 chip->dma_threshold = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001352 if (chip_info->enable_loopback)
1353 chip->cr1 = SSCR1_LBM;
1354 }
1355
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001356 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1357 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1358
Stephen Street8d94cc52006-12-10 02:18:54 -08001359 /* set dma burst and threshold outside of chip_info path so that if
1360 * chip_info goes away after setting chip->enable_dma, the
1361 * burst and threshold can still respond to changes in bits_per_word */
1362 if (chip->enable_dma) {
1363 /* set up legal burst and threshold for dma */
1364 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1365 &chip->dma_burst_size,
1366 &chip->dma_threshold)) {
1367 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1368 "to match bits_per_word\n");
1369 }
1370 }
1371
eric miao2f1a74e2007-11-21 18:50:53 +08001372 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
Stephen Street9708c122006-03-28 14:05:23 -08001373 chip->speed_hz = spi->max_speed_hz;
Stephen Streete0c99052006-03-07 23:53:24 -08001374
1375 chip->cr0 = clk_div
1376 | SSCR0_Motorola
Stephen Street5daa3ba2006-05-20 15:00:19 -07001377 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1378 spi->bits_per_word - 16 : spi->bits_per_word)
Stephen Streete0c99052006-03-07 23:53:24 -08001379 | SSCR0_SSE
1380 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
Justin Clacherty7f6ee1a2007-01-26 00:56:44 -08001381 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1382 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1383 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
Stephen Streete0c99052006-03-07 23:53:24 -08001384
1385 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001386 if (!pxa25x_ssp_comp(drv_data))
David Brownell7d077192009-06-17 16:26:03 -07001387 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
Eric Miaoc9840da2010-03-16 16:48:01 +08001388 clk_get_rate(ssp->clk)
1389 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1390 chip->enable_dma ? "DMA" : "PIO");
Stephen Streete0c99052006-03-07 23:53:24 -08001391 else
David Brownell7d077192009-06-17 16:26:03 -07001392 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
Eric Miaoc9840da2010-03-16 16:48:01 +08001393 clk_get_rate(ssp->clk) / 2
1394 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1395 chip->enable_dma ? "DMA" : "PIO");
Stephen Streete0c99052006-03-07 23:53:24 -08001396
1397 if (spi->bits_per_word <= 8) {
1398 chip->n_bytes = 1;
1399 chip->dma_width = DCMD_WIDTH1;
1400 chip->read = u8_reader;
1401 chip->write = u8_writer;
1402 } else if (spi->bits_per_word <= 16) {
1403 chip->n_bytes = 2;
1404 chip->dma_width = DCMD_WIDTH2;
1405 chip->read = u16_reader;
1406 chip->write = u16_writer;
1407 } else if (spi->bits_per_word <= 32) {
1408 chip->cr0 |= SSCR0_EDSS;
1409 chip->n_bytes = 4;
1410 chip->dma_width = DCMD_WIDTH4;
1411 chip->read = u32_reader;
1412 chip->write = u32_writer;
1413 } else {
1414 dev_err(&spi->dev, "invalid wordsize\n");
Stephen Streete0c99052006-03-07 23:53:24 -08001415 return -ENODEV;
1416 }
Stephen Street9708c122006-03-28 14:05:23 -08001417 chip->bits_per_word = spi->bits_per_word;
Stephen Streete0c99052006-03-07 23:53:24 -08001418
1419 spi_set_ctldata(spi, chip);
1420
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001421 if (drv_data->ssp_type == CE4100_SSP)
1422 return 0;
1423
Eric Miaoa7bb3902009-04-06 19:00:54 -07001424 return setup_cs(spi, chip, chip_info);
Stephen Streete0c99052006-03-07 23:53:24 -08001425}
1426
Hans-Peter Nilsson0ffa0282007-02-12 00:52:45 -08001427static void cleanup(struct spi_device *spi)
Stephen Streete0c99052006-03-07 23:53:24 -08001428{
Hans-Peter Nilsson0ffa0282007-02-12 00:52:45 -08001429 struct chip_data *chip = spi_get_ctldata(spi);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001430 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001431
Daniel Ribeiro7348d822009-05-12 13:19:36 -07001432 if (!chip)
1433 return;
1434
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001435 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
Eric Miaoa7bb3902009-04-06 19:00:54 -07001436 gpio_free(chip->gpio_cs);
1437
Stephen Streete0c99052006-03-07 23:53:24 -08001438 kfree(chip);
1439}
1440
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001441static int __devinit init_queue(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -08001442{
1443 INIT_LIST_HEAD(&drv_data->queue);
1444 spin_lock_init(&drv_data->lock);
1445
1446 drv_data->run = QUEUE_STOPPED;
1447 drv_data->busy = 0;
1448
1449 tasklet_init(&drv_data->pump_transfers,
1450 pump_transfers, (unsigned long)drv_data);
1451
David Howells6d5aefb2006-12-05 19:36:26 +00001452 INIT_WORK(&drv_data->pump_messages, pump_messages);
Stephen Streete0c99052006-03-07 23:53:24 -08001453 drv_data->workqueue = create_singlethread_workqueue(
Kay Sievers6c7377a2009-03-24 16:38:21 -07001454 dev_name(drv_data->master->dev.parent));
Stephen Streete0c99052006-03-07 23:53:24 -08001455 if (drv_data->workqueue == NULL)
1456 return -EBUSY;
1457
1458 return 0;
1459}
1460
1461static int start_queue(struct driver_data *drv_data)
1462{
1463 unsigned long flags;
1464
1465 spin_lock_irqsave(&drv_data->lock, flags);
1466
1467 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1468 spin_unlock_irqrestore(&drv_data->lock, flags);
1469 return -EBUSY;
1470 }
1471
1472 drv_data->run = QUEUE_RUNNING;
1473 drv_data->cur_msg = NULL;
1474 drv_data->cur_transfer = NULL;
1475 drv_data->cur_chip = NULL;
1476 spin_unlock_irqrestore(&drv_data->lock, flags);
1477
1478 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1479
1480 return 0;
1481}
1482
1483static int stop_queue(struct driver_data *drv_data)
1484{
1485 unsigned long flags;
1486 unsigned limit = 500;
1487 int status = 0;
1488
1489 spin_lock_irqsave(&drv_data->lock, flags);
1490
1491 /* This is a bit lame, but is optimized for the common execution path.
1492 * A wait_queue on the drv_data->busy could be used, but then the common
1493 * execution path (pump_messages) would be required to call wake_up or
1494 * friends on every SPI message. Do this instead */
1495 drv_data->run = QUEUE_STOPPED;
Vasily Khoruzhick850a28e2011-04-06 17:49:15 +03001496 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
Stephen Streete0c99052006-03-07 23:53:24 -08001497 spin_unlock_irqrestore(&drv_data->lock, flags);
1498 msleep(10);
1499 spin_lock_irqsave(&drv_data->lock, flags);
1500 }
1501
1502 if (!list_empty(&drv_data->queue) || drv_data->busy)
1503 status = -EBUSY;
1504
1505 spin_unlock_irqrestore(&drv_data->lock, flags);
1506
1507 return status;
1508}
1509
1510static int destroy_queue(struct driver_data *drv_data)
1511{
1512 int status;
1513
1514 status = stop_queue(drv_data);
Stephen Street8d94cc52006-12-10 02:18:54 -08001515 /* we are unloading the module or failing to load (only two calls
1516 * to this routine), and neither call can handle a return value.
1517 * However, destroy_workqueue calls flush_workqueue, and that will
1518 * block until all work is done. If the reason that stop_queue
1519 * timed out is that the work will never finish, then it does no
1520 * good to call destroy_workqueue, so return anyway. */
Stephen Streete0c99052006-03-07 23:53:24 -08001521 if (status != 0)
1522 return status;
1523
1524 destroy_workqueue(drv_data->workqueue);
1525
1526 return 0;
1527}
1528
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001529static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
Stephen Streete0c99052006-03-07 23:53:24 -08001530{
1531 struct device *dev = &pdev->dev;
1532 struct pxa2xx_spi_master *platform_info;
1533 struct spi_master *master;
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001534 struct driver_data *drv_data;
eric miao2f1a74e2007-11-21 18:50:53 +08001535 struct ssp_device *ssp;
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001536 int status;
Stephen Streete0c99052006-03-07 23:53:24 -08001537
1538 platform_info = dev->platform_data;
1539
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001540 ssp = pxa_ssp_request(pdev->id, pdev->name);
eric miao2f1a74e2007-11-21 18:50:53 +08001541 if (ssp == NULL) {
1542 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
Stephen Streete0c99052006-03-07 23:53:24 -08001543 return -ENODEV;
1544 }
1545
1546 /* Allocate master with space for drv_data and null dma buffer */
1547 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1548 if (!master) {
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001549 dev_err(&pdev->dev, "cannot alloc spi_master\n");
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001550 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001551 return -ENOMEM;
1552 }
1553 drv_data = spi_master_get_devdata(master);
1554 drv_data->master = master;
1555 drv_data->master_info = platform_info;
1556 drv_data->pdev = pdev;
eric miao2f1a74e2007-11-21 18:50:53 +08001557 drv_data->ssp = ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001558
Sebastian Andrzej Siewior21486af2010-10-08 18:11:19 +02001559 master->dev.parent = &pdev->dev;
Sebastian Andrzej Siewior21486af2010-10-08 18:11:19 +02001560 master->dev.of_node = pdev->dev.of_node;
David Brownelle7db06b2009-06-17 16:26:04 -07001561 /* the spi->mode bits understood by this driver: */
Daniel Ribeiro50e0a7b2009-06-17 16:26:06 -07001562 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
David Brownelle7db06b2009-06-17 16:26:04 -07001563
Stephen Streete0c99052006-03-07 23:53:24 -08001564 master->bus_num = pdev->id;
1565 master->num_chipselect = platform_info->num_chipselect;
Mike Rapoport7ad0ba92009-04-06 19:00:57 -07001566 master->dma_alignment = DMA_ALIGNMENT;
Stephen Streete0c99052006-03-07 23:53:24 -08001567 master->cleanup = cleanup;
1568 master->setup = setup;
1569 master->transfer = transfer;
1570
eric miao2f1a74e2007-11-21 18:50:53 +08001571 drv_data->ssp_type = ssp->type;
Stephen Streete0c99052006-03-07 23:53:24 -08001572 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1573 sizeof(struct driver_data)), 8);
1574
eric miao2f1a74e2007-11-21 18:50:53 +08001575 drv_data->ioaddr = ssp->mmio_base;
1576 drv_data->ssdr_physical = ssp->phys_base + SSDR;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001577 if (pxa25x_ssp_comp(drv_data)) {
Stephen Streete0c99052006-03-07 23:53:24 -08001578 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1579 drv_data->dma_cr1 = 0;
1580 drv_data->clear_sr = SSSR_ROR;
1581 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1582 } else {
1583 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1584 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1585 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1586 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1587 }
1588
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -08001589 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1590 drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001591 if (status < 0) {
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001592 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
Stephen Streete0c99052006-03-07 23:53:24 -08001593 goto out_error_master_alloc;
1594 }
1595
1596 /* Setup DMA if requested */
1597 drv_data->tx_channel = -1;
1598 drv_data->rx_channel = -1;
1599 if (platform_info->enable_dma) {
1600
1601 /* Get two DMA channels (rx and tx) */
1602 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1603 DMA_PRIO_HIGH,
1604 dma_handler,
1605 drv_data);
1606 if (drv_data->rx_channel < 0) {
1607 dev_err(dev, "problem (%d) requesting rx channel\n",
1608 drv_data->rx_channel);
1609 status = -ENODEV;
1610 goto out_error_irq_alloc;
1611 }
1612 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1613 DMA_PRIO_MEDIUM,
1614 dma_handler,
1615 drv_data);
1616 if (drv_data->tx_channel < 0) {
1617 dev_err(dev, "problem (%d) requesting tx channel\n",
1618 drv_data->tx_channel);
1619 status = -ENODEV;
1620 goto out_error_dma_alloc;
1621 }
1622
eric miao2f1a74e2007-11-21 18:50:53 +08001623 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1624 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
Stephen Streete0c99052006-03-07 23:53:24 -08001625 }
1626
1627 /* Enable SOC clock */
eric miao2f1a74e2007-11-21 18:50:53 +08001628 clk_enable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001629
1630 /* Load default SSP configuration */
1631 write_SSCR0(0, drv_data->ioaddr);
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001632 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1633 SSCR1_TxTresh(TX_THRESH_DFLT),
1634 drv_data->ioaddr);
Eric Miaoc9840da2010-03-16 16:48:01 +08001635 write_SSCR0(SSCR0_SCR(2)
Stephen Streete0c99052006-03-07 23:53:24 -08001636 | SSCR0_Motorola
1637 | SSCR0_DataSize(8),
1638 drv_data->ioaddr);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001639 if (!pxa25x_ssp_comp(drv_data))
Stephen Streete0c99052006-03-07 23:53:24 -08001640 write_SSTO(0, drv_data->ioaddr);
1641 write_SSPSP(0, drv_data->ioaddr);
1642
1643 /* Initial and start queue */
1644 status = init_queue(drv_data);
1645 if (status != 0) {
1646 dev_err(&pdev->dev, "problem initializing queue\n");
1647 goto out_error_clock_enabled;
1648 }
1649 status = start_queue(drv_data);
1650 if (status != 0) {
1651 dev_err(&pdev->dev, "problem starting queue\n");
1652 goto out_error_clock_enabled;
1653 }
1654
1655 /* Register with the SPI framework */
1656 platform_set_drvdata(pdev, drv_data);
1657 status = spi_register_master(master);
1658 if (status != 0) {
1659 dev_err(&pdev->dev, "problem registering spi master\n");
1660 goto out_error_queue_alloc;
1661 }
1662
1663 return status;
1664
1665out_error_queue_alloc:
1666 destroy_queue(drv_data);
1667
1668out_error_clock_enabled:
eric miao2f1a74e2007-11-21 18:50:53 +08001669 clk_disable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001670
1671out_error_dma_alloc:
1672 if (drv_data->tx_channel != -1)
1673 pxa_free_dma(drv_data->tx_channel);
1674 if (drv_data->rx_channel != -1)
1675 pxa_free_dma(drv_data->rx_channel);
1676
1677out_error_irq_alloc:
eric miao2f1a74e2007-11-21 18:50:53 +08001678 free_irq(ssp->irq, drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001679
1680out_error_master_alloc:
1681 spi_master_put(master);
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001682 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001683 return status;
1684}
1685
1686static int pxa2xx_spi_remove(struct platform_device *pdev)
1687{
1688 struct driver_data *drv_data = platform_get_drvdata(pdev);
Julia Lawall51e911e2009-01-06 14:41:45 -08001689 struct ssp_device *ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001690 int status = 0;
1691
1692 if (!drv_data)
1693 return 0;
Julia Lawall51e911e2009-01-06 14:41:45 -08001694 ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001695
1696 /* Remove the queue */
1697 status = destroy_queue(drv_data);
1698 if (status != 0)
Stephen Street8d94cc52006-12-10 02:18:54 -08001699 /* the kernel does not check the return status of this
1700 * this routine (mod->exit, within the kernel). Therefore
1701 * nothing is gained by returning from here, the module is
1702 * going away regardless, and we should not leave any more
1703 * resources allocated than necessary. We cannot free the
1704 * message memory in drv_data->queue, but we can release the
1705 * resources below. I think the kernel should honor -EBUSY
1706 * returns but... */
1707 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1708 "complete, message memory not freed\n");
Stephen Streete0c99052006-03-07 23:53:24 -08001709
1710 /* Disable the SSP at the peripheral and SOC level */
1711 write_SSCR0(0, drv_data->ioaddr);
eric miao2f1a74e2007-11-21 18:50:53 +08001712 clk_disable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001713
1714 /* Release DMA */
1715 if (drv_data->master_info->enable_dma) {
eric miao2f1a74e2007-11-21 18:50:53 +08001716 DRCMR(ssp->drcmr_rx) = 0;
1717 DRCMR(ssp->drcmr_tx) = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001718 pxa_free_dma(drv_data->tx_channel);
1719 pxa_free_dma(drv_data->rx_channel);
1720 }
1721
1722 /* Release IRQ */
eric miao2f1a74e2007-11-21 18:50:53 +08001723 free_irq(ssp->irq, drv_data);
1724
1725 /* Release SSP */
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001726 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001727
1728 /* Disconnect from the SPI framework */
1729 spi_unregister_master(drv_data->master);
1730
1731 /* Prevent double remove */
1732 platform_set_drvdata(pdev, NULL);
1733
1734 return 0;
1735}
1736
1737static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1738{
1739 int status = 0;
1740
1741 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1742 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1743}
1744
1745#ifdef CONFIG_PM
Mike Rapoport86d25932009-07-21 17:50:16 +03001746static int pxa2xx_spi_suspend(struct device *dev)
Stephen Streete0c99052006-03-07 23:53:24 -08001747{
Mike Rapoport86d25932009-07-21 17:50:16 +03001748 struct driver_data *drv_data = dev_get_drvdata(dev);
eric miao2f1a74e2007-11-21 18:50:53 +08001749 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001750 int status = 0;
1751
Stephen Streete0c99052006-03-07 23:53:24 -08001752 status = stop_queue(drv_data);
1753 if (status != 0)
1754 return status;
1755 write_SSCR0(0, drv_data->ioaddr);
eric miao2f1a74e2007-11-21 18:50:53 +08001756 clk_disable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001757
1758 return 0;
1759}
1760
Mike Rapoport86d25932009-07-21 17:50:16 +03001761static int pxa2xx_spi_resume(struct device *dev)
Stephen Streete0c99052006-03-07 23:53:24 -08001762{
Mike Rapoport86d25932009-07-21 17:50:16 +03001763 struct driver_data *drv_data = dev_get_drvdata(dev);
eric miao2f1a74e2007-11-21 18:50:53 +08001764 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001765 int status = 0;
1766
Daniel Ribeiro148da332009-04-21 12:24:43 -07001767 if (drv_data->rx_channel != -1)
1768 DRCMR(drv_data->ssp->drcmr_rx) =
1769 DRCMR_MAPVLD | drv_data->rx_channel;
1770 if (drv_data->tx_channel != -1)
1771 DRCMR(drv_data->ssp->drcmr_tx) =
1772 DRCMR_MAPVLD | drv_data->tx_channel;
1773
Stephen Streete0c99052006-03-07 23:53:24 -08001774 /* Enable the SSP clock */
Eric BENARD0cf942d2008-05-12 14:02:01 -07001775 clk_enable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001776
1777 /* Start the queue running */
1778 status = start_queue(drv_data);
1779 if (status != 0) {
Mike Rapoport86d25932009-07-21 17:50:16 +03001780 dev_err(dev, "problem starting queue (%d)\n", status);
Stephen Streete0c99052006-03-07 23:53:24 -08001781 return status;
1782 }
1783
1784 return 0;
1785}
Mike Rapoport86d25932009-07-21 17:50:16 +03001786
Alexey Dobriyan47145212009-12-14 18:00:08 -08001787static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
Mike Rapoport86d25932009-07-21 17:50:16 +03001788 .suspend = pxa2xx_spi_suspend,
1789 .resume = pxa2xx_spi_resume,
1790};
1791#endif
Stephen Streete0c99052006-03-07 23:53:24 -08001792
1793static struct platform_driver driver = {
1794 .driver = {
Mike Rapoport86d25932009-07-21 17:50:16 +03001795 .name = "pxa2xx-spi",
1796 .owner = THIS_MODULE,
1797#ifdef CONFIG_PM
1798 .pm = &pxa2xx_spi_pm_ops,
1799#endif
Stephen Streete0c99052006-03-07 23:53:24 -08001800 },
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001801 .probe = pxa2xx_spi_probe,
David Brownelld1e44d92007-10-16 01:27:46 -07001802 .remove = pxa2xx_spi_remove,
Stephen Streete0c99052006-03-07 23:53:24 -08001803 .shutdown = pxa2xx_spi_shutdown,
Stephen Streete0c99052006-03-07 23:53:24 -08001804};
1805
1806static int __init pxa2xx_spi_init(void)
1807{
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001808 return platform_driver_register(&driver);
Stephen Streete0c99052006-03-07 23:53:24 -08001809}
Antonio Ospite5b61a742009-09-22 16:46:10 -07001810subsys_initcall(pxa2xx_spi_init);
Stephen Streete0c99052006-03-07 23:53:24 -08001811
1812static void __exit pxa2xx_spi_exit(void)
1813{
1814 platform_driver_unregister(&driver);
1815}
1816module_exit(pxa2xx_spi_exit);