blob: 9f1c084f846f4d3fbbe75d7013cc3065685b3a31 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov80b89872007-08-10 21:02:15 +040011 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 *
14 * TODO
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 * Work out best PLL policy
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
Sergei Shtylyov80b89872007-08-10 21:02:15 +040028#define DRV_VERSION "0.3.4"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
45
46/* key for bus clock timings
47 * bit
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
53 * register access.
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
55 * register access.
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
59 * xfer.
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
61 * register access.
62 * 28 UDMA enable
63 * 29 DMA enable
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
65 * PIO.
66 * 31 FIFO enable.
67 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040068
Jeff Garzik669a5db2006-08-29 18:12:40 -040069/* 66MHz DPLL clocks */
70
71static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2c },
84
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
90 { 0, 0x0d029d5e }
91};
92
93/**
94 * hpt3x2n_find_mode - reset the hpt3x2n bus
95 * @ap: ATA port
96 * @speed: transfer mode
97 *
98 * Return the 32bit register programming information for this channel
99 * that matches the speed provided. For the moment the clocks table
100 * is hard coded but easy to change. This will be needed if we use
101 * different DPLLs
102 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400103
Jeff Garzik669a5db2006-08-29 18:12:40 -0400104static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105{
106 struct hpt_clock *clocks = hpt3x2n_clocks;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400107
Jeff Garzik669a5db2006-08-29 18:12:40 -0400108 while(clocks->xfer_speed) {
109 if (clocks->xfer_speed == speed)
110 return clocks->timing;
111 clocks++;
112 }
113 BUG();
114 return 0xffffffffU; /* silence compiler warning */
115}
116
117/**
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500118 * hpt3x2n_cable_detect - Detect the cable type
119 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400120 *
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500121 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400122 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400123
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500124static int hpt3x2n_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125{
126 u8 scr2, ata66;
127 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400128
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129 pci_read_config_byte(pdev, 0x5B, &scr2);
130 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
131 /* Cable register now active */
132 pci_read_config_byte(pdev, 0x5A, &ata66);
133 /* Restore state */
134 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400135
Jeff Garzik669a5db2006-08-29 18:12:40 -0400136 if (ata66 & (1 << ap->port_no))
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500137 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400138 else
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500139 return ATA_CBL_PATA80;
140}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500142/**
143 * hpt3x2n_pre_reset - reset the hpt3x2n bus
Tejun Heocc0680a2007-08-06 18:36:23 +0900144 * @link: ATA link to reset
Alan Cox28e21c82007-04-26 00:19:25 -0700145 * @deadline: deadline jiffies for the operation
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500146 *
147 * Perform the initial reset handling for the 3x2n series controllers.
148 * Reset the hardware and state machine,
149 */
150
Tejun Heocc0680a2007-08-06 18:36:23 +0900151static int hpt3xn_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500152{
Tejun Heocc0680a2007-08-06 18:36:23 +0900153 struct ata_port *ap = link->ap;
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500154 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 /* Reset the state machine */
Alan Cox28e21c82007-04-26 00:19:25 -0700156 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400157 udelay(100);
Tejun Heod4b2bab2007-02-02 16:50:52 +0900158
Tejun Heocc0680a2007-08-06 18:36:23 +0900159 return ata_std_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400160}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400161
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162/**
163 * hpt3x2n_error_handler - probe the hpt3x2n bus
164 * @ap: ATA port to reset
165 *
166 * Perform the probe reset handling for the 3x2N
167 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400168
Jeff Garzik669a5db2006-08-29 18:12:40 -0400169static void hpt3x2n_error_handler(struct ata_port *ap)
170{
171 ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
172}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400173
Jeff Garzik669a5db2006-08-29 18:12:40 -0400174/**
175 * hpt3x2n_set_piomode - PIO setup
176 * @ap: ATA interface
177 * @adev: device on the interface
178 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400179 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400180 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400181
Jeff Garzik669a5db2006-08-29 18:12:40 -0400182static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
183{
184 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
185 u32 addr1, addr2;
186 u32 reg;
187 u32 mode;
188 u8 fast;
189
190 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
191 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400192
Jeff Garzik669a5db2006-08-29 18:12:40 -0400193 /* Fast interrupt prediction disable, hold off interrupt disable */
194 pci_read_config_byte(pdev, addr2, &fast);
195 fast &= ~0x07;
196 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400197
Jeff Garzik669a5db2006-08-29 18:12:40 -0400198 pci_read_config_dword(pdev, addr1, &reg);
199 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
200 mode &= ~0x8000000; /* No FIFO in PIO */
201 mode &= ~0x30070000; /* Leave config bits alone */
202 reg &= 0x30070000; /* Strip timing bits */
203 pci_write_config_dword(pdev, addr1, reg | mode);
204}
205
206/**
207 * hpt3x2n_set_dmamode - DMA timing setup
208 * @ap: ATA interface
209 * @adev: Device being configured
210 *
211 * Set up the channel for MWDMA or UDMA modes. Much the same as with
212 * PIO, load the mode number and then set MWDMA or UDMA flag.
213 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400214
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
216{
217 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
218 u32 addr1, addr2;
219 u32 reg;
220 u32 mode;
221 u8 fast;
222
223 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
224 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400225
Jeff Garzik669a5db2006-08-29 18:12:40 -0400226 /* Fast interrupt prediction disable, hold off interrupt disable */
227 pci_read_config_byte(pdev, addr2, &fast);
228 fast &= ~0x07;
229 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400230
Jeff Garzik669a5db2006-08-29 18:12:40 -0400231 pci_read_config_dword(pdev, addr1, &reg);
232 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
233 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
234 mode &= ~0xC0000000; /* Leave config bits alone */
235 reg &= 0xC0000000; /* Strip timing bits */
236 pci_write_config_dword(pdev, addr1, reg | mode);
237}
238
239/**
240 * hpt3x2n_bmdma_end - DMA engine stop
241 * @qc: ATA command
242 *
243 * Clean up after the HPT3x2n and later DMA engine
244 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400245
Jeff Garzik669a5db2006-08-29 18:12:40 -0400246static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
247{
248 struct ata_port *ap = qc->ap;
249 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
250 int mscreg = 0x50 + 2 * ap->port_no;
251 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400252
Jeff Garzik669a5db2006-08-29 18:12:40 -0400253 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
254 pci_read_config_byte(pdev, mscreg, &msc_stat);
255 if (bwsr_stat & (1 << ap->port_no))
256 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
257 ata_bmdma_stop(qc);
258}
259
260/**
261 * hpt3x2n_set_clock - clock control
262 * @ap: ATA port
263 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
264 *
265 * Switch the ATA bus clock between the PLL and PCI clock sources
266 * while correctly isolating the bus and resetting internal logic
267 *
268 * We must use the DPLL for
269 * - writing
270 * - second channel UDMA7 (SATA ports) or higher
271 * - 66MHz PCI
Jeff Garzik85cd7252006-08-31 00:03:49 -0400272 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400273 * or we will underclock the device and get reduced performance.
274 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400275
Jeff Garzik669a5db2006-08-29 18:12:40 -0400276static void hpt3x2n_set_clock(struct ata_port *ap, int source)
277{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900278 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400279
Jeff Garzik669a5db2006-08-29 18:12:40 -0400280 /* Tristate the bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900281 iowrite8(0x80, bmdma+0x73);
282 iowrite8(0x80, bmdma+0x77);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400283
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 /* Switch clock and reset channels */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900285 iowrite8(source, bmdma+0x7B);
286 iowrite8(0xC0, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400287
Jeff Garzik669a5db2006-08-29 18:12:40 -0400288 /* Reset state machines */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900289 iowrite8(0x37, bmdma+0x70);
290 iowrite8(0x37, bmdma+0x74);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400291
Jeff Garzik669a5db2006-08-29 18:12:40 -0400292 /* Complete reset */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900293 iowrite8(0x00, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400294
Jeff Garzik669a5db2006-08-29 18:12:40 -0400295 /* Reconnect channels to bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900296 iowrite8(0x00, bmdma+0x73);
297 iowrite8(0x00, bmdma+0x77);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400298}
299
300/* Check if our partner interface is busy */
301
302static int hpt3x2n_pair_idle(struct ata_port *ap)
303{
304 struct ata_host *host = ap->host;
305 struct ata_port *pair = host->ports[ap->port_no ^ 1];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400306
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307 if (pair->hsm_task_state == HSM_ST_IDLE)
308 return 1;
309 return 0;
310}
311
Alana52865c2007-01-24 11:51:38 +0000312static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400313{
314 long flags = (long)ap->host->private_data;
315 /* See if we should use the DPLL */
Alana52865c2007-01-24 11:51:38 +0000316 if (writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400317 return USE_DPLL; /* Needed for write */
318 if (flags & PCI66)
319 return USE_DPLL; /* Needed at 66Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400320 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400321}
322
323static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc)
324{
325 struct ata_taskfile *tf = &qc->tf;
326 struct ata_port *ap = qc->ap;
327 int flags = (long)ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400328
Jeff Garzik669a5db2006-08-29 18:12:40 -0400329 if (hpt3x2n_pair_idle(ap)) {
330 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
331 if ((flags & USE_DPLL) != dpll) {
332 if (dpll == 1)
333 hpt3x2n_set_clock(ap, 0x21);
334 else
335 hpt3x2n_set_clock(ap, 0x23);
336 }
337 }
338 return ata_qc_issue_prot(qc);
339}
340
341static struct scsi_host_template hpt3x2n_sht = {
342 .module = THIS_MODULE,
343 .name = DRV_NAME,
344 .ioctl = ata_scsi_ioctl,
345 .queuecommand = ata_scsi_queuecmd,
346 .can_queue = ATA_DEF_QUEUE,
347 .this_id = ATA_SHT_THIS_ID,
348 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400349 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
350 .emulated = ATA_SHT_EMULATED,
351 .use_clustering = ATA_SHT_USE_CLUSTERING,
352 .proc_name = DRV_NAME,
353 .dma_boundary = ATA_DMA_BOUNDARY,
354 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900355 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400356 .bios_param = ata_std_bios_param,
357};
358
359/*
360 * Configuration for HPT3x2n.
361 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400362
Jeff Garzik669a5db2006-08-29 18:12:40 -0400363static struct ata_port_operations hpt3x2n_port_ops = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364 .set_piomode = hpt3x2n_set_piomode,
365 .set_dmamode = hpt3x2n_set_dmamode,
366 .mode_filter = ata_pci_default_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400367
Jeff Garzik669a5db2006-08-29 18:12:40 -0400368 .tf_load = ata_tf_load,
369 .tf_read = ata_tf_read,
370 .check_status = ata_check_status,
371 .exec_command = ata_exec_command,
372 .dev_select = ata_std_dev_select,
373
374 .freeze = ata_bmdma_freeze,
375 .thaw = ata_bmdma_thaw,
376 .error_handler = hpt3x2n_error_handler,
377 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500378 .cable_detect = hpt3x2n_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400379
380 .bmdma_setup = ata_bmdma_setup,
381 .bmdma_start = ata_bmdma_start,
382 .bmdma_stop = hpt3x2n_bmdma_stop,
383 .bmdma_status = ata_bmdma_status,
384
385 .qc_prep = ata_qc_prep,
386 .qc_issue = hpt3x2n_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400387
Tejun Heo0d5ff562007-02-01 15:06:36 +0900388 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400389
390 .irq_handler = ata_interrupt,
391 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900392 .irq_on = ata_irq_on,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400393
Alan Cox81ad1832007-08-22 22:55:41 +0100394 .port_start = ata_sff_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400395};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400396
397/**
398 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400399 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400400 *
401 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
402 * succeeds
403 */
404
405static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
406{
407 u8 reg5b;
408 u32 reg5c;
409 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400410
Jeff Garzik669a5db2006-08-29 18:12:40 -0400411 for(tries = 0; tries < 0x5000; tries++) {
412 udelay(50);
413 pci_read_config_byte(dev, 0x5b, &reg5b);
414 if (reg5b & 0x80) {
415 /* See if it stays set */
416 for(tries = 0; tries < 0x1000; tries ++) {
417 pci_read_config_byte(dev, 0x5b, &reg5b);
418 /* Failed ? */
419 if ((reg5b & 0x80) == 0)
420 return 0;
421 }
422 /* Turn off tuning, we have the DPLL set */
423 pci_read_config_dword(dev, 0x5c, &reg5c);
424 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
425 return 1;
426 }
427 }
428 /* Never went stable */
429 return 0;
430}
431
432static int hpt3x2n_pci_clock(struct pci_dev *pdev)
433{
434 unsigned long freq;
435 u32 fcnt;
Alan Cox28e21c82007-04-26 00:19:25 -0700436 unsigned long iobase = pci_resource_start(pdev, 4);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400437
Alan Cox28e21c82007-04-26 00:19:25 -0700438 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400439 if ((fcnt >> 12) != 0xABCDE) {
440 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
441 return 33; /* Not BIOS set */
442 }
443 fcnt &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400444
Jeff Garzik669a5db2006-08-29 18:12:40 -0400445 freq = (fcnt * 77) / 192;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400446
Jeff Garzik669a5db2006-08-29 18:12:40 -0400447 /* Clamp to bands */
448 if (freq < 40)
449 return 33;
450 if (freq < 45)
451 return 40;
452 if (freq < 55)
453 return 50;
454 return 66;
455}
456
457/**
458 * hpt3x2n_init_one - Initialise an HPT37X/302
459 * @dev: PCI device
460 * @id: Entry in match table
461 *
462 * Initialise an HPT3x2n device. There are some interesting complications
463 * here. Firstly the chip may report 366 and be one of several variants.
464 * Secondly all the timings depend on the clock for the chip which we must
465 * detect and look up
466 *
467 * This is the known chip mappings. It may be missing a couple of later
468 * releases.
469 *
470 * Chip version PCI Rev Notes
471 * HPT372 4 (HPT366) 5 Other driver
472 * HPT372N 4 (HPT366) 6 UDMA133
473 * HPT372 5 (HPT372) 1 Other driver
474 * HPT372N 5 (HPT372) 2 UDMA133
475 * HPT302 6 (HPT302) * Other driver
476 * HPT302N 6 (HPT302) > 1 UDMA133
477 * HPT371 7 (HPT371) * Other driver
478 * HPT371N 7 (HPT371) > 1 UDMA133
479 * HPT374 8 (HPT374) * Other driver
480 * HPT372N 9 (HPT372N) * UDMA133
481 *
482 * (1) UDMA133 support depends on the bus clock
483 *
484 * To pin down HPT371N
485 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400486
Jeff Garzik669a5db2006-08-29 18:12:40 -0400487static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
488{
489 /* HPT372N and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200490 static const struct ata_port_info info = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400491 .sht = &hpt3x2n_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400492 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400493 .pio_mask = 0x1f,
494 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400495 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400496 .port_ops = &hpt3x2n_port_ops
497 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200498 struct ata_port_info port = info;
499 const struct ata_port_info *ppi[] = { &port, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400500
501 u8 irqmask;
502 u32 class_rev;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400503
Jeff Garzik669a5db2006-08-29 18:12:40 -0400504 unsigned int pci_mhz;
505 unsigned int f_low, f_high;
506 int adjust;
Alan Cox28e21c82007-04-26 00:19:25 -0700507 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400508
Jeff Garzik669a5db2006-08-29 18:12:40 -0400509 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
510 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400511
Jeff Garzik669a5db2006-08-29 18:12:40 -0400512 switch(dev->device) {
513 case PCI_DEVICE_ID_TTI_HPT366:
514 if (class_rev < 6)
515 return -ENODEV;
516 break;
Alan Cox28e21c82007-04-26 00:19:25 -0700517 case PCI_DEVICE_ID_TTI_HPT371:
518 if (class_rev < 2)
519 return -ENODEV;
520 /* 371N if rev > 1 */
521 break;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400522 case PCI_DEVICE_ID_TTI_HPT372:
Alan Cox824cf332007-05-21 14:57:01 +0100523 /* 372N if rev >= 2*/
524 if (class_rev < 2)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400525 return -ENODEV;
526 break;
527 case PCI_DEVICE_ID_TTI_HPT302:
528 if (class_rev < 2)
529 return -ENODEV;
530 break;
531 case PCI_DEVICE_ID_TTI_HPT372N:
532 break;
533 default:
534 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
535 return -ENODEV;
536 }
537
538 /* Ok so this is a chip we support */
539
540 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
541 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
542 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
543 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
544
545 pci_read_config_byte(dev, 0x5A, &irqmask);
546 irqmask &= ~0x10;
547 pci_write_config_byte(dev, 0x5a, irqmask);
548
Alan Cox28e21c82007-04-26 00:19:25 -0700549 /*
550 * HPT371 chips physically have only one channel, the secondary one,
551 * but the primary channel registers do exist! Go figure...
552 * So, we manually disable the non-existing channel here
553 * (if the BIOS hasn't done this already).
554 */
555 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
556 u8 mcr1;
557 pci_read_config_byte(dev, 0x50, &mcr1);
558 mcr1 &= ~0x04;
559 pci_write_config_byte(dev, 0x50, mcr1);
560 }
561
Jeff Garzik669a5db2006-08-29 18:12:40 -0400562 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
563 50 for UDMA100. Right now we always use 66 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400564
Jeff Garzik669a5db2006-08-29 18:12:40 -0400565 pci_mhz = hpt3x2n_pci_clock(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400566
Jeff Garzik669a5db2006-08-29 18:12:40 -0400567 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
568 f_high = f_low + 2; /* Tolerance */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400569
Jeff Garzik669a5db2006-08-29 18:12:40 -0400570 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
571 /* PLL clock */
572 pci_write_config_byte(dev, 0x5B, 0x21);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400573
Jeff Garzik669a5db2006-08-29 18:12:40 -0400574 /* Unlike the 37x we don't try jiggling the frequency */
575 for(adjust = 0; adjust < 8; adjust++) {
576 if (hpt3xn_calibrate_dpll(dev))
577 break;
578 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
579 }
Alan Cox28e21c82007-04-26 00:19:25 -0700580 if (adjust == 8) {
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400581 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
Alan Cox28e21c82007-04-26 00:19:25 -0700582 return -ENODEV;
583 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400584
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400585 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
586 pci_mhz);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400587 /* Set our private data up. We only need a few flags so we use
588 it directly */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200589 port.private_data = NULL;
Alan Cox28e21c82007-04-26 00:19:25 -0700590 if (pci_mhz > 60) {
Tejun Heo1626aeb2007-05-04 12:43:58 +0200591 port.private_data = (void *)PCI66;
Alan Cox28e21c82007-04-26 00:19:25 -0700592 /*
593 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
594 * the MISC. register to stretch the UltraDMA Tss timing.
595 * NOTE: This register is only writeable via I/O space.
596 */
597 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
598 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
599 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400600
Jeff Garzik669a5db2006-08-29 18:12:40 -0400601 /* Now kick off ATA set up */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200602 return ata_pci_init_one(dev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400603}
604
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400605static const struct pci_device_id hpt3x2n[] = {
606 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Alan Cox28e21c82007-04-26 00:19:25 -0700607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
610 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
611
612 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400613};
614
615static struct pci_driver hpt3x2n_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400616 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400617 .id_table = hpt3x2n,
618 .probe = hpt3x2n_init_one,
619 .remove = ata_pci_remove_one
620};
621
622static int __init hpt3x2n_init(void)
623{
624 return pci_register_driver(&hpt3x2n_pci_driver);
625}
626
Jeff Garzik669a5db2006-08-29 18:12:40 -0400627static void __exit hpt3x2n_exit(void)
628{
629 pci_unregister_driver(&hpt3x2n_pci_driver);
630}
631
Jeff Garzik669a5db2006-08-29 18:12:40 -0400632MODULE_AUTHOR("Alan Cox");
633MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
634MODULE_LICENSE("GPL");
635MODULE_DEVICE_TABLE(pci, hpt3x2n);
636MODULE_VERSION(DRV_VERSION);
637
638module_init(hpt3x2n_init);
639module_exit(hpt3x2n_exit);