blob: 25c9a99c377b12142f5014b6e28216a7b5f5e55a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
38
39#include <linux/bitops.h>
40#include <linux/delay.h>
41#include <linux/ethtool.h>
42#include <asm/io.h>
43#include <asm/types.h>
44#include <asm/pgtable.h>
45#include <asm/system.h>
46#include <asm/delay.h>
47#include "mv643xx_eth.h"
48
49/*
50 * The first part is the high level driver of the gigE ethernet ports.
51 */
52
53/* Constants */
54#define VLAN_HLEN 4
55#define FCS_LEN 4
56#define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
57#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
58
59#define INT_CAUSE_UNMASK_ALL 0x0007ffff
60#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#define INT_CAUSE_MASK_ALL 0x00000000
Dale Farnsworth63c9e542005-09-02 13:49:10 -070062#define INT_CAUSE_MASK_ALL_EXT 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
64#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
66#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
67#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
68#else
69#define MAX_DESCS_PER_SKB 1
70#endif
71
72#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
73#define PHY_WAIT_MICRO_SECONDS 10
74
75/* Static function declarations */
76static int eth_port_link_is_up(unsigned int eth_port_num);
77static void eth_port_uc_addr_get(struct net_device *dev,
78 unsigned char *MacAddr);
79static int mv643xx_eth_real_open(struct net_device *);
80static int mv643xx_eth_real_stop(struct net_device *);
81static int mv643xx_eth_change_mtu(struct net_device *, int);
82static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
83static void eth_port_init_mac_tables(unsigned int eth_port_num);
84#ifdef MV643XX_NAPI
85static int mv643xx_poll(struct net_device *dev, int *budget);
86#endif
87static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
88static int ethernet_phy_detect(unsigned int eth_port_num);
89static struct ethtool_ops mv643xx_ethtool_ops;
90
91static char mv643xx_driver_name[] = "mv643xx_eth";
92static char mv643xx_driver_version[] = "1.0";
93
94static void __iomem *mv643xx_eth_shared_base;
95
96/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
Ingo Molnara9f6a0d2005-09-09 13:10:41 -070097static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99static inline u32 mv_read(int offset)
100{
Al Virodc074a82005-04-25 07:55:58 -0700101 void __iomem *reg_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
103 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
104
105 return readl(reg_base + offset);
106}
107
108static inline void mv_write(int offset, u32 data)
109{
Al Virodc074a82005-04-25 07:55:58 -0700110 void __iomem *reg_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111
112 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
113 writel(data, reg_base + offset);
114}
115
116/*
117 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
118 *
119 * Input : pointer to ethernet interface network device structure
120 * new mtu size
121 * Output : 0 upon success, -EINVAL upon failure
122 */
123static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
124{
125 struct mv643xx_private *mp = netdev_priv(dev);
126 unsigned long flags;
127
128 spin_lock_irqsave(&mp->lock, flags);
129
130 if ((new_mtu > 9500) || (new_mtu < 64)) {
131 spin_unlock_irqrestore(&mp->lock, flags);
132 return -EINVAL;
133 }
134
135 dev->mtu = new_mtu;
136 /*
137 * Stop then re-open the interface. This will allocate RX skb's with
138 * the new MTU.
139 * There is a possible danger that the open will not successed, due
140 * to memory is full, which might fail the open function.
141 */
142 if (netif_running(dev)) {
143 if (mv643xx_eth_real_stop(dev))
144 printk(KERN_ERR
145 "%s: Fatal error on stopping device\n",
146 dev->name);
147 if (mv643xx_eth_real_open(dev))
148 printk(KERN_ERR
149 "%s: Fatal error on opening device\n",
150 dev->name);
151 }
152
153 spin_unlock_irqrestore(&mp->lock, flags);
154 return 0;
155}
156
157/*
158 * mv643xx_eth_rx_task
159 *
160 * Fills / refills RX queue on a certain gigabit ethernet port
161 *
162 * Input : pointer to ethernet interface network device structure
163 * Output : N/A
164 */
165static void mv643xx_eth_rx_task(void *data)
166{
167 struct net_device *dev = (struct net_device *)data;
168 struct mv643xx_private *mp = netdev_priv(dev);
169 struct pkt_info pkt_info;
170 struct sk_buff *skb;
171
172 if (test_and_set_bit(0, &mp->rx_task_busy))
173 panic("%s: Error in test_set_bit / clear_bit", dev->name);
174
175 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
176 skb = dev_alloc_skb(RX_SKB_SIZE);
177 if (!skb)
178 break;
179 mp->rx_ring_skbs++;
180 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
181 pkt_info.byte_cnt = RX_SKB_SIZE;
182 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
183 DMA_FROM_DEVICE);
184 pkt_info.return_info = skb;
185 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
186 printk(KERN_ERR
187 "%s: Error allocating RX Ring\n", dev->name);
188 break;
189 }
190 skb_reserve(skb, 2);
191 }
192 clear_bit(0, &mp->rx_task_busy);
193 /*
194 * If RX ring is empty of SKB, set a timer to try allocating
195 * again in a later time .
196 */
197 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
198 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
199 /* After 100mSec */
200 mp->timeout.expires = jiffies + (HZ / 10);
201 add_timer(&mp->timeout);
202 mp->rx_timer_flag = 1;
203 }
204#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
205 else {
206 /* Return interrupts */
207 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
208 INT_CAUSE_UNMASK_ALL);
209 }
210#endif
211}
212
213/*
214 * mv643xx_eth_rx_task_timer_wrapper
215 *
216 * Timer routine to wake up RX queue filling task. This function is
217 * used only in case the RX queue is empty, and all alloc_skb has
218 * failed (due to out of memory event).
219 *
220 * Input : pointer to ethernet interface network device structure
221 * Output : N/A
222 */
223static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
224{
225 struct net_device *dev = (struct net_device *)data;
226 struct mv643xx_private *mp = netdev_priv(dev);
227
228 mp->rx_timer_flag = 0;
229 mv643xx_eth_rx_task((void *)data);
230}
231
232/*
233 * mv643xx_eth_update_mac_address
234 *
235 * Update the MAC address of the port in the address table
236 *
237 * Input : pointer to ethernet interface network device structure
238 * Output : N/A
239 */
240static void mv643xx_eth_update_mac_address(struct net_device *dev)
241{
242 struct mv643xx_private *mp = netdev_priv(dev);
243 unsigned int port_num = mp->port_num;
244
245 eth_port_init_mac_tables(port_num);
246 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
247 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
248}
249
250/*
251 * mv643xx_eth_set_rx_mode
252 *
253 * Change from promiscuos to regular rx mode
254 *
255 * Input : pointer to ethernet interface network device structure
256 * Output : N/A
257 */
258static void mv643xx_eth_set_rx_mode(struct net_device *dev)
259{
260 struct mv643xx_private *mp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 if (dev->flags & IFF_PROMISC)
Dale Farnsworth7342cd82005-09-02 12:36:48 -0700263 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 else
Dale Farnsworth7342cd82005-09-02 12:36:48 -0700265 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
266
267 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268}
269
270/*
271 * mv643xx_eth_set_mac_address
272 *
273 * Change the interface's mac address.
274 * No special hardware thing should be done because interface is always
275 * put in promiscuous mode.
276 *
277 * Input : pointer to ethernet interface network device structure and
278 * a pointer to the designated entry to be added to the cache.
279 * Output : zero upon success, negative upon failure
280 */
281static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
282{
283 int i;
284
285 for (i = 0; i < 6; i++)
286 /* +2 is for the offset of the HW addr type */
287 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
288 mv643xx_eth_update_mac_address(dev);
289 return 0;
290}
291
292/*
293 * mv643xx_eth_tx_timeout
294 *
295 * Called upon a timeout on transmitting a packet
296 *
297 * Input : pointer to ethernet interface network device structure.
298 * Output : N/A
299 */
300static void mv643xx_eth_tx_timeout(struct net_device *dev)
301{
302 struct mv643xx_private *mp = netdev_priv(dev);
303
304 printk(KERN_INFO "%s: TX timeout ", dev->name);
305
306 /* Do the reset outside of interrupt context */
307 schedule_work(&mp->tx_timeout_task);
308}
309
310/*
311 * mv643xx_eth_tx_timeout_task
312 *
313 * Actual routine to reset the adapter when a timeout on Tx has occurred
314 */
315static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
316{
317 struct mv643xx_private *mp = netdev_priv(dev);
318
319 netif_device_detach(dev);
320 eth_port_reset(mp->port_num);
321 eth_port_start(mp);
322 netif_device_attach(dev);
323}
324
325/*
326 * mv643xx_eth_free_tx_queue
327 *
328 * Input : dev - a pointer to the required interface
329 *
330 * Output : 0 if was able to release skb , nonzero otherwise
331 */
332static int mv643xx_eth_free_tx_queue(struct net_device *dev,
333 unsigned int eth_int_cause_ext)
334{
335 struct mv643xx_private *mp = netdev_priv(dev);
336 struct net_device_stats *stats = &mp->stats;
337 struct pkt_info pkt_info;
338 int released = 1;
339
340 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
341 return released;
342
343 spin_lock(&mp->lock);
344
345 /* Check only queue 0 */
346 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
347 if (pkt_info.cmd_sts & BIT0) {
348 printk("%s: Error in TX\n", dev->name);
349 stats->tx_errors++;
350 }
351
352 /*
353 * If return_info is different than 0, release the skb.
354 * The case where return_info is not 0 is only in case
355 * when transmitted a scatter/gather packet, where only
356 * last skb releases the whole chain.
357 */
358 if (pkt_info.return_info) {
359 if (skb_shinfo(pkt_info.return_info)->nr_frags)
360 dma_unmap_page(NULL, pkt_info.buf_ptr,
361 pkt_info.byte_cnt,
362 DMA_TO_DEVICE);
363 else
364 dma_unmap_single(NULL, pkt_info.buf_ptr,
365 pkt_info.byte_cnt,
366 DMA_TO_DEVICE);
367
368 dev_kfree_skb_irq(pkt_info.return_info);
369 released = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 } else
371 dma_unmap_page(NULL, pkt_info.buf_ptr,
372 pkt_info.byte_cnt, DMA_TO_DEVICE);
373 }
374
375 spin_unlock(&mp->lock);
376
377 return released;
378}
379
380/*
381 * mv643xx_eth_receive
382 *
383 * This function is forward packets that are received from the port's
384 * queues toward kernel core or FastRoute them to another interface.
385 *
386 * Input : dev - a pointer to the required interface
387 * max - maximum number to receive (0 means unlimted)
388 *
389 * Output : number of served packets
390 */
391#ifdef MV643XX_NAPI
392static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
393#else
394static int mv643xx_eth_receive_queue(struct net_device *dev)
395#endif
396{
397 struct mv643xx_private *mp = netdev_priv(dev);
398 struct net_device_stats *stats = &mp->stats;
399 unsigned int received_packets = 0;
400 struct sk_buff *skb;
401 struct pkt_info pkt_info;
402
403#ifdef MV643XX_NAPI
Dale Farnsworthb1dd9ca2005-09-01 09:59:23 -0700404 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405#else
406 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
407#endif
408 mp->rx_ring_skbs--;
409 received_packets++;
Dale Farnsworthb1dd9ca2005-09-01 09:59:23 -0700410
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 /* Update statistics. Note byte count includes 4 byte CRC count */
412 stats->rx_packets++;
413 stats->rx_bytes += pkt_info.byte_cnt;
414 skb = pkt_info.return_info;
415 /*
416 * In case received a packet without first / last bits on OR
417 * the error summary bit is on, the packets needs to be dropeed.
418 */
419 if (((pkt_info.cmd_sts
420 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
421 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
422 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
423 stats->rx_dropped++;
424 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
425 ETH_RX_LAST_DESC)) !=
426 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
427 if (net_ratelimit())
428 printk(KERN_ERR
429 "%s: Received packet spread "
430 "on multiple descriptors\n",
431 dev->name);
432 }
433 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
434 stats->rx_errors++;
435
436 dev_kfree_skb_irq(skb);
437 } else {
438 /*
439 * The -4 is for the CRC in the trailer of the
440 * received packet
441 */
442 skb_put(skb, pkt_info.byte_cnt - 4);
443 skb->dev = dev;
444
445 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
446 skb->ip_summed = CHECKSUM_UNNECESSARY;
447 skb->csum = htons(
448 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
449 }
450 skb->protocol = eth_type_trans(skb, dev);
451#ifdef MV643XX_NAPI
452 netif_receive_skb(skb);
453#else
454 netif_rx(skb);
455#endif
456 }
457 }
458
459 return received_packets;
460}
461
462/*
463 * mv643xx_eth_int_handler
464 *
465 * Main interrupt handler for the gigbit ethernet ports
466 *
467 * Input : irq - irq number (not used)
468 * dev_id - a pointer to the required interface's data structure
469 * regs - not used
470 * Output : N/A
471 */
472
473static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
474 struct pt_regs *regs)
475{
476 struct net_device *dev = (struct net_device *)dev_id;
477 struct mv643xx_private *mp = netdev_priv(dev);
478 u32 eth_int_cause, eth_int_cause_ext = 0;
479 unsigned int port_num = mp->port_num;
480
481 /* Read interrupt cause registers */
482 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
483 INT_CAUSE_UNMASK_ALL;
484
485 if (eth_int_cause & BIT1)
486 eth_int_cause_ext = mv_read(
487 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
488 INT_CAUSE_UNMASK_ALL_EXT;
489
490#ifdef MV643XX_NAPI
491 if (!(eth_int_cause & 0x0007fffd)) {
492 /* Dont ack the Rx interrupt */
493#endif
494 /*
495 * Clear specific ethernet port intrerrupt registers by
496 * acknowleding relevant bits.
497 */
498 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
499 ~eth_int_cause);
500 if (eth_int_cause_ext != 0x0)
501 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
502 (port_num), ~eth_int_cause_ext);
503
504 /* UDP change : We may need this */
505 if ((eth_int_cause_ext & 0x0000ffff) &&
506 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
507 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
508 netif_wake_queue(dev);
509#ifdef MV643XX_NAPI
510 } else {
511 if (netif_rx_schedule_prep(dev)) {
512 /* Mask all the interrupts */
513 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
514 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
515 (port_num), 0);
516 __netif_rx_schedule(dev);
517 }
518#else
519 if (eth_int_cause & (BIT2 | BIT11))
520 mv643xx_eth_receive_queue(dev, 0);
521
522 /*
523 * After forwarded received packets to upper layer, add a task
524 * in an interrupts enabled context that refills the RX ring
525 * with skb's.
526 */
527#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
528 /* Unmask all interrupts on ethernet port */
529 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
530 INT_CAUSE_MASK_ALL);
531 queue_task(&mp->rx_task, &tq_immediate);
532 mark_bh(IMMEDIATE_BH);
533#else
534 mp->rx_task.func(dev);
535#endif
536#endif
537 }
538 /* PHY status changed */
539 if (eth_int_cause_ext & (BIT16 | BIT20)) {
540 if (eth_port_link_is_up(port_num)) {
541 netif_carrier_on(dev);
542 netif_wake_queue(dev);
543 /* Start TX queue */
544 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
545 (port_num), 1);
546 } else {
547 netif_carrier_off(dev);
548 netif_stop_queue(dev);
549 }
550 }
551
552 /*
553 * If no real interrupt occured, exit.
554 * This can happen when using gigE interrupt coalescing mechanism.
555 */
556 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
557 return IRQ_NONE;
558
559 return IRQ_HANDLED;
560}
561
562#ifdef MV643XX_COAL
563
564/*
565 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
566 *
567 * DESCRIPTION:
568 * This routine sets the RX coalescing interrupt mechanism parameter.
569 * This parameter is a timeout counter, that counts in 64 t_clk
570 * chunks ; that when timeout event occurs a maskable interrupt
571 * occurs.
572 * The parameter is calculated using the tClk of the MV-643xx chip
573 * , and the required delay of the interrupt in usec.
574 *
575 * INPUT:
576 * unsigned int eth_port_num Ethernet port number
577 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
578 * unsigned int delay Delay in usec
579 *
580 * OUTPUT:
581 * Interrupt coalescing mechanism value is set in MV-643xx chip.
582 *
583 * RETURN:
584 * The interrupt coalescing value set in the gigE port.
585 *
586 */
587static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
588 unsigned int t_clk, unsigned int delay)
589{
590 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
591
592 /* Set RX Coalescing mechanism */
593 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
594 ((coal & 0x3fff) << 8) |
595 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
596 & 0xffc000ff));
597
598 return coal;
599}
600#endif
601
602/*
603 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
604 *
605 * DESCRIPTION:
606 * This routine sets the TX coalescing interrupt mechanism parameter.
607 * This parameter is a timeout counter, that counts in 64 t_clk
608 * chunks ; that when timeout event occurs a maskable interrupt
609 * occurs.
610 * The parameter is calculated using the t_cLK frequency of the
611 * MV-643xx chip and the required delay in the interrupt in uSec
612 *
613 * INPUT:
614 * unsigned int eth_port_num Ethernet port number
615 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
616 * unsigned int delay Delay in uSeconds
617 *
618 * OUTPUT:
619 * Interrupt coalescing mechanism value is set in MV-643xx chip.
620 *
621 * RETURN:
622 * The interrupt coalescing value set in the gigE port.
623 *
624 */
625static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
626 unsigned int t_clk, unsigned int delay)
627{
628 unsigned int coal;
629 coal = ((t_clk / 1000000) * delay) / 64;
630 /* Set TX Coalescing mechanism */
631 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
632 coal << 4);
633 return coal;
634}
635
636/*
637 * mv643xx_eth_open
638 *
639 * This function is called when openning the network device. The function
640 * should initialize all the hardware, initialize cyclic Rx/Tx
641 * descriptors chain and buffers and allocate an IRQ to the network
642 * device.
643 *
644 * Input : a pointer to the network device structure
645 *
646 * Output : zero of success , nonzero if fails.
647 */
648
649static int mv643xx_eth_open(struct net_device *dev)
650{
651 struct mv643xx_private *mp = netdev_priv(dev);
652 unsigned int port_num = mp->port_num;
653 int err;
654
655 spin_lock_irq(&mp->lock);
656
657 err = request_irq(dev->irq, mv643xx_eth_int_handler,
Benjamin Herrenschmidt16b81752005-04-16 15:24:30 -0700658 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659
660 if (err) {
661 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
662 port_num);
663 err = -EAGAIN;
664 goto out;
665 }
666
667 if (mv643xx_eth_real_open(dev)) {
668 printk("%s: Error opening interface\n", dev->name);
669 err = -EBUSY;
670 goto out_free;
671 }
672
673 spin_unlock_irq(&mp->lock);
674
675 return 0;
676
677out_free:
678 free_irq(dev->irq, dev);
679
680out:
681 spin_unlock_irq(&mp->lock);
682
683 return err;
684}
685
686/*
687 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
688 *
689 * DESCRIPTION:
690 * This function prepares a Rx chained list of descriptors and packet
691 * buffers in a form of a ring. The routine must be called after port
692 * initialization routine and before port start routine.
693 * The Ethernet SDMA engine uses CPU bus addresses to access the various
694 * devices in the system (i.e. DRAM). This function uses the ethernet
695 * struct 'virtual to physical' routine (set by the user) to set the ring
696 * with physical addresses.
697 *
698 * INPUT:
699 * struct mv643xx_private *mp Ethernet Port Control srtuct.
700 *
701 * OUTPUT:
702 * The routine updates the Ethernet port control struct with information
703 * regarding the Rx descriptors and buffers.
704 *
705 * RETURN:
706 * None.
707 */
708static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
709{
710 volatile struct eth_rx_desc *p_rx_desc;
711 int rx_desc_num = mp->rx_ring_size;
712 int i;
713
714 /* initialize the next_desc_ptr links in the Rx descriptors ring */
715 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
716 for (i = 0; i < rx_desc_num; i++) {
717 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
718 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
719 }
720
721 /* Save Rx desc pointer to driver struct. */
722 mp->rx_curr_desc_q = 0;
723 mp->rx_used_desc_q = 0;
724
725 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
726
727 /* Add the queue to the list of RX queues of this port */
728 mp->port_rx_queue_command |= 1;
729}
730
731/*
732 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
733 *
734 * DESCRIPTION:
735 * This function prepares a Tx chained list of descriptors and packet
736 * buffers in a form of a ring. The routine must be called after port
737 * initialization routine and before port start routine.
738 * The Ethernet SDMA engine uses CPU bus addresses to access the various
739 * devices in the system (i.e. DRAM). This function uses the ethernet
740 * struct 'virtual to physical' routine (set by the user) to set the ring
741 * with physical addresses.
742 *
743 * INPUT:
744 * struct mv643xx_private *mp Ethernet Port Control srtuct.
745 *
746 * OUTPUT:
747 * The routine updates the Ethernet port control struct with information
748 * regarding the Tx descriptors and buffers.
749 *
750 * RETURN:
751 * None.
752 */
753static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
754{
755 int tx_desc_num = mp->tx_ring_size;
756 struct eth_tx_desc *p_tx_desc;
757 int i;
758
759 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
760 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
761 for (i = 0; i < tx_desc_num; i++) {
762 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
763 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
764 }
765
766 mp->tx_curr_desc_q = 0;
767 mp->tx_used_desc_q = 0;
768#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
769 mp->tx_first_desc_q = 0;
770#endif
771
772 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
773
774 /* Add the queue to the list of Tx queues of this port */
775 mp->port_tx_queue_command |= 1;
776}
777
778/* Helper function for mv643xx_eth_open */
779static int mv643xx_eth_real_open(struct net_device *dev)
780{
781 struct mv643xx_private *mp = netdev_priv(dev);
782 unsigned int port_num = mp->port_num;
783 unsigned int size;
784
785 /* Stop RX Queues */
786 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
787
788 /* Clear the ethernet port interrupts */
789 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
790 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
791
792 /* Unmask RX buffer and TX end interrupt */
793 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
794 INT_CAUSE_UNMASK_ALL);
795
796 /* Unmask phy and link status changes interrupts */
797 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
798 INT_CAUSE_UNMASK_ALL_EXT);
799
800 /* Set the MAC Address */
801 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
802
803 eth_port_init(mp);
804
805 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
806
807 memset(&mp->timeout, 0, sizeof(struct timer_list));
808 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
809 mp->timeout.data = (unsigned long)dev;
810
811 mp->rx_task_busy = 0;
812 mp->rx_timer_flag = 0;
813
814 /* Allocate RX and TX skb rings */
815 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
816 GFP_KERNEL);
817 if (!mp->rx_skb) {
818 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
819 return -ENOMEM;
820 }
821 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
822 GFP_KERNEL);
823 if (!mp->tx_skb) {
824 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
825 kfree(mp->rx_skb);
826 return -ENOMEM;
827 }
828
829 /* Allocate TX ring */
830 mp->tx_ring_skbs = 0;
831 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
832 mp->tx_desc_area_size = size;
833
834 if (mp->tx_sram_size) {
835 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
836 mp->tx_sram_size);
837 mp->tx_desc_dma = mp->tx_sram_addr;
838 } else
839 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
840 &mp->tx_desc_dma,
841 GFP_KERNEL);
842
843 if (!mp->p_tx_desc_area) {
844 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
845 dev->name, size);
846 kfree(mp->rx_skb);
847 kfree(mp->tx_skb);
848 return -ENOMEM;
849 }
850 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
851 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
852
853 ether_init_tx_desc_ring(mp);
854
855 /* Allocate RX ring */
856 mp->rx_ring_skbs = 0;
857 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
858 mp->rx_desc_area_size = size;
859
860 if (mp->rx_sram_size) {
861 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
862 mp->rx_sram_size);
863 mp->rx_desc_dma = mp->rx_sram_addr;
864 } else
865 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
866 &mp->rx_desc_dma,
867 GFP_KERNEL);
868
869 if (!mp->p_rx_desc_area) {
870 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
871 dev->name, size);
872 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
873 dev->name);
874 if (mp->rx_sram_size)
875 iounmap(mp->p_rx_desc_area);
876 else
877 dma_free_coherent(NULL, mp->tx_desc_area_size,
878 mp->p_tx_desc_area, mp->tx_desc_dma);
879 kfree(mp->rx_skb);
880 kfree(mp->tx_skb);
881 return -ENOMEM;
882 }
883 memset((void *)mp->p_rx_desc_area, 0, size);
884
885 ether_init_rx_desc_ring(mp);
886
887 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
888
889 eth_port_start(mp);
890
891 /* Interrupt Coalescing */
892
893#ifdef MV643XX_COAL
894 mp->rx_int_coal =
895 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
896#endif
897
898 mp->tx_int_coal =
899 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
900
901 netif_start_queue(dev);
902
903 return 0;
904}
905
906static void mv643xx_eth_free_tx_rings(struct net_device *dev)
907{
908 struct mv643xx_private *mp = netdev_priv(dev);
909 unsigned int port_num = mp->port_num;
910 unsigned int curr;
911
912 /* Stop Tx Queues */
913 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
914
915 /* Free outstanding skb's on TX rings */
916 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
917 if (mp->tx_skb[curr]) {
918 dev_kfree_skb(mp->tx_skb[curr]);
919 mp->tx_ring_skbs--;
920 }
921 }
922 if (mp->tx_ring_skbs)
923 printk("%s: Error on Tx descriptor free - could not free %d"
924 " descriptors\n", dev->name, mp->tx_ring_skbs);
925
926 /* Free TX ring */
927 if (mp->tx_sram_size)
928 iounmap(mp->p_tx_desc_area);
929 else
930 dma_free_coherent(NULL, mp->tx_desc_area_size,
931 mp->p_tx_desc_area, mp->tx_desc_dma);
932}
933
934static void mv643xx_eth_free_rx_rings(struct net_device *dev)
935{
936 struct mv643xx_private *mp = netdev_priv(dev);
937 unsigned int port_num = mp->port_num;
938 int curr;
939
940 /* Stop RX Queues */
941 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
942
943 /* Free preallocated skb's on RX rings */
944 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
945 if (mp->rx_skb[curr]) {
946 dev_kfree_skb(mp->rx_skb[curr]);
947 mp->rx_ring_skbs--;
948 }
949 }
950
951 if (mp->rx_ring_skbs)
952 printk(KERN_ERR
953 "%s: Error in freeing Rx Ring. %d skb's still"
954 " stuck in RX Ring - ignoring them\n", dev->name,
955 mp->rx_ring_skbs);
956 /* Free RX ring */
957 if (mp->rx_sram_size)
958 iounmap(mp->p_rx_desc_area);
959 else
960 dma_free_coherent(NULL, mp->rx_desc_area_size,
961 mp->p_rx_desc_area, mp->rx_desc_dma);
962}
963
964/*
965 * mv643xx_eth_stop
966 *
967 * This function is used when closing the network device.
968 * It updates the hardware,
969 * release all memory that holds buffers and descriptors and release the IRQ.
970 * Input : a pointer to the device structure
971 * Output : zero if success , nonzero if fails
972 */
973
974/* Helper function for mv643xx_eth_stop */
975
976static int mv643xx_eth_real_stop(struct net_device *dev)
977{
978 struct mv643xx_private *mp = netdev_priv(dev);
979 unsigned int port_num = mp->port_num;
980
981 netif_carrier_off(dev);
982 netif_stop_queue(dev);
983
984 mv643xx_eth_free_tx_rings(dev);
985 mv643xx_eth_free_rx_rings(dev);
986
987 eth_port_reset(mp->port_num);
988
989 /* Disable ethernet port interrupts */
990 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
991 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
992
993 /* Mask RX buffer and TX end interrupt */
994 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
995
996 /* Mask phy and link status changes interrupts */
997 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
998
999 return 0;
1000}
1001
1002static int mv643xx_eth_stop(struct net_device *dev)
1003{
1004 struct mv643xx_private *mp = netdev_priv(dev);
1005
1006 spin_lock_irq(&mp->lock);
1007
1008 mv643xx_eth_real_stop(dev);
1009
1010 free_irq(dev->irq, dev);
1011 spin_unlock_irq(&mp->lock);
1012
1013 return 0;
1014}
1015
1016#ifdef MV643XX_NAPI
1017static void mv643xx_tx(struct net_device *dev)
1018{
1019 struct mv643xx_private *mp = netdev_priv(dev);
1020 struct pkt_info pkt_info;
1021
1022 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1023 if (pkt_info.return_info) {
1024 if (skb_shinfo(pkt_info.return_info)->nr_frags)
1025 dma_unmap_page(NULL, pkt_info.buf_ptr,
1026 pkt_info.byte_cnt,
1027 DMA_TO_DEVICE);
1028 else
1029 dma_unmap_single(NULL, pkt_info.buf_ptr,
1030 pkt_info.byte_cnt,
1031 DMA_TO_DEVICE);
1032
1033 dev_kfree_skb_irq(pkt_info.return_info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 } else
1035 dma_unmap_page(NULL, pkt_info.buf_ptr,
1036 pkt_info.byte_cnt, DMA_TO_DEVICE);
1037 }
1038
1039 if (netif_queue_stopped(dev) &&
1040 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1041 netif_wake_queue(dev);
1042}
1043
1044/*
1045 * mv643xx_poll
1046 *
1047 * This function is used in case of NAPI
1048 */
1049static int mv643xx_poll(struct net_device *dev, int *budget)
1050{
1051 struct mv643xx_private *mp = netdev_priv(dev);
1052 int done = 1, orig_budget, work_done;
1053 unsigned int port_num = mp->port_num;
1054 unsigned long flags;
1055
1056#ifdef MV643XX_TX_FAST_REFILL
1057 if (++mp->tx_clean_threshold > 5) {
1058 spin_lock_irqsave(&mp->lock, flags);
1059 mv643xx_tx(dev);
1060 mp->tx_clean_threshold = 0;
1061 spin_unlock_irqrestore(&mp->lock, flags);
1062 }
1063#endif
1064
1065 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1066 != (u32) mp->rx_used_desc_q) {
1067 orig_budget = *budget;
1068 if (orig_budget > dev->quota)
1069 orig_budget = dev->quota;
1070 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1071 mp->rx_task.func(dev);
1072 *budget -= work_done;
1073 dev->quota -= work_done;
1074 if (work_done >= orig_budget)
1075 done = 0;
1076 }
1077
1078 if (done) {
1079 spin_lock_irqsave(&mp->lock, flags);
1080 __netif_rx_complete(dev);
1081 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1082 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1083 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1084 INT_CAUSE_UNMASK_ALL);
1085 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1086 INT_CAUSE_UNMASK_ALL_EXT);
1087 spin_unlock_irqrestore(&mp->lock, flags);
1088 }
1089
1090 return done ? 0 : 1;
1091}
1092#endif
1093
1094/*
1095 * mv643xx_eth_start_xmit
1096 *
1097 * This function is queues a packet in the Tx descriptor for
1098 * required port.
1099 *
1100 * Input : skb - a pointer to socket buffer
1101 * dev - a pointer to the required port
1102 *
1103 * Output : zero upon success
1104 */
1105static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1106{
1107 struct mv643xx_private *mp = netdev_priv(dev);
1108 struct net_device_stats *stats = &mp->stats;
1109 ETH_FUNC_RET_STATUS status;
1110 unsigned long flags;
1111 struct pkt_info pkt_info;
1112
1113 if (netif_queue_stopped(dev)) {
1114 printk(KERN_ERR
1115 "%s: Tried sending packet when interface is stopped\n",
1116 dev->name);
1117 return 1;
1118 }
1119
1120 /* This is a hard error, log it. */
1121 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1122 (skb_shinfo(skb)->nr_frags + 1)) {
1123 netif_stop_queue(dev);
1124 printk(KERN_ERR
1125 "%s: Bug in mv643xx_eth - Trying to transmit when"
1126 " queue full !\n", dev->name);
1127 return 1;
1128 }
1129
1130 /* Paranoid check - this shouldn't happen */
1131 if (skb == NULL) {
1132 stats->tx_dropped++;
1133 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1134 return 1;
1135 }
1136
1137 spin_lock_irqsave(&mp->lock, flags);
1138
1139 /* Update packet info data structure -- DMA owned, first last */
1140#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1141 if (!skb_shinfo(skb)->nr_frags) {
1142linear:
1143 if (skb->ip_summed != CHECKSUM_HW) {
Dale Farnsworth26006362005-08-22 15:53:29 -07001144 /* Errata BTS #50, IHL must be 5 if no HW checksum */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
Dale Farnsworth26006362005-08-22 15:53:29 -07001146 ETH_TX_FIRST_DESC |
1147 ETH_TX_LAST_DESC |
1148 5 << ETH_TX_IHL_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 pkt_info.l4i_chk = 0;
1150 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151
1152 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
Dale Farnsworth26006362005-08-22 15:53:29 -07001153 ETH_TX_FIRST_DESC |
1154 ETH_TX_LAST_DESC |
1155 ETH_GEN_TCP_UDP_CHECKSUM |
1156 ETH_GEN_IP_V_4_CHECKSUM |
1157 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158 /* CPU already calculated pseudo header checksum. */
1159 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1160 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1161 pkt_info.l4i_chk = skb->h.uh->check;
1162 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1163 pkt_info.l4i_chk = skb->h.th->check;
1164 else {
1165 printk(KERN_ERR
1166 "%s: chksum proto != TCP or UDP\n",
1167 dev->name);
1168 spin_unlock_irqrestore(&mp->lock, flags);
1169 return 1;
1170 }
1171 }
1172 pkt_info.byte_cnt = skb->len;
1173 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1174 DMA_TO_DEVICE);
1175 pkt_info.return_info = skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 status = eth_port_send(mp, &pkt_info);
1177 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1178 printk(KERN_ERR "%s: Error on transmitting packet\n",
1179 dev->name);
1180 stats->tx_bytes += pkt_info.byte_cnt;
1181 } else {
1182 unsigned int frag;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183
1184 /* Since hardware can't handle unaligned fragments smaller
1185 * than 9 bytes, if we find any, we linearize the skb
1186 * and start again. When I've seen it, it's always been
1187 * the first frag (probably near the end of the page),
1188 * but we check all frags to be safe.
1189 */
1190 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1191 skb_frag_t *fragp;
1192
1193 fragp = &skb_shinfo(skb)->frags[frag];
1194 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1195 skb_linearize(skb, GFP_ATOMIC);
1196 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1197 "%d of %d, fixed\n",
1198 dev->name, frag,
1199 skb_shinfo(skb)->nr_frags);
1200 goto linear;
1201 }
1202 }
1203
1204 /* first frag which is skb header */
1205 pkt_info.byte_cnt = skb_headlen(skb);
1206 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1207 skb_headlen(skb),
1208 DMA_TO_DEVICE);
1209 pkt_info.l4i_chk = 0;
1210 pkt_info.return_info = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211
Dale Farnsworth26006362005-08-22 15:53:29 -07001212 if (skb->ip_summed != CHECKSUM_HW)
1213 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1214 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1215 5 << ETH_TX_IHL_SHIFT;
1216 else {
1217 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1218 ETH_GEN_TCP_UDP_CHECKSUM |
1219 ETH_GEN_IP_V_4_CHECKSUM |
1220 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 /* CPU already calculated pseudo header checksum. */
1222 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1223 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1224 pkt_info.l4i_chk = skb->h.uh->check;
1225 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1226 pkt_info.l4i_chk = skb->h.th->check;
1227 else {
1228 printk(KERN_ERR
1229 "%s: chksum proto != TCP or UDP\n",
1230 dev->name);
1231 spin_unlock_irqrestore(&mp->lock, flags);
1232 return 1;
1233 }
1234 }
1235
1236 status = eth_port_send(mp, &pkt_info);
1237 if (status != ETH_OK) {
1238 if ((status == ETH_ERROR))
1239 printk(KERN_ERR
1240 "%s: Error on transmitting packet\n",
1241 dev->name);
1242 if (status == ETH_QUEUE_FULL)
1243 printk("Error on Queue Full \n");
1244 if (status == ETH_QUEUE_LAST_RESOURCE)
1245 printk("Tx resource error \n");
1246 }
1247 stats->tx_bytes += pkt_info.byte_cnt;
1248
1249 /* Check for the remaining frags */
1250 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1251 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1252 pkt_info.l4i_chk = 0x0000;
1253 pkt_info.cmd_sts = 0x00000000;
1254
1255 /* Last Frag enables interrupt and frees the skb */
1256 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1257 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1258 ETH_TX_LAST_DESC;
1259 pkt_info.return_info = skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260 } else {
1261 pkt_info.return_info = 0;
1262 }
1263 pkt_info.l4i_chk = 0;
1264 pkt_info.byte_cnt = this_frag->size;
1265
1266 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1267 this_frag->page_offset,
1268 this_frag->size,
1269 DMA_TO_DEVICE);
1270
1271 status = eth_port_send(mp, &pkt_info);
1272
1273 if (status != ETH_OK) {
1274 if ((status == ETH_ERROR))
1275 printk(KERN_ERR "%s: Error on "
1276 "transmitting packet\n",
1277 dev->name);
1278
1279 if (status == ETH_QUEUE_LAST_RESOURCE)
1280 printk("Tx resource error \n");
1281
1282 if (status == ETH_QUEUE_FULL)
1283 printk("Queue is full \n");
1284 }
1285 stats->tx_bytes += pkt_info.byte_cnt;
1286 }
1287 }
1288#else
1289 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1290 ETH_TX_LAST_DESC;
1291 pkt_info.l4i_chk = 0;
1292 pkt_info.byte_cnt = skb->len;
1293 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1294 DMA_TO_DEVICE);
1295 pkt_info.return_info = skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296 status = eth_port_send(mp, &pkt_info);
1297 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1298 printk(KERN_ERR "%s: Error on transmitting packet\n",
1299 dev->name);
1300 stats->tx_bytes += pkt_info.byte_cnt;
1301#endif
1302
1303 /* Check if TX queue can handle another skb. If not, then
1304 * signal higher layers to stop requesting TX
1305 */
1306 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1307 /*
1308 * Stop getting skb's from upper layers.
1309 * Getting skb's from upper layers will be enabled again after
1310 * packets are released.
1311 */
1312 netif_stop_queue(dev);
1313
1314 /* Update statistics and start of transmittion time */
1315 stats->tx_packets++;
1316 dev->trans_start = jiffies;
1317
1318 spin_unlock_irqrestore(&mp->lock, flags);
1319
1320 return 0; /* success */
1321}
1322
1323/*
1324 * mv643xx_eth_get_stats
1325 *
1326 * Returns a pointer to the interface statistics.
1327 *
1328 * Input : dev - a pointer to the required interface
1329 *
1330 * Output : a pointer to the interface's statistics
1331 */
1332
1333static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1334{
1335 struct mv643xx_private *mp = netdev_priv(dev);
1336
1337 return &mp->stats;
1338}
1339
Dale Farnsworth63c9e542005-09-02 13:49:10 -07001340#ifdef CONFIG_NET_POLL_CONTROLLER
1341static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1342{
1343 int port_num = mp->port_num;
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&mp->lock, flags);
1347 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1348 INT_CAUSE_UNMASK_ALL);
1349 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1350 INT_CAUSE_UNMASK_ALL_EXT);
1351 spin_unlock_irqrestore(&mp->lock, flags);
1352}
1353
1354static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1355{
1356 int port_num = mp->port_num;
1357 unsigned long flags;
1358
1359 spin_lock_irqsave(&mp->lock, flags);
1360 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1361 INT_CAUSE_MASK_ALL);
1362 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1363 INT_CAUSE_MASK_ALL_EXT);
1364 spin_unlock_irqrestore(&mp->lock, flags);
1365}
1366
1367static void mv643xx_netpoll(struct net_device *netdev)
1368{
1369 struct mv643xx_private *mp = netdev_priv(netdev);
1370
1371 mv643xx_disable_irq(mp);
1372 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1373 mv643xx_enable_irq(mp);
1374}
1375#endif
1376
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377/*/
1378 * mv643xx_eth_probe
1379 *
1380 * First function called after registering the network device.
1381 * It's purpose is to initialize the device as an ethernet device,
1382 * fill the ethernet device structure with pointers * to functions,
1383 * and set the MAC address of the interface
1384 *
1385 * Input : struct device *
1386 * Output : -ENOMEM if failed , 0 if success
1387 */
1388static int mv643xx_eth_probe(struct device *ddev)
1389{
1390 struct platform_device *pdev = to_platform_device(ddev);
1391 struct mv643xx_eth_platform_data *pd;
1392 int port_num = pdev->id;
1393 struct mv643xx_private *mp;
1394 struct net_device *dev;
1395 u8 *p;
1396 struct resource *res;
1397 int err;
1398
1399 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1400 if (!dev)
1401 return -ENOMEM;
1402
1403 dev_set_drvdata(ddev, dev);
1404
1405 mp = netdev_priv(dev);
1406
1407 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1408 BUG_ON(!res);
1409 dev->irq = res->start;
1410
1411 mp->port_num = port_num;
1412
1413 dev->open = mv643xx_eth_open;
1414 dev->stop = mv643xx_eth_stop;
1415 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1416 dev->get_stats = mv643xx_eth_get_stats;
1417 dev->set_mac_address = mv643xx_eth_set_mac_address;
1418 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1419
1420 /* No need to Tx Timeout */
1421 dev->tx_timeout = mv643xx_eth_tx_timeout;
1422#ifdef MV643XX_NAPI
1423 dev->poll = mv643xx_poll;
1424 dev->weight = 64;
1425#endif
1426
Dale Farnsworth63c9e542005-09-02 13:49:10 -07001427#ifdef CONFIG_NET_POLL_CONTROLLER
1428 dev->poll_controller = mv643xx_netpoll;
1429#endif
1430
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431 dev->watchdog_timeo = 2 * HZ;
1432 dev->tx_queue_len = mp->tx_ring_size;
1433 dev->base_addr = 0;
1434 dev->change_mtu = mv643xx_eth_change_mtu;
1435 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1436
1437#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1438#ifdef MAX_SKB_FRAGS
1439 /*
1440 * Zero copy can only work if we use Discovery II memory. Else, we will
1441 * have to map the buffers to ISA memory which is only 16 MB
1442 */
1443 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1444#endif
1445#endif
1446
1447 /* Configure the timeout task */
1448 INIT_WORK(&mp->tx_timeout_task,
1449 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1450
1451 spin_lock_init(&mp->lock);
1452
1453 /* set default config values */
1454 eth_port_uc_addr_get(dev, dev->dev_addr);
1455 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1456 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1457 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1458 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1459 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1460 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1461
1462 pd = pdev->dev.platform_data;
1463 if (pd) {
1464 if (pd->mac_addr != NULL)
1465 memcpy(dev->dev_addr, pd->mac_addr, 6);
1466
1467 if (pd->phy_addr || pd->force_phy_addr)
1468 ethernet_phy_set(port_num, pd->phy_addr);
1469
1470 if (pd->port_config || pd->force_port_config)
1471 mp->port_config = pd->port_config;
1472
1473 if (pd->port_config_extend || pd->force_port_config_extend)
1474 mp->port_config_extend = pd->port_config_extend;
1475
1476 if (pd->port_sdma_config || pd->force_port_sdma_config)
1477 mp->port_sdma_config = pd->port_sdma_config;
1478
1479 if (pd->port_serial_control || pd->force_port_serial_control)
1480 mp->port_serial_control = pd->port_serial_control;
1481
1482 if (pd->rx_queue_size)
1483 mp->rx_ring_size = pd->rx_queue_size;
1484
1485 if (pd->tx_queue_size)
1486 mp->tx_ring_size = pd->tx_queue_size;
1487
1488 if (pd->tx_sram_size) {
1489 mp->tx_sram_size = pd->tx_sram_size;
1490 mp->tx_sram_addr = pd->tx_sram_addr;
1491 }
1492
1493 if (pd->rx_sram_size) {
1494 mp->rx_sram_size = pd->rx_sram_size;
1495 mp->rx_sram_addr = pd->rx_sram_addr;
1496 }
1497 }
1498
1499 err = ethernet_phy_detect(port_num);
1500 if (err) {
1501 pr_debug("MV643xx ethernet port %d: "
1502 "No PHY detected at addr %d\n",
1503 port_num, ethernet_phy_get(port_num));
1504 return err;
1505 }
1506
1507 err = register_netdev(dev);
1508 if (err)
1509 goto out;
1510
1511 p = dev->dev_addr;
1512 printk(KERN_NOTICE
1513 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1514 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1515
1516 if (dev->features & NETIF_F_SG)
1517 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1518
1519 if (dev->features & NETIF_F_IP_CSUM)
1520 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1521 dev->name);
1522
1523#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1524 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1525#endif
1526
1527#ifdef MV643XX_COAL
1528 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1529 dev->name);
1530#endif
1531
1532#ifdef MV643XX_NAPI
1533 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1534#endif
1535
1536 return 0;
1537
1538out:
1539 free_netdev(dev);
1540
1541 return err;
1542}
1543
1544static int mv643xx_eth_remove(struct device *ddev)
1545{
1546 struct net_device *dev = dev_get_drvdata(ddev);
1547
1548 unregister_netdev(dev);
1549 flush_scheduled_work();
1550
1551 free_netdev(dev);
1552 dev_set_drvdata(ddev, NULL);
1553 return 0;
1554}
1555
1556static int mv643xx_eth_shared_probe(struct device *ddev)
1557{
1558 struct platform_device *pdev = to_platform_device(ddev);
1559 struct resource *res;
1560
1561 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1562
1563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1564 if (res == NULL)
1565 return -ENODEV;
1566
1567 mv643xx_eth_shared_base = ioremap(res->start,
1568 MV643XX_ETH_SHARED_REGS_SIZE);
1569 if (mv643xx_eth_shared_base == NULL)
1570 return -ENOMEM;
1571
1572 return 0;
1573
1574}
1575
1576static int mv643xx_eth_shared_remove(struct device *ddev)
1577{
1578 iounmap(mv643xx_eth_shared_base);
1579 mv643xx_eth_shared_base = NULL;
1580
1581 return 0;
1582}
1583
1584static struct device_driver mv643xx_eth_driver = {
1585 .name = MV643XX_ETH_NAME,
1586 .bus = &platform_bus_type,
1587 .probe = mv643xx_eth_probe,
1588 .remove = mv643xx_eth_remove,
1589};
1590
1591static struct device_driver mv643xx_eth_shared_driver = {
1592 .name = MV643XX_ETH_SHARED_NAME,
1593 .bus = &platform_bus_type,
1594 .probe = mv643xx_eth_shared_probe,
1595 .remove = mv643xx_eth_shared_remove,
1596};
1597
1598/*
1599 * mv643xx_init_module
1600 *
1601 * Registers the network drivers into the Linux kernel
1602 *
1603 * Input : N/A
1604 *
1605 * Output : N/A
1606 */
1607static int __init mv643xx_init_module(void)
1608{
1609 int rc;
1610
1611 rc = driver_register(&mv643xx_eth_shared_driver);
1612 if (!rc) {
1613 rc = driver_register(&mv643xx_eth_driver);
1614 if (rc)
1615 driver_unregister(&mv643xx_eth_shared_driver);
1616 }
1617 return rc;
1618}
1619
1620/*
1621 * mv643xx_cleanup_module
1622 *
1623 * Registers the network drivers into the Linux kernel
1624 *
1625 * Input : N/A
1626 *
1627 * Output : N/A
1628 */
1629static void __exit mv643xx_cleanup_module(void)
1630{
1631 driver_unregister(&mv643xx_eth_driver);
1632 driver_unregister(&mv643xx_eth_shared_driver);
1633}
1634
1635module_init(mv643xx_init_module);
1636module_exit(mv643xx_cleanup_module);
1637
1638MODULE_LICENSE("GPL");
1639MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1640 " and Dale Farnsworth");
1641MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1642
1643/*
1644 * The second part is the low level driver of the gigE ethernet ports.
1645 */
1646
1647/*
1648 * Marvell's Gigabit Ethernet controller low level driver
1649 *
1650 * DESCRIPTION:
1651 * This file introduce low level API to Marvell's Gigabit Ethernet
1652 * controller. This Gigabit Ethernet Controller driver API controls
1653 * 1) Operations (i.e. port init, start, reset etc').
1654 * 2) Data flow (i.e. port send, receive etc').
1655 * Each Gigabit Ethernet port is controlled via
1656 * struct mv643xx_private.
1657 * This struct includes user configuration information as well as
1658 * driver internal data needed for its operations.
1659 *
1660 * Supported Features:
1661 * - This low level driver is OS independent. Allocating memory for
1662 * the descriptor rings and buffers are not within the scope of
1663 * this driver.
1664 * - The user is free from Rx/Tx queue managing.
1665 * - This low level driver introduce functionality API that enable
1666 * the to operate Marvell's Gigabit Ethernet Controller in a
1667 * convenient way.
1668 * - Simple Gigabit Ethernet port operation API.
1669 * - Simple Gigabit Ethernet port data flow API.
1670 * - Data flow and operation API support per queue functionality.
1671 * - Support cached descriptors for better performance.
1672 * - Enable access to all four DRAM banks and internal SRAM memory
1673 * spaces.
1674 * - PHY access and control API.
1675 * - Port control register configuration API.
1676 * - Full control over Unicast and Multicast MAC configurations.
1677 *
1678 * Operation flow:
1679 *
1680 * Initialization phase
1681 * This phase complete the initialization of the the
1682 * mv643xx_private struct.
1683 * User information regarding port configuration has to be set
1684 * prior to calling the port initialization routine.
1685 *
1686 * In this phase any port Tx/Rx activity is halted, MIB counters
1687 * are cleared, PHY address is set according to user parameter and
1688 * access to DRAM and internal SRAM memory spaces.
1689 *
1690 * Driver ring initialization
1691 * Allocating memory for the descriptor rings and buffers is not
1692 * within the scope of this driver. Thus, the user is required to
1693 * allocate memory for the descriptors ring and buffers. Those
1694 * memory parameters are used by the Rx and Tx ring initialization
1695 * routines in order to curve the descriptor linked list in a form
1696 * of a ring.
1697 * Note: Pay special attention to alignment issues when using
1698 * cached descriptors/buffers. In this phase the driver store
1699 * information in the mv643xx_private struct regarding each queue
1700 * ring.
1701 *
1702 * Driver start
1703 * This phase prepares the Ethernet port for Rx and Tx activity.
1704 * It uses the information stored in the mv643xx_private struct to
1705 * initialize the various port registers.
1706 *
1707 * Data flow:
1708 * All packet references to/from the driver are done using
1709 * struct pkt_info.
1710 * This struct is a unified struct used with Rx and Tx operations.
1711 * This way the user is not required to be familiar with neither
1712 * Tx nor Rx descriptors structures.
1713 * The driver's descriptors rings are management by indexes.
1714 * Those indexes controls the ring resources and used to indicate
1715 * a SW resource error:
1716 * 'current'
1717 * This index points to the current available resource for use. For
1718 * example in Rx process this index will point to the descriptor
1719 * that will be passed to the user upon calling the receive
1720 * routine. In Tx process, this index will point to the descriptor
1721 * that will be assigned with the user packet info and transmitted.
1722 * 'used'
1723 * This index points to the descriptor that need to restore its
1724 * resources. For example in Rx process, using the Rx buffer return
1725 * API will attach the buffer returned in packet info to the
1726 * descriptor pointed by 'used'. In Tx process, using the Tx
1727 * descriptor return will merely return the user packet info with
1728 * the command status of the transmitted buffer pointed by the
1729 * 'used' index. Nevertheless, it is essential to use this routine
1730 * to update the 'used' index.
1731 * 'first'
1732 * This index supports Tx Scatter-Gather. It points to the first
1733 * descriptor of a packet assembled of multiple buffers. For
1734 * example when in middle of Such packet we have a Tx resource
1735 * error the 'curr' index get the value of 'first' to indicate
1736 * that the ring returned to its state before trying to transmit
1737 * this packet.
1738 *
1739 * Receive operation:
1740 * The eth_port_receive API set the packet information struct,
1741 * passed by the caller, with received information from the
1742 * 'current' SDMA descriptor.
1743 * It is the user responsibility to return this resource back
1744 * to the Rx descriptor ring to enable the reuse of this source.
1745 * Return Rx resource is done using the eth_rx_return_buff API.
1746 *
1747 * Transmit operation:
1748 * The eth_port_send API supports Scatter-Gather which enables to
1749 * send a packet spanned over multiple buffers. This means that
1750 * for each packet info structure given by the user and put into
1751 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1752 * bit will be set in the packet info command status field. This
1753 * API also consider restriction regarding buffer alignments and
1754 * sizes.
1755 * The user must return a Tx resource after ensuring the buffer
1756 * has been transmitted to enable the Tx ring indexes to update.
1757 *
1758 * BOARD LAYOUT
1759 * This device is on-board. No jumper diagram is necessary.
1760 *
1761 * EXTERNAL INTERFACE
1762 *
1763 * Prior to calling the initialization routine eth_port_init() the user
1764 * must set the following fields under mv643xx_private struct:
1765 * port_num User Ethernet port number.
1766 * port_mac_addr[6] User defined port MAC address.
1767 * port_config User port configuration value.
1768 * port_config_extend User port config extend value.
1769 * port_sdma_config User port SDMA config value.
1770 * port_serial_control User port serial control value.
1771 *
1772 * This driver data flow is done using the struct pkt_info which
1773 * is a unified struct for Rx and Tx operations:
1774 *
1775 * byte_cnt Tx/Rx descriptor buffer byte count.
1776 * l4i_chk CPU provided TCP Checksum. For Tx operation
1777 * only.
1778 * cmd_sts Tx/Rx descriptor command status.
1779 * buf_ptr Tx/Rx descriptor buffer pointer.
1780 * return_info Tx/Rx user resource return information.
1781 */
1782
1783/* defines */
1784/* SDMA command macros */
1785#define ETH_ENABLE_TX_QUEUE(eth_port) \
1786 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1787
1788/* locals */
1789
1790/* PHY routines */
1791static int ethernet_phy_get(unsigned int eth_port_num);
1792static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1793
1794/* Ethernet Port routines */
1795static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1796 int option);
1797
1798/*
1799 * eth_port_init - Initialize the Ethernet port driver
1800 *
1801 * DESCRIPTION:
1802 * This function prepares the ethernet port to start its activity:
1803 * 1) Completes the ethernet port driver struct initialization toward port
1804 * start routine.
1805 * 2) Resets the device to a quiescent state in case of warm reboot.
1806 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1807 * 4) Clean MAC tables. The reset status of those tables is unknown.
1808 * 5) Set PHY address.
1809 * Note: Call this routine prior to eth_port_start routine and after
1810 * setting user values in the user fields of Ethernet port control
1811 * struct.
1812 *
1813 * INPUT:
1814 * struct mv643xx_private *mp Ethernet port control struct
1815 *
1816 * OUTPUT:
1817 * See description.
1818 *
1819 * RETURN:
1820 * None.
1821 */
1822static void eth_port_init(struct mv643xx_private *mp)
1823{
1824 mp->port_rx_queue_command = 0;
1825 mp->port_tx_queue_command = 0;
1826
1827 mp->rx_resource_err = 0;
1828 mp->tx_resource_err = 0;
1829
1830 eth_port_reset(mp->port_num);
1831
1832 eth_port_init_mac_tables(mp->port_num);
1833
1834 ethernet_phy_reset(mp->port_num);
1835}
1836
1837/*
1838 * eth_port_start - Start the Ethernet port activity.
1839 *
1840 * DESCRIPTION:
1841 * This routine prepares the Ethernet port for Rx and Tx activity:
1842 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1843 * has been initialized a descriptor's ring (using
1844 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1845 * 2. Initialize and enable the Ethernet configuration port by writing to
1846 * the port's configuration and command registers.
1847 * 3. Initialize and enable the SDMA by writing to the SDMA's
1848 * configuration and command registers. After completing these steps,
1849 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1850 *
1851 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1852 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1853 * and ether_init_rx_desc_ring for Rx queues).
1854 *
1855 * INPUT:
1856 * struct mv643xx_private *mp Ethernet port control struct
1857 *
1858 * OUTPUT:
1859 * Ethernet port is ready to receive and transmit.
1860 *
1861 * RETURN:
1862 * None.
1863 */
1864static void eth_port_start(struct mv643xx_private *mp)
1865{
1866 unsigned int port_num = mp->port_num;
1867 int tx_curr_desc, rx_curr_desc;
1868
1869 /* Assignment of Tx CTRP of given queue */
1870 tx_curr_desc = mp->tx_curr_desc_q;
1871 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1872 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1873
1874 /* Assignment of Rx CRDP of given queue */
1875 rx_curr_desc = mp->rx_curr_desc_q;
1876 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1877 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1878
1879 /* Add the assigned Ethernet address to the port's address table */
1880 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1881
1882 /* Assign port configuration and command. */
1883 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1884
1885 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1886 mp->port_config_extend);
1887
1888
1889 /* Increase the Rx side buffer size if supporting GigE */
1890 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1891 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1892 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1893 else
1894 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1895 mp->port_serial_control);
1896
1897 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1898 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1899 MV643XX_ETH_SERIAL_PORT_ENABLE);
1900
1901 /* Assign port SDMA configuration */
1902 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1903 mp->port_sdma_config);
1904
1905 /* Enable port Rx. */
1906 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1907 mp->port_rx_queue_command);
Dale Farnsworth8f543712005-09-02 12:34:35 -07001908
1909 /* Disable port bandwidth limits by clearing MTU register */
1910 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001911}
1912
1913/*
1914 * eth_port_uc_addr_set - This function Set the port Unicast address.
1915 *
1916 * DESCRIPTION:
1917 * This function Set the port Ethernet MAC address.
1918 *
1919 * INPUT:
1920 * unsigned int eth_port_num Port number.
1921 * char * p_addr Address to be set
1922 *
1923 * OUTPUT:
1924 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1925 * To set the unicast table with the proper information.
1926 *
1927 * RETURN:
1928 * N/A.
1929 *
1930 */
1931static void eth_port_uc_addr_set(unsigned int eth_port_num,
1932 unsigned char *p_addr)
1933{
1934 unsigned int mac_h;
1935 unsigned int mac_l;
1936
1937 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1938 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1939 (p_addr[3] << 0);
1940
1941 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1942 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1943
1944 /* Accept frames of this address */
1945 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1946
1947 return;
1948}
1949
1950/*
1951 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1952 * (MAC address) from the ethernet hw registers.
1953 *
1954 * DESCRIPTION:
1955 * This function retrieves the port Ethernet MAC address.
1956 *
1957 * INPUT:
1958 * unsigned int eth_port_num Port number.
1959 * char *MacAddr pointer where the MAC address is stored
1960 *
1961 * OUTPUT:
1962 * Copy the MAC address to the location pointed to by MacAddr
1963 *
1964 * RETURN:
1965 * N/A.
1966 *
1967 */
1968static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1969{
1970 struct mv643xx_private *mp = netdev_priv(dev);
1971 unsigned int mac_h;
1972 unsigned int mac_l;
1973
1974 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1975 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1976
1977 p_addr[0] = (mac_h >> 24) & 0xff;
1978 p_addr[1] = (mac_h >> 16) & 0xff;
1979 p_addr[2] = (mac_h >> 8) & 0xff;
1980 p_addr[3] = mac_h & 0xff;
1981 p_addr[4] = (mac_l >> 8) & 0xff;
1982 p_addr[5] = mac_l & 0xff;
1983}
1984
1985/*
1986 * eth_port_uc_addr - This function Set the port unicast address table
1987 *
1988 * DESCRIPTION:
1989 * This function locates the proper entry in the Unicast table for the
1990 * specified MAC nibble and sets its properties according to function
1991 * parameters.
1992 *
1993 * INPUT:
1994 * unsigned int eth_port_num Port number.
1995 * unsigned char uc_nibble Unicast MAC Address last nibble.
1996 * int option 0 = Add, 1 = remove address.
1997 *
1998 * OUTPUT:
1999 * This function add/removes MAC addresses from the port unicast address
2000 * table.
2001 *
2002 * RETURN:
2003 * true is output succeeded.
2004 * false if option parameter is invalid.
2005 *
2006 */
2007static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2008 int option)
2009{
2010 unsigned int unicast_reg;
2011 unsigned int tbl_offset;
2012 unsigned int reg_offset;
2013
2014 /* Locate the Unicast table entry */
2015 uc_nibble = (0xf & uc_nibble);
2016 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2017 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2018
2019 switch (option) {
2020 case REJECT_MAC_ADDR:
2021 /* Clear accepts frame bit at given unicast DA table entry */
2022 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2023 (eth_port_num) + tbl_offset));
2024
2025 unicast_reg &= (0x0E << (8 * reg_offset));
2026
2027 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2028 (eth_port_num) + tbl_offset), unicast_reg);
2029 break;
2030
2031 case ACCEPT_MAC_ADDR:
2032 /* Set accepts frame bit at unicast DA filter table entry */
2033 unicast_reg =
2034 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2035 (eth_port_num) + tbl_offset));
2036
2037 unicast_reg |= (0x01 << (8 * reg_offset));
2038
2039 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2040 (eth_port_num) + tbl_offset), unicast_reg);
2041
2042 break;
2043
2044 default:
2045 return 0;
2046 }
2047
2048 return 1;
2049}
2050
2051/*
2052 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2053 *
2054 * DESCRIPTION:
2055 * Go through all the DA filter tables (Unicast, Special Multicast &
2056 * Other Multicast) and set each entry to 0.
2057 *
2058 * INPUT:
2059 * unsigned int eth_port_num Ethernet Port number.
2060 *
2061 * OUTPUT:
2062 * Multicast and Unicast packets are rejected.
2063 *
2064 * RETURN:
2065 * None.
2066 */
2067static void eth_port_init_mac_tables(unsigned int eth_port_num)
2068{
2069 int table_index;
2070
2071 /* Clear DA filter unicast table (Ex_dFUT) */
2072 for (table_index = 0; table_index <= 0xC; table_index += 4)
2073 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2074 (eth_port_num) + table_index), 0);
2075
2076 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2077 /* Clear DA filter special multicast table (Ex_dFSMT) */
2078 mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2079 (eth_port_num) + table_index), 0);
2080 /* Clear DA filter other multicast table (Ex_dFOMT) */
2081 mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2082 (eth_port_num) + table_index), 0);
2083 }
2084}
2085
2086/*
2087 * eth_clear_mib_counters - Clear all MIB counters
2088 *
2089 * DESCRIPTION:
2090 * This function clears all MIB counters of a specific ethernet port.
2091 * A read from the MIB counter will reset the counter.
2092 *
2093 * INPUT:
2094 * unsigned int eth_port_num Ethernet Port number.
2095 *
2096 * OUTPUT:
2097 * After reading all MIB counters, the counters resets.
2098 *
2099 * RETURN:
2100 * MIB counter value.
2101 *
2102 */
2103static void eth_clear_mib_counters(unsigned int eth_port_num)
2104{
2105 int i;
2106
2107 /* Perform dummy reads from MIB counters */
2108 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2109 i += 4)
2110 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2111}
2112
2113static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2114{
2115 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2116}
2117
2118static void eth_update_mib_counters(struct mv643xx_private *mp)
2119{
2120 struct mv643xx_mib_counters *p = &mp->mib_counters;
2121 int offset;
2122
2123 p->good_octets_received +=
2124 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2125 p->good_octets_received +=
2126 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2127
2128 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2129 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2130 offset += 4)
2131 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2132
2133 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2134 p->good_octets_sent +=
2135 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2136
2137 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2138 offset <= ETH_MIB_LATE_COLLISION;
2139 offset += 4)
2140 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2141}
2142
2143/*
2144 * ethernet_phy_detect - Detect whether a phy is present
2145 *
2146 * DESCRIPTION:
2147 * This function tests whether there is a PHY present on
2148 * the specified port.
2149 *
2150 * INPUT:
2151 * unsigned int eth_port_num Ethernet Port number.
2152 *
2153 * OUTPUT:
2154 * None
2155 *
2156 * RETURN:
2157 * 0 on success
2158 * -ENODEV on failure
2159 *
2160 */
2161static int ethernet_phy_detect(unsigned int port_num)
2162{
2163 unsigned int phy_reg_data0;
2164 int auto_neg;
2165
2166 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2167 auto_neg = phy_reg_data0 & 0x1000;
2168 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2169 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2170
2171 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2172 if ((phy_reg_data0 & 0x1000) == auto_neg)
2173 return -ENODEV; /* change didn't take */
2174
2175 phy_reg_data0 ^= 0x1000;
2176 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2177 return 0;
2178}
2179
2180/*
2181 * ethernet_phy_get - Get the ethernet port PHY address.
2182 *
2183 * DESCRIPTION:
2184 * This routine returns the given ethernet port PHY address.
2185 *
2186 * INPUT:
2187 * unsigned int eth_port_num Ethernet Port number.
2188 *
2189 * OUTPUT:
2190 * None.
2191 *
2192 * RETURN:
2193 * PHY address.
2194 *
2195 */
2196static int ethernet_phy_get(unsigned int eth_port_num)
2197{
2198 unsigned int reg_data;
2199
2200 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2201
2202 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2203}
2204
2205/*
2206 * ethernet_phy_set - Set the ethernet port PHY address.
2207 *
2208 * DESCRIPTION:
2209 * This routine sets the given ethernet port PHY address.
2210 *
2211 * INPUT:
2212 * unsigned int eth_port_num Ethernet Port number.
2213 * int phy_addr PHY address.
2214 *
2215 * OUTPUT:
2216 * None.
2217 *
2218 * RETURN:
2219 * None.
2220 *
2221 */
2222static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2223{
2224 u32 reg_data;
2225 int addr_shift = 5 * eth_port_num;
2226
2227 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2228 reg_data &= ~(0x1f << addr_shift);
2229 reg_data |= (phy_addr & 0x1f) << addr_shift;
2230 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2231}
2232
2233/*
2234 * ethernet_phy_reset - Reset Ethernet port PHY.
2235 *
2236 * DESCRIPTION:
2237 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2238 *
2239 * INPUT:
2240 * unsigned int eth_port_num Ethernet Port number.
2241 *
2242 * OUTPUT:
2243 * The PHY is reset.
2244 *
2245 * RETURN:
2246 * None.
2247 *
2248 */
2249static void ethernet_phy_reset(unsigned int eth_port_num)
2250{
2251 unsigned int phy_reg_data;
2252
2253 /* Reset the PHY */
2254 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2255 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2256 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2257}
2258
2259/*
2260 * eth_port_reset - Reset Ethernet port
2261 *
2262 * DESCRIPTION:
2263 * This routine resets the chip by aborting any SDMA engine activity and
2264 * clearing the MIB counters. The Receiver and the Transmit unit are in
2265 * idle state after this command is performed and the port is disabled.
2266 *
2267 * INPUT:
2268 * unsigned int eth_port_num Ethernet Port number.
2269 *
2270 * OUTPUT:
2271 * Channel activity is halted.
2272 *
2273 * RETURN:
2274 * None.
2275 *
2276 */
2277static void eth_port_reset(unsigned int port_num)
2278{
2279 unsigned int reg_data;
2280
2281 /* Stop Tx port activity. Check port Tx activity. */
2282 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2283
2284 if (reg_data & 0xFF) {
2285 /* Issue stop command for active channels only */
2286 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2287 (reg_data << 8));
2288
2289 /* Wait for all Tx activity to terminate. */
2290 /* Check port cause register that all Tx queues are stopped */
2291 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2292 & 0xFF)
2293 udelay(10);
2294 }
2295
2296 /* Stop Rx port activity. Check port Rx activity. */
2297 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2298
2299 if (reg_data & 0xFF) {
2300 /* Issue stop command for active channels only */
2301 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2302 (reg_data << 8));
2303
2304 /* Wait for all Rx activity to terminate. */
2305 /* Check port cause register that all Rx queues are stopped */
2306 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2307 & 0xFF)
2308 udelay(10);
2309 }
2310
2311 /* Clear all MIB counters */
2312 eth_clear_mib_counters(port_num);
2313
2314 /* Reset the Enable bit in the Configuration Register */
2315 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2316 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2317 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2318}
2319
Linus Torvalds1da177e2005-04-16 15:20:36 -07002320
2321static int eth_port_autoneg_supported(unsigned int eth_port_num)
2322{
2323 unsigned int phy_reg_data0;
2324
2325 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2326
2327 return phy_reg_data0 & 0x1000;
2328}
2329
2330static int eth_port_link_is_up(unsigned int eth_port_num)
2331{
2332 unsigned int phy_reg_data1;
2333
2334 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2335
2336 if (eth_port_autoneg_supported(eth_port_num)) {
2337 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2338 return 1;
2339 } else if (phy_reg_data1 & 0x4) /* link up */
2340 return 1;
2341
2342 return 0;
2343}
2344
2345/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002346 * eth_port_read_smi_reg - Read PHY registers
2347 *
2348 * DESCRIPTION:
2349 * This routine utilize the SMI interface to interact with the PHY in
2350 * order to perform PHY register read.
2351 *
2352 * INPUT:
2353 * unsigned int port_num Ethernet Port number.
2354 * unsigned int phy_reg PHY register address offset.
2355 * unsigned int *value Register value buffer.
2356 *
2357 * OUTPUT:
2358 * Write the value of a specified PHY register into given buffer.
2359 *
2360 * RETURN:
2361 * false if the PHY is busy or read data is not in valid state.
2362 * true otherwise.
2363 *
2364 */
2365static void eth_port_read_smi_reg(unsigned int port_num,
2366 unsigned int phy_reg, unsigned int *value)
2367{
2368 int phy_addr = ethernet_phy_get(port_num);
2369 unsigned long flags;
2370 int i;
2371
2372 /* the SMI register is a shared resource */
2373 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2374
2375 /* wait for the SMI register to become available */
2376 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2377 if (i == PHY_WAIT_ITERATIONS) {
2378 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2379 goto out;
2380 }
2381 udelay(PHY_WAIT_MICRO_SECONDS);
2382 }
2383
2384 mv_write(MV643XX_ETH_SMI_REG,
2385 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2386
2387 /* now wait for the data to be valid */
2388 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2389 if (i == PHY_WAIT_ITERATIONS) {
2390 printk("mv643xx PHY read timeout, port %d\n", port_num);
2391 goto out;
2392 }
2393 udelay(PHY_WAIT_MICRO_SECONDS);
2394 }
2395
2396 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2397out:
2398 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2399}
2400
2401/*
2402 * eth_port_write_smi_reg - Write to PHY registers
2403 *
2404 * DESCRIPTION:
2405 * This routine utilize the SMI interface to interact with the PHY in
2406 * order to perform writes to PHY registers.
2407 *
2408 * INPUT:
2409 * unsigned int eth_port_num Ethernet Port number.
2410 * unsigned int phy_reg PHY register address offset.
2411 * unsigned int value Register value.
2412 *
2413 * OUTPUT:
2414 * Write the given value to the specified PHY register.
2415 *
2416 * RETURN:
2417 * false if the PHY is busy.
2418 * true otherwise.
2419 *
2420 */
2421static void eth_port_write_smi_reg(unsigned int eth_port_num,
2422 unsigned int phy_reg, unsigned int value)
2423{
2424 int phy_addr;
2425 int i;
2426 unsigned long flags;
2427
2428 phy_addr = ethernet_phy_get(eth_port_num);
2429
2430 /* the SMI register is a shared resource */
2431 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2432
2433 /* wait for the SMI register to become available */
2434 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2435 if (i == PHY_WAIT_ITERATIONS) {
2436 printk("mv643xx PHY busy timeout, port %d\n",
2437 eth_port_num);
2438 goto out;
2439 }
2440 udelay(PHY_WAIT_MICRO_SECONDS);
2441 }
2442
2443 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2444 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2445out:
2446 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2447}
2448
2449/*
2450 * eth_port_send - Send an Ethernet packet
2451 *
2452 * DESCRIPTION:
2453 * This routine send a given packet described by p_pktinfo parameter. It
2454 * supports transmitting of a packet spaned over multiple buffers. The
2455 * routine updates 'curr' and 'first' indexes according to the packet
2456 * segment passed to the routine. In case the packet segment is first,
2457 * the 'first' index is update. In any case, the 'curr' index is updated.
2458 * If the routine get into Tx resource error it assigns 'curr' index as
2459 * 'first'. This way the function can abort Tx process of multiple
2460 * descriptors per packet.
2461 *
2462 * INPUT:
2463 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2464 * struct pkt_info *p_pkt_info User packet buffer.
2465 *
2466 * OUTPUT:
2467 * Tx ring 'curr' and 'first' indexes are updated.
2468 *
2469 * RETURN:
2470 * ETH_QUEUE_FULL in case of Tx resource error.
2471 * ETH_ERROR in case the routine can not access Tx desc ring.
2472 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2473 * ETH_OK otherwise.
2474 *
2475 */
2476#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2477/*
2478 * Modified to include the first descriptor pointer in case of SG
2479 */
2480static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2481 struct pkt_info *p_pkt_info)
2482{
2483 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2484 struct eth_tx_desc *current_descriptor;
2485 struct eth_tx_desc *first_descriptor;
2486 u32 command;
2487
2488 /* Do not process Tx ring in case of Tx ring resource error */
2489 if (mp->tx_resource_err)
2490 return ETH_QUEUE_FULL;
2491
2492 /*
2493 * The hardware requires that each buffer that is <= 8 bytes
2494 * in length must be aligned on an 8 byte boundary.
2495 */
2496 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2497 printk(KERN_ERR
2498 "mv643xx_eth port %d: packet size <= 8 problem\n",
2499 mp->port_num);
2500 return ETH_ERROR;
2501 }
2502
Dale Farnsworthb111ceb2005-09-02 10:25:24 -07002503 mp->tx_ring_skbs++;
2504 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2505
Linus Torvalds1da177e2005-04-16 15:20:36 -07002506 /* Get the Tx Desc ring indexes */
2507 tx_desc_curr = mp->tx_curr_desc_q;
2508 tx_desc_used = mp->tx_used_desc_q;
2509
2510 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2511
2512 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2513
2514 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2515 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2516 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2517 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2518
2519 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2520 ETH_BUFFER_OWNED_BY_DMA;
2521 if (command & ETH_TX_FIRST_DESC) {
2522 tx_first_desc = tx_desc_curr;
2523 mp->tx_first_desc_q = tx_first_desc;
2524 first_descriptor = current_descriptor;
2525 mp->tx_first_command = command;
2526 } else {
2527 tx_first_desc = mp->tx_first_desc_q;
2528 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2529 BUG_ON(first_descriptor == NULL);
2530 current_descriptor->cmd_sts = command;
2531 }
2532
2533 if (command & ETH_TX_LAST_DESC) {
2534 wmb();
2535 first_descriptor->cmd_sts = mp->tx_first_command;
2536
2537 wmb();
2538 ETH_ENABLE_TX_QUEUE(mp->port_num);
2539
2540 /*
2541 * Finish Tx packet. Update first desc in case of Tx resource
2542 * error */
2543 tx_first_desc = tx_next_desc;
2544 mp->tx_first_desc_q = tx_first_desc;
2545 }
2546
2547 /* Check for ring index overlap in the Tx desc ring */
2548 if (tx_next_desc == tx_desc_used) {
2549 mp->tx_resource_err = 1;
2550 mp->tx_curr_desc_q = tx_first_desc;
2551
2552 return ETH_QUEUE_LAST_RESOURCE;
2553 }
2554
2555 mp->tx_curr_desc_q = tx_next_desc;
2556
2557 return ETH_OK;
2558}
2559#else
2560static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2561 struct pkt_info *p_pkt_info)
2562{
2563 int tx_desc_curr;
2564 int tx_desc_used;
2565 struct eth_tx_desc *current_descriptor;
2566 unsigned int command_status;
2567
2568 /* Do not process Tx ring in case of Tx ring resource error */
2569 if (mp->tx_resource_err)
2570 return ETH_QUEUE_FULL;
2571
Dale Farnsworthb111ceb2005-09-02 10:25:24 -07002572 mp->tx_ring_skbs++;
2573 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2574
Linus Torvalds1da177e2005-04-16 15:20:36 -07002575 /* Get the Tx Desc ring indexes */
2576 tx_desc_curr = mp->tx_curr_desc_q;
2577 tx_desc_used = mp->tx_used_desc_q;
2578 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2579
2580 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2581 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2582 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2583 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2584
2585 /* Set last desc with DMA ownership and interrupt enable. */
2586 wmb();
2587 current_descriptor->cmd_sts = command_status |
2588 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2589
2590 wmb();
2591 ETH_ENABLE_TX_QUEUE(mp->port_num);
2592
2593 /* Finish Tx packet. Update first desc in case of Tx resource error */
2594 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2595
2596 /* Update the current descriptor */
2597 mp->tx_curr_desc_q = tx_desc_curr;
2598
2599 /* Check for ring index overlap in the Tx desc ring */
2600 if (tx_desc_curr == tx_desc_used) {
2601 mp->tx_resource_err = 1;
2602 return ETH_QUEUE_LAST_RESOURCE;
2603 }
2604
2605 return ETH_OK;
2606}
2607#endif
2608
2609/*
2610 * eth_tx_return_desc - Free all used Tx descriptors
2611 *
2612 * DESCRIPTION:
2613 * This routine returns the transmitted packet information to the caller.
2614 * It uses the 'first' index to support Tx desc return in case a transmit
2615 * of a packet spanned over multiple buffer still in process.
2616 * In case the Tx queue was in "resource error" condition, where there are
2617 * no available Tx resources, the function resets the resource error flag.
2618 *
2619 * INPUT:
2620 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2621 * struct pkt_info *p_pkt_info User packet buffer.
2622 *
2623 * OUTPUT:
2624 * Tx ring 'first' and 'used' indexes are updated.
2625 *
2626 * RETURN:
2627 * ETH_ERROR in case the routine can not access Tx desc ring.
2628 * ETH_RETRY in case there is transmission in process.
2629 * ETH_END_OF_JOB if the routine has nothing to release.
2630 * ETH_OK otherwise.
2631 *
2632 */
2633static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2634 struct pkt_info *p_pkt_info)
2635{
2636 int tx_desc_used;
2637#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2638 int tx_busy_desc = mp->tx_first_desc_q;
2639#else
2640 int tx_busy_desc = mp->tx_curr_desc_q;
2641#endif
2642 struct eth_tx_desc *p_tx_desc_used;
2643 unsigned int command_status;
2644
2645 /* Get the Tx Desc ring indexes */
2646 tx_desc_used = mp->tx_used_desc_q;
2647
2648 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2649
2650 /* Sanity check */
2651 if (p_tx_desc_used == NULL)
2652 return ETH_ERROR;
2653
2654 /* Stop release. About to overlap the current available Tx descriptor */
2655 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2656 return ETH_END_OF_JOB;
2657
2658 command_status = p_tx_desc_used->cmd_sts;
2659
2660 /* Still transmitting... */
2661 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2662 return ETH_RETRY;
2663
2664 /* Pass the packet information to the caller */
2665 p_pkt_info->cmd_sts = command_status;
2666 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2667 mp->tx_skb[tx_desc_used] = NULL;
2668
2669 /* Update the next descriptor to release. */
2670 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2671
2672 /* Any Tx return cancels the Tx resource error status */
2673 mp->tx_resource_err = 0;
2674
Dale Farnsworthb111ceb2005-09-02 10:25:24 -07002675 BUG_ON(mp->tx_ring_skbs == 0);
2676 mp->tx_ring_skbs--;
2677
Linus Torvalds1da177e2005-04-16 15:20:36 -07002678 return ETH_OK;
2679}
2680
2681/*
2682 * eth_port_receive - Get received information from Rx ring.
2683 *
2684 * DESCRIPTION:
2685 * This routine returns the received data to the caller. There is no
2686 * data copying during routine operation. All information is returned
2687 * using pointer to packet information struct passed from the caller.
2688 * If the routine exhausts Rx ring resources then the resource error flag
2689 * is set.
2690 *
2691 * INPUT:
2692 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2693 * struct pkt_info *p_pkt_info User packet buffer.
2694 *
2695 * OUTPUT:
2696 * Rx ring current and used indexes are updated.
2697 *
2698 * RETURN:
2699 * ETH_ERROR in case the routine can not access Rx desc ring.
2700 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2701 * ETH_END_OF_JOB if there is no received data.
2702 * ETH_OK otherwise.
2703 */
2704static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2705 struct pkt_info *p_pkt_info)
2706{
2707 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2708 volatile struct eth_rx_desc *p_rx_desc;
2709 unsigned int command_status;
2710
2711 /* Do not process Rx ring in case of Rx ring resource error */
2712 if (mp->rx_resource_err)
2713 return ETH_QUEUE_FULL;
2714
2715 /* Get the Rx Desc ring 'curr and 'used' indexes */
2716 rx_curr_desc = mp->rx_curr_desc_q;
2717 rx_used_desc = mp->rx_used_desc_q;
2718
2719 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2720
2721 /* The following parameters are used to save readings from memory */
2722 command_status = p_rx_desc->cmd_sts;
2723 rmb();
2724
2725 /* Nothing to receive... */
2726 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2727 return ETH_END_OF_JOB;
2728
2729 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2730 p_pkt_info->cmd_sts = command_status;
2731 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2732 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2733 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2734
2735 /* Clean the return info field to indicate that the packet has been */
2736 /* moved to the upper layers */
2737 mp->rx_skb[rx_curr_desc] = NULL;
2738
2739 /* Update current index in data structure */
2740 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2741 mp->rx_curr_desc_q = rx_next_curr_desc;
2742
2743 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2744 if (rx_next_curr_desc == rx_used_desc)
2745 mp->rx_resource_err = 1;
2746
2747 return ETH_OK;
2748}
2749
2750/*
2751 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2752 *
2753 * DESCRIPTION:
2754 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2755 * next 'used' descriptor and attached the returned buffer to it.
2756 * In case the Rx ring was in "resource error" condition, where there are
2757 * no available Rx resources, the function resets the resource error flag.
2758 *
2759 * INPUT:
2760 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2761 * struct pkt_info *p_pkt_info Information on returned buffer.
2762 *
2763 * OUTPUT:
2764 * New available Rx resource in Rx descriptor ring.
2765 *
2766 * RETURN:
2767 * ETH_ERROR in case the routine can not access Rx desc ring.
2768 * ETH_OK otherwise.
2769 */
2770static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2771 struct pkt_info *p_pkt_info)
2772{
2773 int used_rx_desc; /* Where to return Rx resource */
2774 volatile struct eth_rx_desc *p_used_rx_desc;
2775
2776 /* Get 'used' Rx descriptor */
2777 used_rx_desc = mp->rx_used_desc_q;
2778 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2779
2780 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2781 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2782 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2783
2784 /* Flush the write pipe */
2785
2786 /* Return the descriptor to DMA ownership */
2787 wmb();
2788 p_used_rx_desc->cmd_sts =
2789 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2790 wmb();
2791
2792 /* Move the used descriptor pointer to the next descriptor */
2793 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2794
2795 /* Any Rx return cancels the Rx resource error status */
2796 mp->rx_resource_err = 0;
2797
2798 return ETH_OK;
2799}
2800
2801/************* Begin ethtool support *************************/
2802
2803struct mv643xx_stats {
2804 char stat_string[ETH_GSTRING_LEN];
2805 int sizeof_stat;
2806 int stat_offset;
2807};
2808
2809#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2810 offsetof(struct mv643xx_private, m)
2811
2812static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2813 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2814 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2815 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2816 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2817 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2818 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2819 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2820 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2821 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2822 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2823 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2824 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2825 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2826 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2827 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2828 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2829 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2830 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2831 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2832 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2833 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2834 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2835 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2836 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2837 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2838 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2839 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2840 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2841 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2842 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2843 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2844 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2845 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2846 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2847 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2848 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2849 { "collision", MV643XX_STAT(mib_counters.collision) },
2850 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2851};
2852
2853#define MV643XX_STATS_LEN \
2854 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2855
2856static int
2857mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2858{
2859 struct mv643xx_private *mp = netdev->priv;
2860 int port_num = mp->port_num;
2861 int autoneg = eth_port_autoneg_supported(port_num);
2862 int mode_10_bit;
2863 int auto_duplex;
2864 int half_duplex = 0;
2865 int full_duplex = 0;
2866 int auto_speed;
2867 int speed_10 = 0;
2868 int speed_100 = 0;
2869 int speed_1000 = 0;
2870
2871 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2872 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
2873
2874 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
2875
2876 if (mode_10_bit) {
2877 ecmd->supported = SUPPORTED_10baseT_Half;
2878 } else {
2879 ecmd->supported = (SUPPORTED_10baseT_Half |
2880 SUPPORTED_10baseT_Full |
2881 SUPPORTED_100baseT_Half |
2882 SUPPORTED_100baseT_Full |
2883 SUPPORTED_1000baseT_Full |
2884 (autoneg ? SUPPORTED_Autoneg : 0) |
2885 SUPPORTED_TP);
2886
2887 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
2888 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
2889
2890 ecmd->advertising = ADVERTISED_TP;
2891
2892 if (autoneg) {
2893 ecmd->advertising |= ADVERTISED_Autoneg;
2894
2895 if (auto_duplex) {
2896 half_duplex = 1;
2897 full_duplex = 1;
2898 } else {
2899 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
2900 full_duplex = 1;
2901 else
2902 half_duplex = 1;
2903 }
2904
2905 if (auto_speed) {
2906 speed_10 = 1;
2907 speed_100 = 1;
2908 speed_1000 = 1;
2909 } else {
2910 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
2911 speed_1000 = 1;
2912 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
2913 speed_100 = 1;
2914 else
2915 speed_10 = 1;
2916 }
2917
2918 if (speed_10 & half_duplex)
2919 ecmd->advertising |= ADVERTISED_10baseT_Half;
2920 if (speed_10 & full_duplex)
2921 ecmd->advertising |= ADVERTISED_10baseT_Full;
2922 if (speed_100 & half_duplex)
2923 ecmd->advertising |= ADVERTISED_100baseT_Half;
2924 if (speed_100 & full_duplex)
2925 ecmd->advertising |= ADVERTISED_100baseT_Full;
2926 if (speed_1000)
2927 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2928 }
2929 }
2930
2931 ecmd->port = PORT_TP;
2932 ecmd->phy_address = ethernet_phy_get(port_num);
2933
2934 ecmd->transceiver = XCVR_EXTERNAL;
2935
2936 if (netif_carrier_ok(netdev)) {
2937 if (mode_10_bit)
2938 ecmd->speed = SPEED_10;
2939 else {
2940 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
2941 ecmd->speed = SPEED_1000;
2942 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
2943 ecmd->speed = SPEED_100;
2944 else
2945 ecmd->speed = SPEED_10;
2946 }
2947
2948 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
2949 ecmd->duplex = DUPLEX_FULL;
2950 else
2951 ecmd->duplex = DUPLEX_HALF;
2952 } else {
2953 ecmd->speed = -1;
2954 ecmd->duplex = -1;
2955 }
2956
2957 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2958 return 0;
2959}
2960
2961static void
2962mv643xx_get_drvinfo(struct net_device *netdev,
2963 struct ethtool_drvinfo *drvinfo)
2964{
2965 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2966 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2967 strncpy(drvinfo->fw_version, "N/A", 32);
2968 strncpy(drvinfo->bus_info, "mv643xx", 32);
2969 drvinfo->n_stats = MV643XX_STATS_LEN;
2970}
2971
2972static int
2973mv643xx_get_stats_count(struct net_device *netdev)
2974{
2975 return MV643XX_STATS_LEN;
2976}
2977
2978static void
2979mv643xx_get_ethtool_stats(struct net_device *netdev,
2980 struct ethtool_stats *stats, uint64_t *data)
2981{
2982 struct mv643xx_private *mp = netdev->priv;
2983 int i;
2984
2985 eth_update_mib_counters(mp);
2986
2987 for(i = 0; i < MV643XX_STATS_LEN; i++) {
2988 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
2989 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
2990 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2991 }
2992}
2993
2994static void
2995mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
2996{
2997 int i;
2998
2999 switch(stringset) {
3000 case ETH_SS_STATS:
3001 for (i=0; i < MV643XX_STATS_LEN; i++) {
3002 memcpy(data + i * ETH_GSTRING_LEN,
3003 mv643xx_gstrings_stats[i].stat_string,
3004 ETH_GSTRING_LEN);
3005 }
3006 break;
3007 }
3008}
3009
3010static struct ethtool_ops mv643xx_ethtool_ops = {
3011 .get_settings = mv643xx_get_settings,
3012 .get_drvinfo = mv643xx_get_drvinfo,
3013 .get_link = ethtool_op_get_link,
3014 .get_sg = ethtool_op_get_sg,
3015 .set_sg = ethtool_op_set_sg,
3016 .get_strings = mv643xx_get_strings,
3017 .get_stats_count = mv643xx_get_stats_count,
3018 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3019};
3020
3021/************* End ethtool support *************************/