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gerrit-public.fairphone.software / kernel / msm-4.9 / b46637d59f1160dee5d8e03498e667ab36c2be04 / . / drivers / clk / rockchip / clk-rk3368.c
blob: a2bb12200465cf34483eeaa0045b517e63747d17 [file] [log] [blame]
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]1/*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <dt-bindings/clock/rk3368-cru.h>
20#include "clk.h"
21
22#define RK3368_GRF_SOC_STATUS0 0x480
23
24enum rk3368_plls {
25 apllb, aplll, dpll, cpll, gpll, npll,
26};
27
28static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
29 RK3066_PLL_RATE(2208000000, 1, 92, 1),
30 RK3066_PLL_RATE(2184000000, 1, 91, 1),
31 RK3066_PLL_RATE(2160000000, 1, 90, 1),
32 RK3066_PLL_RATE(2136000000, 1, 89, 1),
33 RK3066_PLL_RATE(2112000000, 1, 88, 1),
34 RK3066_PLL_RATE(2088000000, 1, 87, 1),
35 RK3066_PLL_RATE(2064000000, 1, 86, 1),
36 RK3066_PLL_RATE(2040000000, 1, 85, 1),
37 RK3066_PLL_RATE(2016000000, 1, 84, 1),
38 RK3066_PLL_RATE(1992000000, 1, 83, 1),
39 RK3066_PLL_RATE(1968000000, 1, 82, 1),
40 RK3066_PLL_RATE(1944000000, 1, 81, 1),
41 RK3066_PLL_RATE(1920000000, 1, 80, 1),
42 RK3066_PLL_RATE(1896000000, 1, 79, 1),
43 RK3066_PLL_RATE(1872000000, 1, 78, 1),
44 RK3066_PLL_RATE(1848000000, 1, 77, 1),
45 RK3066_PLL_RATE(1824000000, 1, 76, 1),
46 RK3066_PLL_RATE(1800000000, 1, 75, 1),
47 RK3066_PLL_RATE(1776000000, 1, 74, 1),
48 RK3066_PLL_RATE(1752000000, 1, 73, 1),
49 RK3066_PLL_RATE(1728000000, 1, 72, 1),
50 RK3066_PLL_RATE(1704000000, 1, 71, 1),
51 RK3066_PLL_RATE(1680000000, 1, 70, 1),
52 RK3066_PLL_RATE(1656000000, 1, 69, 1),
53 RK3066_PLL_RATE(1632000000, 1, 68, 1),
54 RK3066_PLL_RATE(1608000000, 1, 67, 1),
55 RK3066_PLL_RATE(1560000000, 1, 65, 1),
56 RK3066_PLL_RATE(1512000000, 1, 63, 1),
57 RK3066_PLL_RATE(1488000000, 1, 62, 1),
58 RK3066_PLL_RATE(1464000000, 1, 61, 1),
59 RK3066_PLL_RATE(1440000000, 1, 60, 1),
60 RK3066_PLL_RATE(1416000000, 1, 59, 1),
61 RK3066_PLL_RATE(1392000000, 1, 58, 1),
62 RK3066_PLL_RATE(1368000000, 1, 57, 1),
63 RK3066_PLL_RATE(1344000000, 1, 56, 1),
64 RK3066_PLL_RATE(1320000000, 1, 55, 1),
65 RK3066_PLL_RATE(1296000000, 1, 54, 1),
66 RK3066_PLL_RATE(1272000000, 1, 53, 1),
67 RK3066_PLL_RATE(1248000000, 1, 52, 1),
68 RK3066_PLL_RATE(1224000000, 1, 51, 1),
69 RK3066_PLL_RATE(1200000000, 1, 50, 1),
70 RK3066_PLL_RATE(1176000000, 1, 49, 1),
71 RK3066_PLL_RATE(1128000000, 1, 47, 1),
72 RK3066_PLL_RATE(1104000000, 1, 46, 1),
73 RK3066_PLL_RATE(1008000000, 1, 84, 2),
74 RK3066_PLL_RATE( 912000000, 1, 76, 2),
75 RK3066_PLL_RATE( 888000000, 1, 74, 2),
76 RK3066_PLL_RATE( 816000000, 1, 68, 2),
77 RK3066_PLL_RATE( 792000000, 1, 66, 2),
78 RK3066_PLL_RATE( 696000000, 1, 58, 2),
79 RK3066_PLL_RATE( 672000000, 1, 56, 2),
80 RK3066_PLL_RATE( 648000000, 1, 54, 2),
81 RK3066_PLL_RATE( 624000000, 1, 52, 2),
82 RK3066_PLL_RATE( 600000000, 1, 50, 2),
83 RK3066_PLL_RATE( 576000000, 1, 48, 2),
84 RK3066_PLL_RATE( 552000000, 1, 46, 2),
85 RK3066_PLL_RATE( 528000000, 1, 88, 4),
86 RK3066_PLL_RATE( 504000000, 1, 84, 4),
87 RK3066_PLL_RATE( 480000000, 1, 80, 4),
88 RK3066_PLL_RATE( 456000000, 1, 76, 4),
89 RK3066_PLL_RATE( 408000000, 1, 68, 4),
90 RK3066_PLL_RATE( 312000000, 1, 52, 4),
91 RK3066_PLL_RATE( 252000000, 1, 84, 8),
92 RK3066_PLL_RATE( 216000000, 1, 72, 8),
93 RK3066_PLL_RATE( 126000000, 2, 84, 8),
94 RK3066_PLL_RATE( 48000000, 2, 32, 8),
95 { /* sentinel */ },
96};
97
98PNAME(mux_pll_p) = { "xin24m", "xin32k" };
99PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
100PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
101PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
102PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
103PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
104
105PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
106PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
107PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
108PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
109PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
110 "usbphy_480m" };
111PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
112 "npll" };
113PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
114PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
115 "usbphy_480m" };
116
117PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac",
118 "ext_i2s", "xin12m" };
119PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
120PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac",
121 "dummy", "xin12m" };
122PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac",
123 "ext_i2s", "xin12m" };
zhangqingd566ebc2016-01-25 08:56:00 -0800[diff] [blame]124PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]125PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
126PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" };
127PNAME(mux_hsic_usbphy480m_p) = { "usbotg_out", "dummy" };
128PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy_480m" };
129PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
130PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
131PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
132PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
133PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
134PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
135PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
136
137static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
138 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
139 RK3368_PLL_CON(3), 8, 1, 0, rk3368_pll_rates),
140 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
141 RK3368_PLL_CON(7), 8, 0, 0, rk3368_pll_rates),
142 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
143 RK3368_PLL_CON(11), 8, 2, 0, NULL),
144 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
145 RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
146 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
147 RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
148 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
149 RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
150};
151
152static struct clk_div_table div_ddrphy_t[] = {
153 { .val = 0, .div = 1 },
154 { .val = 1, .div = 2 },
155 { .val = 3, .div = 4 },
156 { /* sentinel */ },
157};
158
159#define MFLAGS CLK_MUX_HIWORD_MASK
160#define DFLAGS CLK_DIVIDER_HIWORD_MASK
161#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
162#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
163
164static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
165 .core_reg = RK3368_CLKSEL_CON(0),
166 .div_core_shift = 0,
167 .div_core_mask = 0x1f,
Heiko Stuebner535ebd42016-01-19 10:01:08 +0100[diff] [blame]168 .mux_core_shift = 7,
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]169};
170
171static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
172 .core_reg = RK3368_CLKSEL_CON(2),
173 .div_core_shift = 0,
174 .div_core_mask = 0x1f,
175 .mux_core_shift = 7,
176};
177
178#define RK3368_DIV_ACLKM_MASK 0x1f
179#define RK3368_DIV_ACLKM_SHIFT 8
180#define RK3368_DIV_ATCLK_MASK 0x1f
181#define RK3368_DIV_ATCLK_SHIFT 0
182#define RK3368_DIV_PCLK_DBG_MASK 0x1f
183#define RK3368_DIV_PCLK_DBG_SHIFT 8
184
185#define RK3368_CLKSEL0(_offs, _aclkm) \
186 { \
Heiko Stuebner8ad0df32015-12-01 22:23:45 +0100[diff] [blame]187 .reg = RK3368_CLKSEL_CON(0 + _offs), \
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
189 RK3368_DIV_ACLKM_SHIFT), \
190 }
191#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
192 { \
Heiko Stuebner8ad0df32015-12-01 22:23:45 +0100[diff] [blame]193 .reg = RK3368_CLKSEL_CON(1 + _offs), \
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
195 RK3368_DIV_ATCLK_SHIFT) | \
196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
197 RK3368_DIV_PCLK_DBG_SHIFT), \
198 }
199
200/* cluster_b: aclkm in clksel0, rest in clksel1 */
201#define RK3368_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
202 { \
203 .prate = _prate, \
204 .divs = { \
205 RK3368_CLKSEL0(0, _aclkm), \
206 RK3368_CLKSEL1(0, _atclk, _pdbg), \
207 }, \
208 }
209
210/* cluster_l: aclkm in clksel2, rest in clksel3 */
211#define RK3368_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
212 { \
213 .prate = _prate, \
214 .divs = { \
215 RK3368_CLKSEL0(2, _aclkm), \
216 RK3368_CLKSEL1(2, _atclk, _pdbg), \
217 }, \
218 }
219
220static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
Heiko Stuebnerc6d5fe22016-01-19 10:09:22 +0100[diff] [blame]221 RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
222 RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
223 RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
224 RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
225 RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
226 RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
227 RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
228 RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
229 RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
230 RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]231};
232
233static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
Heiko Stuebnerc6d5fe22016-01-19 10:09:22 +0100[diff] [blame]234 RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
235 RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
236 RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
237 RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
238 RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
239 RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
240 RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
241 RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
242 RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
243 RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]244};
245
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]246static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
247 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
248 RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
249
250static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
251 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
252 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
253
254static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
255 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
256 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
257
258static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
259 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
260 RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
261
262static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
263 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
264 RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
265
266static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
267 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
268 RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
269
270static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
271 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
272 RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
273
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]274static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
275 /*
276 * Clock-Architecture Diagram 2
277 */
278
Heiko Stuebner36714522015-06-20 16:06:02 +0200[diff] [blame]279 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
280
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]281 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
282 RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
283
284 GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
285 RK3368_CLKGATE_CON(0), 0, GFLAGS),
286 GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
287 RK3368_CLKGATE_CON(0), 1, GFLAGS),
288
289 GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
290 RK3368_CLKGATE_CON(0), 4, GFLAGS),
291 GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
292 RK3368_CLKGATE_CON(0), 5, GFLAGS),
293
294 DIV(0, "aclkm_core_b", "armclkb", 0,
295 RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
296 DIV(0, "atclk_core_b", "armclkb", 0,
297 RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
298 DIV(0, "pclk_dbg_b", "armclkb", 0,
299 RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
300
301 DIV(0, "aclkm_core_l", "armclkl", 0,
302 RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
303 DIV(0, "atclk_core_l", "armclkl", 0,
304 RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
305 DIV(0, "pclk_dbg_l", "armclkl", 0,
306 RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
307
308 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
309 RK3368_CLKGATE_CON(0), 9, GFLAGS),
310 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
311 RK3368_CLKGATE_CON(0), 10, GFLAGS),
312 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
313 RK3368_CLKGATE_CON(0), 8, GFLAGS),
314 COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
315 RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
316 COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
317 RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
318 RK3368_CLKGATE_CON(0), 13, GFLAGS),
319
320 COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
321 RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
322 RK3368_CLKGATE_CON(0), 12, GFLAGS),
323 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
324
325 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
326 RK3368_CLKGATE_CON(1), 8, GFLAGS),
327 GATE(0, "gpll_ddr", "gpll", 0,
328 RK3368_CLKGATE_CON(1), 9, GFLAGS),
329 COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
330 RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
331
Heiko Stuebner36714522015-06-20 16:06:02 +0200[diff] [blame]332 FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]333 RK3368_CLKGATE_CON(6), 14, GFLAGS),
334 GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
335 RK3368_CLKGATE_CON(6), 15, GFLAGS),
336
337 GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
338 RK3368_CLKGATE_CON(1), 10, GFLAGS),
339 GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
340 RK3368_CLKGATE_CON(1), 11, GFLAGS),
341 COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
342 RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
343
344 GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
345 RK3368_CLKGATE_CON(1), 0, GFLAGS),
346 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
347 RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
348 RK3368_CLKGATE_CON(1), 2, GFLAGS),
349 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
350 RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
351 RK3368_CLKGATE_CON(1), 1, GFLAGS),
352 COMPOSITE_NOMUX(0, "sclk_crypto", "aclk_bus_src", 0,
353 RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
354 RK3368_CLKGATE_CON(7), 2, GFLAGS),
355
356 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
357 RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
358 RK3368_CLKGATE_CON(1), 3, GFLAGS),
359 /*
360 * stclk_mcu is listed as child of fclk_mcu_src in diagram 5,
361 * but stclk_mcu has an additional own divider in diagram 2
362 */
363 COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", 0,
364 RK3368_CLKSEL_CON(12), 8, 3, DFLAGS,
365 RK3368_CLKGATE_CON(13), 13, GFLAGS),
366
367 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
368 RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
369 RK3368_CLKGATE_CON(6), 1, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]370 COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
371 RK3368_CLKSEL_CON(28), 0,
372 RK3368_CLKGATE_CON(6), 2, GFLAGS,
373 &rk3368_i2s_8ch_fracmux),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]374 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
375 RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
376 RK3368_CLKGATE_CON(6), 0, GFLAGS),
377 GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
378 RK3368_CLKGATE_CON(6), 3, GFLAGS),
379 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
380 RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
381 RK3368_CLKGATE_CON(6), 4, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]382 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
383 RK3368_CLKSEL_CON(32), 0,
384 RK3368_CLKGATE_CON(6), 5, GFLAGS,
385 &rk3368_spdif_8ch_fracmux),
386 GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
387 RK3368_CLKGATE_CON(6), 6, GFLAGS),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]388 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
389 RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
390 RK3368_CLKGATE_CON(5), 13, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]391 COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
392 RK3368_CLKSEL_CON(54), 0,
393 RK3368_CLKGATE_CON(5), 14, GFLAGS,
394 &rk3368_i2s_2ch_fracmux),
395 GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
396 RK3368_CLKGATE_CON(5), 15, GFLAGS),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]397
398 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
399 RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
400 RK3368_CLKGATE_CON(6), 12, GFLAGS),
401 GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
402 RK3368_CLKGATE_CON(13), 7, GFLAGS),
403
404 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
405 RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
406 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
407 RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
408 RK3368_CLKGATE_CON(2), 4, GFLAGS),
409 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
410 RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
411
412 /*
413 * Clock-Architecture Diagram 3
414 */
415
Heiko Stuebner0f28d982016-01-20 19:22:38 +0100[diff] [blame]416 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]417 RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
418 RK3368_CLKGATE_CON(4), 6, GFLAGS),
Heiko Stuebner0f28d982016-01-20 19:22:38 +0100[diff] [blame]419 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]420 RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
421 RK3368_CLKGATE_CON(4), 7, GFLAGS),
422
423 /*
Heiko Stuebner36714522015-06-20 16:06:02 +0200[diff] [blame]424 * We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system,
425 * so we ignore the mux and make clocks nodes as following,
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]426 */
Heiko Stuebner36714522015-06-20 16:06:02 +0200[diff] [blame]427 FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4,
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]428 RK3368_CLKGATE_CON(4), 8, GFLAGS),
429
430 COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
431 RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
432 RK3368_CLKGATE_CON(5), 1, GFLAGS),
433 COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
434 RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
435 RK3368_CLKGATE_CON(5), 2, GFLAGS),
436
437 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
438 RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
439 RK3368_CLKGATE_CON(4), 0, GFLAGS),
440 DIV(0, "hclk_vio", "aclk_vio0", 0,
441 RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
442
443 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
444 RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
445 RK3368_CLKGATE_CON(4), 3, GFLAGS),
446 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
447 RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
448 RK3368_CLKGATE_CON(4), 4, GFLAGS),
449
450 COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0,
451 RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
452 RK3368_CLKGATE_CON(4), 1, GFLAGS),
453
454 GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
455 RK3368_CLKGATE_CON(4), 2, GFLAGS),
456
457 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
458 RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
459 RK3368_CLKGATE_CON(4), 9, GFLAGS),
460
461 GATE(0, "pclk_isp_in", "ext_isp", 0,
462 RK3368_CLKGATE_CON(17), 2, GFLAGS),
463 INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in",
464 RK3368_CLKSEL_CON(21), 6, IFLAGS),
465
466 GATE(0, "pclk_vip_in", "ext_vip", 0,
467 RK3368_CLKGATE_CON(16), 13, GFLAGS),
468 INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in",
469 RK3368_CLKSEL_CON(21), 13, IFLAGS),
470
471 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
472 RK3368_CLKGATE_CON(4), 13, GFLAGS),
473 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
Heiko Stuebnerfd0c0742016-01-20 21:47:57 +0100[diff] [blame]474 RK3368_CLKGATE_CON(4), 12, GFLAGS),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]475
476 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
477 RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
478 RK3368_CLKGATE_CON(4), 5, GFLAGS),
479 COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
480 RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
481
482 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
483 RK3368_CLKSEL_CON(23), 8, 1, MFLAGS,
484 RK3368_CLKGATE_CON(5), 4, GFLAGS),
485 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
486 RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
487 RK3368_CLKGATE_CON(5), 3, GFLAGS),
488
489 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
490 RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
491 RK3368_CLKGATE_CON(5), 5, GFLAGS),
492
493 DIV(0, "pclk_pd_alive", "gpll", 0,
494 RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
495
496 /* sclk_timer has a gate in the sgrf */
497
498 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
499 RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
500 RK3368_CLKGATE_CON(7), 9, GFLAGS),
501 GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
502 RK3368_CLKGATE_CON(7), 3, GFLAGS),
503 COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
504 RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
505 RK3368_CLKGATE_CON(4), 11, GFLAGS),
506 MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
507 RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
508 COMPOSITE_NOMUX(0, "aclk_gpu_mem_pre", "aclk_gpu_src", 0,
509 RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
510 RK3368_CLKGATE_CON(5), 8, GFLAGS),
511 COMPOSITE_NOMUX(0, "aclk_gpu_cfg_pre", "aclk_gpu_src", 0,
512 RK3368_CLKSEL_CON(16), 8, 5, DFLAGS,
513 RK3368_CLKGATE_CON(5), 9, GFLAGS),
514 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
515 RK3368_CLKGATE_CON(7), 11, GFLAGS),
516
517 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
518 RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
519 RK3368_CLKGATE_CON(3), 0, GFLAGS),
520 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
521 RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
522 RK3368_CLKGATE_CON(3), 3, GFLAGS),
523 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
524 RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
525 RK3368_CLKGATE_CON(3), 2, GFLAGS),
526 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
527 RK3368_CLKGATE_CON(3), 1, GFLAGS),
528
529 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
530
531 /*
532 * Clock-Architecture Diagram 4
533 */
534
535 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
536 RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
537 RK3368_CLKGATE_CON(3), 7, GFLAGS),
538 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
539 RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
540 RK3368_CLKGATE_CON(3), 8, GFLAGS),
541 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
542 RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
543 RK3368_CLKGATE_CON(3), 9, GFLAGS),
544
545
546 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
547 RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
548 RK3368_CLKGATE_CON(7), 12, GFLAGS),
549 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
550 RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
551 RK3368_CLKGATE_CON(7), 13, GFLAGS),
552 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
553 RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
554 RK3368_CLKGATE_CON(7), 15, GFLAGS),
555
556 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
557 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
558
559 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3368_SDIO0_CON0, 1),
560 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
561
562 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1),
563 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0),
564
565 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
566 RK3368_CLKGATE_CON(8), 1, GFLAGS),
567
568 /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
569 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
570 RK3368_CLKGATE_CON(8), 4, GFLAGS),
571
572 /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
573 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
574 RK3368_CLKSEL_CON(25), 0, 6, DFLAGS,
575 RK3368_CLKGATE_CON(3), 5, GFLAGS),
576
577 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
578 RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
579 RK3368_CLKGATE_CON(3), 6, GFLAGS),
580
581 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
582 RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
583 RK3368_CLKGATE_CON(7), 8, GFLAGS),
584
585 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
586 RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
587 RK3368_CLKGATE_CON(6), 7, GFLAGS),
588
589 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
590 RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
591 RK3368_CLKGATE_CON(2), 0, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]592 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
593 RK3368_CLKSEL_CON(34), 0,
594 RK3368_CLKGATE_CON(2), 1, GFLAGS,
595 &rk3368_uart0_fracmux),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]596
597 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
598 RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
599 RK3368_CLKGATE_CON(2), 2, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]600 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
601 RK3368_CLKSEL_CON(36), 0,
602 RK3368_CLKGATE_CON(2), 3, GFLAGS,
603 &rk3368_uart1_fracmux),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]604
605 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
606 RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
607 RK3368_CLKGATE_CON(2), 6, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]608 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
609 RK3368_CLKSEL_CON(40), 0,
610 RK3368_CLKGATE_CON(2), 7, GFLAGS,
611 &rk3368_uart3_fracmux),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]612
613 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
614 RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
615 RK3368_CLKGATE_CON(2), 8, GFLAGS),
Elaine Zhang7af8a262016-02-24 08:44:11 +0800[diff] [blame]616 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
617 RK3368_CLKSEL_CON(42), 0,
618 RK3368_CLKGATE_CON(2), 9, GFLAGS,
619 &rk3368_uart4_fracmux),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]620
621 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
622 RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
623 RK3368_CLKGATE_CON(3), 4, GFLAGS),
624 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
625 RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
626 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
627 RK3368_CLKGATE_CON(7), 7, GFLAGS),
628 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
629 RK3368_CLKGATE_CON(7), 6, GFLAGS),
630 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
631 RK3368_CLKGATE_CON(7), 4, GFLAGS),
632 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
633 RK3368_CLKGATE_CON(7), 5, GFLAGS),
634
635 GATE(0, "jtag", "ext_jtag", 0,
636 RK3368_CLKGATE_CON(7), 0, GFLAGS),
637
638 COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
639 RK3368_CLKSEL_CON(26), 8, 2, MFLAGS,
640 RK3368_CLKGATE_CON(8), 0, GFLAGS),
641 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
642 RK3368_CLKSEL_CON(26), 12, 2, MFLAGS,
643 RK3368_CLKGATE_CON(8), 7, GFLAGS),
644 GATE(SCLK_HSICPHY12M, "sclk_hsicphy12m", "xin12m", 0,
645 RK3368_CLKGATE_CON(8), 6, GFLAGS),
646
647 /*
648 * Clock-Architecture Diagram 5
649 */
650
651 /* aclk_cci_pre gates */
652 GATE(0, "aclk_core_niu_cpup", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 4, GFLAGS),
653 GATE(0, "aclk_core_niu_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 3, GFLAGS),
654 GATE(0, "aclk_cci400", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 2, GFLAGS),
655 GATE(0, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 1, GFLAGS),
656 GATE(0, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 0, GFLAGS),
657
658 /* aclkm_core_* gates */
659 GATE(0, "aclk_adb400s_pd_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 0, GFLAGS),
660 GATE(0, "aclk_adb400s_pd_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
661
662 /* armclk* gates */
663 GATE(0, "sclk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 1, GFLAGS),
664 GATE(0, "sclk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
665
666 /* sclk_cs_pre gates */
667 GATE(0, "sclk_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 7, GFLAGS),
668 GATE(0, "pclk_core_niu_sdbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 6, GFLAGS),
669 GATE(0, "hclk_core_niu_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 5, GFLAGS),
670
671 /* aclk_bus gates */
672 GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
673 GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
674 GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
675 GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
676 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
677 GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
678
679 /* sclk_ddr gates */
680 GATE(0, "nclk_ddrupctl", "sclk_ddr", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
681
682 /* clk_hsadc_tsp is part of diagram2 */
683
684 /* fclk_mcu_src gates */
685 GATE(0, "hclk_noc_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 14, GFLAGS),
686 GATE(0, "fclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 12, GFLAGS),
687 GATE(0, "hclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 11, GFLAGS),
688
689 /* hclk_cpu gates */
690 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
691 GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
692 GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
693 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
694 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 10, GFLAGS),
695 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
696 GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
697
698 /* pclk_cpu gates */
699 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
700 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
701 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
702 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
703 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
704 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
705 GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
706 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
707 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
708 GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
709 GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
710
711 /*
712 * video clk gates
713 * aclk_video(_pre) can actually select between parents of aclk_vdpu
714 * and aclk_vepu by setting bit GRF_SOC_CON0[7].
715 */
716 GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
717 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_src", 0, RK3368_CLKGATE_CON(15), 3, GFLAGS),
718 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
719 GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
720
721 /* aclk_rga_pre gates */
722 GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
723 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
724 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
725
726 /* aclk_vio0 gates */
727 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
728 GATE(ACLK_VIO0_NOC, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
729 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
730 GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
731 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
732
733 /* sclk_isp gates */
734 GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
735 GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
736
737 /* hclk_vio gates */
738 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
739 GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
740 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
741 GATE(HCLK_VOP, "hclk_vop", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
742 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
743 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
744 GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
745 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
746
747 /*
748 * pclk_vio gates
749 * pclk_vio comes from the exactly same source as hclk_vio
750 */
751 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
752 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 9, GFLAGS),
753 GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
754 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
755 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
756 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
757
758 /* ext_vip gates in diagram3 */
759
760 /* gpu gates */
761 GATE(SCLK_GPU_CORE, "sclk_gpu_core", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 2, GFLAGS),
762 GATE(ACLK_GPU_MEM, "aclk_gpu_mem", "aclk_gpu_mem_pre", 0, RK3368_CLKGATE_CON(18), 1, GFLAGS),
763 GATE(ACLK_GPU_CFG, "aclk_gpu_cfg", "aclk_gpu_cfg_pre", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
764
765 /* aclk_peri gates */
766 GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
767 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 2, GFLAGS),
768 GATE(HCLK_SFC, "hclk_sfc", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
769 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
770 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 8, GFLAGS),
771 GATE(ACLK_PERI_MMU, "aclk_peri_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(21), 4, GFLAGS),
772
773 /* hclk_peri gates */
774 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
775 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
776 GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
777 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
778 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
779 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
780 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
781 GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
782 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
783 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
784 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
785 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
786 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
787 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
788 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
789
790 /* pclk_peri gates */
791 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
792 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
793 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
794 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
795 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
796 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 10, GFLAGS),
797 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
798 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
799 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
800 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 6, GFLAGS),
801 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
802 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
803 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
804 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
805 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
806
807 /* pclk_pd_alive gates */
Jianqun xu8931f8e2016-01-07 17:18:07 +0800[diff] [blame]808 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
809 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
810 GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
811 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
812 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
813 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
814 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]815
816 /*
817 * pclk_vio gates
818 * pclk_vio comes from the exactly same source as hclk_vio
819 */
820 GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
821 GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
822
823 /* pclk_pd_pmu gates */
Jianqun xu8931f8e2016-01-07 17:18:07 +0800[diff] [blame]824 GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
825 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
826 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
827 GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
828 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
829 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]830
831 /* timer gates */
832 GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
833 GATE(0, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
834 GATE(0, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
835 GATE(0, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
836 GATE(0, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
837 GATE(0, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
838 GATE(0, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
839 GATE(0, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
840 GATE(0, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
841 GATE(0, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
842 GATE(0, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
843 GATE(0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
844};
845
Heiko Stübner380528f2015-09-13 13:20:36 +0200[diff] [blame]846static const char *const rk3368_critical_clocks[] __initconst = {
Jianqun xu941c4d32015-12-02 21:22:31 +0800[diff] [blame]847 "aclk_bus",
848 "aclk_peri",
Caesar Wanga7ce4052015-12-01 17:13:24 +0800[diff] [blame]849 /*
850 * pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
851 * but needs to stay enabled there (including its parents) at all times.
852 */
853 "pclk_pwm1",
Heiko Stübner380528f2015-09-13 13:20:36 +0200[diff] [blame]854 "pclk_pd_pmu",
855};
856
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]857static void __init rk3368_clk_init(struct device_node *np)
858{
859 void __iomem *reg_base;
860 struct clk *clk;
861
862 reg_base = of_iomap(np, 0);
863 if (!reg_base) {
864 pr_err("%s: could not map cru region\n", __func__);
865 return;
866 }
867
868 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
869
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]870 /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
871 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
872 if (IS_ERR(clk))
873 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
874 __func__, PTR_ERR(clk));
875 else
876 rockchip_clk_add_lookup(clk, PCLK_WDT);
877
878 rockchip_clk_register_plls(rk3368_pll_clks,
879 ARRAY_SIZE(rk3368_pll_clks),
880 RK3368_GRF_SOC_STATUS0);
881 rockchip_clk_register_branches(rk3368_clk_branches,
882 ARRAY_SIZE(rk3368_clk_branches));
Heiko Stübner380528f2015-09-13 13:20:36 +0200[diff] [blame]883 rockchip_clk_protect_critical(rk3368_critical_clocks,
884 ARRAY_SIZE(rk3368_critical_clocks));
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]885
886 rockchip_clk_register_armclk(ARMCLKB, "armclkb",
887 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
888 &rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
889 ARRAY_SIZE(rk3368_cpuclkb_rates));
890
891 rockchip_clk_register_armclk(ARMCLKL, "armclkl",
892 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
893 &rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
894 ARRAY_SIZE(rk3368_cpuclkl_rates));
895
896 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
897 ROCKCHIP_SOFTRST_HIWORD_MASK);
898
Heiko Stuebnerdfff24b2015-12-18 17:51:55 +0100[diff] [blame]899 rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL);
Heiko Stuebner3536c972015-07-05 11:00:20 +0200[diff] [blame]900}
901CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);