Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 30 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "i915_drm.h" |
| 34 | #include "i915_drv.h" |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 35 | #include "i915_trace.h" |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 36 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include <linux/console.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 39 | #include <linux/module.h> |
Zhao Yakui | 354ff96 | 2009-07-08 14:13:12 +0800 | [diff] [blame] | 40 | #include "drm_crtc_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 41 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 42 | static int i915_modeset __read_mostly = -1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 43 | module_param_named(modeset, i915_modeset, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 44 | MODULE_PARM_DESC(modeset, |
| 45 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
| 46 | "1=on, -1=force vga console preference [default])"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 47 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 48 | unsigned int i915_fbpercrtc __always_unused = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 49 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 51 | int i915_panel_ignore_lid __read_mostly = 0; |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 52 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 53 | MODULE_PARM_DESC(panel_ignore_lid, |
| 54 | "Override lid status (0=autodetect [default], 1=lid open, " |
| 55 | "-1=lid closed)"); |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 56 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 57 | unsigned int i915_powersave __read_mostly = 1; |
Chris Wilson | 0aa9927 | 2010-11-02 09:20:50 +0000 | [diff] [blame] | 58 | module_param_named(powersave, i915_powersave, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 59 | MODULE_PARM_DESC(powersave, |
| 60 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 61 | |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 62 | int i915_semaphores __read_mostly = -1; |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 63 | module_param_named(semaphores, i915_semaphores, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 64 | MODULE_PARM_DESC(semaphores, |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 65 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 66 | |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 67 | int i915_enable_rc6 __read_mostly = -1; |
Jesse Barnes | f57f9c1 | 2012-04-11 09:39:02 -0700 | [diff] [blame] | 68 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 69 | MODULE_PARM_DESC(i915_enable_rc6, |
Eugeni Dodonov | 83b7f9a | 2012-03-23 11:57:18 -0300 | [diff] [blame] | 70 | "Enable power-saving render C-state 6. " |
| 71 | "Different stages can be selected via bitmask values " |
| 72 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " |
| 73 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " |
| 74 | "default: -1 (use per-chip default)"); |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 75 | |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 76 | int i915_enable_fbc __read_mostly = -1; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 77 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 78 | MODULE_PARM_DESC(i915_enable_fbc, |
| 79 | "Enable frame buffer compression for power savings " |
Keith Packard | cd0de03 | 2011-09-19 21:34:19 -0700 | [diff] [blame] | 80 | "(default: -1 (use per-chip default))"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 81 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 82 | unsigned int i915_lvds_downclock __read_mostly = 0; |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 83 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 84 | MODULE_PARM_DESC(lvds_downclock, |
| 85 | "Use panel (LVDS/eDP) downclocking for power savings " |
| 86 | "(default: false)"); |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 87 | |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 88 | int i915_lvds_channel_mode __read_mostly; |
| 89 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); |
| 90 | MODULE_PARM_DESC(lvds_channel_mode, |
| 91 | "Specify LVDS channel mode " |
| 92 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); |
| 93 | |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 94 | int i915_panel_use_ssc __read_mostly = -1; |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 95 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 96 | MODULE_PARM_DESC(lvds_use_ssc, |
| 97 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " |
Keith Packard | 72bbe58 | 2011-09-26 16:09:45 -0700 | [diff] [blame] | 98 | "(default: auto from VBT)"); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 99 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 100 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 101 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 102 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
Mathias Fröhlich | c10e408 | 2012-03-01 06:44:35 +0100 | [diff] [blame] | 103 | "Override/Ignore selection of SDVO panel mode in the VBT " |
| 104 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 105 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 106 | static bool i915_try_reset __read_mostly = true; |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 107 | module_param_named(reset, i915_try_reset, bool, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 108 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 109 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 110 | bool i915_enable_hangcheck __read_mostly = true; |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 111 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 112 | MODULE_PARM_DESC(enable_hangcheck, |
| 113 | "Periodically check GPU activity for detecting hangs. " |
| 114 | "WARNING: Disabling this can cause system wide hangs. " |
| 115 | "(default: true)"); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 116 | |
Daniel Vetter | 650dc07 | 2012-04-02 10:08:35 +0200 | [diff] [blame] | 117 | int i915_enable_ppgtt __read_mostly = -1; |
| 118 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 119 | MODULE_PARM_DESC(i915_enable_ppgtt, |
| 120 | "Enable PPGTT (default: true)"); |
| 121 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 122 | static struct drm_driver driver; |
Zhenyu Wang | 1f7a6e3 | 2010-02-23 14:05:24 +0800 | [diff] [blame] | 123 | extern int intel_agp_enabled; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 124 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 125 | #define INTEL_VGA_DEVICE(id, info) { \ |
Daniel Vetter | 80a2901 | 2011-10-11 10:59:05 +0200 | [diff] [blame] | 126 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 127 | .class_mask = 0xff0000, \ |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 128 | .vendor = 0x8086, \ |
| 129 | .device = id, \ |
| 130 | .subvendor = PCI_ANY_ID, \ |
| 131 | .subdevice = PCI_ANY_ID, \ |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 132 | .driver_data = (unsigned long) info } |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 133 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 134 | static const struct intel_device_info intel_i830_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 135 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 136 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 137 | }; |
| 138 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 139 | static const struct intel_device_info intel_845g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 140 | .gen = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 141 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 142 | }; |
| 143 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 144 | static const struct intel_device_info intel_i85x_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 145 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 146 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 147 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 148 | }; |
| 149 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 150 | static const struct intel_device_info intel_i865g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 151 | .gen = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 152 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 153 | }; |
| 154 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 155 | static const struct intel_device_info intel_i915g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 156 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 157 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 158 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 159 | static const struct intel_device_info intel_i915gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 160 | .gen = 3, .is_mobile = 1, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 161 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 162 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 163 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 164 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 165 | static const struct intel_device_info intel_i945g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 166 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 167 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 168 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 169 | static const struct intel_device_info intel_i945gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 170 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 171 | .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 172 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 173 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 174 | }; |
| 175 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 176 | static const struct intel_device_info intel_i965g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 177 | .gen = 4, .is_broadwater = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 178 | .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 179 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 180 | }; |
| 181 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 182 | static const struct intel_device_info intel_i965gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 183 | .gen = 4, .is_crestline = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 184 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 185 | .has_overlay = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 186 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 187 | }; |
| 188 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 189 | static const struct intel_device_info intel_g33_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 190 | .gen = 3, .is_g33 = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 192 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 193 | }; |
| 194 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 195 | static const struct intel_device_info intel_g45_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 196 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 197 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 198 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 199 | }; |
| 200 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 201 | static const struct intel_device_info intel_gm45_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 202 | .gen = 4, .is_g4x = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 203 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 204 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 205 | .supports_tv = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 206 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 207 | }; |
| 208 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 209 | static const struct intel_device_info intel_pineview_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 210 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 211 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 212 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 213 | }; |
| 214 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 215 | static const struct intel_device_info intel_ironlake_d_info = { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 216 | .gen = 5, |
Eugeni Dodonov | 5a117db | 2012-01-05 09:34:29 -0200 | [diff] [blame] | 217 | .need_gfx_hws = 1, .has_hotplug = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 218 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 219 | }; |
| 220 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 221 | static const struct intel_device_info intel_ironlake_m_info = { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 222 | .gen = 5, .is_mobile = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 223 | .need_gfx_hws = 1, .has_hotplug = 1, |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 224 | .has_fbc = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 225 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 226 | }; |
| 227 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 228 | static const struct intel_device_info intel_sandybridge_d_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 229 | .gen = 6, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 230 | .need_gfx_hws = 1, .has_hotplug = 1, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 231 | .has_bsd_ring = 1, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 232 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 233 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 234 | .has_force_wake = 1, |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 235 | }; |
| 236 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 237 | static const struct intel_device_info intel_sandybridge_m_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 238 | .gen = 6, .is_mobile = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 239 | .need_gfx_hws = 1, .has_hotplug = 1, |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 240 | .has_fbc = 1, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 241 | .has_bsd_ring = 1, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 242 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 243 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 244 | .has_force_wake = 1, |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 245 | }; |
| 246 | |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 247 | static const struct intel_device_info intel_ivybridge_d_info = { |
| 248 | .is_ivybridge = 1, .gen = 7, |
| 249 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 250 | .has_bsd_ring = 1, |
| 251 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 252 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 253 | .has_force_wake = 1, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 254 | }; |
| 255 | |
| 256 | static const struct intel_device_info intel_ivybridge_m_info = { |
| 257 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
| 258 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 259 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
| 260 | .has_bsd_ring = 1, |
| 261 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 262 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 263 | .has_force_wake = 1, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 264 | }; |
| 265 | |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 266 | static const struct intel_device_info intel_valleyview_m_info = { |
| 267 | .gen = 7, .is_mobile = 1, |
| 268 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 269 | .has_fbc = 0, |
| 270 | .has_bsd_ring = 1, |
| 271 | .has_blt_ring = 1, |
| 272 | .is_valleyview = 1, |
| 273 | }; |
| 274 | |
| 275 | static const struct intel_device_info intel_valleyview_d_info = { |
| 276 | .gen = 7, |
| 277 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 278 | .has_fbc = 0, |
| 279 | .has_bsd_ring = 1, |
| 280 | .has_blt_ring = 1, |
| 281 | .is_valleyview = 1, |
| 282 | }; |
| 283 | |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 284 | static const struct intel_device_info intel_haswell_d_info = { |
| 285 | .is_haswell = 1, .gen = 7, |
| 286 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 287 | .has_bsd_ring = 1, |
| 288 | .has_blt_ring = 1, |
| 289 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 290 | .has_force_wake = 1, |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 291 | }; |
| 292 | |
| 293 | static const struct intel_device_info intel_haswell_m_info = { |
| 294 | .is_haswell = 1, .gen = 7, .is_mobile = 1, |
| 295 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 296 | .has_bsd_ring = 1, |
| 297 | .has_blt_ring = 1, |
| 298 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 299 | .has_force_wake = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 300 | }; |
| 301 | |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 302 | static const struct pci_device_id pciidlist[] = { /* aka */ |
| 303 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ |
| 304 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ |
| 305 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 306 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 307 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
| 308 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
| 309 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
| 310 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
| 311 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
| 312 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
| 313 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
| 314 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
| 315 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
| 316 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
| 317 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
| 318 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
| 319 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
| 320 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
| 321 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
| 322 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
| 323 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
| 324 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
| 325 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
| 326 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
| 327 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
| 328 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
Chris Wilson | 41a5142 | 2010-09-17 08:22:30 +0100 | [diff] [blame] | 329 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 330 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
| 331 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
| 332 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
| 333 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 334 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 335 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
| 336 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 337 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 338 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
Zhenyu Wang | 4fefe43 | 2010-08-19 09:46:16 +0800 | [diff] [blame] | 339 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 340 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 341 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
| 342 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
| 343 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
| 344 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
| 345 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
Eugeni Dodonov | cc22a93 | 2012-03-29 20:55:48 -0300 | [diff] [blame] | 346 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
Eugeni Dodonov | c14f528 | 2012-05-09 15:37:32 -0300 | [diff] [blame] | 347 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
| 348 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
Paulo Zanoni | da612d8 | 2012-08-06 18:45:01 -0300 | [diff] [blame] | 349 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
Eugeni Dodonov | c14f528 | 2012-05-09 15:37:32 -0300 | [diff] [blame] | 350 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
| 351 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
Paulo Zanoni | da612d8 | 2012-08-06 18:45:01 -0300 | [diff] [blame] | 352 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
Eugeni Dodonov | c14f528 | 2012-05-09 15:37:32 -0300 | [diff] [blame] | 353 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
| 354 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
Paulo Zanoni | da612d8 | 2012-08-06 18:45:01 -0300 | [diff] [blame] | 355 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
| 356 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
| 357 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
| 358 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ |
| 359 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
| 360 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
| 361 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ |
| 362 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
| 363 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
| 364 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ |
| 365 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
| 366 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
| 367 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ |
| 368 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
| 369 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
| 370 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ |
| 371 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
| 372 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
| 373 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
| 374 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ |
| 375 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
| 376 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ |
| 377 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ |
| 378 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
| 379 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ |
| 380 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ |
| 381 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
| 382 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ |
Jesse Barnes | ff049b6 | 2012-06-20 10:53:13 -0700 | [diff] [blame] | 383 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
| 384 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
| 385 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 386 | {0, 0, 0} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | }; |
| 388 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 389 | #if defined(CONFIG_DRM_I915_KMS) |
| 390 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 391 | #endif |
| 392 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 393 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 394 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 395 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 396 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 397 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 398 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 399 | void intel_detect_pch(struct drm_device *dev) |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 400 | { |
| 401 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 402 | struct pci_dev *pch; |
| 403 | |
| 404 | /* |
| 405 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
| 406 | * make graphics device passthrough work easy for VMM, that only |
| 407 | * need to expose ISA bridge to let driver know the real hardware |
| 408 | * underneath. This is a requirement from virtualization team. |
| 409 | */ |
| 410 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 411 | if (pch) { |
| 412 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
| 413 | int id; |
| 414 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
| 415 | |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 416 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
| 417 | dev_priv->pch_type = PCH_IBX; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 418 | dev_priv->num_pch_pll = 2; |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 419 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
| 420 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 421 | dev_priv->pch_type = PCH_CPT; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 422 | dev_priv->num_pch_pll = 2; |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 423 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 424 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
| 425 | /* PantherPoint is CPT compatible */ |
| 426 | dev_priv->pch_type = PCH_CPT; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 427 | dev_priv->num_pch_pll = 2; |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 428 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 429 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 430 | dev_priv->pch_type = PCH_LPT; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 431 | dev_priv->num_pch_pll = 0; |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 432 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 433 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 434 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 435 | } |
| 436 | pci_dev_put(pch); |
| 437 | } |
| 438 | } |
| 439 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 440 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
| 441 | { |
| 442 | if (INTEL_INFO(dev)->gen < 6) |
| 443 | return 0; |
| 444 | |
| 445 | if (i915_semaphores >= 0) |
| 446 | return i915_semaphores; |
| 447 | |
Daniel Vetter | 59de329 | 2012-04-02 20:48:43 +0200 | [diff] [blame] | 448 | #ifdef CONFIG_INTEL_IOMMU |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 449 | /* Enable semaphores on SNB when IO remapping is off */ |
Daniel Vetter | 59de329 | 2012-04-02 20:48:43 +0200 | [diff] [blame] | 450 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 451 | return false; |
| 452 | #endif |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 453 | |
| 454 | return 1; |
| 455 | } |
| 456 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 457 | static int i915_drm_freeze(struct drm_device *dev) |
| 458 | { |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 459 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 460 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 461 | drm_kms_helper_poll_disable(dev); |
| 462 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 463 | pci_save_state(dev->pdev); |
| 464 | |
| 465 | /* If KMS is active, we do the leavevt stuff here */ |
| 466 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 467 | int error = i915_gem_idle(dev); |
| 468 | if (error) { |
| 469 | dev_err(&dev->pdev->dev, |
| 470 | "GEM idle failed, resume might fail\n"); |
| 471 | return error; |
| 472 | } |
| 473 | drm_irq_uninstall(dev); |
| 474 | } |
| 475 | |
| 476 | i915_save_state(dev); |
| 477 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 478 | intel_opregion_fini(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 479 | |
| 480 | /* Modeset on resume, not lid events */ |
| 481 | dev_priv->modeset_on_lid = 0; |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 482 | |
Dave Airlie | 3fa016a | 2012-03-28 10:48:49 +0100 | [diff] [blame] | 483 | console_lock(); |
| 484 | intel_fbdev_set_suspend(dev, 1); |
| 485 | console_unlock(); |
| 486 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 487 | return 0; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 488 | } |
| 489 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 490 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 491 | { |
| 492 | int error; |
| 493 | |
| 494 | if (!dev || !dev->dev_private) { |
| 495 | DRM_ERROR("dev: %p\n", dev); |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 496 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 497 | return -ENODEV; |
| 498 | } |
| 499 | |
Dave Airlie | b932ccb | 2008-02-20 10:02:20 +1000 | [diff] [blame] | 500 | if (state.event == PM_EVENT_PRETHAW) |
| 501 | return 0; |
| 502 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 503 | |
| 504 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 505 | return 0; |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 506 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 507 | error = i915_drm_freeze(dev); |
| 508 | if (error) |
| 509 | return error; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 510 | |
Dave Airlie | b932ccb | 2008-02-20 10:02:20 +1000 | [diff] [blame] | 511 | if (state.event == PM_EVENT_SUSPEND) { |
| 512 | /* Shut down the device */ |
| 513 | pci_disable_device(dev->pdev); |
| 514 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 515 | } |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 520 | static int i915_drm_thaw(struct drm_device *dev) |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 521 | { |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 522 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 523 | int error = 0; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 524 | |
Chris Wilson | d1c3b17 | 2010-12-08 14:26:19 +0000 | [diff] [blame] | 525 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 526 | mutex_lock(&dev->struct_mutex); |
| 527 | i915_gem_restore_gtt_mappings(dev); |
| 528 | mutex_unlock(&dev->struct_mutex); |
| 529 | } |
| 530 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 531 | i915_restore_state(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 532 | intel_opregion_setup(dev); |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 533 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 534 | /* KMS EnterVT equivalent */ |
| 535 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Paulo Zanoni | 40579ab | 2012-07-03 15:57:33 -0300 | [diff] [blame] | 536 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 537 | ironlake_init_pch_refclk(dev); |
| 538 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 539 | mutex_lock(&dev->struct_mutex); |
| 540 | dev_priv->mm.suspended = 0; |
| 541 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 542 | error = i915_gem_init_hw(dev); |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 543 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 544 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 545 | intel_modeset_init_hw(dev); |
Chris Wilson | 500f714 | 2011-01-24 15:14:41 +0000 | [diff] [blame] | 546 | drm_mode_config_reset(dev); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 547 | drm_irq_install(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 548 | |
Zhao Yakui | 354ff96 | 2009-07-08 14:13:12 +0800 | [diff] [blame] | 549 | /* Resume the modeset for every activated CRTC */ |
Sean Paul | 927a2f1 | 2012-03-23 08:52:58 -0400 | [diff] [blame] | 550 | mutex_lock(&dev->mode_config.mutex); |
Zhao Yakui | 354ff96 | 2009-07-08 14:13:12 +0800 | [diff] [blame] | 551 | drm_helper_resume_force_mode(dev); |
Sean Paul | 927a2f1 | 2012-03-23 08:52:58 -0400 | [diff] [blame] | 552 | mutex_unlock(&dev->mode_config.mutex); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 553 | } |
Jesse Barnes | 1daed3f | 2011-01-05 12:01:25 -0800 | [diff] [blame] | 554 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 555 | intel_opregion_init(dev); |
| 556 | |
Linus Torvalds | c9354c8 | 2009-11-02 09:29:55 -0800 | [diff] [blame] | 557 | dev_priv->modeset_on_lid = 0; |
Jesse Barnes | 06891e2 | 2009-09-14 10:58:48 -0700 | [diff] [blame] | 558 | |
Dave Airlie | 3fa016a | 2012-03-28 10:48:49 +0100 | [diff] [blame] | 559 | console_lock(); |
| 560 | intel_fbdev_set_suspend(dev, 0); |
| 561 | console_unlock(); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 562 | return error; |
| 563 | } |
| 564 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 565 | int i915_resume(struct drm_device *dev) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 566 | { |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 567 | int ret; |
| 568 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 569 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 570 | return 0; |
| 571 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 572 | if (pci_enable_device(dev->pdev)) |
| 573 | return -EIO; |
| 574 | |
| 575 | pci_set_master(dev->pdev); |
| 576 | |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 577 | ret = i915_drm_thaw(dev); |
| 578 | if (ret) |
| 579 | return ret; |
| 580 | |
| 581 | drm_kms_helper_poll_enable(dev); |
| 582 | return 0; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 583 | } |
| 584 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 585 | static int i8xx_do_reset(struct drm_device *dev) |
Chris Wilson | dc96e9b | 2010-10-01 12:05:06 +0100 | [diff] [blame] | 586 | { |
| 587 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 588 | |
| 589 | if (IS_I85X(dev)) |
| 590 | return -ENODEV; |
| 591 | |
| 592 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); |
| 593 | POSTING_READ(D_STATE); |
| 594 | |
| 595 | if (IS_I830(dev) || IS_845G(dev)) { |
| 596 | I915_WRITE(DEBUG_RESET_I830, |
| 597 | DEBUG_RESET_DISPLAY | |
| 598 | DEBUG_RESET_RENDER | |
| 599 | DEBUG_RESET_FULL); |
| 600 | POSTING_READ(DEBUG_RESET_I830); |
| 601 | msleep(1); |
| 602 | |
| 603 | I915_WRITE(DEBUG_RESET_I830, 0); |
| 604 | POSTING_READ(DEBUG_RESET_I830); |
| 605 | } |
| 606 | |
| 607 | msleep(1); |
| 608 | |
| 609 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); |
| 610 | POSTING_READ(D_STATE); |
| 611 | |
| 612 | return 0; |
| 613 | } |
| 614 | |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 615 | static int i965_reset_complete(struct drm_device *dev) |
| 616 | { |
| 617 | u8 gdrst; |
Kenneth Graunke | eeccdca | 2010-09-11 01:24:50 -0700 | [diff] [blame] | 618 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
Daniel Vetter | 5fe9fe8 | 2012-05-02 21:33:52 +0200 | [diff] [blame] | 619 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 620 | } |
| 621 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 622 | static int i965_do_reset(struct drm_device *dev) |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 623 | { |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 624 | int ret; |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 625 | u8 gdrst; |
| 626 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 627 | /* |
| 628 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 629 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 630 | * triggers the reset; when done, the hardware will clear it. |
| 631 | */ |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 632 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 633 | pci_write_config_byte(dev->pdev, I965_GDRST, |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 634 | gdrst | GRDOM_RENDER | |
| 635 | GRDOM_RESET_ENABLE); |
| 636 | ret = wait_for(i965_reset_complete(dev), 500); |
| 637 | if (ret) |
| 638 | return ret; |
| 639 | |
| 640 | /* We can't reset render&media without also resetting display ... */ |
| 641 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 642 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 643 | gdrst | GRDOM_MEDIA | |
| 644 | GRDOM_RESET_ENABLE); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 645 | |
| 646 | return wait_for(i965_reset_complete(dev), 500); |
| 647 | } |
| 648 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 649 | static int ironlake_do_reset(struct drm_device *dev) |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 650 | { |
| 651 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 652 | u32 gdrst; |
| 653 | int ret; |
| 654 | |
| 655 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 656 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 657 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 658 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 659 | if (ret) |
| 660 | return ret; |
| 661 | |
| 662 | /* We can't reset render&media without also resetting display ... */ |
| 663 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 664 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 665 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 666 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 667 | } |
| 668 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 669 | static int gen6_do_reset(struct drm_device *dev) |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 670 | { |
| 671 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 672 | int ret; |
| 673 | unsigned long irqflags; |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 674 | |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 675 | /* Hold gt_lock across reset to prevent any register access |
| 676 | * with forcewake not set correctly |
| 677 | */ |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 678 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 679 | |
| 680 | /* Reset the chip */ |
| 681 | |
| 682 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 683 | * for fifo space for the write or forcewake the chip for |
| 684 | * the read |
| 685 | */ |
| 686 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); |
| 687 | |
| 688 | /* Spin waiting for the device to ack the reset request */ |
| 689 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
| 690 | |
| 691 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 692 | if (dev_priv->forcewake_count) |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 693 | dev_priv->gt.force_wake_get(dev_priv); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 694 | else |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 695 | dev_priv->gt.force_wake_put(dev_priv); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 696 | |
| 697 | /* Restore fifo count */ |
| 698 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 699 | |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 700 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
| 701 | return ret; |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 702 | } |
| 703 | |
Ben Widawsky | 8e96d9c | 2012-06-04 14:42:56 -0700 | [diff] [blame] | 704 | int intel_gpu_reset(struct drm_device *dev) |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 705 | { |
Daniel Vetter | 2b9dc9a | 2012-04-27 15:17:43 +0200 | [diff] [blame] | 706 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 707 | int ret = -ENODEV; |
| 708 | |
| 709 | switch (INTEL_INFO(dev)->gen) { |
| 710 | case 7: |
| 711 | case 6: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 712 | ret = gen6_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 713 | break; |
| 714 | case 5: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 715 | ret = ironlake_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 716 | break; |
| 717 | case 4: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 718 | ret = i965_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 719 | break; |
| 720 | case 2: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 721 | ret = i8xx_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 722 | break; |
| 723 | } |
| 724 | |
Daniel Vetter | 2b9dc9a | 2012-04-27 15:17:43 +0200 | [diff] [blame] | 725 | /* Also reset the gpu hangman. */ |
| 726 | if (dev_priv->stop_rings) { |
| 727 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); |
| 728 | dev_priv->stop_rings = 0; |
| 729 | if (ret == -ENODEV) { |
| 730 | DRM_ERROR("Reset not implemented, but ignoring " |
| 731 | "error for simulated gpu hangs\n"); |
| 732 | ret = 0; |
| 733 | } |
| 734 | } |
| 735 | |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 736 | return ret; |
| 737 | } |
| 738 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 739 | /** |
Eugeni Dodonov | f3953dc | 2011-11-28 16:15:17 -0200 | [diff] [blame] | 740 | * i915_reset - reset chip after a hang |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 741 | * @dev: drm device to reset |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 742 | * |
| 743 | * Reset the chip. Useful if a hang is detected. Returns zero on successful |
| 744 | * reset or otherwise an error code. |
| 745 | * |
| 746 | * Procedure is fairly simple: |
| 747 | * - reset the chip using the reset reg |
| 748 | * - re-init context state |
| 749 | * - re-init hardware status page |
| 750 | * - re-init ring buffer |
| 751 | * - re-init interrupt state |
| 752 | * - re-init display |
| 753 | */ |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 754 | int i915_reset(struct drm_device *dev) |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 755 | { |
| 756 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 757 | int ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 758 | |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 759 | if (!i915_try_reset) |
| 760 | return 0; |
| 761 | |
Daniel Vetter | d54a02c | 2012-07-04 22:18:39 +0200 | [diff] [blame] | 762 | mutex_lock(&dev->struct_mutex); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 763 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 764 | i915_gem_reset(dev); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 765 | |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 766 | ret = -ENODEV; |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 767 | if (get_seconds() - dev_priv->last_gpu_reset < 5) |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 768 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 769 | else |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 770 | ret = intel_gpu_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 771 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 772 | dev_priv->last_gpu_reset = get_seconds(); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 773 | if (ret) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 774 | DRM_ERROR("Failed to reset chip.\n"); |
Daniel J Blueman | f953c93 | 2010-05-17 14:23:52 +0100 | [diff] [blame] | 775 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 776 | return ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | /* Ok, now get things going again... */ |
| 780 | |
| 781 | /* |
| 782 | * Everything depends on having the GTT running, so we need to start |
| 783 | * there. Fortunately we don't need to do this unless we reset the |
| 784 | * chip at a PCI level. |
| 785 | * |
| 786 | * Next we need to restore the context, but we don't use those |
| 787 | * yet either... |
| 788 | * |
| 789 | * Ring buffer needs to be re-initialized in the KMS case, or if X |
| 790 | * was running at the time of the reset (i.e. we weren't VT |
| 791 | * switched away). |
| 792 | */ |
| 793 | if (drm_core_check_feature(dev, DRIVER_MODESET) || |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 794 | !dev_priv->mm.suspended) { |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 795 | struct intel_ring_buffer *ring; |
| 796 | int i; |
| 797 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 798 | dev_priv->mm.suspended = 0; |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 799 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 800 | i915_gem_init_swizzling(dev); |
| 801 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 802 | for_each_ring(ring, dev_priv, i) |
| 803 | ring->init(ring); |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 804 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 805 | i915_gem_context_init(dev); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 806 | i915_gem_init_ppgtt(dev); |
| 807 | |
Daniel Vetter | 8e88a2b | 2012-06-19 18:40:00 +0200 | [diff] [blame] | 808 | /* |
| 809 | * It would make sense to re-init all the other hw state, at |
| 810 | * least the rps/rc6/emon init done within modeset_init_hw. For |
| 811 | * some unknown reason, this blows up my ilk, so don't. |
| 812 | */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 813 | |
Daniel Vetter | 8e88a2b | 2012-06-19 18:40:00 +0200 | [diff] [blame] | 814 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 815 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 816 | drm_irq_uninstall(dev); |
| 817 | drm_irq_install(dev); |
Daniel Vetter | bcbc324 | 2012-04-27 15:17:41 +0200 | [diff] [blame] | 818 | } else { |
| 819 | mutex_unlock(&dev->struct_mutex); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 820 | } |
| 821 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 822 | return 0; |
| 823 | } |
| 824 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 825 | static int __devinit |
| 826 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 827 | { |
Daniel Vetter | 01a0685 | 2012-06-25 15:58:49 +0200 | [diff] [blame] | 828 | struct intel_device_info *intel_info = |
| 829 | (struct intel_device_info *) ent->driver_data; |
| 830 | |
Chris Wilson | 5fe49d8 | 2011-02-01 19:43:02 +0000 | [diff] [blame] | 831 | /* Only bind to function 0 of the device. Early generations |
| 832 | * used function 1 as a placeholder for multi-head. This causes |
| 833 | * us confusion instead, especially on the systems where both |
| 834 | * functions have the same PCI-ID! |
| 835 | */ |
| 836 | if (PCI_FUNC(pdev->devfn)) |
| 837 | return -ENODEV; |
| 838 | |
Daniel Vetter | 01a0685 | 2012-06-25 15:58:49 +0200 | [diff] [blame] | 839 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
| 840 | * implementation for gen3 (and only gen3) that used legacy drm maps |
| 841 | * (gasp!) to share buffers between X and the client. Hence we need to |
| 842 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ |
| 843 | if (intel_info->gen != 3) { |
| 844 | driver.driver_features &= |
| 845 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); |
| 846 | } else if (!intel_agp_enabled) { |
| 847 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
| 848 | return -ENODEV; |
| 849 | } |
| 850 | |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 851 | return drm_get_pci_dev(pdev, ent, &driver); |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | static void |
| 855 | i915_pci_remove(struct pci_dev *pdev) |
| 856 | { |
| 857 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 858 | |
| 859 | drm_put_dev(dev); |
| 860 | } |
| 861 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 862 | static int i915_pm_suspend(struct device *dev) |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 863 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 864 | struct pci_dev *pdev = to_pci_dev(dev); |
| 865 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 866 | int error; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 867 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 868 | if (!drm_dev || !drm_dev->dev_private) { |
| 869 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 870 | return -ENODEV; |
| 871 | } |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 872 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 873 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 874 | return 0; |
| 875 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 876 | error = i915_drm_freeze(drm_dev); |
| 877 | if (error) |
| 878 | return error; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 879 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 880 | pci_disable_device(pdev); |
| 881 | pci_set_power_state(pdev, PCI_D3hot); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 882 | |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 883 | return 0; |
| 884 | } |
| 885 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 886 | static int i915_pm_resume(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 887 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 888 | struct pci_dev *pdev = to_pci_dev(dev); |
| 889 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 890 | |
| 891 | return i915_resume(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 892 | } |
| 893 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 894 | static int i915_pm_freeze(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 895 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 896 | struct pci_dev *pdev = to_pci_dev(dev); |
| 897 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 898 | |
| 899 | if (!drm_dev || !drm_dev->dev_private) { |
| 900 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 901 | return -ENODEV; |
| 902 | } |
| 903 | |
| 904 | return i915_drm_freeze(drm_dev); |
| 905 | } |
| 906 | |
| 907 | static int i915_pm_thaw(struct device *dev) |
| 908 | { |
| 909 | struct pci_dev *pdev = to_pci_dev(dev); |
| 910 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 911 | |
| 912 | return i915_drm_thaw(drm_dev); |
| 913 | } |
| 914 | |
| 915 | static int i915_pm_poweroff(struct device *dev) |
| 916 | { |
| 917 | struct pci_dev *pdev = to_pci_dev(dev); |
| 918 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 919 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 920 | return i915_drm_freeze(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 921 | } |
| 922 | |
Chris Wilson | b4b78d1 | 2010-06-06 15:40:20 +0100 | [diff] [blame] | 923 | static const struct dev_pm_ops i915_pm_ops = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 924 | .suspend = i915_pm_suspend, |
| 925 | .resume = i915_pm_resume, |
| 926 | .freeze = i915_pm_freeze, |
| 927 | .thaw = i915_pm_thaw, |
| 928 | .poweroff = i915_pm_poweroff, |
| 929 | .restore = i915_pm_resume, |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 930 | }; |
| 931 | |
Laurent Pinchart | 78b6855 | 2012-05-17 13:27:22 +0200 | [diff] [blame] | 932 | static const struct vm_operations_struct i915_gem_vm_ops = { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 933 | .fault = i915_gem_fault, |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 934 | .open = drm_gem_vm_open, |
| 935 | .close = drm_gem_vm_close, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 936 | }; |
| 937 | |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 938 | static const struct file_operations i915_driver_fops = { |
| 939 | .owner = THIS_MODULE, |
| 940 | .open = drm_open, |
| 941 | .release = drm_release, |
| 942 | .unlocked_ioctl = drm_ioctl, |
| 943 | .mmap = drm_gem_mmap, |
| 944 | .poll = drm_poll, |
| 945 | .fasync = drm_fasync, |
| 946 | .read = drm_read, |
| 947 | #ifdef CONFIG_COMPAT |
| 948 | .compat_ioctl = i915_compat_ioctl, |
| 949 | #endif |
| 950 | .llseek = noop_llseek, |
| 951 | }; |
| 952 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | static struct drm_driver driver = { |
Michael Witten | 0c54781 | 2011-08-25 17:55:54 +0000 | [diff] [blame] | 954 | /* Don't use MTRRs here; the Xserver or userspace app should |
| 955 | * deal with them for Intel hardware. |
Dave Airlie | 792d2b9 | 2005-11-11 23:30:27 +1100 | [diff] [blame] | 956 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 957 | .driver_features = |
| 958 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 959 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 960 | .load = i915_driver_load, |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 961 | .unload = i915_driver_unload, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 962 | .open = i915_driver_open, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 963 | .lastclose = i915_driver_lastclose, |
| 964 | .preclose = i915_driver_preclose, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 965 | .postclose = i915_driver_postclose, |
Rafael J. Wysocki | d8e2920 | 2010-01-09 00:45:33 +0100 | [diff] [blame] | 966 | |
| 967 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ |
| 968 | .suspend = i915_suspend, |
| 969 | .resume = i915_resume, |
| 970 | |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 971 | .device_is_agp = i915_driver_device_is_agp, |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 972 | .master_create = i915_master_create, |
| 973 | .master_destroy = i915_master_destroy, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 974 | #if defined(CONFIG_DEBUG_FS) |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 975 | .debugfs_init = i915_debugfs_init, |
| 976 | .debugfs_cleanup = i915_debugfs_cleanup, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 977 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 978 | .gem_init_object = i915_gem_init_object, |
| 979 | .gem_free_object = i915_gem_free_object, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 980 | .gem_vm_ops = &i915_gem_vm_ops, |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 981 | |
| 982 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 983 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 984 | .gem_prime_export = i915_gem_prime_export, |
| 985 | .gem_prime_import = i915_gem_prime_import, |
| 986 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 987 | .dumb_create = i915_gem_dumb_create, |
| 988 | .dumb_map_offset = i915_gem_mmap_gtt, |
| 989 | .dumb_destroy = i915_gem_dumb_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 990 | .ioctls = i915_ioctls, |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 991 | .fops = &i915_driver_fops, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 992 | .name = DRIVER_NAME, |
| 993 | .desc = DRIVER_DESC, |
| 994 | .date = DRIVER_DATE, |
| 995 | .major = DRIVER_MAJOR, |
| 996 | .minor = DRIVER_MINOR, |
| 997 | .patchlevel = DRIVER_PATCHLEVEL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | }; |
| 999 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1000 | static struct pci_driver i915_pci_driver = { |
| 1001 | .name = DRIVER_NAME, |
| 1002 | .id_table = pciidlist, |
| 1003 | .probe = i915_pci_probe, |
| 1004 | .remove = i915_pci_remove, |
| 1005 | .driver.pm = &i915_pm_ops, |
| 1006 | }; |
| 1007 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | static int __init i915_init(void) |
| 1009 | { |
| 1010 | driver.num_ioctls = i915_max_ioctl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1011 | |
| 1012 | /* |
| 1013 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless |
| 1014 | * explicitly disabled with the module pararmeter. |
| 1015 | * |
| 1016 | * Otherwise, just follow the parameter (defaulting to off). |
| 1017 | * |
| 1018 | * Allow optional vga_text_mode_force boot option to override |
| 1019 | * the default behavior. |
| 1020 | */ |
| 1021 | #if defined(CONFIG_DRM_I915_KMS) |
| 1022 | if (i915_modeset != 0) |
| 1023 | driver.driver_features |= DRIVER_MODESET; |
| 1024 | #endif |
| 1025 | if (i915_modeset == 1) |
| 1026 | driver.driver_features |= DRIVER_MODESET; |
| 1027 | |
| 1028 | #ifdef CONFIG_VGA_CONSOLE |
| 1029 | if (vgacon_text_force() && i915_modeset == -1) |
| 1030 | driver.driver_features &= ~DRIVER_MODESET; |
| 1031 | #endif |
| 1032 | |
Chris Wilson | 3885c6b | 2011-01-23 10:45:14 +0000 | [diff] [blame] | 1033 | if (!(driver.driver_features & DRIVER_MODESET)) |
| 1034 | driver.get_vblank_timestamp = NULL; |
| 1035 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1036 | return drm_pci_init(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1037 | } |
| 1038 | |
| 1039 | static void __exit i915_exit(void) |
| 1040 | { |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1041 | drm_pci_exit(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1042 | } |
| 1043 | |
| 1044 | module_init(i915_init); |
| 1045 | module_exit(i915_exit); |
| 1046 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1047 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 1048 | MODULE_DESCRIPTION(DRIVER_DESC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1049 | MODULE_LICENSE("GPL and additional rights"); |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1050 | |
Jesse Barnes | b7d8409 | 2012-03-22 14:38:43 -0700 | [diff] [blame] | 1051 | /* We give fast paths for the really cool registers */ |
| 1052 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 1053 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
| 1054 | ((reg) < 0x40000) && \ |
| 1055 | ((reg) != FORCEWAKE)) |
Jesse Barnes | b7d8409 | 2012-03-22 14:38:43 -0700 | [diff] [blame] | 1056 | |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1057 | static bool IS_DISPLAYREG(u32 reg) |
| 1058 | { |
| 1059 | /* |
| 1060 | * This should make it easier to transition modules over to the |
| 1061 | * new register block scheme, since we can do it incrementally. |
| 1062 | */ |
Daniel Vetter | a7e806d | 2012-07-11 16:27:55 +0200 | [diff] [blame] | 1063 | if (reg >= VLV_DISPLAY_BASE) |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1064 | return false; |
| 1065 | |
| 1066 | if (reg >= RENDER_RING_BASE && |
| 1067 | reg < RENDER_RING_BASE + 0xff) |
| 1068 | return false; |
| 1069 | if (reg >= GEN6_BSD_RING_BASE && |
| 1070 | reg < GEN6_BSD_RING_BASE + 0xff) |
| 1071 | return false; |
| 1072 | if (reg >= BLT_RING_BASE && |
| 1073 | reg < BLT_RING_BASE + 0xff) |
| 1074 | return false; |
| 1075 | |
| 1076 | if (reg == PGTBL_ER) |
| 1077 | return false; |
| 1078 | |
| 1079 | if (reg >= IPEIR_I965 && |
| 1080 | reg < HWSTAM) |
| 1081 | return false; |
| 1082 | |
| 1083 | if (reg == MI_MODE) |
| 1084 | return false; |
| 1085 | |
| 1086 | if (reg == GFX_MODE_GEN7) |
| 1087 | return false; |
| 1088 | |
| 1089 | if (reg == RENDER_HWS_PGA_GEN7 || |
| 1090 | reg == BSD_HWS_PGA_GEN7 || |
| 1091 | reg == BLT_HWS_PGA_GEN7) |
| 1092 | return false; |
| 1093 | |
| 1094 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
| 1095 | reg == GEN6_BSD_RNCID) |
| 1096 | return false; |
| 1097 | |
| 1098 | if (reg == GEN6_BLITTER_ECOSKPD) |
| 1099 | return false; |
| 1100 | |
| 1101 | if (reg >= 0x4000c && |
| 1102 | reg <= 0x4002c) |
| 1103 | return false; |
| 1104 | |
| 1105 | if (reg >= 0x4f000 && |
| 1106 | reg <= 0x4f08f) |
| 1107 | return false; |
| 1108 | |
| 1109 | if (reg >= 0x4f100 && |
| 1110 | reg <= 0x4f11f) |
| 1111 | return false; |
| 1112 | |
| 1113 | if (reg >= VLV_MASTER_IER && |
| 1114 | reg <= GEN6_PMIER) |
| 1115 | return false; |
| 1116 | |
| 1117 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
| 1118 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
| 1119 | return false; |
| 1120 | |
| 1121 | if (reg >= VLV_IIR_RW && |
| 1122 | reg <= VLV_ISR) |
| 1123 | return false; |
| 1124 | |
| 1125 | if (reg == FORCEWAKE_VLV || |
| 1126 | reg == FORCEWAKE_ACK_VLV) |
| 1127 | return false; |
| 1128 | |
| 1129 | if (reg == GEN6_GDRST) |
| 1130 | return false; |
| 1131 | |
| 1132 | return true; |
| 1133 | } |
| 1134 | |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1135 | #define __i915_read(x, y) \ |
| 1136 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| 1137 | u##x val = 0; \ |
| 1138 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1139 | unsigned long irqflags; \ |
| 1140 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
| 1141 | if (dev_priv->forcewake_count == 0) \ |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 1142 | dev_priv->gt.force_wake_get(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1143 | val = read##y(dev_priv->regs + reg); \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1144 | if (dev_priv->forcewake_count == 0) \ |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 1145 | dev_priv->gt.force_wake_put(dev_priv); \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1146 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1147 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
| 1148 | val = read##y(dev_priv->regs + reg + 0x180000); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1149 | } else { \ |
| 1150 | val = read##y(dev_priv->regs + reg); \ |
| 1151 | } \ |
| 1152 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
| 1153 | return val; \ |
| 1154 | } |
| 1155 | |
| 1156 | __i915_read(8, b) |
| 1157 | __i915_read(16, w) |
| 1158 | __i915_read(32, l) |
| 1159 | __i915_read(64, q) |
| 1160 | #undef __i915_read |
| 1161 | |
| 1162 | #define __i915_write(x, y) \ |
| 1163 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1164 | u32 __fifo_ret = 0; \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1165 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
| 1166 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1167 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1168 | } \ |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1169 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
| 1170 | write##y(val, dev_priv->regs + reg + 0x180000); \ |
| 1171 | } else { \ |
| 1172 | write##y(val, dev_priv->regs + reg); \ |
| 1173 | } \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1174 | if (unlikely(__fifo_ret)) { \ |
| 1175 | gen6_gt_check_fifodbg(dev_priv); \ |
| 1176 | } \ |
Ben Widawsky | b4c145c | 2012-08-20 16:15:14 -0700 | [diff] [blame^] | 1177 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
| 1178 | DRM_ERROR("Unclaimed write to %x\n", reg); \ |
| 1179 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ |
| 1180 | } \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1181 | } |
| 1182 | __i915_write(8, b) |
| 1183 | __i915_write(16, w) |
| 1184 | __i915_write(32, l) |
| 1185 | __i915_write(64, q) |
| 1186 | #undef __i915_write |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 1187 | |
| 1188 | static const struct register_whitelist { |
| 1189 | uint64_t offset; |
| 1190 | uint32_t size; |
| 1191 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 1192 | } whitelist[] = { |
| 1193 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, |
| 1194 | }; |
| 1195 | |
| 1196 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 1197 | void *data, struct drm_file *file) |
| 1198 | { |
| 1199 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1200 | struct drm_i915_reg_read *reg = data; |
| 1201 | struct register_whitelist const *entry = whitelist; |
| 1202 | int i; |
| 1203 | |
| 1204 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 1205 | if (entry->offset == reg->offset && |
| 1206 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 1207 | break; |
| 1208 | } |
| 1209 | |
| 1210 | if (i == ARRAY_SIZE(whitelist)) |
| 1211 | return -EINVAL; |
| 1212 | |
| 1213 | switch (entry->size) { |
| 1214 | case 8: |
| 1215 | reg->val = I915_READ64(reg->offset); |
| 1216 | break; |
| 1217 | case 4: |
| 1218 | reg->val = I915_READ(reg->offset); |
| 1219 | break; |
| 1220 | case 2: |
| 1221 | reg->val = I915_READ16(reg->offset); |
| 1222 | break; |
| 1223 | case 1: |
| 1224 | reg->val = I915_READ8(reg->offset); |
| 1225 | break; |
| 1226 | default: |
| 1227 | WARN_ON(1); |
| 1228 | return -EINVAL; |
| 1229 | } |
| 1230 | |
| 1231 | return 0; |
| 1232 | } |